Functions that access the ITM debug interface. More...

Collaboration diagram for ITM Functions:

Variables
uint32_t APSR_Type::_reserved0:16
	bit: 0..15 Reserved More...
uint32_t APSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t APSR_Type::_reserved1:7
	bit: 20..26 Reserved More...
uint32_t APSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t APSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t APSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t APSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t APSR_Type::N:1
	bit: 31 Negative condition code flag More...
struct {
uint32_t APSR_Type::_reserved0:16
	bit: 0..15 Reserved More...
uint32_t APSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t APSR_Type::_reserved1:7
	bit: 20..26 Reserved More...
uint32_t APSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t APSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t APSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t APSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t APSR_Type::N:1
	bit: 31 Negative condition code flag More...
}	APSR_Type::b
	Structure used for bit access.
uint32_t	APSR_Type::w
	Type used for word access.
uint32_t IPSR_Type::ISR:9
	bit: 0. More...
uint32_t IPSR_Type::_reserved0:23
	bit: 9..31 Reserved More...
struct {
uint32_t IPSR_Type::ISR:9
	bit: 0. More...
uint32_t IPSR_Type::_reserved0:23
	bit: 9..31 Reserved More...
}	IPSR_Type::b
	Structure used for bit access.
uint32_t	IPSR_Type::w
	Type used for word access.
uint32_t xPSR_Type::ISR:9
	bit: 0. More...
uint32_t xPSR_Type::_reserved0:7
	bit: 9..15 Reserved More...
uint32_t xPSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t xPSR_Type::_reserved1:4
	bit: 20..23 Reserved More...
uint32_t xPSR_Type::T:1
	bit: 24 Thumb bit (read 0) More...
uint32_t xPSR_Type::IT:2
	bit: 25..26 saved IT state (read 0) More...
uint32_t xPSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t xPSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t xPSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t xPSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t xPSR_Type::N:1
	bit: 31 Negative condition code flag More...
struct {
uint32_t xPSR_Type::ISR:9
	bit: 0. More...
uint32_t xPSR_Type::_reserved0:7
	bit: 9..15 Reserved More...
uint32_t xPSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t xPSR_Type::_reserved1:4
	bit: 20..23 Reserved More...
uint32_t xPSR_Type::T:1
	bit: 24 Thumb bit (read 0) More...
uint32_t xPSR_Type::IT:2
	bit: 25..26 saved IT state (read 0) More...
uint32_t xPSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t xPSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t xPSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t xPSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t xPSR_Type::N:1
	bit: 31 Negative condition code flag More...
}	xPSR_Type::b
	Structure used for bit access.
uint32_t	xPSR_Type::w
	Type used for word access.
uint32_t CONTROL_Type::nPRIV:1
	bit: 0 Execution privilege in Thread mode More...
uint32_t CONTROL_Type::SPSEL:1
	bit: 1 Stack-pointer select More...
uint32_t CONTROL_Type::FPCA:1
	bit: 2 Floating-point context active More...
uint32_t CONTROL_Type::SFPA:1
	bit: 3 Secure floating-point active More...
uint32_t CONTROL_Type::_reserved1:28
	bit: 4..31 Reserved More...
struct {
uint32_t CONTROL_Type::nPRIV:1
	bit: 0 Execution privilege in Thread mode More...
uint32_t CONTROL_Type::SPSEL:1
	bit: 1 Stack-pointer select More...
uint32_t CONTROL_Type::FPCA:1
	bit: 2 Floating-point context active More...
uint32_t CONTROL_Type::SFPA:1
	bit: 3 Secure floating-point active More...
uint32_t CONTROL_Type::_reserved1:28
	bit: 4..31 Reserved More...
}	CONTROL_Type::b
	Structure used for bit access.
uint32_t	CONTROL_Type::w
	Type used for word access.
__IOM uint32_t	NVIC_Type::ISER [16U]
	Offset: 0x000 (R/W) Interrupt Set Enable Register.
uint32_t	NVIC_Type::RESERVED0 [16U]
__IOM uint32_t	NVIC_Type::ICER [16U]
	Offset: 0x080 (R/W) Interrupt Clear Enable Register.
uint32_t	NVIC_Type::RSERVED1 [16U]
__IOM uint32_t	NVIC_Type::ISPR [16U]
	Offset: 0x100 (R/W) Interrupt Set Pending Register.
uint32_t	NVIC_Type::RESERVED2 [16U]
__IOM uint32_t	NVIC_Type::ICPR [16U]
	Offset: 0x180 (R/W) Interrupt Clear Pending Register.
uint32_t	NVIC_Type::RESERVED3 [16U]
__IOM uint32_t	NVIC_Type::IABR [16U]
	Offset: 0x200 (R/W) Interrupt Active bit Register.
uint32_t	NVIC_Type::RESERVED4 [16U]
__IOM uint32_t	NVIC_Type::ITNS [16U]
	Offset: 0x280 (R/W) Interrupt Non-Secure State Register.
uint32_t	NVIC_Type::RESERVED5 [16U]
__IOM uint8_t	NVIC_Type::IPR [496U]
	Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide).
uint32_t	NVIC_Type::RESERVED6 [580U]
__OM uint32_t	NVIC_Type::STIR
	Offset: 0xE00 ( /W) Software Trigger Interrupt Register.
__IM uint32_t	SCB_Type::CPUID
	Offset: 0x000 (R/ ) CPUID Base Register.
__IOM uint32_t	SCB_Type::ICSR
	Offset: 0x004 (R/W) Interrupt Control and State Register.
__IOM uint32_t	SCB_Type::VTOR
	Offset: 0x008 (R/W) Vector Table Offset Register.
__IOM uint32_t	SCB_Type::AIRCR
	Offset: 0x00C (R/W) Application Interrupt and Reset Control Register.
__IOM uint32_t	SCB_Type::SCR
	Offset: 0x010 (R/W) System Control Register.
__IOM uint32_t	SCB_Type::CCR
	Offset: 0x014 (R/W) Configuration Control Register.
__IOM uint32_t	SCB_Type::SHCSR
	Offset: 0x024 (R/W) System Handler Control and State Register.
__IOM uint32_t	SCB_Type::CFSR
	Offset: 0x028 (R/W) Configurable Fault Status Register.
__IOM uint32_t	SCB_Type::HFSR
	Offset: 0x02C (R/W) HardFault Status Register.
__IOM uint32_t	SCB_Type::DFSR
	Offset: 0x030 (R/W) Debug Fault Status Register.
__IOM uint32_t	SCB_Type::MMFAR
	Offset: 0x034 (R/W) MemManage Fault Address Register.
__IOM uint32_t	SCB_Type::BFAR
	Offset: 0x038 (R/W) BusFault Address Register.
__IOM uint32_t	SCB_Type::AFSR
	Offset: 0x03C (R/W) Auxiliary Fault Status Register.
__IM uint32_t	SCB_Type::ID_PFR [2U]
	Offset: 0x040 (R/ ) Processor Feature Register.
__IM uint32_t	SCB_Type::ID_DFR
	Offset: 0x048 (R/ ) Debug Feature Register.
__IM uint32_t	SCB_Type::ID_AFR
	Offset: 0x04C (R/ ) Auxiliary Feature Register.
__IM uint32_t	SCB_Type::ID_MMFR [4U]
	Offset: 0x050 (R/ ) Memory Model Feature Register.
__IM uint32_t	SCB_Type::ID_ISAR [6U]
	Offset: 0x060 (R/ ) Instruction Set Attributes Register.
__IM uint32_t	SCB_Type::CLIDR
	Offset: 0x078 (R/ ) Cache Level ID register.
__IM uint32_t	SCB_Type::CTR
	Offset: 0x07C (R/ ) Cache Type register.
__IM uint32_t	SCB_Type::CCSIDR
	Offset: 0x080 (R/ ) Cache Size ID Register.
__IOM uint32_t	SCB_Type::CSSELR
	Offset: 0x084 (R/W) Cache Size Selection Register.
__IOM uint32_t	SCB_Type::CPACR
	Offset: 0x088 (R/W) Coprocessor Access Control Register.
__IOM uint32_t	SCB_Type::NSACR
	Offset: 0x08C (R/W) Non-Secure Access Control Register.
uint32_t	SCB_Type::RESERVED7 [21U]
__IOM uint32_t	SCB_Type::SFSR
	Offset: 0x0E4 (R/W) Secure Fault Status Register.
__IOM uint32_t	SCB_Type::SFAR
	Offset: 0x0E8 (R/W) Secure Fault Address Register.
uint32_t	SCB_Type::RESERVED3 [69U]
__OM uint32_t	SCB_Type::STIR
	Offset: 0x200 ( /W) Software Triggered Interrupt Register.
__IOM uint32_t	SCB_Type::RFSR
	Offset: 0x204 (R/W) RAS Fault Status Register.
uint32_t	SCB_Type::RESERVED4 [14U]
__IM uint32_t	SCB_Type::MVFR0
	Offset: 0x240 (R/ ) Media and VFP Feature Register 0.
__IM uint32_t	SCB_Type::MVFR1
	Offset: 0x244 (R/ ) Media and VFP Feature Register 1.
__IM uint32_t	SCB_Type::MVFR2
	Offset: 0x248 (R/ ) Media and VFP Feature Register 2.
uint32_t	SCB_Type::RESERVED5 [1U]
__OM uint32_t	SCB_Type::ICIALLU
	Offset: 0x250 ( /W) I-Cache Invalidate All to PoU.
uint32_t	SCB_Type::RESERVED6 [1U]
__OM uint32_t	SCB_Type::ICIMVAU
	Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU.
__OM uint32_t	SCB_Type::DCIMVAC
	Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC.
__OM uint32_t	SCB_Type::DCISW
	Offset: 0x260 ( /W) D-Cache Invalidate by Set-way.
__OM uint32_t	SCB_Type::DCCMVAU
	Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU.
__OM uint32_t	SCB_Type::DCCMVAC
	Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC.
__OM uint32_t	SCB_Type::DCCSW
	Offset: 0x26C ( /W) D-Cache Clean by Set-way.
__OM uint32_t	SCB_Type::DCCIMVAC
	Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC.
__OM uint32_t	SCB_Type::DCCISW
	Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way.
__OM uint32_t	SCB_Type::BPIALL
	Offset: 0x278 ( /W) Branch Predictor Invalidate All.
uint32_t	SCnSCB_Type::RESERVED0 [1U]
__IM uint32_t	SCnSCB_Type::ICTR
	Offset: 0x004 (R/ ) Interrupt Controller Type Register.
__IOM uint32_t	SCnSCB_Type::ACTLR
	Offset: 0x008 (R/W) Auxiliary Control Register.
__IOM uint32_t	SCnSCB_Type::CPPWR
	Offset: 0x00C (R/W) Coprocessor Power Control Register.
__IOM uint32_t	SysTick_Type::CTRL
	Offset: 0x000 (R/W) SysTick Control and Status Register.
__IOM uint32_t	SysTick_Type::LOAD
	Offset: 0x004 (R/W) SysTick Reload Value Register.
__IOM uint32_t	SysTick_Type::VAL
	Offset: 0x008 (R/W) SysTick Current Value Register.
__IM uint32_t	SysTick_Type::CALIB
	Offset: 0x00C (R/ ) SysTick Calibration Register.
__OM uint8_t ITM_Type::u8
	Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More...
__OM uint16_t ITM_Type::u16
	Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More...
__OM uint32_t ITM_Type::u32
	Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More...
union {
__OM uint8_t ITM_Type::u8
	Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More...
__OM uint16_t ITM_Type::u16
	Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More...
__OM uint32_t ITM_Type::u32
	Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More...
}	ITM_Type::PORT [32U]
	Offset: 0x000 ( /W) ITM Stimulus Port Registers.
uint32_t	ITM_Type::RESERVED0 [864U]
__IOM uint32_t	ITM_Type::TER
	Offset: 0xE00 (R/W) ITM Trace Enable Register.
uint32_t	ITM_Type::RESERVED1 [15U]
__IOM uint32_t	ITM_Type::TPR
	Offset: 0xE40 (R/W) ITM Trace Privilege Register.
uint32_t	ITM_Type::RESERVED2 [15U]
__IOM uint32_t	ITM_Type::TCR
	Offset: 0xE80 (R/W) ITM Trace Control Register.
uint32_t	ITM_Type::RESERVED3 [32U]
uint32_t	ITM_Type::RESERVED4 [43U]
__OM uint32_t	ITM_Type::LAR
	Offset: 0xFB0 ( /W) ITM Lock Access Register.
__IM uint32_t	ITM_Type::LSR
	Offset: 0xFB4 (R/ ) ITM Lock Status Register.
uint32_t	ITM_Type::RESERVED5 [1U]
__IM uint32_t	ITM_Type::DEVARCH
	Offset: 0xFBC (R/ ) ITM Device Architecture Register.
uint32_t	ITM_Type::RESERVED6 [3U]
__IM uint32_t	ITM_Type::DEVTYPE
	Offset: 0xFCC (R/ ) ITM Device Type Register.
__IM uint32_t	ITM_Type::PID4
	Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4.
__IM uint32_t	ITM_Type::PID5
	Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5.
__IM uint32_t	ITM_Type::PID6
	Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6.
__IM uint32_t	ITM_Type::PID7
	Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7.
__IM uint32_t	ITM_Type::PID0
	Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0.
__IM uint32_t	ITM_Type::PID1
	Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1.
__IM uint32_t	ITM_Type::PID2
	Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2.
__IM uint32_t	ITM_Type::PID3
	Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3.
__IM uint32_t	ITM_Type::CID0
	Offset: 0xFF0 (R/ ) ITM Component Identification Register #0.
__IM uint32_t	ITM_Type::CID1
	Offset: 0xFF4 (R/ ) ITM Component Identification Register #1.
__IM uint32_t	ITM_Type::CID2
	Offset: 0xFF8 (R/ ) ITM Component Identification Register #2.
__IM uint32_t	ITM_Type::CID3
	Offset: 0xFFC (R/ ) ITM Component Identification Register #3.
__IOM uint32_t	DWT_Type::CTRL
	Offset: 0x000 (R/W) Control Register.
__IOM uint32_t	DWT_Type::CYCCNT
	Offset: 0x004 (R/W) Cycle Count Register.
__IOM uint32_t	DWT_Type::CPICNT
	Offset: 0x008 (R/W) CPI Count Register.
__IOM uint32_t	DWT_Type::EXCCNT
	Offset: 0x00C (R/W) Exception Overhead Count Register.
__IOM uint32_t	DWT_Type::SLEEPCNT
	Offset: 0x010 (R/W) Sleep Count Register.
__IOM uint32_t	DWT_Type::LSUCNT
	Offset: 0x014 (R/W) LSU Count Register.
__IOM uint32_t	DWT_Type::FOLDCNT
	Offset: 0x018 (R/W) Folded-instruction Count Register.
__IM uint32_t	DWT_Type::PCSR
	Offset: 0x01C (R/ ) Program Counter Sample Register.
__IOM uint32_t	DWT_Type::COMP0
	Offset: 0x020 (R/W) Comparator Register 0.
uint32_t	DWT_Type::RESERVED1 [1U]
__IOM uint32_t	DWT_Type::FUNCTION0
	Offset: 0x028 (R/W) Function Register 0.
uint32_t	DWT_Type::RESERVED2 [1U]
__IOM uint32_t	DWT_Type::COMP1
	Offset: 0x030 (R/W) Comparator Register 1.
uint32_t	DWT_Type::RESERVED3 [1U]
__IOM uint32_t	DWT_Type::FUNCTION1
	Offset: 0x038 (R/W) Function Register 1.
uint32_t	DWT_Type::RESERVED4 [1U]
__IOM uint32_t	DWT_Type::COMP2
	Offset: 0x040 (R/W) Comparator Register 2.
uint32_t	DWT_Type::RESERVED5 [1U]
__IOM uint32_t	DWT_Type::FUNCTION2
	Offset: 0x048 (R/W) Function Register 2.
uint32_t	DWT_Type::RESERVED6 [1U]
__IOM uint32_t	DWT_Type::COMP3
	Offset: 0x050 (R/W) Comparator Register 3.
uint32_t	DWT_Type::RESERVED7 [1U]
__IOM uint32_t	DWT_Type::FUNCTION3
	Offset: 0x058 (R/W) Function Register 3.
uint32_t	DWT_Type::RESERVED8 [1U]
__IOM uint32_t	DWT_Type::COMP4
	Offset: 0x060 (R/W) Comparator Register 4.
uint32_t	DWT_Type::RESERVED9 [1U]
__IOM uint32_t	DWT_Type::FUNCTION4
	Offset: 0x068 (R/W) Function Register 4.
uint32_t	DWT_Type::RESERVED10 [1U]
__IOM uint32_t	DWT_Type::COMP5
	Offset: 0x070 (R/W) Comparator Register 5.
uint32_t	DWT_Type::RESERVED11 [1U]
__IOM uint32_t	DWT_Type::FUNCTION5
	Offset: 0x078 (R/W) Function Register 5.
uint32_t	DWT_Type::RESERVED12 [1U]
__IOM uint32_t	DWT_Type::COMP6
	Offset: 0x080 (R/W) Comparator Register 6.
uint32_t	DWT_Type::RESERVED13 [1U]
__IOM uint32_t	DWT_Type::FUNCTION6
	Offset: 0x088 (R/W) Function Register 6.
uint32_t	DWT_Type::RESERVED14 [1U]
__IOM uint32_t	DWT_Type::COMP7
	Offset: 0x090 (R/W) Comparator Register 7.
uint32_t	DWT_Type::RESERVED15 [1U]
__IOM uint32_t	DWT_Type::FUNCTION7
	Offset: 0x098 (R/W) Function Register 7.
uint32_t	DWT_Type::RESERVED16 [1U]
__IOM uint32_t	DWT_Type::COMP8
	Offset: 0x0A0 (R/W) Comparator Register 8.
uint32_t	DWT_Type::RESERVED17 [1U]
__IOM uint32_t	DWT_Type::FUNCTION8
	Offset: 0x0A8 (R/W) Function Register 8.
uint32_t	DWT_Type::RESERVED18 [1U]
__IOM uint32_t	DWT_Type::COMP9
	Offset: 0x0B0 (R/W) Comparator Register 9.
uint32_t	DWT_Type::RESERVED19 [1U]
__IOM uint32_t	DWT_Type::FUNCTION9
	Offset: 0x0B8 (R/W) Function Register 9.
uint32_t	DWT_Type::RESERVED20 [1U]
__IOM uint32_t	DWT_Type::COMP10
	Offset: 0x0C0 (R/W) Comparator Register 10.
uint32_t	DWT_Type::RESERVED21 [1U]
__IOM uint32_t	DWT_Type::FUNCTION10
	Offset: 0x0C8 (R/W) Function Register 10.
uint32_t	DWT_Type::RESERVED22 [1U]
__IOM uint32_t	DWT_Type::COMP11
	Offset: 0x0D0 (R/W) Comparator Register 11.
uint32_t	DWT_Type::RESERVED23 [1U]
__IOM uint32_t	DWT_Type::FUNCTION11
	Offset: 0x0D8 (R/W) Function Register 11.
uint32_t	DWT_Type::RESERVED24 [1U]
__IOM uint32_t	DWT_Type::COMP12
	Offset: 0x0E0 (R/W) Comparator Register 12.
uint32_t	DWT_Type::RESERVED25 [1U]
__IOM uint32_t	DWT_Type::FUNCTION12
	Offset: 0x0E8 (R/W) Function Register 12.
uint32_t	DWT_Type::RESERVED26 [1U]
__IOM uint32_t	DWT_Type::COMP13
	Offset: 0x0F0 (R/W) Comparator Register 13.
uint32_t	DWT_Type::RESERVED27 [1U]
__IOM uint32_t	DWT_Type::FUNCTION13
	Offset: 0x0F8 (R/W) Function Register 13.
uint32_t	DWT_Type::RESERVED28 [1U]
__IOM uint32_t	DWT_Type::COMP14
	Offset: 0x100 (R/W) Comparator Register 14.
uint32_t	DWT_Type::RESERVED29 [1U]
__IOM uint32_t	DWT_Type::FUNCTION14
	Offset: 0x108 (R/W) Function Register 14.
uint32_t	DWT_Type::RESERVED30 [1U]
__IOM uint32_t	DWT_Type::COMP15
	Offset: 0x110 (R/W) Comparator Register 15.
uint32_t	DWT_Type::RESERVED31 [1U]
__IOM uint32_t	DWT_Type::FUNCTION15
	Offset: 0x118 (R/W) Function Register 15.
uint32_t	DWT_Type::RESERVED32 [934U]
__IM uint32_t	DWT_Type::LSR
	Offset: 0xFB4 (R ) Lock Status Register.
uint32_t	DWT_Type::RESERVED33 [1U]
__IM uint32_t	DWT_Type::DEVARCH
	Offset: 0xFBC (R/ ) Device Architecture Register.
__IM uint32_t	TPI_Type::SSPSR
	Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register.
__IOM uint32_t	TPI_Type::CSPSR
	Offset: 0x004 (R/W) Current Parallel Port Sizes Register.
uint32_t	TPI_Type::RESERVED0 [2U]
__IOM uint32_t	TPI_Type::ACPR
	Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register.
uint32_t	TPI_Type::RESERVED1 [55U]
__IOM uint32_t	TPI_Type::SPPR
	Offset: 0x0F0 (R/W) Selected Pin Protocol Register.
uint32_t	TPI_Type::RESERVED2 [131U]
__IM uint32_t	TPI_Type::FFSR
	Offset: 0x300 (R/ ) Formatter and Flush Status Register.
__IOM uint32_t	TPI_Type::FFCR
	Offset: 0x304 (R/W) Formatter and Flush Control Register.
__IOM uint32_t	TPI_Type::PSCR
	Offset: 0x308 (R/W) Periodic Synchronization Control Register.
uint32_t	TPI_Type::RESERVED3 [809U]
__OM uint32_t	TPI_Type::LAR
	Offset: 0xFB0 ( /W) Software Lock Access Register.
__IM uint32_t	TPI_Type::LSR
	Offset: 0xFB4 (R/ ) Software Lock Status Register.
uint32_t	TPI_Type::RESERVED4 [4U]
__IM uint32_t	TPI_Type::TYPE
	Offset: 0xFC8 (R/ ) Device Identifier Register.
__IM uint32_t	TPI_Type::DEVTYPE
	Offset: 0xFCC (R/ ) Device Type Register.
__IM uint32_t	MPU_Type::TYPE
	Offset: 0x000 (R/ ) MPU Type Register.
__IOM uint32_t	MPU_Type::CTRL
	Offset: 0x004 (R/W) MPU Control Register.
__IOM uint32_t	MPU_Type::RNR
	Offset: 0x008 (R/W) MPU Region Number Register.
__IOM uint32_t	MPU_Type::RBAR
	Offset: 0x00C (R/W) MPU Region Base Address Register.
__IOM uint32_t	MPU_Type::RLAR
	Offset: 0x010 (R/W) MPU Region Limit Address Register.
__IOM uint32_t	MPU_Type::RBAR_A1
	Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1.
__IOM uint32_t	MPU_Type::RLAR_A1
	Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1.
__IOM uint32_t	MPU_Type::RBAR_A2
	Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2.
__IOM uint32_t	MPU_Type::RLAR_A2
	Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2.
__IOM uint32_t	MPU_Type::RBAR_A3
	Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3.
__IOM uint32_t	MPU_Type::RLAR_A3
	Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3.
uint32_t	MPU_Type::RESERVED0 [1]
__IOM uint32_t MPU_Type::MAIR [2]
__IOM uint32_t MPU_Type::MAIR0
	Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
__IOM uint32_t MPU_Type::MAIR1
	Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
struct {
__IOM uint32_t MPU_Type::MAIR0
	Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
__IOM uint32_t MPU_Type::MAIR1
	Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
}
union {
__IOM uint32_t MPU_Type::MAIR [2]
struct {
__IOM uint32_t MPU_Type::MAIR0
	Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
__IOM uint32_t MPU_Type::MAIR1
	Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
}
};
uint32_t	FPU_Type::RESERVED0 [1U]
__IOM uint32_t	FPU_Type::FPCCR
	Offset: 0x004 (R/W) Floating-Point Context Control Register.
__IOM uint32_t	FPU_Type::FPCAR
	Offset: 0x008 (R/W) Floating-Point Context Address Register.
__IOM uint32_t	FPU_Type::FPDSCR
	Offset: 0x00C (R/W) Floating-Point Default Status Control Register.
__IM uint32_t	FPU_Type::MVFR0
	Offset: 0x010 (R/ ) Media and VFP Feature Register 0.
__IM uint32_t	FPU_Type::MVFR1
	Offset: 0x014 (R/ ) Media and VFP Feature Register 1.
__IM uint32_t	FPU_Type::MVFR2
	Offset: 0x018 (R/ ) Media and VFP Feature Register 2.
__IOM uint32_t	CoreDebug_Type::DHCSR
	Offset: 0x000 (R/W) Debug Halting Control and Status Register.
__OM uint32_t	CoreDebug_Type::DCRSR
	Offset: 0x004 ( /W) Debug Core Register Selector Register.
__IOM uint32_t	CoreDebug_Type::DCRDR
	Offset: 0x008 (R/W) Debug Core Register Data Register.
__IOM uint32_t	CoreDebug_Type::DEMCR
	Offset: 0x00C (R/W) Debug Exception and Monitor Control Register.
__OM uint32_t	CoreDebug_Type::DSCEMCR
	Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register.
__IOM uint32_t	CoreDebug_Type::DAUTHCTRL
	Offset: 0x014 (R/W) Debug Authentication Control Register.
__IOM uint32_t	CoreDebug_Type::DSCSR
	Offset: 0x018 (R/W) Debug Security Control and Status Register.
__IOM uint32_t	DCB_Type::DHCSR
	Offset: 0x000 (R/W) Debug Halting Control and Status Register.
__OM uint32_t	DCB_Type::DCRSR
	Offset: 0x004 ( /W) Debug Core Register Selector Register.
__IOM uint32_t	DCB_Type::DCRDR
	Offset: 0x008 (R/W) Debug Core Register Data Register.
__IOM uint32_t	DCB_Type::DEMCR
	Offset: 0x00C (R/W) Debug Exception and Monitor Control Register.
__OM uint32_t	DCB_Type::DSCEMCR
	Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register.
__IOM uint32_t	DCB_Type::DAUTHCTRL
	Offset: 0x014 (R/W) Debug Authentication Control Register.
__IOM uint32_t	DCB_Type::DSCSR
	Offset: 0x018 (R/W) Debug Security Control and Status Register.
__OM uint32_t	DIB_Type::DLAR
	Offset: 0x000 ( /W) SCS Software Lock Access Register.
__IM uint32_t	DIB_Type::DLSR
	Offset: 0x004 (R/ ) SCS Software Lock Status Register.
__IM uint32_t	DIB_Type::DAUTHSTATUS
	Offset: 0x008 (R/ ) Debug Authentication Status Register.
__IM uint32_t	DIB_Type::DDEVARCH
	Offset: 0x00C (R/ ) SCS Device Architecture Register.
__IM uint32_t	DIB_Type::DDEVTYPE
	Offset: 0x010 (R/ ) SCS Device Type Register.
uint32_t APSR_Type::_reserved0:16
	bit: 0..15 Reserved More...
uint32_t APSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t APSR_Type::_reserved1:7
	bit: 20..26 Reserved More...
uint32_t APSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t APSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t APSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t APSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t APSR_Type::N:1
	bit: 31 Negative condition code flag More...
struct {
uint32_t APSR_Type::_reserved0:16
	bit: 0..15 Reserved More...
uint32_t APSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t APSR_Type::_reserved1:7
	bit: 20..26 Reserved More...
uint32_t APSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t APSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t APSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t APSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t APSR_Type::N:1
	bit: 31 Negative condition code flag More...
}	APSR_Type::b
	Structure used for bit access.
uint32_t IPSR_Type::ISR:9
	bit: 0. More...
uint32_t IPSR_Type::_reserved0:23
	bit: 9..31 Reserved More...
struct {
uint32_t IPSR_Type::ISR:9
	bit: 0. More...
uint32_t IPSR_Type::_reserved0:23
	bit: 9..31 Reserved More...
}	IPSR_Type::b
	Structure used for bit access.
uint32_t xPSR_Type::ISR:9
	bit: 0. More...
uint32_t xPSR_Type::_reserved0:7
	bit: 9..15 Reserved More...
uint32_t xPSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t xPSR_Type::_reserved1:4
	bit: 20..23 Reserved More...
uint32_t xPSR_Type::T:1
	bit: 24 Thumb bit (read 0) More...
uint32_t xPSR_Type::IT:2
	bit: 25..26 saved IT state (read 0) More...
uint32_t xPSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t xPSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t xPSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t xPSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t xPSR_Type::N:1
	bit: 31 Negative condition code flag More...
struct {
uint32_t xPSR_Type::ISR:9
	bit: 0. More...
uint32_t xPSR_Type::_reserved0:7
	bit: 9..15 Reserved More...
uint32_t xPSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t xPSR_Type::_reserved1:4
	bit: 20..23 Reserved More...
uint32_t xPSR_Type::T:1
	bit: 24 Thumb bit (read 0) More...
uint32_t xPSR_Type::IT:2
	bit: 25..26 saved IT state (read 0) More...
uint32_t xPSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t xPSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t xPSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t xPSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t xPSR_Type::N:1
	bit: 31 Negative condition code flag More...
}	xPSR_Type::b
	Structure used for bit access.
uint32_t CONTROL_Type::nPRIV:1
	bit: 0 Execution privilege in Thread mode More...
uint32_t CONTROL_Type::SPSEL:1
	bit: 1 Stack-pointer select More...
uint32_t CONTROL_Type::FPCA:1
	bit: 2 Floating-point context active More...
uint32_t CONTROL_Type::SFPA:1
	bit: 3 Secure floating-point active More...
uint32_t CONTROL_Type::_reserved1:28
	bit: 4..31 Reserved More...
struct {
uint32_t CONTROL_Type::nPRIV:1
	bit: 0 Execution privilege in Thread mode More...
uint32_t CONTROL_Type::SPSEL:1
	bit: 1 Stack-pointer select More...
uint32_t CONTROL_Type::FPCA:1
	bit: 2 Floating-point context active More...
uint32_t CONTROL_Type::SFPA:1
	bit: 3 Secure floating-point active More...
uint32_t CONTROL_Type::_reserved1:28
	bit: 4..31 Reserved More...
}	CONTROL_Type::b
	Structure used for bit access.
__OM uint8_t ITM_Type::u8
	Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More...
__OM uint16_t ITM_Type::u16
	Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More...
__OM uint32_t ITM_Type::u32
	Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More...
union {
__OM uint8_t ITM_Type::u8
	Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More...
__OM uint16_t ITM_Type::u16
	Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More...
__OM uint32_t ITM_Type::u32
	Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More...
}	ITM_Type::PORT [32U]
	Offset: 0x000 ( /W) ITM Stimulus Port Registers.
__IOM uint32_t MPU_Type::MAIR [2]
__IOM uint32_t MPU_Type::MAIR0
	Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
__IOM uint32_t MPU_Type::MAIR1
	Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
struct {
__IOM uint32_t MPU_Type::MAIR0
	Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
__IOM uint32_t MPU_Type::MAIR1
	Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
}
union {
__IOM uint32_t MPU_Type::MAIR [2]
struct {
__IOM uint32_t MPU_Type::MAIR0
	Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
__IOM uint32_t MPU_Type::MAIR1
	Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
}
};
uint32_t APSR_Type::_reserved0:27
	bit: 0..26 Reserved More...
uint32_t APSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t APSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t APSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t APSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t APSR_Type::N:1
	bit: 31 Negative condition code flag More...
struct {
uint32_t APSR_Type::_reserved0:27
	bit: 0..26 Reserved More...
uint32_t APSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t APSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t APSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t APSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t APSR_Type::N:1
	bit: 31 Negative condition code flag More...
}	APSR_Type::b
	Structure used for bit access.
uint32_t IPSR_Type::ISR:9
	bit: 0. More...
uint32_t IPSR_Type::_reserved0:23
	bit: 9..31 Reserved More...
struct {
uint32_t IPSR_Type::ISR:9
	bit: 0. More...
uint32_t IPSR_Type::_reserved0:23
	bit: 9..31 Reserved More...
}	IPSR_Type::b
	Structure used for bit access.
uint32_t xPSR_Type::ISR:9
	bit: 0. More...
uint32_t xPSR_Type::_reserved0:1
	bit: 9 Reserved More...
uint32_t xPSR_Type::ICI_IT_1:6
	bit: 10..15 ICI/IT part 1 More...
uint32_t xPSR_Type::_reserved1:8
	bit: 16..23 Reserved More...
uint32_t xPSR_Type::T:1
	bit: 24 Thumb bit More...
uint32_t xPSR_Type::ICI_IT_2:2
	bit: 25..26 ICI/IT part 2 More...
uint32_t xPSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t xPSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t xPSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t xPSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t xPSR_Type::N:1
	bit: 31 Negative condition code flag More...
struct {
uint32_t xPSR_Type::ISR:9
	bit: 0. More...
uint32_t xPSR_Type::_reserved0:1
	bit: 9 Reserved More...
uint32_t xPSR_Type::ICI_IT_1:6
	bit: 10..15 ICI/IT part 1 More...
uint32_t xPSR_Type::_reserved1:8
	bit: 16..23 Reserved More...
uint32_t xPSR_Type::T:1
	bit: 24 Thumb bit More...
uint32_t xPSR_Type::ICI_IT_2:2
	bit: 25..26 ICI/IT part 2 More...
uint32_t xPSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t xPSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t xPSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t xPSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t xPSR_Type::N:1
	bit: 31 Negative condition code flag More...
}	xPSR_Type::b
	Structure used for bit access.
uint32_t CONTROL_Type::nPRIV:1
	bit: 0 Execution privilege in Thread mode More...
uint32_t CONTROL_Type::SPSEL:1
	bit: 1 Stack to be used More...
uint32_t CONTROL_Type::_reserved1:30
	bit: 2..31 Reserved More...
struct {
uint32_t CONTROL_Type::nPRIV:1
	bit: 0 Execution privilege in Thread mode More...
uint32_t CONTROL_Type::SPSEL:1
	bit: 1 Stack to be used More...
uint32_t CONTROL_Type::_reserved1:30
	bit: 2..31 Reserved More...
}	CONTROL_Type::b
	Structure used for bit access.
__IOM uint8_t	NVIC_Type::IP [240U]
	Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide).
__IOM uint8_t	SCB_Type::SHP [12U]
	Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15).
__IM uint32_t	SCB_Type::PFR [2U]
	Offset: 0x040 (R/ ) Processor Feature Register.
__IM uint32_t	SCB_Type::DFR
	Offset: 0x048 (R/ ) Debug Feature Register.
__IM uint32_t	SCB_Type::ADR
	Offset: 0x04C (R/ ) Auxiliary Feature Register.
__IM uint32_t	SCB_Type::MMFR [4U]
	Offset: 0x050 (R/ ) Memory Model Feature Register.
__IM uint32_t	SCB_Type::ISAR [5U]
	Offset: 0x060 (R/ ) Instruction Set Attributes Register.
uint32_t	SCnSCB_Type::RESERVED1 [1U]
__OM uint8_t ITM_Type::u8
	Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More...
__OM uint16_t ITM_Type::u16
	Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More...
__OM uint32_t ITM_Type::u32
	Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More...
union {
__OM uint8_t ITM_Type::u8
	Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More...
__OM uint16_t ITM_Type::u16
	Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More...
__OM uint32_t ITM_Type::u32
	Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More...
}	ITM_Type::PORT [32U]
	Offset: 0x000 ( /W) ITM Stimulus Port Registers.
__IOM uint32_t	DWT_Type::MASK0
	Offset: 0x024 (R/W) Mask Register 0.
__IOM uint32_t	DWT_Type::MASK1
	Offset: 0x034 (R/W) Mask Register 1.
__IOM uint32_t	DWT_Type::MASK2
	Offset: 0x044 (R/W) Mask Register 2.
__IOM uint32_t	DWT_Type::MASK3
	Offset: 0x054 (R/W) Mask Register 3.
__IM uint32_t	TPI_Type::FSCR
	Offset: 0x308 (R/ ) Formatter Synchronization Counter Register.
__IM uint32_t	TPI_Type::FIFO0
	Offset: 0xEEC (R/ ) Integration ETM Data.
__IM uint32_t	TPI_Type::ITATBCTR2
	Offset: 0xEF0 (R/ ) ITATBCTR2.
__IM uint32_t	TPI_Type::FIFO1
	Offset: 0xEFC (R/ ) Integration ITM Data.
__IOM uint32_t	MPU_Type::RASR_A1
	Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register.
__IOM uint32_t	MPU_Type::RASR_A2
	Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register.
__IOM uint32_t	MPU_Type::RASR_A3
	Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register.
uint32_t APSR_Type::_reserved0:16
	bit: 0..15 Reserved More...
uint32_t APSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t APSR_Type::_reserved1:7
	bit: 20..26 Reserved More...
uint32_t APSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t APSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t APSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t APSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t APSR_Type::N:1
	bit: 31 Negative condition code flag More...
struct {
uint32_t APSR_Type::_reserved0:16
	bit: 0..15 Reserved More...
uint32_t APSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t APSR_Type::_reserved1:7
	bit: 20..26 Reserved More...
uint32_t APSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t APSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t APSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t APSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t APSR_Type::N:1
	bit: 31 Negative condition code flag More...
}	APSR_Type::b
	Structure used for bit access.
uint32_t IPSR_Type::ISR:9
	bit: 0. More...
uint32_t IPSR_Type::_reserved0:23
	bit: 9..31 Reserved More...
struct {
uint32_t IPSR_Type::ISR:9
	bit: 0. More...
uint32_t IPSR_Type::_reserved0:23
	bit: 9..31 Reserved More...
}	IPSR_Type::b
	Structure used for bit access.
uint32_t xPSR_Type::ISR:9
	bit: 0. More...
uint32_t xPSR_Type::_reserved0:7
	bit: 9..15 Reserved More...
uint32_t xPSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t xPSR_Type::_reserved1:4
	bit: 20..23 Reserved More...
uint32_t xPSR_Type::T:1
	bit: 24 Thumb bit (read 0) More...
uint32_t xPSR_Type::IT:2
	bit: 25..26 saved IT state (read 0) More...
uint32_t xPSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t xPSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t xPSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t xPSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t xPSR_Type::N:1
	bit: 31 Negative condition code flag More...
struct {
uint32_t xPSR_Type::ISR:9
	bit: 0. More...
uint32_t xPSR_Type::_reserved0:7
	bit: 9..15 Reserved More...
uint32_t xPSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t xPSR_Type::_reserved1:4
	bit: 20..23 Reserved More...
uint32_t xPSR_Type::T:1
	bit: 24 Thumb bit (read 0) More...
uint32_t xPSR_Type::IT:2
	bit: 25..26 saved IT state (read 0) More...
uint32_t xPSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t xPSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t xPSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t xPSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t xPSR_Type::N:1
	bit: 31 Negative condition code flag More...
}	xPSR_Type::b
	Structure used for bit access.
uint32_t CONTROL_Type::nPRIV:1
	bit: 0 Execution privilege in Thread mode More...
uint32_t CONTROL_Type::SPSEL:1
	bit: 1 Stack-pointer select More...
uint32_t CONTROL_Type::FPCA:1
	bit: 2 Floating-point context active More...
uint32_t CONTROL_Type::SFPA:1
	bit: 3 Secure floating-point active More...
uint32_t CONTROL_Type::_reserved1:28
	bit: 4..31 Reserved More...
struct {
uint32_t CONTROL_Type::nPRIV:1
	bit: 0 Execution privilege in Thread mode More...
uint32_t CONTROL_Type::SPSEL:1
	bit: 1 Stack-pointer select More...
uint32_t CONTROL_Type::FPCA:1
	bit: 2 Floating-point context active More...
uint32_t CONTROL_Type::SFPA:1
	bit: 3 Secure floating-point active More...
uint32_t CONTROL_Type::_reserved1:28
	bit: 4..31 Reserved More...
}	CONTROL_Type::b
	Structure used for bit access.
__OM uint8_t ITM_Type::u8
	Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More...
__OM uint16_t ITM_Type::u16
	Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More...
__OM uint32_t ITM_Type::u32
	Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More...
union {
__OM uint8_t ITM_Type::u8
	Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More...
__OM uint16_t ITM_Type::u16
	Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More...
__OM uint32_t ITM_Type::u32
	Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More...
}	ITM_Type::PORT [32U]
	Offset: 0x000 ( /W) ITM Stimulus Port Registers.
__IOM uint32_t MPU_Type::MAIR [2]
__IOM uint32_t MPU_Type::MAIR0
	Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
__IOM uint32_t MPU_Type::MAIR1
	Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
struct {
__IOM uint32_t MPU_Type::MAIR0
	Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
__IOM uint32_t MPU_Type::MAIR1
	Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
}
union {
__IOM uint32_t MPU_Type::MAIR [2]
struct {
__IOM uint32_t MPU_Type::MAIR0
	Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
__IOM uint32_t MPU_Type::MAIR1
	Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
}
};
uint32_t APSR_Type::_reserved0:16
	bit: 0..15 Reserved More...
uint32_t APSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t APSR_Type::_reserved1:7
	bit: 20..26 Reserved More...
uint32_t APSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t APSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t APSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t APSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t APSR_Type::N:1
	bit: 31 Negative condition code flag More...
struct {
uint32_t APSR_Type::_reserved0:16
	bit: 0..15 Reserved More...
uint32_t APSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t APSR_Type::_reserved1:7
	bit: 20..26 Reserved More...
uint32_t APSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t APSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t APSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t APSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t APSR_Type::N:1
	bit: 31 Negative condition code flag More...
}	APSR_Type::b
	Structure used for bit access.
uint32_t IPSR_Type::ISR:9
	bit: 0. More...
uint32_t IPSR_Type::_reserved0:23
	bit: 9..31 Reserved More...
struct {
uint32_t IPSR_Type::ISR:9
	bit: 0. More...
uint32_t IPSR_Type::_reserved0:23
	bit: 9..31 Reserved More...
}	IPSR_Type::b
	Structure used for bit access.
uint32_t xPSR_Type::ISR:9
	bit: 0. More...
uint32_t xPSR_Type::_reserved0:7
	bit: 9..15 Reserved More...
uint32_t xPSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t xPSR_Type::_reserved1:4
	bit: 20..23 Reserved More...
uint32_t xPSR_Type::T:1
	bit: 24 Thumb bit (read 0) More...
uint32_t xPSR_Type::IT:2
	bit: 25..26 saved IT state (read 0) More...
uint32_t xPSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t xPSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t xPSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t xPSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t xPSR_Type::N:1
	bit: 31 Negative condition code flag More...
struct {
uint32_t xPSR_Type::ISR:9
	bit: 0. More...
uint32_t xPSR_Type::_reserved0:7
	bit: 9..15 Reserved More...
uint32_t xPSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t xPSR_Type::_reserved1:4
	bit: 20..23 Reserved More...
uint32_t xPSR_Type::T:1
	bit: 24 Thumb bit (read 0) More...
uint32_t xPSR_Type::IT:2
	bit: 25..26 saved IT state (read 0) More...
uint32_t xPSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t xPSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t xPSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t xPSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t xPSR_Type::N:1
	bit: 31 Negative condition code flag More...
}	xPSR_Type::b
	Structure used for bit access.
uint32_t CONTROL_Type::nPRIV:1
	bit: 0 Execution privilege in Thread mode More...
uint32_t CONTROL_Type::SPSEL:1
	bit: 1 Stack-pointer select More...
uint32_t CONTROL_Type::FPCA:1
	bit: 2 Floating-point context active More...
uint32_t CONTROL_Type::SFPA:1
	bit: 3 Secure floating-point active More...
uint32_t CONTROL_Type::_reserved1:28
	bit: 4..31 Reserved More...
struct {
uint32_t CONTROL_Type::nPRIV:1
	bit: 0 Execution privilege in Thread mode More...
uint32_t CONTROL_Type::SPSEL:1
	bit: 1 Stack-pointer select More...
uint32_t CONTROL_Type::FPCA:1
	bit: 2 Floating-point context active More...
uint32_t CONTROL_Type::SFPA:1
	bit: 3 Secure floating-point active More...
uint32_t CONTROL_Type::_reserved1:28
	bit: 4..31 Reserved More...
}	CONTROL_Type::b
	Structure used for bit access.
__OM uint8_t ITM_Type::u8
	Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More...
__OM uint16_t ITM_Type::u16
	Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More...
__OM uint32_t ITM_Type::u32
	Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More...
union {
__OM uint8_t ITM_Type::u8
	Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More...
__OM uint16_t ITM_Type::u16
	Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More...
__OM uint32_t ITM_Type::u32
	Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More...
}	ITM_Type::PORT [32U]
	Offset: 0x000 ( /W) ITM Stimulus Port Registers.
__IOM uint32_t MPU_Type::MAIR [2]
__IOM uint32_t MPU_Type::MAIR0
	Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
__IOM uint32_t MPU_Type::MAIR1
	Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
struct {
__IOM uint32_t MPU_Type::MAIR0
	Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
__IOM uint32_t MPU_Type::MAIR1
	Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
}
union {
__IOM uint32_t MPU_Type::MAIR [2]
struct {
__IOM uint32_t MPU_Type::MAIR0
	Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
__IOM uint32_t MPU_Type::MAIR1
	Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
}
};
uint32_t APSR_Type::_reserved0:16
	bit: 0..15 Reserved More...
uint32_t APSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t APSR_Type::_reserved1:7
	bit: 20..26 Reserved More...
uint32_t APSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t APSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t APSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t APSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t APSR_Type::N:1
	bit: 31 Negative condition code flag More...
struct {
uint32_t APSR_Type::_reserved0:16
	bit: 0..15 Reserved More...
uint32_t APSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t APSR_Type::_reserved1:7
	bit: 20..26 Reserved More...
uint32_t APSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t APSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t APSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t APSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t APSR_Type::N:1
	bit: 31 Negative condition code flag More...
}	APSR_Type::b
	Structure used for bit access.
uint32_t IPSR_Type::ISR:9
	bit: 0. More...
uint32_t IPSR_Type::_reserved0:23
	bit: 9..31 Reserved More...
struct {
uint32_t IPSR_Type::ISR:9
	bit: 0. More...
uint32_t IPSR_Type::_reserved0:23
	bit: 9..31 Reserved More...
}	IPSR_Type::b
	Structure used for bit access.
uint32_t xPSR_Type::ISR:9
	bit: 0. More...
uint32_t xPSR_Type::_reserved0:1
	bit: 9 Reserved More...
uint32_t xPSR_Type::ICI_IT_1:6
	bit: 10..15 ICI/IT part 1 More...
uint32_t xPSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t xPSR_Type::_reserved1:4
	bit: 20..23 Reserved More...
uint32_t xPSR_Type::T:1
	bit: 24 Thumb bit More...
uint32_t xPSR_Type::ICI_IT_2:2
	bit: 25..26 ICI/IT part 2 More...
uint32_t xPSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t xPSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t xPSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t xPSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t xPSR_Type::N:1
	bit: 31 Negative condition code flag More...
struct {
uint32_t xPSR_Type::ISR:9
	bit: 0. More...
uint32_t xPSR_Type::_reserved0:1
	bit: 9 Reserved More...
uint32_t xPSR_Type::ICI_IT_1:6
	bit: 10..15 ICI/IT part 1 More...
uint32_t xPSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t xPSR_Type::_reserved1:4
	bit: 20..23 Reserved More...
uint32_t xPSR_Type::T:1
	bit: 24 Thumb bit More...
uint32_t xPSR_Type::ICI_IT_2:2
	bit: 25..26 ICI/IT part 2 More...
uint32_t xPSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t xPSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t xPSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t xPSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t xPSR_Type::N:1
	bit: 31 Negative condition code flag More...
}	xPSR_Type::b
	Structure used for bit access.
uint32_t CONTROL_Type::nPRIV:1
	bit: 0 Execution privilege in Thread mode More...
uint32_t CONTROL_Type::SPSEL:1
	bit: 1 Stack to be used More...
uint32_t CONTROL_Type::FPCA:1
	bit: 2 FP extension active flag More...
uint32_t CONTROL_Type::_reserved0:29
	bit: 3..31 Reserved More...
struct {
uint32_t CONTROL_Type::nPRIV:1
	bit: 0 Execution privilege in Thread mode More...
uint32_t CONTROL_Type::SPSEL:1
	bit: 1 Stack to be used More...
uint32_t CONTROL_Type::FPCA:1
	bit: 2 FP extension active flag More...
uint32_t CONTROL_Type::_reserved0:29
	bit: 3..31 Reserved More...
}	CONTROL_Type::b
	Structure used for bit access.
__OM uint8_t ITM_Type::u8
	Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More...
__OM uint16_t ITM_Type::u16
	Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More...
__OM uint32_t ITM_Type::u32
	Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More...
union {
__OM uint8_t ITM_Type::u8
	Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More...
__OM uint16_t ITM_Type::u16
	Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More...
__OM uint32_t ITM_Type::u32
	Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More...
}	ITM_Type::PORT [32U]
	Offset: 0x000 ( /W) ITM Stimulus Port Registers.
uint32_t APSR_Type::_reserved0:16
	bit: 0..15 Reserved More...
uint32_t APSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t APSR_Type::_reserved1:7
	bit: 20..26 Reserved More...
uint32_t APSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t APSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t APSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t APSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t APSR_Type::N:1
	bit: 31 Negative condition code flag More...
struct {
uint32_t APSR_Type::_reserved0:16
	bit: 0..15 Reserved More...
uint32_t APSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t APSR_Type::_reserved1:7
	bit: 20..26 Reserved More...
uint32_t APSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t APSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t APSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t APSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t APSR_Type::N:1
	bit: 31 Negative condition code flag More...
}	APSR_Type::b
	Structure used for bit access.
uint32_t IPSR_Type::ISR:9
	bit: 0. More...
uint32_t IPSR_Type::_reserved0:23
	bit: 9..31 Reserved More...
struct {
uint32_t IPSR_Type::ISR:9
	bit: 0. More...
uint32_t IPSR_Type::_reserved0:23
	bit: 9..31 Reserved More...
}	IPSR_Type::b
	Structure used for bit access.
uint32_t xPSR_Type::ISR:9
	bit: 0. More...
uint32_t xPSR_Type::_reserved0:7
	bit: 9..15 Reserved More...
uint32_t xPSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t xPSR_Type::_reserved1:4
	bit: 20..23 Reserved More...
uint32_t xPSR_Type::T:1
	bit: 24 Thumb bit (read 0) More...
uint32_t xPSR_Type::IT:2
	bit: 25..26 saved IT state (read 0) More...
uint32_t xPSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t xPSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t xPSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t xPSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t xPSR_Type::N:1
	bit: 31 Negative condition code flag More...
struct {
uint32_t xPSR_Type::ISR:9
	bit: 0. More...
uint32_t xPSR_Type::_reserved0:7
	bit: 9..15 Reserved More...
uint32_t xPSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t xPSR_Type::_reserved1:4
	bit: 20..23 Reserved More...
uint32_t xPSR_Type::T:1
	bit: 24 Thumb bit (read 0) More...
uint32_t xPSR_Type::IT:2
	bit: 25..26 saved IT state (read 0) More...
uint32_t xPSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t xPSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t xPSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t xPSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t xPSR_Type::N:1
	bit: 31 Negative condition code flag More...
}	xPSR_Type::b
	Structure used for bit access.
uint32_t CONTROL_Type::nPRIV:1
	bit: 0 Execution privilege in Thread mode More...
uint32_t CONTROL_Type::SPSEL:1
	bit: 1 Stack-pointer select More...
uint32_t CONTROL_Type::FPCA:1
	bit: 2 Floating-point context active More...
uint32_t CONTROL_Type::SFPA:1
	bit: 3 Secure floating-point active More...
uint32_t CONTROL_Type::_reserved1:28
	bit: 4..31 Reserved More...
struct {
uint32_t CONTROL_Type::nPRIV:1
	bit: 0 Execution privilege in Thread mode More...
uint32_t CONTROL_Type::SPSEL:1
	bit: 1 Stack-pointer select More...
uint32_t CONTROL_Type::FPCA:1
	bit: 2 Floating-point context active More...
uint32_t CONTROL_Type::SFPA:1
	bit: 3 Secure floating-point active More...
uint32_t CONTROL_Type::_reserved1:28
	bit: 4..31 Reserved More...
}	CONTROL_Type::b
	Structure used for bit access.
uint32_t	ICB_Type::RESERVED0 [1U]
__IM uint32_t	ICB_Type::ICTR
	Offset: 0x004 (R/ ) Interrupt Controller Type Register.
__IOM uint32_t	ICB_Type::ACTLR
	Offset: 0x008 (R/W) Auxiliary Control Register.
__IOM uint32_t	ICB_Type::CPPWR
	Offset: 0x00C (R/W) Coprocessor Power Control Register.
__OM uint8_t ITM_Type::u8
	Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More...
__OM uint16_t ITM_Type::u16
	Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More...
__OM uint32_t ITM_Type::u32
	Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More...
union {
__OM uint8_t ITM_Type::u8
	Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More...
__OM uint16_t ITM_Type::u16
	Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More...
__OM uint32_t ITM_Type::u32
	Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More...
}	ITM_Type::PORT [32U]
	Offset: 0x000 ( /W) ITM Stimulus Port Registers.
__IOM uint32_t	MemSysCtl_Type::MSCR
	Offset: 0x000 (R/W) Memory System Control Register.
__IOM uint32_t	MemSysCtl_Type::PFCR
	Offset: 0x004 (R/W) Prefetcher Control Register.
uint32_t	MemSysCtl_Type::RESERVED1 [2U]
__IOM uint32_t	MemSysCtl_Type::ITCMCR
	Offset: 0x010 (R/W) ITCM Control Register.
__IOM uint32_t	MemSysCtl_Type::DTCMCR
	Offset: 0x014 (R/W) DTCM Control Register.
__IOM uint32_t	MemSysCtl_Type::PAHBCR
	Offset: 0x018 (R/W) P-AHB Control Register.
uint32_t	MemSysCtl_Type::RESERVED2 [313U]
__IOM uint32_t	MemSysCtl_Type::ITGU_CTRL
	Offset: 0x500 (R/W) ITGU Control Register.
__IOM uint32_t	MemSysCtl_Type::ITGU_CFG
	Offset: 0x504 (R/W) ITGU Configuration Register.
uint32_t	MemSysCtl_Type::RESERVED3 [2U]
__IOM uint32_t	MemSysCtl_Type::ITGU_LUT [16U]
	Offset: 0x510 (R/W) ITGU Look Up Table Register.
uint32_t	MemSysCtl_Type::RESERVED4 [44U]
__IOM uint32_t	MemSysCtl_Type::DTGU_CTRL
	Offset: 0x600 (R/W) DTGU Control Registers.
__IOM uint32_t	MemSysCtl_Type::DTGU_CFG
	Offset: 0x604 (R/W) DTGU Configuration Register.
uint32_t	MemSysCtl_Type::RESERVED5 [2U]
__IOM uint32_t	MemSysCtl_Type::DTGU_LUT [16U]
	Offset: 0x610 (R/W) DTGU Look Up Table Register.
__IOM uint32_t	PwrModCtl_Type::CPDLPSTATE
	Offset: 0x000 (R/W) Core Power Domain Low Power State Register.
__IOM uint32_t	PwrModCtl_Type::DPDLPSTATE
	Offset: 0x004 (R/W) Debug Power Domain Low Power State Register.
__OM uint32_t	EWIC_Type::EVENTSPR
	Offset: 0x000 ( /W) Event Set Pending Register.
uint32_t	EWIC_Type::RESERVED0 [31U]
__IM uint32_t	EWIC_Type::EVENTMASKA
	Offset: 0x080 (R/W) Event Mask A Register.
__IM uint32_t	EWIC_Type::EVENTMASK [15]
	Offset: 0x084 (R/W) Event Mask Register.
__IOM uint32_t	ErrBnk_Type::IEBR0
	Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0.
__IOM uint32_t	ErrBnk_Type::IEBR1
	Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1.
uint32_t	ErrBnk_Type::RESERVED0 [2U]
__IOM uint32_t	ErrBnk_Type::DEBR0
	Offset: 0x010 (R/W) Data Cache Error Bank Register 0.
__IOM uint32_t	ErrBnk_Type::DEBR1
	Offset: 0x014 (R/W) Data Cache Error Bank Register 1.
uint32_t	ErrBnk_Type::RESERVED1 [2U]
__IOM uint32_t	ErrBnk_Type::TEBR0
	Offset: 0x020 (R/W) TCM Error Bank Register 0.
uint32_t	ErrBnk_Type::RESERVED2 [1U]
__IOM uint32_t	ErrBnk_Type::TEBR1
	Offset: 0x028 (R/W) TCM Error Bank Register 1.
__OM uint32_t	PrcCfgInf_Type::CFGINFOSEL
	Offset: 0x000 ( /W) Processor Configuration Information Selection Register.
__IM uint32_t	PrcCfgInf_Type::CFGINFORD
	Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register.
__IM uint32_t	STL_Type::STLNVICPENDOR
	Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register.
__IM uint32_t	STL_Type::STLNVICACTVOR
	Offset: 0x004 (R/ ) NVIC Active Priority Tree Register.
uint32_t	STL_Type::RESERVED0 [2U]
__OM uint32_t	STL_Type::STLIDMPUSR
	Offset: 0x010 ( /W) MPU Sanple Register.
__IM uint32_t	STL_Type::STLIMPUOR
	Offset: 0x014 (R/ ) MPU Region Hit Register.
__IM uint32_t	STL_Type::STLD0MPUOR
	Offset: 0x018 (R/ ) MPU Memory Attributes Register 0.
__IM uint32_t	STL_Type::STLD1MPUOR
	Offset: 0x01C (R/ ) MPU Memory Attributes Register 1.
__IOM uint32_t MPU_Type::MAIR [2]
__IOM uint32_t MPU_Type::MAIR0
	Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
__IOM uint32_t MPU_Type::MAIR1
	Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
struct {
__IOM uint32_t MPU_Type::MAIR0
	Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
__IOM uint32_t MPU_Type::MAIR1
	Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
}
union {
__IOM uint32_t MPU_Type::MAIR [2]
struct {
__IOM uint32_t MPU_Type::MAIR0
	Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
__IOM uint32_t MPU_Type::MAIR1
	Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
}
};
uint32_t APSR_Type::_reserved0:16
	bit: 0..15 Reserved More...
uint32_t APSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t APSR_Type::_reserved1:7
	bit: 20..26 Reserved More...
uint32_t APSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t APSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t APSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t APSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t APSR_Type::N:1
	bit: 31 Negative condition code flag More...
struct {
uint32_t APSR_Type::_reserved0:16
	bit: 0..15 Reserved More...
uint32_t APSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t APSR_Type::_reserved1:7
	bit: 20..26 Reserved More...
uint32_t APSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t APSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t APSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t APSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t APSR_Type::N:1
	bit: 31 Negative condition code flag More...
}	APSR_Type::b
	Structure used for bit access.
uint32_t IPSR_Type::ISR:9
	bit: 0. More...
uint32_t IPSR_Type::_reserved0:23
	bit: 9..31 Reserved More...
struct {
uint32_t IPSR_Type::ISR:9
	bit: 0. More...
uint32_t IPSR_Type::_reserved0:23
	bit: 9..31 Reserved More...
}	IPSR_Type::b
	Structure used for bit access.
uint32_t xPSR_Type::ISR:9
	bit: 0. More...
uint32_t xPSR_Type::_reserved0:1
	bit: 9 Reserved More...
uint32_t xPSR_Type::ICI_IT_1:6
	bit: 10..15 ICI/IT part 1 More...
uint32_t xPSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t xPSR_Type::_reserved1:4
	bit: 20..23 Reserved More...
uint32_t xPSR_Type::T:1
	bit: 24 Thumb bit More...
uint32_t xPSR_Type::ICI_IT_2:2
	bit: 25..26 ICI/IT part 2 More...
uint32_t xPSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t xPSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t xPSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t xPSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t xPSR_Type::N:1
	bit: 31 Negative condition code flag More...
struct {
uint32_t xPSR_Type::ISR:9
	bit: 0. More...
uint32_t xPSR_Type::_reserved0:1
	bit: 9 Reserved More...
uint32_t xPSR_Type::ICI_IT_1:6
	bit: 10..15 ICI/IT part 1 More...
uint32_t xPSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t xPSR_Type::_reserved1:4
	bit: 20..23 Reserved More...
uint32_t xPSR_Type::T:1
	bit: 24 Thumb bit More...
uint32_t xPSR_Type::ICI_IT_2:2
	bit: 25..26 ICI/IT part 2 More...
uint32_t xPSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t xPSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t xPSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t xPSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t xPSR_Type::N:1
	bit: 31 Negative condition code flag More...
}	xPSR_Type::b
	Structure used for bit access.
uint32_t CONTROL_Type::nPRIV:1
	bit: 0 Execution privilege in Thread mode More...
uint32_t CONTROL_Type::SPSEL:1
	bit: 1 Stack to be used More...
uint32_t CONTROL_Type::FPCA:1
	bit: 2 FP extension active flag More...
uint32_t CONTROL_Type::_reserved0:29
	bit: 3..31 Reserved More...
struct {
uint32_t CONTROL_Type::nPRIV:1
	bit: 0 Execution privilege in Thread mode More...
uint32_t CONTROL_Type::SPSEL:1
	bit: 1 Stack to be used More...
uint32_t CONTROL_Type::FPCA:1
	bit: 2 FP extension active flag More...
uint32_t CONTROL_Type::_reserved0:29
	bit: 3..31 Reserved More...
}	CONTROL_Type::b
	Structure used for bit access.
__IM uint32_t	SCB_Type::ID_MFR [4U]
	Offset: 0x050 (R/ ) Memory Model Feature Register.
__IOM uint32_t	SCB_Type::ITCMCR
	Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register.
__IOM uint32_t	SCB_Type::DTCMCR
	Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers.
__IOM uint32_t	SCB_Type::AHBPCR
	Offset: 0x298 (R/W) AHBP Control Register.
__IOM uint32_t	SCB_Type::CACR
	Offset: 0x29C (R/W) L1 Cache Control Register.
__IOM uint32_t	SCB_Type::AHBSCR
	Offset: 0x2A0 (R/W) AHB Slave Control Register.
uint32_t	SCB_Type::RESERVED8 [1U]
__IOM uint32_t	SCB_Type::ABFSR
	Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register.
__OM uint8_t ITM_Type::u8
	Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More...
__OM uint16_t ITM_Type::u16
	Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More...
__OM uint32_t ITM_Type::u32
	Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More...
union {
__OM uint8_t ITM_Type::u8
	Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More...
__OM uint16_t ITM_Type::u16
	Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More...
__OM uint32_t ITM_Type::u32
	Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More...
}	ITM_Type::PORT [32U]
	Offset: 0x000 ( /W) ITM Stimulus Port Registers.
__OM uint32_t	DWT_Type::LAR
	Offset: 0xFB0 ( W) Lock Access Register.
uint32_t APSR_Type::_reserved0:16
	bit: 0..15 Reserved More...
uint32_t APSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t APSR_Type::_reserved1:7
	bit: 20..26 Reserved More...
uint32_t APSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t APSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t APSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t APSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t APSR_Type::N:1
	bit: 31 Negative condition code flag More...
struct {
uint32_t APSR_Type::_reserved0:16
	bit: 0..15 Reserved More...
uint32_t APSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t APSR_Type::_reserved1:7
	bit: 20..26 Reserved More...
uint32_t APSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t APSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t APSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t APSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t APSR_Type::N:1
	bit: 31 Negative condition code flag More...
}	APSR_Type::b
	Structure used for bit access.
uint32_t IPSR_Type::ISR:9
	bit: 0. More...
uint32_t IPSR_Type::_reserved0:23
	bit: 9..31 Reserved More...
struct {
uint32_t IPSR_Type::ISR:9
	bit: 0. More...
uint32_t IPSR_Type::_reserved0:23
	bit: 9..31 Reserved More...
}	IPSR_Type::b
	Structure used for bit access.
uint32_t xPSR_Type::ISR:9
	bit: 0. More...
uint32_t xPSR_Type::_reserved0:7
	bit: 9..15 Reserved More...
uint32_t xPSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t xPSR_Type::_reserved1:1
	bit: 20 Reserved More...
uint32_t xPSR_Type::B:1
	bit: 21 BTI active (read 0) More...
uint32_t xPSR_Type::_reserved2:2
	bit: 22..23 Reserved More...
uint32_t xPSR_Type::T:1
	bit: 24 Thumb bit (read 0) More...
uint32_t xPSR_Type::IT:2
	bit: 25..26 saved IT state (read 0) More...
uint32_t xPSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t xPSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t xPSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t xPSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t xPSR_Type::N:1
	bit: 31 Negative condition code flag More...
struct {
uint32_t xPSR_Type::ISR:9
	bit: 0. More...
uint32_t xPSR_Type::_reserved0:7
	bit: 9..15 Reserved More...
uint32_t xPSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t xPSR_Type::_reserved1:1
	bit: 20 Reserved More...
uint32_t xPSR_Type::B:1
	bit: 21 BTI active (read 0) More...
uint32_t xPSR_Type::_reserved2:2
	bit: 22..23 Reserved More...
uint32_t xPSR_Type::T:1
	bit: 24 Thumb bit (read 0) More...
uint32_t xPSR_Type::IT:2
	bit: 25..26 saved IT state (read 0) More...
uint32_t xPSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t xPSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t xPSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t xPSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t xPSR_Type::N:1
	bit: 31 Negative condition code flag More...
}	xPSR_Type::b
	Structure used for bit access.
uint32_t CONTROL_Type::nPRIV:1
	bit: 0 Execution privilege in Thread mode More...
uint32_t CONTROL_Type::SPSEL:1
	bit: 1 Stack-pointer select More...
uint32_t CONTROL_Type::FPCA:1
	bit: 2 Floating-point context active More...
uint32_t CONTROL_Type::SFPA:1
	bit: 3 Secure floating-point active More...
uint32_t CONTROL_Type::BTI_EN:1
	bit: 4 Privileged branch target identification enable More...
uint32_t CONTROL_Type::UBTI_EN:1
	bit: 5 Unprivileged branch target identification enable More...
uint32_t CONTROL_Type::PAC_EN:1
	bit: 6 Privileged pointer authentication enable More...
uint32_t CONTROL_Type::UPAC_EN:1
	bit: 7 Unprivileged pointer authentication enable More...
uint32_t CONTROL_Type::_reserved1:24
	bit: 8..31 Reserved More...
struct {
uint32_t CONTROL_Type::nPRIV:1
	bit: 0 Execution privilege in Thread mode More...
uint32_t CONTROL_Type::SPSEL:1
	bit: 1 Stack-pointer select More...
uint32_t CONTROL_Type::FPCA:1
	bit: 2 Floating-point context active More...
uint32_t CONTROL_Type::SFPA:1
	bit: 3 Secure floating-point active More...
uint32_t CONTROL_Type::BTI_EN:1
	bit: 4 Privileged branch target identification enable More...
uint32_t CONTROL_Type::UBTI_EN:1
	bit: 5 Unprivileged branch target identification enable More...
uint32_t CONTROL_Type::PAC_EN:1
	bit: 6 Privileged pointer authentication enable More...
uint32_t CONTROL_Type::UPAC_EN:1
	bit: 7 Unprivileged pointer authentication enable More...
uint32_t CONTROL_Type::_reserved1:24
	bit: 8..31 Reserved More...
}	CONTROL_Type::b
	Structure used for bit access.
__OM uint8_t ITM_Type::u8
	Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More...
__OM uint16_t ITM_Type::u16
	Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More...
__OM uint32_t ITM_Type::u32
	Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More...
union {
__OM uint8_t ITM_Type::u8
	Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More...
__OM uint16_t ITM_Type::u16
	Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More...
__OM uint32_t ITM_Type::u32
	Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More...
}	ITM_Type::PORT [32U]
	Offset: 0x000 ( /W) ITM Stimulus Port Registers.
__IOM uint32_t MPU_Type::MAIR [2]
__IOM uint32_t MPU_Type::MAIR0
	Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
__IOM uint32_t MPU_Type::MAIR1
	Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
struct {
__IOM uint32_t MPU_Type::MAIR0
	Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
__IOM uint32_t MPU_Type::MAIR1
	Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
}
union {
__IOM uint32_t MPU_Type::MAIR [2]
struct {
__IOM uint32_t MPU_Type::MAIR0
	Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
__IOM uint32_t MPU_Type::MAIR1
	Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
}
};
uint32_t APSR_Type::_reserved0:27
	bit: 0..26 Reserved More...
uint32_t APSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t APSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t APSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t APSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t APSR_Type::N:1
	bit: 31 Negative condition code flag More...
struct {
uint32_t APSR_Type::_reserved0:27
	bit: 0..26 Reserved More...
uint32_t APSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t APSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t APSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t APSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t APSR_Type::N:1
	bit: 31 Negative condition code flag More...
}	APSR_Type::b
	Structure used for bit access.
uint32_t IPSR_Type::ISR:9
	bit: 0. More...
uint32_t IPSR_Type::_reserved0:23
	bit: 9..31 Reserved More...
struct {
uint32_t IPSR_Type::ISR:9
	bit: 0. More...
uint32_t IPSR_Type::_reserved0:23
	bit: 9..31 Reserved More...
}	IPSR_Type::b
	Structure used for bit access.
uint32_t xPSR_Type::ISR:9
	bit: 0. More...
uint32_t xPSR_Type::_reserved0:1
	bit: 9 Reserved More...
uint32_t xPSR_Type::ICI_IT_1:6
	bit: 10..15 ICI/IT part 1 More...
uint32_t xPSR_Type::_reserved1:8
	bit: 16..23 Reserved More...
uint32_t xPSR_Type::T:1
	bit: 24 Thumb bit More...
uint32_t xPSR_Type::ICI_IT_2:2
	bit: 25..26 ICI/IT part 2 More...
uint32_t xPSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t xPSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t xPSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t xPSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t xPSR_Type::N:1
	bit: 31 Negative condition code flag More...
struct {
uint32_t xPSR_Type::ISR:9
	bit: 0. More...
uint32_t xPSR_Type::_reserved0:1
	bit: 9 Reserved More...
uint32_t xPSR_Type::ICI_IT_1:6
	bit: 10..15 ICI/IT part 1 More...
uint32_t xPSR_Type::_reserved1:8
	bit: 16..23 Reserved More...
uint32_t xPSR_Type::T:1
	bit: 24 Thumb bit More...
uint32_t xPSR_Type::ICI_IT_2:2
	bit: 25..26 ICI/IT part 2 More...
uint32_t xPSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t xPSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t xPSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t xPSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t xPSR_Type::N:1
	bit: 31 Negative condition code flag More...
}	xPSR_Type::b
	Structure used for bit access.
uint32_t CONTROL_Type::nPRIV:1
	bit: 0 Execution privilege in Thread mode More...
uint32_t CONTROL_Type::SPSEL:1
	bit: 1 Stack to be used More...
uint32_t CONTROL_Type::_reserved1:30
	bit: 2..31 Reserved More...
struct {
uint32_t CONTROL_Type::nPRIV:1
	bit: 0 Execution privilege in Thread mode More...
uint32_t CONTROL_Type::SPSEL:1
	bit: 1 Stack to be used More...
uint32_t CONTROL_Type::_reserved1:30
	bit: 2..31 Reserved More...
}	CONTROL_Type::b
	Structure used for bit access.
__OM uint8_t ITM_Type::u8
	Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More...
__OM uint16_t ITM_Type::u16
	Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More...
__OM uint32_t ITM_Type::u32
	Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More...
union {
__OM uint8_t ITM_Type::u8
	Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More...
__OM uint16_t ITM_Type::u16
	Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More...
__OM uint32_t ITM_Type::u32
	Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More...
}	ITM_Type::PORT [32U]
	Offset: 0x000 ( /W) ITM Stimulus Port Registers.
uint32_t APSR_Type::_reserved0:16
	bit: 0..15 Reserved More...
uint32_t APSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t APSR_Type::_reserved1:7
	bit: 20..26 Reserved More...
uint32_t APSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t APSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t APSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t APSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t APSR_Type::N:1
	bit: 31 Negative condition code flag More...
struct {
uint32_t APSR_Type::_reserved0:16
	bit: 0..15 Reserved More...
uint32_t APSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t APSR_Type::_reserved1:7
	bit: 20..26 Reserved More...
uint32_t APSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t APSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t APSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t APSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t APSR_Type::N:1
	bit: 31 Negative condition code flag More...
}	APSR_Type::b
	Structure used for bit access.
uint32_t IPSR_Type::ISR:9
	bit: 0. More...
uint32_t IPSR_Type::_reserved0:23
	bit: 9..31 Reserved More...
struct {
uint32_t IPSR_Type::ISR:9
	bit: 0. More...
uint32_t IPSR_Type::_reserved0:23
	bit: 9..31 Reserved More...
}	IPSR_Type::b
	Structure used for bit access.
uint32_t xPSR_Type::ISR:9
	bit: 0. More...
uint32_t xPSR_Type::_reserved0:7
	bit: 9..15 Reserved More...
uint32_t xPSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t xPSR_Type::_reserved1:4
	bit: 20..23 Reserved More...
uint32_t xPSR_Type::T:1
	bit: 24 Thumb bit (read 0) More...
uint32_t xPSR_Type::IT:2
	bit: 25..26 saved IT state (read 0) More...
uint32_t xPSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t xPSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t xPSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t xPSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t xPSR_Type::N:1
	bit: 31 Negative condition code flag More...
struct {
uint32_t xPSR_Type::ISR:9
	bit: 0. More...
uint32_t xPSR_Type::_reserved0:7
	bit: 9..15 Reserved More...
uint32_t xPSR_Type::GE:4
	bit: 16..19 Greater than or Equal flags More...
uint32_t xPSR_Type::_reserved1:4
	bit: 20..23 Reserved More...
uint32_t xPSR_Type::T:1
	bit: 24 Thumb bit (read 0) More...
uint32_t xPSR_Type::IT:2
	bit: 25..26 saved IT state (read 0) More...
uint32_t xPSR_Type::Q:1
	bit: 27 Saturation condition flag More...
uint32_t xPSR_Type::V:1
	bit: 28 Overflow condition code flag More...
uint32_t xPSR_Type::C:1
	bit: 29 Carry condition code flag More...
uint32_t xPSR_Type::Z:1
	bit: 30 Zero condition code flag More...
uint32_t xPSR_Type::N:1
	bit: 31 Negative condition code flag More...
}	xPSR_Type::b
	Structure used for bit access.
uint32_t CONTROL_Type::nPRIV:1
	bit: 0 Execution privilege in Thread mode More...
uint32_t CONTROL_Type::SPSEL:1
	bit: 1 Stack-pointer select More...
uint32_t CONTROL_Type::FPCA:1
	bit: 2 Floating-point context active More...
uint32_t CONTROL_Type::SFPA:1
	bit: 3 Secure floating-point active More...
uint32_t CONTROL_Type::_reserved1:28
	bit: 4..31 Reserved More...
struct {
uint32_t CONTROL_Type::nPRIV:1
	bit: 0 Execution privilege in Thread mode More...
uint32_t CONTROL_Type::SPSEL:1
	bit: 1 Stack-pointer select More...
uint32_t CONTROL_Type::FPCA:1
	bit: 2 Floating-point context active More...
uint32_t CONTROL_Type::SFPA:1
	bit: 3 Secure floating-point active More...
uint32_t CONTROL_Type::_reserved1:28
	bit: 4..31 Reserved More...
}	CONTROL_Type::b
	Structure used for bit access.
uint32_t	SCB_Type::RESERVED_ADD1 [21U]
__IOM uint32_t	EMSS_Type::CACR
	Offset: 0x0 (R/W) L1 Cache Control Register.
__IOM uint32_t	EMSS_Type::ITCMCR
	Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register.
__IOM uint32_t	EMSS_Type::DTCMCR
	Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers.
__OM uint8_t ITM_Type::u8
	Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More...
__OM uint16_t ITM_Type::u16
	Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More...
__OM uint32_t ITM_Type::u32
	Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More...
union {
__OM uint8_t ITM_Type::u8
	Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More...
__OM uint16_t ITM_Type::u16
	Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More...
__OM uint32_t ITM_Type::u32
	Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More...
}	ITM_Type::PORT [32U]
	Offset: 0x000 ( /W) ITM Stimulus Port Registers.
__IOM uint32_t MPU_Type::MAIR [2]
__IOM uint32_t MPU_Type::MAIR0
	Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
__IOM uint32_t MPU_Type::MAIR1
	Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
struct {
__IOM uint32_t MPU_Type::MAIR0
	Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
__IOM uint32_t MPU_Type::MAIR1
	Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
}
union {
__IOM uint32_t MPU_Type::MAIR [2]
struct {
__IOM uint32_t MPU_Type::MAIR0
	Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
__IOM uint32_t MPU_Type::MAIR1
	Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
}
};
volatile int32_t	ITM_RxBuffer
	External variable to receive characters.
__STATIC_INLINE uint32_t	ITM_SendChar (uint32_t ch)
	ITM Send Character.
__STATIC_INLINE int32_t	ITM_ReceiveChar (void)
	ITM Receive Character.
__STATIC_INLINE int32_t	ITM_CheckChar (void)
	ITM Check Character.
volatile int32_t	ITM_RxBuffer
	External variable to receive characters.
volatile int32_t	ITM_RxBuffer
	External variable to receive characters.
volatile int32_t	ITM_RxBuffer
	External variable to receive characters.
volatile int32_t	ITM_RxBuffer
	External variable to receive characters.
volatile int32_t	ITM_RxBuffer
	External variable to receive characters.
volatile int32_t	ITM_RxBuffer
	External variable to receive characters.
volatile int32_t	ITM_RxBuffer
	External variable to receive characters.
volatile int32_t	ITM_RxBuffer
	External variable to receive characters.
volatile int32_t	ITM_RxBuffer
	External variable to receive characters.
volatile int32_t	ITM_RxBuffer
	External variable to receive characters.
#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
	Value identifying ITM_RxBuffer is ready for next character.
#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
	Value identifying ITM_RxBuffer is ready for next character.
#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
	Value identifying ITM_RxBuffer is ready for next character.
#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
	Value identifying ITM_RxBuffer is ready for next character.
#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
	Value identifying ITM_RxBuffer is ready for next character.
#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
	Value identifying ITM_RxBuffer is ready for next character.
#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
	Value identifying ITM_RxBuffer is ready for next character.
#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
	Value identifying ITM_RxBuffer is ready for next character.
#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
	Value identifying ITM_RxBuffer is ready for next character.
#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
	Value identifying ITM_RxBuffer is ready for next character.
#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
	Value identifying ITM_RxBuffer is ready for next character.

Detailed Description

Functions that access the ITM debug interface.

Macro Definition Documentation

◆ ITM_RXBUFFER_EMPTY [1/11]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 4152 of file core_armv81mml.h.

Referenced by ITM_CheckChar(), and ITM_ReceiveChar().

◆ ITM_RXBUFFER_EMPTY [2/11]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 3133 of file core_armv8mml.h.

◆ ITM_RXBUFFER_EMPTY [3/11]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 1867 of file core_cm3.h.

◆ ITM_RXBUFFER_EMPTY [4/11]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 3201 of file core_cm33.h.

◆ ITM_RXBUFFER_EMPTY [5/11]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 3201 of file core_cm35p.h.

◆ ITM_RXBUFFER_EMPTY [6/11]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 2053 of file core_cm4.h.

◆ ITM_RXBUFFER_EMPTY [7/11]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 4741 of file core_cm55.h.

◆ ITM_RXBUFFER_EMPTY [8/11]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 2290 of file core_cm7.h.

◆ ITM_RXBUFFER_EMPTY [9/11]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 4596 of file core_cm85.h.

◆ ITM_RXBUFFER_EMPTY [10/11]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 1841 of file core_sc300.h.

◆ ITM_RXBUFFER_EMPTY [11/11]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 3516 of file core_starmc1.h.

Function Documentation

◆ ITM_CheckChar()

__STATIC_INLINE int32_t ITM_CheckChar ( void )

ITM Check Character.

Checks whether a character is pending for reading in the variable ITM_RxBuffer.

Returns: 0 No character available.; 1 Character available.

Definition at line 4204 of file core_armv81mml.h.

References __STATIC_INLINE, ITM_RxBuffer, and ITM_RXBUFFER_EMPTY.

◆ ITM_ReceiveChar()

__STATIC_INLINE int32_t ITM_ReceiveChar ( void )

ITM Receive Character.

Inputs a character via the external variable ITM_RxBuffer.

Returns: Received character.; -1 No character pending.

Definition at line 4184 of file core_armv81mml.h.

References __STATIC_INLINE, ch(), ITM_RxBuffer, and ITM_RXBUFFER_EMPTY.

◆ ITM_SendChar()

__STATIC_INLINE uint32_t ITM_SendChar ( uint32_t ch )

ITM Send Character.

Transmits a character via the ITM channel 0, and

Just returns when no debugger is connected that has booked the output.
Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Parameters

[in] ch Character to transmit.

Returns
Character to transmit.

Definition at line 4163 of file core_armv81mml.h.

References __NOP, __STATIC_INLINE, ch(), ITM, and ITM_TCR_ITMENA_Msk.

Variable Documentation

◆ [union]

union { ... } MPU_Type

◆ [struct]

struct { ... } MPU_Type

◆ [union]

union { ... } MPU_Type

◆ [union]

union { ... } MPU_Type

◆ [struct]

struct { ... } MPU_Type

◆ [struct]

struct { ... } MPU_Type

◆ [union]

union { ... } MPU_Type

◆ [struct]

struct { ... } MPU_Type

◆ [union]

union { ... } MPU_Type

◆ [struct]

struct { ... } MPU_Type

◆ [struct]

struct { ... } MPU_Type

◆ [union]

union { ... } MPU_Type

◆ [union]

union { ... } MPU_Type

◆ [struct]

struct { ... } MPU_Type

◆ [] [1/38]

uint32_t { ... } ::_reserved0

bit: 0..15 Reserved

Definition at line 332 of file core_armv81mml.h.

◆ [] [2/38]

uint32_t { ... } ::_reserved0

bit: 0..15 Reserved

Definition at line 330 of file core_cm85.h.

◆ [] [3/38]

uint32_t { ... } ::_reserved0

bit: 0..15 Reserved

Definition at line 268 of file core_cm4.h.

◆ [] [4/38]

uint32_t { ... } ::_reserved0

bit: 0..15 Reserved

Definition at line 334 of file core_cm55.h.

◆ [] [5/38]

uint32_t { ... } ::_reserved0

bit: 0..15 Reserved

Definition at line 331 of file core_starmc1.h.

◆ [] [6/38]

uint32_t { ... } ::_reserved0

bit: 0..15 Reserved

Definition at line 325 of file core_cm35p.h.

◆ [] [7/38]

uint32_t { ... } ::_reserved0

bit: 0..15 Reserved

Definition at line 325 of file core_cm33.h.

◆ [] [8/38]

uint32_t { ... } ::_reserved0

bit: 0..15 Reserved

Definition at line 325 of file core_armv8mml.h.

◆ [] [9/38]

uint32_t { ... } ::_reserved0

bit: 0..26 Reserved

Definition at line 215 of file core_sc300.h.

◆ [] [10/38]

uint32_t { ... } ::_reserved0

bit: 0..15 Reserved

Definition at line 283 of file core_cm7.h.

◆ [] [11/38]

uint32_t { ... } ::_reserved0

bit: 0..26 Reserved

Definition at line 215 of file core_cm3.h.

◆ _reserved0 [12/38]

uint32_t APSR_Type::_reserved0

bit: 0..15 Reserved

bit: 0..26 Reserved

bit: 0..27 Reserved

Definition at line 332 of file core_armv81mml.h.

◆ [] [13/38]

uint32_t { ... } ::_reserved0

bit: 3..31 Reserved

Definition at line 398 of file core_cm7.h.

◆ [] [14/38]

uint32_t { ... } ::_reserved0

bit: 3..31 Reserved

Definition at line 383 of file core_cm4.h.

◆ [] [15/38]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 370 of file core_cm85.h.

◆ [] [16/38]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 250 of file core_cm3.h.

◆ [] [17/38]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 374 of file core_cm55.h.

◆ [] [18/38]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 371 of file core_starmc1.h.

◆ [] [19/38]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 250 of file core_sc300.h.

◆ [] [20/38]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 308 of file core_cm4.h.

◆ [] [21/38]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 323 of file core_cm7.h.

◆ [] [22/38]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 365 of file core_armv8mml.h.

◆ [] [23/38]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 365 of file core_cm33.h.

◆ [] [24/38]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 372 of file core_armv81mml.h.

◆ [] [25/38]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 365 of file core_cm35p.h.

◆ _reserved0 [26/38]

uint32_t IPSR_Type::_reserved0

bit: 9..31 Reserved

Definition at line 372 of file core_armv81mml.h.

◆ [] [27/38]

uint32_t { ... } ::_reserved0

bit: 9..15 Reserved

Definition at line 388 of file core_cm85.h.

◆ [] [28/38]

uint32_t { ... } ::_reserved0

bit: 9..15 Reserved

Definition at line 389 of file core_starmc1.h.

◆ [] [29/38]

uint32_t { ... } ::_reserved0

bit: 9 Reserved

Definition at line 341 of file core_cm7.h.

◆ [] [30/38]

uint32_t { ... } ::_reserved0

bit: 9..15 Reserved

Definition at line 383 of file core_cm35p.h.

◆ [] [31/38]

uint32_t { ... } ::_reserved0

bit: 9..15 Reserved

Definition at line 392 of file core_cm55.h.

◆ [] [32/38]

uint32_t { ... } ::_reserved0

bit: 9 Reserved

Definition at line 268 of file core_cm3.h.

◆ [] [33/38]

uint32_t { ... } ::_reserved0

bit: 9 Reserved

Definition at line 326 of file core_cm4.h.

◆ [] [34/38]

uint32_t { ... } ::_reserved0

bit: 9 Reserved

Definition at line 268 of file core_sc300.h.

◆ [] [35/38]

uint32_t { ... } ::_reserved0

bit: 9..15 Reserved

Definition at line 390 of file core_armv81mml.h.

◆ [] [36/38]

uint32_t { ... } ::_reserved0

bit: 9..15 Reserved

Definition at line 383 of file core_armv8mml.h.

◆ [] [37/38]

uint32_t { ... } ::_reserved0

bit: 9..15 Reserved

Definition at line 383 of file core_cm33.h.

◆ _reserved0 [38/38]

uint32_t xPSR_Type::_reserved0

bit: 9..15 Reserved

bit: 9 Reserved

bit: 9..23 Reserved

Definition at line 390 of file core_armv81mml.h.

◆ [] [1/32]

uint32_t { ... } ::_reserved1

bit: 20..26 Reserved

Definition at line 334 of file core_armv81mml.h.

◆ [] [2/32]

uint32_t { ... } ::_reserved1

bit: 20..26 Reserved

Definition at line 332 of file core_cm85.h.

◆ [] [3/32]

uint32_t { ... } ::_reserved1

bit: 20..26 Reserved

Definition at line 270 of file core_cm4.h.

◆ [] [4/32]

uint32_t { ... } ::_reserved1

bit: 20..26 Reserved

Definition at line 336 of file core_cm55.h.

◆ [] [5/32]

uint32_t { ... } ::_reserved1

bit: 20..26 Reserved

Definition at line 333 of file core_starmc1.h.

◆ [] [6/32]

uint32_t { ... } ::_reserved1

bit: 20..26 Reserved

Definition at line 327 of file core_cm35p.h.

◆ [] [7/32]

uint32_t { ... } ::_reserved1

bit: 20..26 Reserved

Definition at line 327 of file core_cm33.h.

◆ [] [8/32]

uint32_t { ... } ::_reserved1

bit: 20..26 Reserved

Definition at line 327 of file core_armv8mml.h.

◆ [] [9/32]

uint32_t { ... } ::_reserved1

bit: 20..26 Reserved

Definition at line 285 of file core_cm7.h.

◆ _reserved1 [10/32]

uint32_t APSR_Type::_reserved1

bit: 20..26 Reserved

Definition at line 334 of file core_armv81mml.h.

◆ [] [11/32]

uint32_t { ... } ::_reserved1

bit: 4..31 Reserved

Definition at line 437 of file core_cm35p.h.

◆ [] [12/32]

uint32_t { ... } ::_reserved1

bit: 4..31 Reserved

Definition at line 437 of file core_cm33.h.

◆ [] [13/32]

uint32_t { ... } ::_reserved1

bit: 4..31 Reserved

Definition at line 444 of file core_armv81mml.h.

◆ [] [14/32]

uint32_t { ... } ::_reserved1

bit: 2..31 Reserved

Definition at line 320 of file core_sc300.h.

◆ [] [15/32]

uint32_t { ... } ::_reserved1

bit: 4..31 Reserved

Definition at line 437 of file core_armv8mml.h.

◆ [] [16/32]

uint32_t { ... } ::_reserved1

bit: 4..31 Reserved

Definition at line 446 of file core_cm55.h.

◆ [] [17/32]

uint32_t { ... } ::_reserved1

bit: 2..31 Reserved

Definition at line 320 of file core_cm3.h.

◆ [] [18/32]

uint32_t { ... } ::_reserved1

bit: 4..31 Reserved

Definition at line 443 of file core_starmc1.h.

◆ [] [19/32]

uint32_t { ... } ::_reserved1

bit: 8..31 Reserved

Definition at line 451 of file core_cm85.h.

◆ _reserved1 [20/32]

uint32_t CONTROL_Type::_reserved1

bit: 4..31 Reserved

bit: 8..31 Reserved

bit: 2..31 Reserved

Definition at line 444 of file core_armv81mml.h.

◆ [] [21/32]

uint32_t { ... } ::_reserved1

bit: 20 Reserved

Definition at line 390 of file core_cm85.h.

◆ [] [22/32]

uint32_t { ... } ::_reserved1

bit: 20..23 Reserved

Definition at line 391 of file core_starmc1.h.

◆ [] [23/32]

uint32_t { ... } ::_reserved1

bit: 20..23 Reserved

Definition at line 344 of file core_cm7.h.

◆ [] [24/32]

uint32_t { ... } ::_reserved1

bit: 20..23 Reserved

Definition at line 385 of file core_cm35p.h.

◆ [] [25/32]

uint32_t { ... } ::_reserved1

bit: 20..23 Reserved

Definition at line 394 of file core_cm55.h.

◆ [] [26/32]

uint32_t { ... } ::_reserved1

bit: 16..23 Reserved

Definition at line 270 of file core_cm3.h.

◆ [] [27/32]

uint32_t { ... } ::_reserved1

bit: 20..23 Reserved

Definition at line 329 of file core_cm4.h.

◆ [] [28/32]

uint32_t { ... } ::_reserved1

bit: 16..23 Reserved

Definition at line 270 of file core_sc300.h.

◆ [] [29/32]

uint32_t { ... } ::_reserved1

bit: 20..23 Reserved

Definition at line 392 of file core_armv81mml.h.

◆ [] [30/32]

uint32_t { ... } ::_reserved1

bit: 20..23 Reserved

Definition at line 385 of file core_armv8mml.h.

◆ [] [31/32]

uint32_t { ... } ::_reserved1

bit: 20..23 Reserved

Definition at line 385 of file core_cm33.h.

◆ _reserved1 [32/32]

uint32_t xPSR_Type::_reserved1

bit: 20..23 Reserved

bit: 20 Reserved

bit: 16..23 Reserved

bit: 25..27 Reserved

Definition at line 392 of file core_armv81mml.h.

◆ [] [1/2]

uint32_t { ... } ::_reserved2

bit: 22..23 Reserved

Definition at line 392 of file core_cm85.h.

◆ _reserved2 [2/2]

uint32_t xPSR_Type::_reserved2

bit: 22..23 Reserved

Definition at line 392 of file core_cm85.h.

◆ ABFSR

__IOM uint32_t SCB_Type::ABFSR

Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register.

Definition at line 512 of file core_cm7.h.

◆ ACPR

__IOM uint32_t TPI_Type::ACPR

Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register.

Definition at line 1370 of file core_armv81mml.h.

◆ ACTLR [1/2]

__IOM uint32_t ICB_Type::ACTLR

Offset: 0x008 (R/W) Auxiliary Control Register.

Definition at line 1007 of file core_cm55.h.

◆ ACTLR [2/2]

__IOM uint32_t SCnSCB_Type::ACTLR

Offset: 0x008 (R/W) Auxiliary Control Register.

Definition at line 1005 of file core_armv81mml.h.

◆ ADR

__IM uint32_t SCB_Type::ADR

Offset: 0x04C (R/ ) Auxiliary Feature Register.

Definition at line 397 of file core_cm3.h.

◆ AFSR

__IOM uint32_t SCB_Type::AFSR

Offset: 0x03C (R/W) Auxiliary Fault Status Register.

Definition at line 526 of file core_armv81mml.h.

◆ AHBPCR

__IOM uint32_t SCB_Type::AHBPCR

Offset: 0x298 (R/W) AHBP Control Register.

Definition at line 508 of file core_cm7.h.

◆ AHBSCR

__IOM uint32_t SCB_Type::AHBSCR

Offset: 0x2A0 (R/W) AHB Slave Control Register.

Definition at line 510 of file core_cm7.h.

◆ AIRCR

__IOM uint32_t SCB_Type::AIRCR

Offset: 0x00C (R/W) Application Interrupt and Reset Control Register.

Definition at line 516 of file core_armv81mml.h.

◆ [] [1/2]

uint32_t { ... } ::B

bit: 21 BTI active (read 0)

Definition at line 391 of file core_cm85.h.

◆ B [2/2]

uint32_t xPSR_Type::B

bit: 21 BTI active (read 0)

Definition at line 391 of file core_cm85.h.