Type definitions for the NVIC Registers. More...

Collaboration diagram for Nested Vectored Interrupt Controller (NVIC):

Topics
	System Control Block (SCB)
	Type definitions for the System Control Block Registers.

Classes
struct	NVIC_Type
	Structure type to access the Nested Vectored Interrupt Controller (NVIC). More...
#define	NVIC_STIR_INTID_Pos 0U
	STIR: INTLINESNUM Position.
#define	NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/)
	STIR: INTLINESNUM Mask.
#define	NVIC_STIR_INTID_Pos 0U
	STIR: INTLINESNUM Position.
#define	NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/)
	STIR: INTLINESNUM Mask.
#define	NVIC_STIR_INTID_Pos 0U
	STIR: INTLINESNUM Position.
#define	NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/)
	STIR: INTLINESNUM Mask.
#define	NVIC_STIR_INTID_Pos 0U
	STIR: INTLINESNUM Position.
#define	NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/)
	STIR: INTLINESNUM Mask.
#define	NVIC_STIR_INTID_Pos 0U
	STIR: INTLINESNUM Position.
#define	NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/)
	STIR: INTLINESNUM Mask.
#define	NVIC_STIR_INTID_Pos 0U
	STIR: INTLINESNUM Position.
#define	NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/)
	STIR: INTLINESNUM Mask.
#define	NVIC_STIR_INTID_Pos 0U
	STIR: INTLINESNUM Position.
#define	NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/)
	STIR: INTLINESNUM Mask.
#define	NVIC_STIR_INTID_Pos 0U
	STIR: INTLINESNUM Position.
#define	NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/)
	STIR: INTLINESNUM Mask.
#define	NVIC_STIR_INTID_Pos 0U
	STIR: INTLINESNUM Position.
#define	NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/)
	STIR: INTLINESNUM Mask.
#define	NVIC_STIR_INTID_Pos 0U
	STIR: INTLINESNUM Position.
#define	NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/)
	STIR: INTLINESNUM Mask.
#define	NVIC_STIR_INTID_Pos 0U
	STIR: INTLINESNUM Position.
#define	NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/)
	STIR: INTLINESNUM Mask.

Detailed Description

Type definitions for the NVIC Registers.

Macro Definition Documentation

◆ NVIC_STIR_INTID_Msk [1/11]

#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

STIR: INTLINESNUM Mask.

Definition at line 496 of file core_armv81mml.h.

◆ NVIC_STIR_INTID_Msk [2/11]

#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

STIR: INTLINESNUM Mask.

Definition at line 489 of file core_armv8mml.h.

◆ NVIC_STIR_INTID_Msk [3/11]

#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

STIR: INTLINESNUM Mask.

Definition at line 364 of file core_cm3.h.

◆ NVIC_STIR_INTID_Msk [4/11]

#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

STIR: INTLINESNUM Mask.

Definition at line 489 of file core_cm33.h.

◆ NVIC_STIR_INTID_Msk [5/11]

#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

STIR: INTLINESNUM Mask.

Definition at line 489 of file core_cm35p.h.

◆ NVIC_STIR_INTID_Msk [6/11]

#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

STIR: INTLINESNUM Mask.

Definition at line 430 of file core_cm4.h.

◆ NVIC_STIR_INTID_Msk [7/11]

#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

STIR: INTLINESNUM Mask.

Definition at line 498 of file core_cm55.h.

◆ NVIC_STIR_INTID_Msk [8/11]

#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

STIR: INTLINESNUM Mask.

Definition at line 445 of file core_cm7.h.

◆ NVIC_STIR_INTID_Msk [9/11]

#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

STIR: INTLINESNUM Mask.

Definition at line 515 of file core_cm85.h.

◆ NVIC_STIR_INTID_Msk [10/11]

#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

STIR: INTLINESNUM Mask.

Definition at line 364 of file core_sc300.h.

◆ NVIC_STIR_INTID_Msk [11/11]

#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)

STIR: INTLINESNUM Mask.

Definition at line 495 of file core_starmc1.h.