CMSIS Cortex-M0+ Core Peripheral Access Layer Header File. More...

#include <stdint.h>
#include "cmsis_version.h"
#include "cmsis_compiler.h"
#include "mpu_armv7.h"

Include dependency graph for core_cm0plus.h:

Classes
union	APSR_Type
	Union type to access the Application Program Status Register (APSR). More...
union	IPSR_Type
	Union type to access the Interrupt Program Status Register (IPSR). More...
union	xPSR_Type
	Union type to access the Special-Purpose Program Status Registers (xPSR). More...
union	CONTROL_Type
	Union type to access the Control Registers (CONTROL). More...
struct	NVIC_Type
	Structure type to access the Nested Vectored Interrupt Controller (NVIC). More...
struct	SCB_Type
	Structure type to access the System Control Block (SCB). More...
struct	SysTick_Type
	Structure type to access the System Timer (SysTick). More...
struct	MPU_Type
	Structure type to access the Memory Protection Unit (MPU). More...

Macros
#define	__CORE_CM0PLUS_H_GENERIC

#define	__CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)

#define	__CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
#define	__CM0PLUS_CMSIS_VERSION
#define	__CORTEX_M (0U)
	Cortex-M Core.
#define	__FPU_USED 0U
	__FPU_USED indicates whether an FPU is used or not.
#define	__CORE_CM0PLUS_H_DEPENDANT
#define	__I volatile const
	Defines 'read only' permissions.
#define	__O volatile
	Defines 'write only' permissions.
#define	__IO volatile
	Defines 'read / write' permissions.
#define	__IM volatile const /! Defines 'read only' structure member permissions /
#define	__OM volatile /! Defines 'write only' structure member permissions /
#define	__IOM volatile /! Defines 'read / write' structure member permissions /

#define	APSR_N_Pos 31U
	APSR: N Position.
#define	APSR_N_Msk (1UL << APSR_N_Pos)
	APSR: N Mask.
#define	APSR_Z_Pos 30U
	APSR: Z Position.
#define	APSR_Z_Msk (1UL << APSR_Z_Pos)
	APSR: Z Mask.
#define	APSR_C_Pos 29U
	APSR: C Position.
#define	APSR_C_Msk (1UL << APSR_C_Pos)
	APSR: C Mask.
#define	APSR_V_Pos 28U
	APSR: V Position.
#define	APSR_V_Msk (1UL << APSR_V_Pos)
	APSR: V Mask.
#define	IPSR_ISR_Pos 0U
	IPSR: ISR Position.
#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)
	IPSR: ISR Mask.
#define	xPSR_N_Pos 31U
	xPSR: N Position
#define	xPSR_N_Msk (1UL << xPSR_N_Pos)
	xPSR: N Mask
#define	xPSR_Z_Pos 30U
	xPSR: Z Position
#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)
	xPSR: Z Mask
#define	xPSR_C_Pos 29U
	xPSR: C Position
#define	xPSR_C_Msk (1UL << xPSR_C_Pos)
	xPSR: C Mask
#define	xPSR_V_Pos 28U
	xPSR: V Position
#define	xPSR_V_Msk (1UL << xPSR_V_Pos)
	xPSR: V Mask
#define	xPSR_T_Pos 24U
	xPSR: T Position
#define	xPSR_T_Msk (1UL << xPSR_T_Pos)
	xPSR: T Mask
#define	xPSR_ISR_Pos 0U
	xPSR: ISR Position
#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)
	xPSR: ISR Mask
#define	CONTROL_SPSEL_Pos 1U
	CONTROL: SPSEL Position.
#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
	CONTROL: SPSEL Mask.
#define	CONTROL_nPRIV_Pos 0U
	CONTROL: nPRIV Position.
#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)
	CONTROL: nPRIV Mask.
#define	SCB_CPUID_IMPLEMENTER_Pos 24U
	SCB CPUID: IMPLEMENTER Position.
#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
	SCB CPUID: IMPLEMENTER Mask.
#define	SCB_CPUID_VARIANT_Pos 20U
	SCB CPUID: VARIANT Position.
#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
	SCB CPUID: VARIANT Mask.
#define	SCB_CPUID_ARCHITECTURE_Pos 16U
	SCB CPUID: ARCHITECTURE Position.
#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
	SCB CPUID: ARCHITECTURE Mask.
#define	SCB_CPUID_PARTNO_Pos 4U
	SCB CPUID: PARTNO Position.
#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
	SCB CPUID: PARTNO Mask.
#define	SCB_CPUID_REVISION_Pos 0U
	SCB CPUID: REVISION Position.
#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)
	SCB CPUID: REVISION Mask.
#define	SCB_ICSR_NMIPENDSET_Pos 31U
	SCB ICSR: NMIPENDSET Position.
#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
	SCB ICSR: NMIPENDSET Mask.
#define	SCB_ICSR_PENDSVSET_Pos 28U
	SCB ICSR: PENDSVSET Position.
#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
	SCB ICSR: PENDSVSET Mask.
#define	SCB_ICSR_PENDSVCLR_Pos 27U
	SCB ICSR: PENDSVCLR Position.
#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
	SCB ICSR: PENDSVCLR Mask.
#define	SCB_ICSR_PENDSTSET_Pos 26U
	SCB ICSR: PENDSTSET Position.
#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
	SCB ICSR: PENDSTSET Mask.
#define	SCB_ICSR_PENDSTCLR_Pos 25U
	SCB ICSR: PENDSTCLR Position.
#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
	SCB ICSR: PENDSTCLR Mask.
#define	SCB_ICSR_ISRPREEMPT_Pos 23U
	SCB ICSR: ISRPREEMPT Position.
#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
	SCB ICSR: ISRPREEMPT Mask.
#define	SCB_ICSR_ISRPENDING_Pos 22U
	SCB ICSR: ISRPENDING Position.
#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
	SCB ICSR: ISRPENDING Mask.
#define	SCB_ICSR_VECTPENDING_Pos 12U
	SCB ICSR: VECTPENDING Position.
#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
	SCB ICSR: VECTPENDING Mask.
#define	SCB_ICSR_VECTACTIVE_Pos 0U
	SCB ICSR: VECTACTIVE Position.
#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)
	SCB ICSR: VECTACTIVE Mask.
#define	SCB_AIRCR_VECTKEY_Pos 16U
	SCB AIRCR: VECTKEY Position.
#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
	SCB AIRCR: VECTKEY Mask.
#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U
	SCB AIRCR: VECTKEYSTAT Position.
#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
	SCB AIRCR: VECTKEYSTAT Mask.
#define	SCB_AIRCR_ENDIANESS_Pos 15U
	SCB AIRCR: ENDIANESS Position.
#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
	SCB AIRCR: ENDIANESS Mask.
#define	SCB_AIRCR_SYSRESETREQ_Pos 2U
	SCB AIRCR: SYSRESETREQ Position.
#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
	SCB AIRCR: SYSRESETREQ Mask.
#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U
	SCB AIRCR: VECTCLRACTIVE Position.
#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
	SCB AIRCR: VECTCLRACTIVE Mask.
#define	SCB_SCR_SEVONPEND_Pos 4U
	SCB SCR: SEVONPEND Position.
#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
	SCB SCR: SEVONPEND Mask.
#define	SCB_SCR_SLEEPDEEP_Pos 2U
	SCB SCR: SLEEPDEEP Position.
#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
	SCB SCR: SLEEPDEEP Mask.
#define	SCB_SCR_SLEEPONEXIT_Pos 1U
	SCB SCR: SLEEPONEXIT Position.
#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
	SCB SCR: SLEEPONEXIT Mask.
#define	SCB_CCR_UNALIGN_TRP_Pos 3U
	SCB CCR: UNALIGN_TRP Position.
#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
	SCB CCR: UNALIGN_TRP Mask.
#define	SCB_SHCSR_SVCALLPENDED_Pos 15U
	SCB SHCSR: SVCALLPENDED Position.
#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
	SCB SHCSR: SVCALLPENDED Mask.
#define	SysTick_CTRL_COUNTFLAG_Pos 16U
	SysTick CTRL: COUNTFLAG Position.
#define	SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
	SysTick CTRL: COUNTFLAG Mask.
#define	SysTick_CTRL_CLKSOURCE_Pos 2U
	SysTick CTRL: CLKSOURCE Position.
#define	SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
	SysTick CTRL: CLKSOURCE Mask.
#define	SysTick_CTRL_TICKINT_Pos 1U
	SysTick CTRL: TICKINT Position.
#define	SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
	SysTick CTRL: TICKINT Mask.
#define	SysTick_CTRL_ENABLE_Pos 0U
	SysTick CTRL: ENABLE Position.
#define	SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/)
	SysTick CTRL: ENABLE Mask.
#define	SysTick_LOAD_RELOAD_Pos 0U
	SysTick LOAD: RELOAD Position.
#define	SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/)
	SysTick LOAD: RELOAD Mask.
#define	SysTick_VAL_CURRENT_Pos 0U
	SysTick VAL: CURRENT Position.
#define	SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/)
	SysTick VAL: CURRENT Mask.
#define	SysTick_CALIB_NOREF_Pos 31U
	SysTick CALIB: NOREF Position.
#define	SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
	SysTick CALIB: NOREF Mask.
#define	SysTick_CALIB_SKEW_Pos 30U
	SysTick CALIB: SKEW Position.
#define	SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
	SysTick CALIB: SKEW Mask.
#define	SysTick_CALIB_TENMS_Pos 0U
	SysTick CALIB: TENMS Position.
#define	SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/)
	SysTick CALIB: TENMS Mask.
#define	MPU_TYPE_RALIASES 1U
#define	MPU_TYPE_IREGION_Pos 16U
	MPU TYPE: IREGION Position.
#define	MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
	MPU TYPE: IREGION Mask.
#define	MPU_TYPE_DREGION_Pos 8U
	MPU TYPE: DREGION Position.
#define	MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
	MPU TYPE: DREGION Mask.
#define	MPU_TYPE_SEPARATE_Pos 0U
	MPU TYPE: SEPARATE Position.
#define	MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/)
	MPU TYPE: SEPARATE Mask.
#define	MPU_CTRL_PRIVDEFENA_Pos 2U
	MPU CTRL: PRIVDEFENA Position.
#define	MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
	MPU CTRL: PRIVDEFENA Mask.
#define	MPU_CTRL_HFNMIENA_Pos 1U
	MPU CTRL: HFNMIENA Position.
#define	MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
	MPU CTRL: HFNMIENA Mask.
#define	MPU_CTRL_ENABLE_Pos 0U
	MPU CTRL: ENABLE Position.
#define	MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/)
	MPU CTRL: ENABLE Mask.
#define	MPU_RNR_REGION_Pos 0U
	MPU RNR: REGION Position.
#define	MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/)
	MPU RNR: REGION Mask.
#define	_VAL2FLD(field, value)
	Mask and shift a bit field value for use in a register bit range.
#define	_FLD2VAL(field, value)
	Mask and shift a register value to extract a bit filed value.
#define	SCS_BASE (0xE000E000UL)
	System Control Space Base Address.
#define	SysTick_BASE (SCS_BASE + 0x0010UL)
	SysTick Base Address.
#define	NVIC_BASE (SCS_BASE + 0x0100UL)
	NVIC Base Address.
#define	SCB_BASE (SCS_BASE + 0x0D00UL)
	System Control Block Base Address.
#define	SCB ((SCB_Type *) SCB_BASE )
	SCB configuration struct.
#define	SysTick ((SysTick_Type *) SysTick_BASE )
	SysTick configuration struct.
#define	NVIC ((NVIC_Type *) NVIC_BASE )
	NVIC configuration struct.
#define	MPU_BASE (SCS_BASE + 0x0D90UL)
	Memory Protection Unit.
#define	MPU ((MPU_Type *) MPU_BASE )
	Memory Protection Unit.
#define	NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define	NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define	NVIC_EnableIRQ __NVIC_EnableIRQ
#define	NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define	NVIC_DisableIRQ __NVIC_DisableIRQ
#define	NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define	NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define	NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define	NVIC_SetPriority __NVIC_SetPriority
#define	NVIC_GetPriority __NVIC_GetPriority
#define	NVIC_SystemReset __NVIC_SystemReset
#define	NVIC_SetVector __NVIC_SetVector
#define	NVIC_GetVector __NVIC_GetVector
#define	NVIC_USER_IRQ_OFFSET 16

#define	SCB_CCR_STKALIGN_Pos 9U
	SCB CCR: STKALIGN Position.
#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
	SCB CCR: STKALIGN Mask.
#define	MPU_RBAR_ADDR_Pos 8U
	MPU RBAR: ADDR Position.
#define	MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
	MPU RBAR: ADDR Mask.
#define	MPU_RBAR_VALID_Pos 4U
	MPU RBAR: VALID Position.
#define	MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
	MPU RBAR: VALID Mask.
#define	MPU_RBAR_REGION_Pos 0U
	MPU RBAR: REGION Position.
#define	MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/)
	MPU RBAR: REGION Mask.
#define	MPU_RASR_ATTRS_Pos 16U
	MPU RASR: MPU Region Attribute field Position.
#define	MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
	MPU RASR: MPU Region Attribute field Mask.
#define	MPU_RASR_XN_Pos 28U
	MPU RASR: ATTRS.XN Position.
#define	MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
	MPU RASR: ATTRS.XN Mask.
#define	MPU_RASR_AP_Pos 24U
	MPU RASR: ATTRS.AP Position.
#define	MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
	MPU RASR: ATTRS.AP Mask.
#define	MPU_RASR_TEX_Pos 19U
	MPU RASR: ATTRS.TEX Position.
#define	MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
	MPU RASR: ATTRS.TEX Mask.
#define	MPU_RASR_S_Pos 18U
	MPU RASR: ATTRS.S Position.
#define	MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
	MPU RASR: ATTRS.S Mask.
#define	MPU_RASR_C_Pos 17U
	MPU RASR: ATTRS.C Position.
#define	MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
	MPU RASR: ATTRS.C Mask.
#define	MPU_RASR_B_Pos 16U
	MPU RASR: ATTRS.B Position.
#define	MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
	MPU RASR: ATTRS.B Mask.
#define	MPU_RASR_SRD_Pos 8U
	MPU RASR: Sub-Region Disable Position.
#define	MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
	MPU RASR: Sub-Region Disable Mask.
#define	MPU_RASR_SIZE_Pos 1U
	MPU RASR: Region Size Field Position.
#define	MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
	MPU RASR: Region Size Field Mask.
#define	MPU_RASR_ENABLE_Pos 0U
	MPU RASR: Region enable bit Position.
#define	MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/)
	MPU RASR: Region enable bit Disable Mask.
#define	EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define	EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define	EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */

#define	_BIT_SHIFT(IRQn)
#define	_SHP_IDX(IRQn)
#define	_IP_IDX(IRQn)

#define	__NVIC_SetPriorityGrouping(X)
#define	__NVIC_GetPriorityGrouping()

Functions

__STATIC_INLINE void	__NVIC_EnableIRQ (IRQn_Type IRQn)
	Enable Interrupt.
__STATIC_INLINE uint32_t	__NVIC_GetEnableIRQ (IRQn_Type IRQn)
	Get Interrupt Enable status.
__STATIC_INLINE void	__NVIC_DisableIRQ (IRQn_Type IRQn)
	Disable Interrupt.
__STATIC_INLINE uint32_t	__NVIC_GetPendingIRQ (IRQn_Type IRQn)
	Get Pending Interrupt.
__STATIC_INLINE void	__NVIC_SetPendingIRQ (IRQn_Type IRQn)
	Set Pending Interrupt.
__STATIC_INLINE void	__NVIC_ClearPendingIRQ (IRQn_Type IRQn)
	Clear Pending Interrupt.
__STATIC_INLINE void	__NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)
	Set Interrupt Priority.
__STATIC_INLINE uint32_t	__NVIC_GetPriority (IRQn_Type IRQn)
	Get Interrupt Priority.
__STATIC_INLINE uint32_t	NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
	Encode Priority.
__STATIC_INLINE void	NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t const pPreemptPriority, uint32_t const pSubPriority)
	Decode Priority.
__STATIC_INLINE void	__NVIC_SetVector (IRQn_Type IRQn, uint32_t vector)
	Set Interrupt Vector.
__STATIC_INLINE uint32_t	__NVIC_GetVector (IRQn_Type IRQn)
	Get Interrupt Vector.
__NO_RETURN __STATIC_INLINE void	__NVIC_SystemReset (void)
	System Reset.
__STATIC_INLINE uint32_t	SCB_GetFPUType (void)
	get FPU type
__STATIC_INLINE uint32_t	SysTick_Config (uint32_t ticks)
	System Tick Configuration.

Detailed Description

CMSIS Cortex-M0+ Core Peripheral Access Layer Header File.

Version: V5.0.9

Date: 21. August 2019

Definition in file core_cm0plus.h.

Macro Definition Documentation

◆ __CM0PLUS_CMSIS_VERSION

#define __CM0PLUS_CMSIS_VERSION

Value:

((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \

__CM0PLUS_CMSIS_VERSION_SUB )

__CM0PLUS_CMSIS_VERSION_MAIN

#define __CM0PLUS_CMSIS_VERSION_MAIN

Definition core_cm0plus.h:66

__CM0PLUS_CMSIS_VERSION_SUB

#define __CM0PLUS_CMSIS_VERSION_SUB

Definition core_cm0plus.h:67

Deprecated: CMSIS HAL version number

Definition at line 68 of file core_cm0plus.h.

◆ __CM0PLUS_CMSIS_VERSION_MAIN

#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)

Deprecated: [31:16] CMSIS HAL main version

Definition at line 66 of file core_cm0plus.h.

◆ __CM0PLUS_CMSIS_VERSION_SUB

#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)

Deprecated: [15:0] CMSIS HAL sub version

Definition at line 67 of file core_cm0plus.h.

◆ __CORE_CM0PLUS_H_DEPENDANT

#define __CORE_CM0PLUS_H_DEPENDANT

Definition at line 127 of file core_cm0plus.h.

◆ __CORE_CM0PLUS_H_GENERIC

#define __CORE_CM0PLUS_H_GENERIC

Definition at line 32 of file core_cm0plus.h.

◆ __CORTEX_M

#define __CORTEX_M (0U)

Cortex-M Core.

Definition at line 71 of file core_cm0plus.h.

◆ __FPU_USED

#define __FPU_USED 0U

__FPU_USED indicates whether an FPU is used or not.

This core does not support an FPU at all

Definition at line 76 of file core_cm0plus.h.

◆ __I

#define __I volatile const

Defines 'read only' permissions.

Definition at line 172 of file core_cm0plus.h.

◆ __IM

#define __IM volatile const /*! Defines 'read only' structure member permissions */

Definition at line 178 of file core_cm0plus.h.

◆ __IO

#define __IO volatile

Defines 'read / write' permissions.

Definition at line 175 of file core_cm0plus.h.

◆ __IOM

#define __IOM volatile /*! Defines 'read / write' structure member permissions */

Definition at line 180 of file core_cm0plus.h.

◆ __O

#define __O volatile

Defines 'write only' permissions.

Definition at line 174 of file core_cm0plus.h.

◆ __OM

#define __OM volatile /*! Defines 'write only' structure member permissions */

Definition at line 179 of file core_cm0plus.h.

Classes

Macros

Functions