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MPU_Type Struct Reference
Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » Implementation Control Block register (ICB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » Implementation Control Block register (ICB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Memory System Control Registers (IMPLEMENTATION DEFINED) » Power Mode Control Registers » External Wakeup Interrupt Controller Registers » Error Banking Registers (IMPLEMENTATION DEFINED) » Processor Configuration Information Registers (IMPLEMENTATION DEFINED) » Software Test Library Observation Registers » Trace Port Interface (TPI) » Memory Protection Unit (MPU)

Structure type to access the Memory Protection Unit (MPU). More...

#include <core_armv81mml.h>

Public Attributes

__IM uint32_t TYPE
 Offset: 0x000 (R/ ) MPU Type Register.
__IOM uint32_t CTRL
 Offset: 0x004 (R/W) MPU Control Register.
__IOM uint32_t RNR
 Offset: 0x008 (R/W) MPU Region Number Register.
__IOM uint32_t RBAR
 Offset: 0x00C (R/W) MPU Region Base Address Register.
__IOM uint32_t RLAR
 Offset: 0x010 (R/W) MPU Region Limit Address Register.
__IOM uint32_t RBAR_A1
 Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1.
__IOM uint32_t RLAR_A1
 Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1.
__IOM uint32_t RBAR_A2
 Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2.
__IOM uint32_t RLAR_A2
 Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2.
__IOM uint32_t RBAR_A3
 Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3.
__IOM uint32_t RLAR_A3
 Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3.
uint32_t RESERVED0 [1]
union { 
   __IOM uint32_t   MPU_Type::MAIR [2] 
   struct { 
      __IOM uint32_t   MPU_Type::MAIR0 
 Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
      __IOM uint32_t   MPU_Type::MAIR1 
 Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
   } 
}; 
union { 
   __IOM uint32_t   MPU_Type::MAIR [2] 
   struct { 
      __IOM uint32_t   MPU_Type::MAIR0 
 Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
      __IOM uint32_t   MPU_Type::MAIR1 
 Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
   } 
}; 
union { 
   __IOM uint32_t   MPU_Type::MAIR [2] 
   struct { 
      __IOM uint32_t   MPU_Type::MAIR0 
 Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
      __IOM uint32_t   MPU_Type::MAIR1 
 Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
   } 
}; 
__IOM uint32_t RASR
 Offset: 0x010 (R/W) MPU Region Attribute and Size Register.
union { 
   __IOM uint32_t   MPU_Type::MAIR [2] 
   struct { 
      __IOM uint32_t   MPU_Type::MAIR0 
 Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
      __IOM uint32_t   MPU_Type::MAIR1 
 Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
   } 
}; 
__IOM uint32_t RASR_A1
 Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register.
__IOM uint32_t RASR_A2
 Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register.
__IOM uint32_t RASR_A3
 Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register.
union { 
   __IOM uint32_t   MPU_Type::MAIR [2] 
   struct { 
      __IOM uint32_t   MPU_Type::MAIR0 
 Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
      __IOM uint32_t   MPU_Type::MAIR1 
 Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
   } 
}; 
union { 
   __IOM uint32_t   MPU_Type::MAIR [2] 
   struct { 
      __IOM uint32_t   MPU_Type::MAIR0 
 Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
      __IOM uint32_t   MPU_Type::MAIR1 
 Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
   } 
}; 
union { 
   __IOM uint32_t   MPU_Type::MAIR [2] 
   struct { 
      __IOM uint32_t   MPU_Type::MAIR0 
 Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
      __IOM uint32_t   MPU_Type::MAIR1 
 Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
   } 
}; 
union { 
   __IOM uint32_t   MPU_Type::MAIR [2] 
   struct { 
      __IOM uint32_t   MPU_Type::MAIR0 
 Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
      __IOM uint32_t   MPU_Type::MAIR1 
 Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
   } 
}; 
union { 
   __IOM uint32_t   MPU_Type::MAIR [2] 
   struct { 
      __IOM uint32_t   MPU_Type::MAIR0 
 Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0. More...
      __IOM uint32_t   MPU_Type::MAIR1 
 Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1. More...
   } 
}; 

Detailed Description

Structure type to access the Memory Protection Unit (MPU).

Definition at line 2280 of file core_armv81mml.h.

The documentation for this struct was generated from the following files: