- Generated by
1.15.0
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STAR
Cal STAR — firmware, DAQ server, and engine design
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Structure type to access the System Control Block (SCB). More...
#include <core_armv81mml.h>
Public Attributes | |
| __IM uint32_t | CPUID |
| Offset: 0x000 (R/ ) CPUID Base Register. | |
| __IOM uint32_t | ICSR |
| Offset: 0x004 (R/W) Interrupt Control and State Register. | |
| __IOM uint32_t | VTOR |
| Offset: 0x008 (R/W) Vector Table Offset Register. | |
| __IOM uint32_t | AIRCR |
| Offset: 0x00C (R/W) Application Interrupt and Reset Control Register. | |
| __IOM uint32_t | SCR |
| Offset: 0x010 (R/W) System Control Register. | |
| __IOM uint32_t | CCR |
| Offset: 0x014 (R/W) Configuration Control Register. | |
| __IOM uint8_t | SHPR [12U] |
| Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15). | |
| __IOM uint32_t | SHCSR |
| Offset: 0x024 (R/W) System Handler Control and State Register. | |
| __IOM uint32_t | CFSR |
| Offset: 0x028 (R/W) Configurable Fault Status Register. | |
| __IOM uint32_t | HFSR |
| Offset: 0x02C (R/W) HardFault Status Register. | |
| __IOM uint32_t | DFSR |
| Offset: 0x030 (R/W) Debug Fault Status Register. | |
| __IOM uint32_t | MMFAR |
| Offset: 0x034 (R/W) MemManage Fault Address Register. | |
| __IOM uint32_t | BFAR |
| Offset: 0x038 (R/W) BusFault Address Register. | |
| __IOM uint32_t | AFSR |
| Offset: 0x03C (R/W) Auxiliary Fault Status Register. | |
| __IM uint32_t | ID_PFR [2U] |
| Offset: 0x040 (R/ ) Processor Feature Register. | |
| __IM uint32_t | ID_DFR |
| Offset: 0x048 (R/ ) Debug Feature Register. | |
| __IM uint32_t | ID_AFR |
| Offset: 0x04C (R/ ) Auxiliary Feature Register. | |
| __IM uint32_t | ID_MMFR [4U] |
| Offset: 0x050 (R/ ) Memory Model Feature Register. | |
| __IM uint32_t | ID_ISAR [6U] |
| Offset: 0x060 (R/ ) Instruction Set Attributes Register. | |
| __IM uint32_t | CLIDR |
| Offset: 0x078 (R/ ) Cache Level ID register. | |
| __IM uint32_t | CTR |
| Offset: 0x07C (R/ ) Cache Type register. | |
| __IM uint32_t | CCSIDR |
| Offset: 0x080 (R/ ) Cache Size ID Register. | |
| __IOM uint32_t | CSSELR |
| Offset: 0x084 (R/W) Cache Size Selection Register. | |
| __IOM uint32_t | CPACR |
| Offset: 0x088 (R/W) Coprocessor Access Control Register. | |
| __IOM uint32_t | NSACR |
| Offset: 0x08C (R/W) Non-Secure Access Control Register. | |
| uint32_t | RESERVED7 [21U] |
| __IOM uint32_t | SFSR |
| Offset: 0x0E4 (R/W) Secure Fault Status Register. | |
| __IOM uint32_t | SFAR |
| Offset: 0x0E8 (R/W) Secure Fault Address Register. | |
| uint32_t | RESERVED3 [69U] |
| __OM uint32_t | STIR |
| Offset: 0x200 ( /W) Software Triggered Interrupt Register. | |
| __IOM uint32_t | RFSR |
| Offset: 0x204 (R/W) RAS Fault Status Register. | |
| uint32_t | RESERVED4 [14U] |
| __IM uint32_t | MVFR0 |
| Offset: 0x240 (R/ ) Media and VFP Feature Register 0. | |
| __IM uint32_t | MVFR1 |
| Offset: 0x244 (R/ ) Media and VFP Feature Register 1. | |
| __IM uint32_t | MVFR2 |
| Offset: 0x248 (R/ ) Media and VFP Feature Register 2. | |
| uint32_t | RESERVED5 [1U] |
| __OM uint32_t | ICIALLU |
| Offset: 0x250 ( /W) I-Cache Invalidate All to PoU. | |
| uint32_t | RESERVED6 [1U] |
| __OM uint32_t | ICIMVAU |
| Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU. | |
| __OM uint32_t | DCIMVAC |
| Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC. | |
| __OM uint32_t | DCISW |
| Offset: 0x260 ( /W) D-Cache Invalidate by Set-way. | |
| __OM uint32_t | DCCMVAU |
| Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU. | |
| __OM uint32_t | DCCMVAC |
| Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC. | |
| __OM uint32_t | DCCSW |
| Offset: 0x26C ( /W) D-Cache Clean by Set-way. | |
| __OM uint32_t | DCCIMVAC |
| Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC. | |
| __OM uint32_t | DCCISW |
| Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way. | |
| __OM uint32_t | BPIALL |
| Offset: 0x278 ( /W) Branch Predictor Invalidate All. | |
| uint32_t | RESERVED0 |
| uint32_t | RESERVED1 |
| __IOM uint32_t | SHPR [2U] |
| Offset: 0x01C (R/W) System Handlers Priority Registers. | |
| __IOM uint32_t | SHP [2U] |
| Offset: 0x01C (R/W) System Handlers Priority Registers. | |
| __IOM uint8_t | SHP [12U] |
| Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15). | |
| __IM uint32_t | PFR [2U] |
| Offset: 0x040 (R/ ) Processor Feature Register. | |
| __IM uint32_t | DFR |
| Offset: 0x048 (R/ ) Debug Feature Register. | |
| __IM uint32_t | ADR |
| Offset: 0x04C (R/ ) Auxiliary Feature Register. | |
| __IM uint32_t | MMFR [4U] |
| Offset: 0x050 (R/ ) Memory Model Feature Register. | |
| __IM uint32_t | ISAR [5U] |
| Offset: 0x060 (R/ ) Instruction Set Attributes Register. | |
| __IM uint32_t | ID_MFR [4U] |
| Offset: 0x050 (R/ ) Memory Model Feature Register. | |
| __IOM uint32_t | ITCMCR |
| Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register. | |
| __IOM uint32_t | DTCMCR |
| Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers. | |
| __IOM uint32_t | AHBPCR |
| Offset: 0x298 (R/W) AHBP Control Register. | |
| __IOM uint32_t | CACR |
| Offset: 0x29C (R/W) L1 Cache Control Register. | |
| __IOM uint32_t | AHBSCR |
| Offset: 0x2A0 (R/W) AHB Slave Control Register. | |
| uint32_t | RESERVED8 [1U] |
| __IOM uint32_t | ABFSR |
| Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register. | |
| __IOM uint32_t | SFCR |
| Offset: 0x290 (R/W) Security Features Control Register. | |
| uint32_t | RESERVED_ADD1 [21U] |
Structure type to access the System Control Block (SCB).
Definition at line 511 of file core_armv81mml.h.
1.15.0