STAR
Cal STAR — firmware, DAQ server, and engine design
Loading...
Searching...
No Matches
core_cm7.h
Go to the documentation of this file.
1/**************************************************************************//**
2 * @file core_cm7.h
3 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
4 * @version V5.1.6
5 * @date 04. June 2021
6 ******************************************************************************/
7/*
8 * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25#if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27#elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29#endif
30
31#ifndef __CORE_CM7_H_GENERIC
32#define __CORE_CM7_H_GENERIC
33
34#include <stdint.h>
35
36#ifdef __cplusplus
37 extern "C" {
38#endif
39
40/**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55/*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58/**
59 \ingroup Cortex_M7
60 @{
61 */
62
63#include "cmsis_version.h"
64
65/* CMSIS CM7 definitions */
66#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
67#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
68#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
69 __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
70
71#define __CORTEX_M (7U) /*!< Cortex-M Core */
72
73/** __FPU_USED indicates whether an FPU is used or not.
74 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
75*/
76#if defined ( __CC_ARM )
77 #if defined __TARGET_FPU_VFP
78 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
79 #define __FPU_USED 1U
80 #else
81 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
82 #define __FPU_USED 0U
83 #endif
84 #else
85 #define __FPU_USED 0U
86 #endif
87
88#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
89 #if defined __ARM_FP
90 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
91 #define __FPU_USED 1U
92 #else
93 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
94 #define __FPU_USED 0U
95 #endif
96 #else
97 #define __FPU_USED 0U
98 #endif
99
100#elif defined ( __GNUC__ )
101 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
102 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
103 #define __FPU_USED 1U
104 #else
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106 #define __FPU_USED 0U
107 #endif
108 #else
109 #define __FPU_USED 0U
110 #endif
111
112#elif defined ( __ICCARM__ )
113 #if defined __ARMVFP__
114 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
115 #define __FPU_USED 1U
116 #else
117 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
118 #define __FPU_USED 0U
119 #endif
120 #else
121 #define __FPU_USED 0U
122 #endif
123
124#elif defined ( __TI_ARM__ )
125 #if defined __TI_VFP_SUPPORT__
126 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
127 #define __FPU_USED 1U
128 #else
129 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
130 #define __FPU_USED 0U
131 #endif
132 #else
133 #define __FPU_USED 0U
134 #endif
135
136#elif defined ( __TASKING__ )
137 #if defined __FPU_VFP__
138 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
139 #define __FPU_USED 1U
140 #else
141 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
142 #define __FPU_USED 0U
143 #endif
144 #else
145 #define __FPU_USED 0U
146 #endif
147
148#elif defined ( __CSMC__ )
149 #if ( __CSMC__ & 0x400U)
150 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
151 #define __FPU_USED 1U
152 #else
153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
154 #define __FPU_USED 0U
155 #endif
156 #else
157 #define __FPU_USED 0U
158 #endif
159
160#endif
161
162#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
163
164
165#ifdef __cplusplus
166}
167#endif
168
169#endif /* __CORE_CM7_H_GENERIC */
170
171#ifndef __CMSIS_GENERIC
172
173#ifndef __CORE_CM7_H_DEPENDANT
174#define __CORE_CM7_H_DEPENDANT
175
176#ifdef __cplusplus
177 extern "C" {
178#endif
179
180/* check device defines and use defaults */
181#if defined __CHECK_DEVICE_DEFINES
182 #ifndef __CM7_REV
183 #define __CM7_REV 0x0000U
184 #warning "__CM7_REV not defined in device header file; using default!"
185 #endif
186
187 #ifndef __FPU_PRESENT
188 #define __FPU_PRESENT 0U
189 #warning "__FPU_PRESENT not defined in device header file; using default!"
190 #endif
191
192 #ifndef __MPU_PRESENT
193 #define __MPU_PRESENT 0U
194 #warning "__MPU_PRESENT not defined in device header file; using default!"
195 #endif
196
197 #ifndef __ICACHE_PRESENT
198 #define __ICACHE_PRESENT 0U
199 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
200 #endif
201
202 #ifndef __DCACHE_PRESENT
203 #define __DCACHE_PRESENT 0U
204 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
205 #endif
206
207 #ifndef __DTCM_PRESENT
208 #define __DTCM_PRESENT 0U
209 #warning "__DTCM_PRESENT not defined in device header file; using default!"
210 #endif
211
212 #ifndef __VTOR_PRESENT
213 #define __VTOR_PRESENT 1U
214 #warning "__VTOR_PRESENT not defined in device header file; using default!"
215 #endif
216
217 #ifndef __NVIC_PRIO_BITS
218 #define __NVIC_PRIO_BITS 3U
219 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
220 #endif
221
222 #ifndef __Vendor_SysTickConfig
223 #define __Vendor_SysTickConfig 0U
224 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
225 #endif
226#endif
227
228/* IO definitions (access restrictions to peripheral registers) */
229/**
230 \defgroup CMSIS_glob_defs CMSIS Global Defines
231
232 <strong>IO Type Qualifiers</strong> are used
233 \li to specify the access to peripheral variables.
234 \li for automatic generation of peripheral register debug information.
235*/
236#ifdef __cplusplus
237 #define __I volatile /*!< Defines 'read only' permissions */
238#else
239 #define __I volatile const /*!< Defines 'read only' permissions */
240#endif
241#define __O volatile /*!< Defines 'write only' permissions */
242#define __IO volatile /*!< Defines 'read / write' permissions */
243
244/* following defines should be used for structure members */
245#define __IM volatile const /*! Defines 'read only' structure member permissions */
246#define __OM volatile /*! Defines 'write only' structure member permissions */
247#define __IOM volatile /*! Defines 'read / write' structure member permissions */
248
249/*@} end of group Cortex_M7 */
250
251
252
253/*******************************************************************************
254 * Register Abstraction
255 Core Register contain:
256 - Core Register
257 - Core NVIC Register
258 - Core SCB Register
259 - Core SysTick Register
260 - Core Debug Register
261 - Core MPU Register
262 - Core FPU Register
263 ******************************************************************************/
264/**
265 \defgroup CMSIS_core_register Defines and Type Definitions
266 \brief Type definitions and defines for Cortex-M processor based devices.
267*/
268
269/**
270 \ingroup CMSIS_core_register
271 \defgroup CMSIS_CORE Status and Control Registers
272 \brief Core Register type definitions.
273 @{
274 */
275
276/**
277 \brief Union type to access the Application Program Status Register (APSR).
278 */
279typedef union
280{
281 struct
282 {
283 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
284 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
285 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
286 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
287 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
288 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
289 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
290 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
291 } b; /*!< Structure used for bit access */
292 uint32_t w; /*!< Type used for word access */
293} APSR_Type;
294
295/* APSR Register Definitions */
296#define APSR_N_Pos 31U /*!< APSR: N Position */
297#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
298
299#define APSR_Z_Pos 30U /*!< APSR: Z Position */
300#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
301
302#define APSR_C_Pos 29U /*!< APSR: C Position */
303#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
304
305#define APSR_V_Pos 28U /*!< APSR: V Position */
306#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
307
308#define APSR_Q_Pos 27U /*!< APSR: Q Position */
309#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
310
311#define APSR_GE_Pos 16U /*!< APSR: GE Position */
312#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
313
314
315/**
316 \brief Union type to access the Interrupt Program Status Register (IPSR).
317 */
318typedef union
319{
320 struct
321 {
322 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
323 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
324 } b; /*!< Structure used for bit access */
325 uint32_t w; /*!< Type used for word access */
326} IPSR_Type;
327
328/* IPSR Register Definitions */
329#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
330#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
331
332
333/**
334 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
335 */
336typedef union
337{
338 struct
339 {
340 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
341 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
342 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
343 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
344 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
345 uint32_t T:1; /*!< bit: 24 Thumb bit */
346 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
347 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
348 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
349 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
350 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
351 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
352 } b; /*!< Structure used for bit access */
353 uint32_t w; /*!< Type used for word access */
354} xPSR_Type;
355
356/* xPSR Register Definitions */
357#define xPSR_N_Pos 31U /*!< xPSR: N Position */
358#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
359
360#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
361#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
362
363#define xPSR_C_Pos 29U /*!< xPSR: C Position */
364#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
365
366#define xPSR_V_Pos 28U /*!< xPSR: V Position */
367#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
368
369#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
370#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
371
372#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
373#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
374
375#define xPSR_T_Pos 24U /*!< xPSR: T Position */
376#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
377
378#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
379#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
380
381#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
382#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
383
384#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
385#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
386
387
388/**
389 \brief Union type to access the Control Registers (CONTROL).
390 */
391typedef union
392{
393 struct
394 {
395 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
396 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
397 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
398 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
399 } b; /*!< Structure used for bit access */
400 uint32_t w; /*!< Type used for word access */
401} CONTROL_Type;
402
403/* CONTROL Register Definitions */
404#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
405#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
406
407#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
408#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
409
410#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
411#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
412
413/*@} end of group CMSIS_CORE */
414
415
416/**
417 \ingroup CMSIS_core_register
418 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
419 \brief Type definitions for the NVIC Registers
420 @{
421 */
422
423/**
424 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
425 */
426typedef struct
427{
428 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
429 uint32_t RESERVED0[24U];
430 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
431 uint32_t RESERVED1[24U];
432 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
433 uint32_t RESERVED2[24U];
434 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
435 uint32_t RESERVED3[24U];
436 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
437 uint32_t RESERVED4[56U];
438 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
439 uint32_t RESERVED5[644U];
440 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
441} NVIC_Type;
442
443/* Software Triggered Interrupt Register Definitions */
444#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
445#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
446
447/*@} end of group CMSIS_NVIC */
448
449
450/**
451 \ingroup CMSIS_core_register
452 \defgroup CMSIS_SCB System Control Block (SCB)
453 \brief Type definitions for the System Control Block Registers
454 @{
455 */
456
457/**
458 \brief Structure type to access the System Control Block (SCB).
459 */
460typedef struct
461{
462 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
463 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
464 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
465 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
466 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
467 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
468 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
469 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
470 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
471 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
472 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
473 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
474 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
475 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
476 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
477 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
478 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
479 __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
480 __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
481 uint32_t RESERVED0[1U];
482 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
483 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
484 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
485 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
486 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
487 uint32_t RESERVED3[93U];
488 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
489 uint32_t RESERVED4[15U];
490 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
491 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
492 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
493 uint32_t RESERVED5[1U];
494 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
495 uint32_t RESERVED6[1U];
496 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
497 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
498 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
499 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
500 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
501 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
502 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
503 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
504 __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */
505 uint32_t RESERVED7[5U];
506 __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
507 __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
508 __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
509 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
510 __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
511 uint32_t RESERVED8[1U];
512 __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
513} SCB_Type;
514
515/* SCB CPUID Register Definitions */
516#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
517#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
518
519#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
520#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
521
522#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
523#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
524
525#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
526#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
527
528#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
529#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
530
531/* SCB Interrupt Control State Register Definitions */
532#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
533#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
534
535#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
536#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
537
538#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
539#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
540
541#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
542#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
543
544#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
545#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
546
547#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
548#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
549
550#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
551#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
552
553#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
554#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
555
556#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
557#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
558
559#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
560#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
561
562/* SCB Vector Table Offset Register Definitions */
563#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
564#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
565
566/* SCB Application Interrupt and Reset Control Register Definitions */
567#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
568#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
569
570#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
571#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
572
573#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
574#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
575
576#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
577#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
578
579#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
580#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
581
582#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
583#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
584
585#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
586#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
587
588/* SCB System Control Register Definitions */
589#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
590#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
591
592#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
593#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
594
595#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
596#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
597
598/* SCB Configuration Control Register Definitions */
599#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
600#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
601
602#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
603#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
604
605#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
606#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
607
608#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
609#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
610
611#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
612#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
613
614#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
615#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
616
617#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
618#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
619
620#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
621#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
622
623#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
624#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
625
626/* SCB System Handler Control and State Register Definitions */
627#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
628#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
629
630#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
631#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
632
633#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
634#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
635
636#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
637#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
638
639#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
640#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
641
642#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
643#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
644
645#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
646#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
647
648#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
649#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
650
651#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
652#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
653
654#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
655#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
656
657#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
658#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
659
660#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
661#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
662
663#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
664#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
665
666#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
667#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
668
669/* SCB Configurable Fault Status Register Definitions */
670#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
671#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
672
673#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
674#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
675
676#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
677#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
678
679/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
680#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
681#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
682
683#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
684#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
685
686#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
687#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
688
689#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
690#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
691
692#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
693#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
694
695#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
696#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
697
698/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
699#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
700#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
701
702#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
703#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
704
705#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
706#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
707
708#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
709#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
710
711#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
712#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
713
714#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
715#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
716
717#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
718#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
719
720/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
721#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
722#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
723
724#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
725#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
726
727#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
728#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
729
730#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
731#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
732
733#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
734#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
735
736#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
737#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
738
739/* SCB Hard Fault Status Register Definitions */
740#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
741#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
742
743#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
744#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
745
746#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
747#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
748
749/* SCB Debug Fault Status Register Definitions */
750#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
751#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
752
753#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
754#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
755
756#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
757#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
758
759#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
760#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
761
762#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
763#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
764
765/* SCB Cache Level ID Register Definitions */
766#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
767#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
768
769#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
770#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
771
772/* SCB Cache Type Register Definitions */
773#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
774#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
775
776#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
777#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
778
779#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
780#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
781
782#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
783#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
784
785#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
786#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
787
788/* SCB Cache Size ID Register Definitions */
789#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
790#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
791
792#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
793#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
794
795#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
796#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
797
798#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
799#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
800
801#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
802#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
803
804#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
805#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
806
807#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
808#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
809
810/* SCB Cache Size Selection Register Definitions */
811#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
812#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
813
814#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
815#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
816
817/* SCB Software Triggered Interrupt Register Definitions */
818#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
819#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
820
821/* SCB D-Cache Invalidate by Set-way Register Definitions */
822#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
823#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
824
825#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
826#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
827
828/* SCB D-Cache Clean by Set-way Register Definitions */
829#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
830#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
831
832#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
833#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
834
835/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
836#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
837#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
838
839#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
840#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
841
842/* Instruction Tightly-Coupled Memory Control Register Definitions */
843#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
844#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
845
846#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
847#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
848
849#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
850#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
851
852#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
853#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
854
855/* Data Tightly-Coupled Memory Control Register Definitions */
856#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
857#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
858
859#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
860#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
861
862#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
863#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
864
865#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
866#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
867
868/* AHBP Control Register Definitions */
869#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
870#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
871
872#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
873#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
874
875/* L1 Cache Control Register Definitions */
876#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
877#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
878
879#define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */
880#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */
881
882#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */
883#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */
884
885#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
886#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
887
888/* AHBS Control Register Definitions */
889#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
890#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
891
892#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
893#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
894
895#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
896#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
897
898/* Auxiliary Bus Fault Status Register Definitions */
899#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
900#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
901
902#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
903#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
904
905#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
906#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
907
908#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
909#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
910
911#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
912#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
913
914#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
915#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
916
917/*@} end of group CMSIS_SCB */
918
919
920/**
921 \ingroup CMSIS_core_register
922 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
923 \brief Type definitions for the System Control and ID Register not in the SCB
924 @{
925 */
926
927/**
928 \brief Structure type to access the System Control and ID Register not in the SCB.
929 */
930typedef struct
931{
932 uint32_t RESERVED0[1U];
933 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
934 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
935} SCnSCB_Type;
936
937/* Interrupt Controller Type Register Definitions */
938#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
939#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
940
941/* Auxiliary Control Register Definitions */
942#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */
943#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */
944
945#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */
946#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */
947
948#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */
949#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */
950
951#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */
952#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */
953
954#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */
955#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */
956
957#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */
958#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */
959
960#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
961#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
962
963#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
964#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
965
966#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
967#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
968
969#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
970#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
971
972#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
973#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
974
975/*@} end of group CMSIS_SCnotSCB */
976
977
978/**
979 \ingroup CMSIS_core_register
980 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
981 \brief Type definitions for the System Timer Registers.
982 @{
983 */
984
985/**
986 \brief Structure type to access the System Timer (SysTick).
987 */
988typedef struct
989{
990 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
991 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
992 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
993 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
994} SysTick_Type;
995
996/* SysTick Control / Status Register Definitions */
997#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
998#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
999
1000#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
1001#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
1002
1003#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
1004#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
1005
1006#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
1007#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
1008
1009/* SysTick Reload Register Definitions */
1010#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
1011#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
1012
1013/* SysTick Current Register Definitions */
1014#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
1015#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
1016
1017/* SysTick Calibration Register Definitions */
1018#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
1019#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
1020
1021#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
1022#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
1023
1024#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
1025#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
1026
1027/*@} end of group CMSIS_SysTick */
1028
1029
1030/**
1031 \ingroup CMSIS_core_register
1032 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
1033 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
1034 @{
1035 */
1036
1037/**
1038 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
1039 */
1040typedef struct
1041{
1042 __OM union
1043 {
1044 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
1045 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
1046 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
1047 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
1048 uint32_t RESERVED0[864U];
1049 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
1050 uint32_t RESERVED1[15U];
1051 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
1052 uint32_t RESERVED2[15U];
1053 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
1054 uint32_t RESERVED3[32U];
1055 uint32_t RESERVED4[43U];
1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
1057 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
1058 uint32_t RESERVED5[6U];
1059 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
1060 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
1061 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
1062 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
1063 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
1064 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
1065 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
1066 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
1067 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
1068 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
1069 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
1070 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
1071} ITM_Type;
1072
1073/* ITM Trace Privilege Register Definitions */
1074#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
1075#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
1076
1077/* ITM Trace Control Register Definitions */
1078#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
1079#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
1080
1081#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
1082#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
1083
1084#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
1085#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
1086
1087#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
1088#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
1089
1090#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
1091#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
1092
1093#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
1094#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
1095
1096#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
1097#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
1098
1099#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
1100#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
1101
1102#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
1103#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
1104
1105/* ITM Lock Status Register Definitions */
1106#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
1107#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
1108
1109#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
1110#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
1111
1112#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
1113#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
1114
1115/*@}*/ /* end of group CMSIS_ITM */
1116
1117
1118/**
1119 \ingroup CMSIS_core_register
1120 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
1121 \brief Type definitions for the Data Watchpoint and Trace (DWT)
1122 @{
1123 */
1124
1125/**
1126 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
1127 */
1128typedef struct
1129{
1130 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
1131 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
1132 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
1133 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
1134 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
1135 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
1136 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
1137 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
1138 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
1139 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
1140 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
1141 uint32_t RESERVED0[1U];
1142 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
1143 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
1144 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
1145 uint32_t RESERVED1[1U];
1146 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
1147 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
1148 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
1149 uint32_t RESERVED2[1U];
1150 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
1151 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
1152 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
1153 uint32_t RESERVED3[981U];
1154 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
1155 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1156} DWT_Type;
1157
1158/* DWT Control Register Definitions */
1159#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
1160#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
1161
1162#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
1163#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
1164
1165#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
1166#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
1167
1168#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
1169#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
1170
1171#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
1172#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
1173
1174#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
1175#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
1176
1177#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
1178#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
1179
1180#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
1181#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
1182
1183#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
1184#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
1185
1186#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
1187#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
1188
1189#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
1190#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
1191
1192#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
1193#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
1194
1195#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
1196#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
1197
1198#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
1199#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
1200
1201#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
1202#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
1203
1204#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
1205#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
1206
1207#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
1208#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
1209
1210#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
1211#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
1212
1213/* DWT CPI Count Register Definitions */
1214#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
1215#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
1216
1217/* DWT Exception Overhead Count Register Definitions */
1218#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
1219#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
1220
1221/* DWT Sleep Count Register Definitions */
1222#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
1223#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
1224
1225/* DWT LSU Count Register Definitions */
1226#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
1227#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
1228
1229/* DWT Folded-instruction Count Register Definitions */
1230#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
1231#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
1232
1233/* DWT Comparator Mask Register Definitions */
1234#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
1235#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
1236
1237/* DWT Comparator Function Register Definitions */
1238#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
1239#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
1240
1241#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
1242#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
1243
1244#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
1245#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
1246
1247#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
1248#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
1249
1250#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
1251#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
1252
1253#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
1254#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
1255
1256#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
1257#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
1258
1259#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
1260#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
1261
1262#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
1263#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
1264
1265/*@}*/ /* end of group CMSIS_DWT */
1266
1267
1268/**
1269 \ingroup CMSIS_core_register
1270 \defgroup CMSIS_TPI Trace Port Interface (TPI)
1271 \brief Type definitions for the Trace Port Interface (TPI)
1272 @{
1273 */
1274
1275/**
1276 \brief Structure type to access the Trace Port Interface Register (TPI).
1277 */
1278typedef struct
1279{
1280 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
1281 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
1282 uint32_t RESERVED0[2U];
1283 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1284 uint32_t RESERVED1[55U];
1285 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1286 uint32_t RESERVED2[131U];
1287 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1288 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1289 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
1290 uint32_t RESERVED3[759U];
1291 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1292 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1293 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1294 uint32_t RESERVED4[1U];
1295 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1296 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1297 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1298 uint32_t RESERVED5[39U];
1299 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1300 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1301 uint32_t RESERVED7[8U];
1302 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1303 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
1304} TPI_Type;
1305
1306/* TPI Asynchronous Clock Prescaler Register Definitions */
1307#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
1308#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
1309
1310/* TPI Selected Pin Protocol Register Definitions */
1311#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
1312#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
1313
1314/* TPI Formatter and Flush Status Register Definitions */
1315#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
1316#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
1317
1318#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
1319#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
1320
1321#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
1322#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
1323
1324#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
1325#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
1326
1327/* TPI Formatter and Flush Control Register Definitions */
1328#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
1329#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
1330
1331#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
1332#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
1333
1334/* TPI TRIGGER Register Definitions */
1335#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
1336#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
1337
1338/* TPI Integration ETM Data Register Definitions (FIFO0) */
1339#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
1340#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
1341
1342#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
1343#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
1344
1345#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
1346#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
1347
1348#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
1349#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
1350
1351#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
1352#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
1353
1354#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
1355#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
1356
1357#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
1358#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
1359
1360/* TPI ITATBCTR2 Register Definitions */
1361#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
1362#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
1363
1364#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
1365#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
1366
1367/* TPI Integration ITM Data Register Definitions (FIFO1) */
1368#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
1369#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
1370
1371#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
1372#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
1373
1374#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
1375#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
1376
1377#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
1378#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
1379
1380#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
1381#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
1382
1383#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
1384#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
1385
1386#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
1387#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
1388
1389/* TPI ITATBCTR0 Register Definitions */
1390#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
1391#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
1392
1393#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
1394#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
1395
1396/* TPI Integration Mode Control Register Definitions */
1397#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
1398#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
1399
1400/* TPI DEVID Register Definitions */
1401#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
1402#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1403
1404#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
1405#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1406
1407#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
1408#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1409
1410#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
1411#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1412
1413#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
1414#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1415
1416#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
1417#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
1418
1419/* TPI DEVTYPE Register Definitions */
1420#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
1421#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
1422
1423#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
1424#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1425
1426/*@}*/ /* end of group CMSIS_TPI */
1427
1428
1429#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1430/**
1431 \ingroup CMSIS_core_register
1432 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1433 \brief Type definitions for the Memory Protection Unit (MPU)
1434 @{
1435 */
1436
1437/**
1438 \brief Structure type to access the Memory Protection Unit (MPU).
1439 */
1440typedef struct
1441{
1442 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1443 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1444 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1445 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1446 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1447 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1448 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1449 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1450 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1451 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1452 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1453} MPU_Type;
1454
1455#define MPU_TYPE_RALIASES 4U
1456
1457/* MPU Type Register Definitions */
1458#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1459#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1460
1461#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1462#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1463
1464#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1465#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1466
1467/* MPU Control Register Definitions */
1468#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1469#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1470
1471#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1472#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1473
1474#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1475#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1476
1477/* MPU Region Number Register Definitions */
1478#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1479#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1480
1481/* MPU Region Base Address Register Definitions */
1482#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
1483#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1484
1485#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
1486#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1487
1488#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
1489#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
1490
1491/* MPU Region Attribute and Size Register Definitions */
1492#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
1493#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1494
1495#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
1496#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1497
1498#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
1499#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1500
1501#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
1502#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1503
1504#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
1505#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1506
1507#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
1508#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1509
1510#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
1511#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1512
1513#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
1514#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1515
1516#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
1517#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1518
1519#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
1520#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
1521
1522/*@} end of group CMSIS_MPU */
1523#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
1524
1525
1526/**
1527 \ingroup CMSIS_core_register
1528 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1529 \brief Type definitions for the Floating Point Unit (FPU)
1530 @{
1531 */
1532
1533/**
1534 \brief Structure type to access the Floating Point Unit (FPU).
1535 */
1536typedef struct
1537{
1538 uint32_t RESERVED0[1U];
1539 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1540 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1541 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1542 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
1543 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
1544 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
1545} FPU_Type;
1546
1547/* Floating-Point Context Control Register Definitions */
1548#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
1549#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1550
1551#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
1552#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1553
1554#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
1555#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1556
1557#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
1558#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1559
1560#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
1561#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1562
1563#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
1564#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1565
1566#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
1567#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1568
1569#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
1570#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1571
1572#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
1573#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
1574
1575/* Floating-Point Context Address Register Definitions */
1576#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
1577#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1578
1579/* Floating-Point Default Status Control Register Definitions */
1580#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
1581#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1582
1583#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
1584#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1585
1586#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
1587#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1588
1589#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
1590#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1591
1592/* Media and FP Feature Register 0 Definitions */
1593#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
1594#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
1595
1596#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
1597#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
1598
1599#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
1600#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
1601
1602#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
1603#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
1604
1605#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
1606#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
1607
1608#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
1609#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
1610
1611#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
1612#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
1613
1614#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
1615#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
1616
1617/* Media and FP Feature Register 1 Definitions */
1618#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
1619#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
1620
1621#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
1622#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1623
1624#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
1625#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1626
1627#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
1628#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
1629
1630/* Media and FP Feature Register 2 Definitions */
1631
1632#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
1633#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */
1634
1635/*@} end of group CMSIS_FPU */
1636
1637
1638/**
1639 \ingroup CMSIS_core_register
1640 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1641 \brief Type definitions for the Core Debug Registers
1642 @{
1643 */
1644
1645/**
1646 \brief Structure type to access the Core Debug Register (CoreDebug).
1647 */
1648typedef struct
1649{
1650 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1651 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1652 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1653 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1654} CoreDebug_Type;
1655
1656/* Debug Halting Control and Status Register Definitions */
1657#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
1658#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1659
1660#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
1661#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1662
1663#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1664#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1665
1666#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
1667#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1668
1669#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
1670#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1671
1672#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
1673#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1674
1675#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
1676#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1677
1678#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1679#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1680
1681#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
1682#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1683
1684#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
1685#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1686
1687#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
1688#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1689
1690#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1691#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1692
1693/* Debug Core Register Selector Register Definitions */
1694#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
1695#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1696
1697#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
1698#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
1699
1700/* Debug Exception and Monitor Control Register Definitions */
1701#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
1702#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1703
1704#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
1705#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1706
1707#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
1708#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1709
1710#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
1711#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1712
1713#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
1714#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1715
1716#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
1717#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1718
1719#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
1720#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1721
1722#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
1723#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1724
1725#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
1726#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1727
1728#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
1729#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1730
1731#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1732#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1733
1734#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
1735#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1736
1737#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
1738#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1739
1740/*@} end of group CMSIS_CoreDebug */
1741
1742
1743/**
1744 \ingroup CMSIS_core_register
1745 \defgroup CMSIS_core_bitfield Core register bit field macros
1746 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1747 @{
1748 */
1749
1750/**
1751 \brief Mask and shift a bit field value for use in a register bit range.
1752 \param[in] field Name of the register bit field.
1753 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1754 \return Masked and shifted value.
1755*/
1756#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1757
1758/**
1759 \brief Mask and shift a register value to extract a bit filed value.
1760 \param[in] field Name of the register bit field.
1761 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
1762 \return Masked and shifted bit field value.
1763*/
1764#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1765
1766/*@} end of group CMSIS_core_bitfield */
1767
1768
1769/**
1770 \ingroup CMSIS_core_register
1771 \defgroup CMSIS_core_base Core Definitions
1772 \brief Definitions for base addresses, unions, and structures.
1773 @{
1774 */
1775
1776/* Memory mapping of Core Hardware */
1777#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1778#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1779#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1780#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1781#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1782#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1783#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1784#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1785
1786#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1787#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1788#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1789#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1790#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1791#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1792#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1793#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1794
1795#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1796 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1797 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1798#endif
1799
1800#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
1801#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
1802
1803/*@} */
1804
1805
1806
1807/*******************************************************************************
1808 * Hardware Abstraction Layer
1809 Core Function Interface contains:
1810 - Core NVIC Functions
1811 - Core SysTick Functions
1812 - Core Debug Functions
1813 - Core Register Access Functions
1814 ******************************************************************************/
1815/**
1816 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1817*/
1818
1819
1820
1821/* ########################## NVIC functions #################################### */
1822/**
1823 \ingroup CMSIS_Core_FunctionInterface
1824 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1825 \brief Functions that manage interrupts and exceptions via the NVIC.
1826 @{
1827 */
1828
1829#ifdef CMSIS_NVIC_VIRTUAL
1830 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1831 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1832 #endif
1833 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1834#else
1835 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1836 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1837 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1838 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1839 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1840 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1841 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1842 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1843 #define NVIC_GetActive __NVIC_GetActive
1844 #define NVIC_SetPriority __NVIC_SetPriority
1845 #define NVIC_GetPriority __NVIC_GetPriority
1846 #define NVIC_SystemReset __NVIC_SystemReset
1847#endif /* CMSIS_NVIC_VIRTUAL */
1848
1849#ifdef CMSIS_VECTAB_VIRTUAL
1850 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1851 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1852 #endif
1853 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1854#else
1855 #define NVIC_SetVector __NVIC_SetVector
1856 #define NVIC_GetVector __NVIC_GetVector
1857#endif /* (CMSIS_VECTAB_VIRTUAL) */
1858
1859#define NVIC_USER_IRQ_OFFSET 16
1860
1861
1862/* The following EXC_RETURN values are saved the LR on exception entry */
1863#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
1864#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
1865#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
1866#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
1867#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
1868#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
1869
1870
1871/**
1872 \brief Set Priority Grouping
1873 \details Sets the priority grouping field using the required unlock sequence.
1874 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1875 Only values from 0..7 are used.
1876 In case of a conflict between priority grouping and available
1877 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1878 \param [in] PriorityGroup Priority grouping field.
1879 */
1880__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1881{
1882 uint32_t reg_value;
1883 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1884
1885 reg_value = SCB->AIRCR; /* read old register configuration */
1886 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1887 reg_value = (reg_value |
1888 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1889 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
1890 SCB->AIRCR = reg_value;
1891}
1892
1893
1894/**
1895 \brief Get Priority Grouping
1896 \details Reads the priority grouping field from the NVIC Interrupt Controller.
1897 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1898 */
1899__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
1900{
1901 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1902}
1903
1904
1905/**
1906 \brief Enable Interrupt
1907 \details Enables a device specific interrupt in the NVIC interrupt controller.
1908 \param [in] IRQn Device specific interrupt number.
1909 \note IRQn must not be negative.
1910 */
1911__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1912{
1913 if ((int32_t)(IRQn) >= 0)
1914 {
1915 __COMPILER_BARRIER();
1916 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1917 __COMPILER_BARRIER();
1918 }
1919}
1920
1921
1922/**
1923 \brief Get Interrupt Enable status
1924 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
1925 \param [in] IRQn Device specific interrupt number.
1926 \return 0 Interrupt is not enabled.
1927 \return 1 Interrupt is enabled.
1928 \note IRQn must not be negative.
1929 */
1930__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1931{
1932 if ((int32_t)(IRQn) >= 0)
1933 {
1934 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1935 }
1936 else
1937 {
1938 return(0U);
1939 }
1940}
1941
1942
1943/**
1944 \brief Disable Interrupt
1945 \details Disables a device specific interrupt in the NVIC interrupt controller.
1946 \param [in] IRQn Device specific interrupt number.
1947 \note IRQn must not be negative.
1948 */
1949__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1950{
1951 if ((int32_t)(IRQn) >= 0)
1952 {
1953 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1954 __DSB();
1955 __ISB();
1956 }
1957}
1958
1959
1960/**
1961 \brief Get Pending Interrupt
1962 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
1963 \param [in] IRQn Device specific interrupt number.
1964 \return 0 Interrupt status is not pending.
1965 \return 1 Interrupt status is pending.
1966 \note IRQn must not be negative.
1967 */
1968__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1969{
1970 if ((int32_t)(IRQn) >= 0)
1971 {
1972 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1973 }
1974 else
1975 {
1976 return(0U);
1977 }
1978}
1979
1980
1981/**
1982 \brief Set Pending Interrupt
1983 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
1984 \param [in] IRQn Device specific interrupt number.
1985 \note IRQn must not be negative.
1986 */
1987__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1988{
1989 if ((int32_t)(IRQn) >= 0)
1990 {
1991 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1992 }
1993}
1994
1995
1996/**
1997 \brief Clear Pending Interrupt
1998 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
1999 \param [in] IRQn Device specific interrupt number.
2000 \note IRQn must not be negative.
2001 */
2002__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2003{
2004 if ((int32_t)(IRQn) >= 0)
2005 {
2006 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2007 }
2008}
2009
2010
2011/**
2012 \brief Get Active Interrupt
2013 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
2014 \param [in] IRQn Device specific interrupt number.
2015 \return 0 Interrupt status is not active.
2016 \return 1 Interrupt status is active.
2017 \note IRQn must not be negative.
2018 */
2019__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2020{
2021 if ((int32_t)(IRQn) >= 0)
2022 {
2023 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2024 }
2025 else
2026 {
2027 return(0U);
2028 }
2029}
2030
2031
2032/**
2033 \brief Set Interrupt Priority
2034 \details Sets the priority of a device specific interrupt or a processor exception.
2035 The interrupt number can be positive to specify a device specific interrupt,
2036 or negative to specify a processor exception.
2037 \param [in] IRQn Interrupt number.
2038 \param [in] priority Priority to set.
2039 \note The priority cannot be set for every processor exception.
2040 */
2041__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2042{
2043 if ((int32_t)(IRQn) >= 0)
2044 {
2045 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2046 }
2047 else
2048 {
2049 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2050 }
2051}
2052
2053
2054/**
2055 \brief Get Interrupt Priority
2056 \details Reads the priority of a device specific interrupt or a processor exception.
2057 The interrupt number can be positive to specify a device specific interrupt,
2058 or negative to specify a processor exception.
2059 \param [in] IRQn Interrupt number.
2060 \return Interrupt Priority.
2061 Value is aligned automatically to the implemented priority bits of the microcontroller.
2062 */
2063__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2064{
2065
2066 if ((int32_t)(IRQn) >= 0)
2067 {
2068 return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2069 }
2070 else
2071 {
2072 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2073 }
2074}
2075
2076
2077/**
2078 \brief Encode Priority
2079 \details Encodes the priority for an interrupt with the given priority group,
2080 preemptive priority value, and subpriority value.
2081 In case of a conflict between priority grouping and available
2082 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2083 \param [in] PriorityGroup Used priority group.
2084 \param [in] PreemptPriority Preemptive priority value (starting from 0).
2085 \param [in] SubPriority Subpriority value (starting from 0).
2086 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
2087 */
2088__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2089{
2090 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2091 uint32_t PreemptPriorityBits;
2092 uint32_t SubPriorityBits;
2093
2094 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2095 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2096
2097 return (
2098 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2099 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2100 );
2101}
2102
2103
2104/**
2105 \brief Decode Priority
2106 \details Decodes an interrupt priority value with a given priority group to
2107 preemptive priority value and subpriority value.
2108 In case of a conflict between priority grouping and available
2109 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
2110 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
2111 \param [in] PriorityGroup Used priority group.
2112 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
2113 \param [out] pSubPriority Subpriority value (starting from 0).
2114 */
2115__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2116{
2117 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2118 uint32_t PreemptPriorityBits;
2119 uint32_t SubPriorityBits;
2120
2121 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2122 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2123
2124 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2125 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2126}
2127
2128
2129/**
2130 \brief Set Interrupt Vector
2131 \details Sets an interrupt vector in SRAM based interrupt vector table.
2132 The interrupt number can be positive to specify a device specific interrupt,
2133 or negative to specify a processor exception.
2134 VTOR must been relocated to SRAM before.
2135 \param [in] IRQn Interrupt number
2136 \param [in] vector Address of interrupt handler function
2137 */
2138__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2139{
2140 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2141 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2142 __DSB();
2143}
2144
2145
2146/**
2147 \brief Get Interrupt Vector
2148 \details Reads an interrupt vector from interrupt vector table.
2149 The interrupt number can be positive to specify a device specific interrupt,
2150 or negative to specify a processor exception.
2151 \param [in] IRQn Interrupt number.
2152 \return Address of interrupt handler function
2153 */
2154__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2155{
2156 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2157 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2158}
2159
2160
2161/**
2162 \brief System Reset
2163 \details Initiates a system reset request to reset the MCU.
2164 */
2165__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
2166{
2167 __DSB(); /* Ensure all outstanding memory accesses included
2168 buffered write are completed before reset */
2169 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2170 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2171 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2172 __DSB(); /* Ensure completion of memory access */
2173
2174 for(;;) /* wait until reset */
2175 {
2176 __NOP();
2177 }
2178}
2179
2180/*@} end of CMSIS_Core_NVICFunctions */
2181
2182
2183/* ########################## MPU functions #################################### */
2184
2185#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2186
2187#include "mpu_armv7.h"
2188
2189#endif
2190
2191
2192/* ########################## FPU functions #################################### */
2193/**
2194 \ingroup CMSIS_Core_FunctionInterface
2195 \defgroup CMSIS_Core_FpuFunctions FPU Functions
2196 \brief Function that provides FPU type.
2197 @{
2198 */
2199
2200/**
2201 \brief get FPU type
2202 \details returns the FPU type
2203 \returns
2204 - \b 0: No FPU
2205 - \b 1: Single precision FPU
2206 - \b 2: Double + Single precision FPU
2207 */
2208__STATIC_INLINE uint32_t SCB_GetFPUType(void)
2209{
2210 uint32_t mvfr0;
2211
2212 mvfr0 = SCB->MVFR0;
2213 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
2214 {
2215 return 2U; /* Double + Single precision FPU */
2216 }
2217 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2218 {
2219 return 1U; /* Single precision FPU */
2220 }
2221 else
2222 {
2223 return 0U; /* No FPU */
2224 }
2225}
2226
2227/*@} end of CMSIS_Core_FpuFunctions */
2228
2229
2230/* ########################## Cache functions #################################### */
2231
2232#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
2233 (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
2234#include "cachel1_armv7.h"
2235#endif
2236
2237
2238/* ################################## SysTick function ############################################ */
2239/**
2240 \ingroup CMSIS_Core_FunctionInterface
2241 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
2242 \brief Functions that configure the System.
2243 @{
2244 */
2245
2246#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2247
2248/**
2249 \brief System Tick Configuration
2250 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
2251 Counter is in free running mode to generate periodic interrupts.
2252 \param [in] ticks Number of ticks between two interrupts.
2253 \return 0 Function succeeded.
2254 \return 1 Function failed.
2255 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2256 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
2257 must contain a vendor-specific implementation of this function.
2258 */
2259__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2260{
2261 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2262 {
2263 return (1UL); /* Reload value impossible */
2264 }
2265
2266 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2267 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2268 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2269 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2270 SysTick_CTRL_TICKINT_Msk |
2271 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2272 return (0UL); /* Function successful */
2273}
2274
2275#endif
2276
2277/*@} end of CMSIS_Core_SysTickFunctions */
2278
2279
2280
2281/* ##################################### Debug In/Output function ########################################### */
2282/**
2283 \ingroup CMSIS_Core_FunctionInterface
2284 \defgroup CMSIS_core_DebugFunctions ITM Functions
2285 \brief Functions that access the ITM debug interface.
2286 @{
2287 */
2288
2289extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
2290#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
2291
2292
2293/**
2294 \brief ITM Send Character
2295 \details Transmits a character via the ITM channel 0, and
2296 \li Just returns when no debugger is connected that has booked the output.
2297 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
2298 \param [in] ch Character to transmit.
2299 \returns Character to transmit.
2300 */
2301__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2302{
2303 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2304 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2305 {
2306 while (ITM->PORT[0U].u32 == 0UL)
2307 {
2308 __NOP();
2309 }
2310 ITM->PORT[0U].u8 = (uint8_t)ch;
2311 }
2312 return (ch);
2313}
2314
2315
2316/**
2317 \brief ITM Receive Character
2318 \details Inputs a character via the external variable \ref ITM_RxBuffer.
2319 \return Received character.
2320 \return -1 No character pending.
2321 */
2322__STATIC_INLINE int32_t ITM_ReceiveChar (void)
2323{
2324 int32_t ch = -1; /* no character available */
2325
2326 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2327 {
2328 ch = ITM_RxBuffer;
2329 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2330 }
2331
2332 return (ch);
2333}
2334
2335
2336/**
2337 \brief ITM Check Character
2338 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
2339 \return 0 No character available.
2340 \return 1 Character available.
2341 */
2342__STATIC_INLINE int32_t ITM_CheckChar (void)
2343{
2344
2345 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2346 {
2347 return (0); /* no character available */
2348 }
2349 else
2350 {
2351 return (1); /* character available */
2352 }
2353}
2354
2355/*@} end of CMSIS_core_DebugFunctions */
2356
2357
2358
2359
2360#ifdef __cplusplus
2361}
2362#endif
2363
2364#endif /* __CORE_CM7_H_DEPENDANT */
2365
2366#endif /* __CMSIS_GENERIC */
cachel1_armv7.h
__NO_RETURN
#define __NO_RETURN
Definition cmsis_armcc.h:70
__COMPILER_BARRIER
#define __COMPILER_BARRIER()
Definition cmsis_armcc.h:109
__STATIC_INLINE
#define __STATIC_INLINE
Definition cmsis_armcc.h:64
cmsis_compiler.h
CMSIS compiler generic header file.
cmsis_version.h
CMSIS Core(M) Version definitions.
__OM
#define __OM
Definition core_armv81mml.h:294
__IM
#define __IM
Definition core_armv81mml.h:293
__IOM
#define __IOM
Definition core_armv81mml.h:295
__OM
#define __OM
Definition core_starmc1.h:293
__IM
#define __IM
Definition core_starmc1.h:292
__IOM
#define __IOM
Definition core_starmc1.h:294
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
SysTick CTRL: ENABLE Mask.
Definition core_armv81mml.h:1045
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
SysTick LOAD: RELOAD Mask.
Definition core_armv81mml.h:1049
FPU_MVFR0_Double_precision_Msk
#define FPU_MVFR0_Double_precision_Msk
MVFR0: Double-precision bits Mask.
Definition core_armv8mml.h:1698
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
ITM TCR: ITM Enable bit Mask.
Definition core_armv81mml.h:1154
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
SCB AIRCR: PRIGROUP Mask.
Definition core_armv81mml.h:639
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
SCB AIRCR: VECTKEY Mask.
Definition core_armv81mml.h:624
FPU_MVFR0_Single_precision_Msk
#define FPU_MVFR0_Single_precision_Msk
MVFR0: Single-precision bits Mask.
Definition core_armv8mml.h:1701
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
SysTick CTRL: TICKINT Mask.
Definition core_armv81mml.h:1042
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
SysTick CTRL: CLKSOURCE Mask.
Definition core_armv81mml.h:1039
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
SCB AIRCR: VECTKEY Position.
Definition core_armv81mml.h:623
SCB
#define SCB
SCB configuration struct.
Definition core_armv81mml.h:3106
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
SCB AIRCR: SYSRESETREQ Mask.
Definition core_armv81mml.h:651
ITM
#define ITM
ITM configuration struct.
Definition core_armv81mml.h:3109
NVIC
#define NVIC
NVIC configuration struct.
Definition core_armv81mml.h:3108
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
SCB AIRCR: PRIGROUP Position.
Definition core_armv81mml.h:638
SysTick
#define SysTick
SysTick configuration struct.
Definition core_armv81mml.h:3107
__NVIC_SetPriorityGrouping
#define __NVIC_SetPriorityGrouping(X)
Definition core_armv8mbl.h:1440
__NVIC_GetPriorityGrouping
#define __NVIC_GetPriorityGrouping()
Get Priority Grouping.
Definition core_armv8mbl.h:1441
__DSB
#define __DSB()
Data Synchronization Barrier.
Definition cmsis_armcc.h:182
__ISB
#define __ISB()
Instruction Synchronization Barrier.
Definition cmsis_armcc.h:175
__NOP
#define __NOP
No Operation.
Definition cmsis_armcc.h:144
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition core_armv81mml.h:3611
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition core_armv81mml.h:3584
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition core_armv81mml.h:3561
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition core_armv81mml.h:3600
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition core_armv81mml.h:3487
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition core_armv81mml.h:3381
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition core_armv81mml.h:3347
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition core_armv81mml.h:3862
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition core_armv81mml.h:3290
NVIC_USER_IRQ_OFFSET
#define NVIC_USER_IRQ_OFFSET
Definition core_armv81mml.h:3225
__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition core_armv81mml.h:3398
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition core_armv81mml.h:3366
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition core_armv81mml.h:3309
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition core_armv81mml.h:3534
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition core_armv81mml.h:3328
NVIC_SetPriority
#define NVIC_SetPriority
Definition core_cm7.h:1844
SysTick_Config
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Definition core_armv81mml.h:4091
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition core_armv81mml.h:3509
SCB_Type::RESERVED0
uint32_t RESERVED0
Definition core_armv8mbl.h:390
SCB_Type::DCCMVAC
__OM uint32_t DCCMVAC
Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC.
Definition core_armv81mml.h:555
SCB_Type::AHBPCR
__IOM uint32_t AHBPCR
Offset: 0x298 (R/W) AHBP Control Register.
Definition core_cm7.h:508
xPSR_Type::@110032104134153262135352365045213354132277276257::ISR
uint32_t ISR
bit: 0.
Definition core_cm7.h:340
SCB_Type::RESERVED6
uint32_t RESERVED6[1U]
Definition core_armv81mml.h:550
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
External variable to receive characters.
APSR_Type::@346325020050364244253017031205121042066344265156::_reserved0
uint32_t _reserved0
bit: 0..15 Reserved
Definition core_cm7.h:283
SCB_Type::DCISW
__OM uint32_t DCISW
Offset: 0x260 ( /W) D-Cache Invalidate by Set-way.
Definition core_armv81mml.h:553
SCB_Type::MVFR2
__IM uint32_t MVFR2
Offset: 0x248 (R/ ) Media and VFP Feature Register 2.
Definition core_armv81mml.h:547
SCB_Type::DTCMCR
__IOM uint32_t DTCMCR
Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers.
Definition core_cm7.h:507
APSR_Type::@346325020050364244253017031205121042066344265156::GE
uint32_t GE
bit: 16..19 Greater than or Equal flags
Definition core_cm7.h:284
ITM_Type::@345054245047314041340112351057146113330103110047::u8
__OM uint8_t u8
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit.
Definition core_cm7.h:1044
ITM_Type::@345054245047314041340112351057146113330103110047::u32
__OM uint32_t u32
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit.
Definition core_cm7.h:1046
APSR_Type::@346325020050364244253017031205121042066344265156::Q
uint32_t Q
bit: 27 Saturation condition flag
Definition core_cm7.h:286
APSR_Type::@346325020050364244253017031205121042066344265156::_reserved1
uint32_t _reserved1
bit: 20..26 Reserved
Definition core_cm7.h:285
SCB_Type::ABFSR
__IOM uint32_t ABFSR
Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register.
Definition core_cm7.h:512
SCB_Type::RESERVED8
uint32_t RESERVED8[1U]
Definition core_cm7.h:511
CONTROL_Type::@071163213331312025104010137211370167142341364310::SPSEL
uint32_t SPSEL
bit: 1 Stack to be used
Definition core_cm7.h:396
DWT_Type::LSR
__IM uint32_t LSR
Offset: 0xFB4 (R ) Lock Status Register.
Definition core_armv81mml.h:1253
DWT_Type::LAR
__OM uint32_t LAR
Offset: 0xFB0 ( W) Lock Access Register.
Definition core_cm7.h:1154
SCB_Type::DCIMVAC
__OM uint32_t DCIMVAC
Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC.
Definition core_armv81mml.h:552
SCB_Type::DCCIMVAC
__OM uint32_t DCCIMVAC
Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC.
Definition core_armv81mml.h:557
SCB_Type::CACR
__IOM uint32_t CACR
Offset: 0x29C (R/W) L1 Cache Control Register.
Definition core_cm7.h:509
xPSR_Type::@110032104134153262135352365045213354132277276257::C
uint32_t C
bit: 29 Carry condition code flag
Definition core_cm7.h:349
SCB_Type::ICIALLU
__OM uint32_t ICIALLU
Offset: 0x250 ( /W) I-Cache Invalidate All to PoU.
Definition core_armv81mml.h:549
SCB_Type::ID_ISAR
__IM uint32_t ID_ISAR[6U]
Offset: 0x060 (R/ ) Instruction Set Attributes Register.
Definition core_armv81mml.h:531
SCB_Type::ICIMVAU
__OM uint32_t ICIMVAU
Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU.
Definition core_armv81mml.h:551
ITM_Type::@345054245047314041340112351057146113330103110047::u16
__OM uint16_t u16
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit.
Definition core_cm7.h:1045
APSR_Type::@346325020050364244253017031205121042066344265156::Z
uint32_t Z
bit: 30 Zero condition code flag
Definition core_cm7.h:289
xPSR_Type::@110032104134153262135352365045213354132277276257::Q
uint32_t Q
bit: 27 Saturation condition flag
Definition core_cm7.h:347
SCB_Type::MVFR1
__IM uint32_t MVFR1
Offset: 0x244 (R/ ) Media and VFP Feature Register 1.
Definition core_armv81mml.h:546
SCB_Type::RESERVED3
uint32_t RESERVED3[69U]
Definition core_armv81mml.h:541
SCB_Type::ID_MFR
__IM uint32_t ID_MFR[4U]
Offset: 0x050 (R/ ) Memory Model Feature Register.
Definition core_cm7.h:479
SCB_Type::MVFR0
__IM uint32_t MVFR0
Offset: 0x240 (R/ ) Media and VFP Feature Register 0.
Definition core_armv81mml.h:545
CONTROL_Type::@071163213331312025104010137211370167142341364310::FPCA
uint32_t FPCA
bit: 2 FP extension active flag
Definition core_cm7.h:397
APSR_Type::@346325020050364244253017031205121042066344265156::C
uint32_t C
bit: 29 Carry condition code flag
Definition core_cm7.h:288
CONTROL_Type::@071163213331312025104010137211370167142341364310::_reserved0
uint32_t _reserved0
bit: 3..31 Reserved
Definition core_cm7.h:398
xPSR_Type::@110032104134153262135352365045213354132277276257::_reserved0
uint32_t _reserved0
bit: 9 Reserved
Definition core_cm7.h:341
SCB_Type::AHBSCR
__IOM uint32_t AHBSCR
Offset: 0x2A0 (R/W) AHB Slave Control Register.
Definition core_cm7.h:510
xPSR_Type::@110032104134153262135352365045213354132277276257::ICI_IT_2
uint32_t ICI_IT_2
bit: 25..26 ICI/IT part 2
Definition core_cm7.h:346
APSR_Type::@346325020050364244253017031205121042066344265156::N
uint32_t N
bit: 31 Negative condition code flag
Definition core_cm7.h:290
xPSR_Type::@110032104134153262135352365045213354132277276257::N
uint32_t N
bit: 31 Negative condition code flag
Definition core_cm7.h:351
APSR_Type::@346325020050364244253017031205121042066344265156::V
uint32_t V
bit: 28 Overflow condition code flag
Definition core_cm7.h:287
SCB_Type::RESERVED7
uint32_t RESERVED7[21U]
Definition core_armv81mml.h:538
xPSR_Type::@110032104134153262135352365045213354132277276257::Z
uint32_t Z
bit: 30 Zero condition code flag
Definition core_cm7.h:350
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Value identifying ITM_RxBuffer is ready for next character.
Definition core_armv81mml.h:4152
xPSR_Type::@110032104134153262135352365045213354132277276257::T
uint32_t T
bit: 24 Thumb bit
Definition core_cm7.h:345
IPSR_Type::@174102030375103342057030027301204361202220137361::ISR
uint32_t ISR
bit: 0.
Definition core_cm7.h:322
SCB_Type::DCCMVAU
__OM uint32_t DCCMVAU
Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU.
Definition core_armv81mml.h:554
SCB_Type::BPIALL
__OM uint32_t BPIALL
Offset: 0x278 ( /W) Branch Predictor Invalidate All.
Definition core_armv81mml.h:559
SCB_Type::DCCSW
__OM uint32_t DCCSW
Offset: 0x26C ( /W) D-Cache Clean by Set-way.
Definition core_armv81mml.h:556
CONTROL_Type::@071163213331312025104010137211370167142341364310::nPRIV
uint32_t nPRIV
bit: 0 Execution privilege in Thread mode
Definition core_cm7.h:395
SCB_Type::ITCMCR
__IOM uint32_t ITCMCR
Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register.
Definition core_cm7.h:506
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition core_armv81mml.h:4184
SCB_Type::CPACR
__IOM uint32_t CPACR
Offset: 0x088 (R/W) Coprocessor Access Control Register.
Definition core_armv81mml.h:536
ITM_SendChar
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
ITM Send Character.
Definition core_armv81mml.h:4163
xPSR_Type::@110032104134153262135352365045213354132277276257::_reserved1
uint32_t _reserved1
bit: 20..23 Reserved
Definition core_cm7.h:344
SCB_Type::CSSELR
__IOM uint32_t CSSELR
Offset: 0x084 (R/W) Cache Size Selection Register.
Definition core_armv81mml.h:535
SCB_Type::STIR
__OM uint32_t STIR
Offset: 0x200 ( /W) Software Triggered Interrupt Register.
Definition core_armv81mml.h:542
SCB_Type::CLIDR
__IM uint32_t CLIDR
Offset: 0x078 (R/ ) Cache Level ID register.
Definition core_armv81mml.h:532
xPSR_Type::@110032104134153262135352365045213354132277276257::V
uint32_t V
bit: 28 Overflow condition code flag
Definition core_cm7.h:348
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition core_armv81mml.h:4204
IPSR_Type::@174102030375103342057030027301204361202220137361::_reserved0
uint32_t _reserved0
bit: 9..31 Reserved
Definition core_cm7.h:323
xPSR_Type::@110032104134153262135352365045213354132277276257::GE
uint32_t GE
bit: 16..19 Greater than or Equal flags
Definition core_cm7.h:343
SCB_Type::RESERVED5
uint32_t RESERVED5[1U]
Definition core_armv81mml.h:548
SCB_Type::CTR
__IM uint32_t CTR
Offset: 0x07C (R/ ) Cache Type register.
Definition core_armv81mml.h:533
SCB_Type::DCCISW
__OM uint32_t DCCISW
Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way.
Definition core_armv81mml.h:558
SCB_Type::RESERVED4
uint32_t RESERVED4[14U]
Definition core_armv81mml.h:544
xPSR_Type::@110032104134153262135352365045213354132277276257::ICI_IT_1
uint32_t ICI_IT_1
bit: 10..15 ICI/IT part 1
Definition core_cm7.h:342
SCB_Type::CCSIDR
__IM uint32_t CCSIDR
Offset: 0x080 (R/ ) Cache Size ID Register.
Definition core_armv81mml.h:534
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
CM7 uses 4 Bits for the Priority Levels.
Definition stm32h723xx.h:216
COMP2
#define COMP2
Definition stm32h723xx.h:2470
COMP1
#define COMP1
Definition stm32h723xx.h:2469
IRQn_Type
IRQn_Type
STM32H7XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32h723xx.h:49
SysTick_IRQn
@ SysTick_IRQn
15 Cortex-M System Tick Interrupt
Definition stm32h723xx.h:59
b
*brief create JSON pointer *sa reference_tokens const string_t const string_t & b
Definition json.hpp:13878
mpu_armv7.h
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition core_armv81mml.h:2624
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition core_armv81mml.h:1180
FPU_Type
Structure type to access the Floating Point Unit (FPU).
Definition core_armv81mml.h:2483
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition core_armv81mml.h:1079
MPU_Type
Structure type to access the Memory Protection Unit (MPU).
Definition core_armv81mml.h:2281
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition core_armv81mml.h:476
SCB_Type
Structure type to access the System Control Block (SCB).
Definition core_armv81mml.h:512
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition core_armv81mml.h:1002
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition core_armv81mml.h:1027
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition core_armv81mml.h:1366
ch
static std::string ch(int ain, const std::string &kind, const std::string &extra="", const std::string &board="lj")
Definition test_t7.cpp:98
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition core_armv81mml.h:329
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition core_armv81mml.h:437
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition core_armv81mml.h:368
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition core_armv81mml.h:386