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core_sc300.h
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1/**************************************************************************//**
2 * @file core_sc300.h
3 * @brief CMSIS SC300 Core Peripheral Access Layer Header File
4 * @version V5.0.10
5 * @date 04. June 2021
6 ******************************************************************************/
7/*
8 * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25#if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27#elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29#endif
30
31#ifndef __CORE_SC300_H_GENERIC
32#define __CORE_SC300_H_GENERIC
33
34#include <stdint.h>
35
36#ifdef __cplusplus
37 extern "C" {
38#endif
39
40/**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55/*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58/**
59 \ingroup SC3000
60 @{
61 */
62
63#include "cmsis_version.h"
64
65/* CMSIS SC300 definitions */
66#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
67#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
68#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
69 __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
70
71#define __CORTEX_SC (300U) /*!< Cortex secure core */
72
73/** __FPU_USED indicates whether an FPU is used or not.
74 This core does not support an FPU at all
75*/
76#define __FPU_USED 0U
77
78#if defined ( __CC_ARM )
79 #if defined __TARGET_FPU_VFP
80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
81 #endif
82
83#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84 #if defined __ARM_FP
85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
86 #endif
87
88#elif defined ( __GNUC__ )
89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
91 #endif
92
93#elif defined ( __ICCARM__ )
94 #if defined __ARMVFP__
95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96 #endif
97
98#elif defined ( __TI_ARM__ )
99 #if defined __TI_VFP_SUPPORT__
100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
101 #endif
102
103#elif defined ( __TASKING__ )
104 #if defined __FPU_VFP__
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106 #endif
107
108#elif defined ( __CSMC__ )
109 #if ( __CSMC__ & 0x400U)
110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
111 #endif
112
113#endif
114
115#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
116
117
118#ifdef __cplusplus
119}
120#endif
121
122#endif /* __CORE_SC300_H_GENERIC */
123
124#ifndef __CMSIS_GENERIC
125
126#ifndef __CORE_SC300_H_DEPENDANT
127#define __CORE_SC300_H_DEPENDANT
128
129#ifdef __cplusplus
130 extern "C" {
131#endif
132
133/* check device defines and use defaults */
134#if defined __CHECK_DEVICE_DEFINES
135 #ifndef __SC300_REV
136 #define __SC300_REV 0x0000U
137 #warning "__SC300_REV not defined in device header file; using default!"
138 #endif
139
140 #ifndef __MPU_PRESENT
141 #define __MPU_PRESENT 0U
142 #warning "__MPU_PRESENT not defined in device header file; using default!"
143 #endif
144
145 #ifndef __VTOR_PRESENT
146 #define __VTOR_PRESENT 1U
147 #warning "__VTOR_PRESENT not defined in device header file; using default!"
148 #endif
149
150 #ifndef __NVIC_PRIO_BITS
151 #define __NVIC_PRIO_BITS 3U
152 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
153 #endif
154
155 #ifndef __Vendor_SysTickConfig
156 #define __Vendor_SysTickConfig 0U
157 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
158 #endif
159#endif
160
161/* IO definitions (access restrictions to peripheral registers) */
162/**
163 \defgroup CMSIS_glob_defs CMSIS Global Defines
164
165 <strong>IO Type Qualifiers</strong> are used
166 \li to specify the access to peripheral variables.
167 \li for automatic generation of peripheral register debug information.
168*/
169#ifdef __cplusplus
170 #define __I volatile /*!< Defines 'read only' permissions */
171#else
172 #define __I volatile const /*!< Defines 'read only' permissions */
173#endif
174#define __O volatile /*!< Defines 'write only' permissions */
175#define __IO volatile /*!< Defines 'read / write' permissions */
176
177/* following defines should be used for structure members */
178#define __IM volatile const /*! Defines 'read only' structure member permissions */
179#define __OM volatile /*! Defines 'write only' structure member permissions */
180#define __IOM volatile /*! Defines 'read / write' structure member permissions */
181
182/*@} end of group SC300 */
183
184
185
186/*******************************************************************************
187 * Register Abstraction
188 Core Register contain:
189 - Core Register
190 - Core NVIC Register
191 - Core SCB Register
192 - Core SysTick Register
193 - Core Debug Register
194 - Core MPU Register
195 ******************************************************************************/
196/**
197 \defgroup CMSIS_core_register Defines and Type Definitions
198 \brief Type definitions and defines for Cortex-M processor based devices.
199*/
200
201/**
202 \ingroup CMSIS_core_register
203 \defgroup CMSIS_CORE Status and Control Registers
204 \brief Core Register type definitions.
205 @{
206 */
207
208/**
209 \brief Union type to access the Application Program Status Register (APSR).
210 */
211typedef union
212{
213 struct
214 {
215 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
216 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
217 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
218 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
219 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
220 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
221 } b; /*!< Structure used for bit access */
222 uint32_t w; /*!< Type used for word access */
223} APSR_Type;
224
225/* APSR Register Definitions */
226#define APSR_N_Pos 31U /*!< APSR: N Position */
227#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
228
229#define APSR_Z_Pos 30U /*!< APSR: Z Position */
230#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
231
232#define APSR_C_Pos 29U /*!< APSR: C Position */
233#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
234
235#define APSR_V_Pos 28U /*!< APSR: V Position */
236#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
237
238#define APSR_Q_Pos 27U /*!< APSR: Q Position */
239#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
240
241
242/**
243 \brief Union type to access the Interrupt Program Status Register (IPSR).
244 */
245typedef union
246{
247 struct
248 {
249 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
250 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
251 } b; /*!< Structure used for bit access */
252 uint32_t w; /*!< Type used for word access */
253} IPSR_Type;
254
255/* IPSR Register Definitions */
256#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
257#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
258
259
260/**
261 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
262 */
263typedef union
264{
265 struct
266 {
267 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
268 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
269 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
270 uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
271 uint32_t T:1; /*!< bit: 24 Thumb bit */
272 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
273 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
274 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
275 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
276 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
277 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
278 } b; /*!< Structure used for bit access */
279 uint32_t w; /*!< Type used for word access */
280} xPSR_Type;
281
282/* xPSR Register Definitions */
283#define xPSR_N_Pos 31U /*!< xPSR: N Position */
284#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
285
286#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
287#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
288
289#define xPSR_C_Pos 29U /*!< xPSR: C Position */
290#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
291
292#define xPSR_V_Pos 28U /*!< xPSR: V Position */
293#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
294
295#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
296#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
297
298#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
299#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
300
301#define xPSR_T_Pos 24U /*!< xPSR: T Position */
302#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
303
304#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
305#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
306
307#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
308#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
309
310
311/**
312 \brief Union type to access the Control Registers (CONTROL).
313 */
314typedef union
315{
316 struct
317 {
318 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
319 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
320 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
321 } b; /*!< Structure used for bit access */
322 uint32_t w; /*!< Type used for word access */
323} CONTROL_Type;
324
325/* CONTROL Register Definitions */
326#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
327#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
328
329#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
330#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
331
332/*@} end of group CMSIS_CORE */
333
334
335/**
336 \ingroup CMSIS_core_register
337 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
338 \brief Type definitions for the NVIC Registers
339 @{
340 */
341
342/**
343 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
344 */
345typedef struct
346{
347 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
348 uint32_t RESERVED0[24U];
349 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
350 uint32_t RESERVED1[24U];
351 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
352 uint32_t RESERVED2[24U];
353 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
354 uint32_t RESERVED3[24U];
355 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
356 uint32_t RESERVED4[56U];
357 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
358 uint32_t RESERVED5[644U];
359 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
360} NVIC_Type;
361
362/* Software Triggered Interrupt Register Definitions */
363#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
364#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
365
366/*@} end of group CMSIS_NVIC */
367
368
369/**
370 \ingroup CMSIS_core_register
371 \defgroup CMSIS_SCB System Control Block (SCB)
372 \brief Type definitions for the System Control Block Registers
373 @{
374 */
375
376/**
377 \brief Structure type to access the System Control Block (SCB).
378 */
379typedef struct
380{
381 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
382 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
383 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
384 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
385 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
386 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
387 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
388 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
389 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
390 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
391 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
392 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
393 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
394 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
395 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
396 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
397 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
398 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
399 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
400 uint32_t RESERVED0[5U];
401 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
402 uint32_t RESERVED1[129U];
403 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
404} SCB_Type;
405
406/* SCB CPUID Register Definitions */
407#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
408#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
409
410#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
411#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
412
413#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
414#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
415
416#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
417#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
418
419#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
420#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
421
422/* SCB Interrupt Control State Register Definitions */
423#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
424#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
425
426#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
427#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
428
429#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
430#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
431
432#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
433#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
434
435#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
436#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
437
438#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
439#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
440
441#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
442#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
443
444#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
445#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
446
447#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
448#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
449
450#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
451#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
452
453/* SCB Vector Table Offset Register Definitions */
454#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
455#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
456
457#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
458#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
459
460/* SCB Application Interrupt and Reset Control Register Definitions */
461#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
462#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
463
464#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
465#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
466
467#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
468#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
469
470#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
471#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
472
473#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
474#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
475
476#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
477#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
478
479#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
480#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
481
482/* SCB System Control Register Definitions */
483#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
484#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
485
486#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
487#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
488
489#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
490#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
491
492/* SCB Configuration Control Register Definitions */
493#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
494#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
495
496#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
497#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
498
499#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
500#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
501
502#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
503#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
504
505#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
506#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
507
508#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
509#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
510
511/* SCB System Handler Control and State Register Definitions */
512#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
513#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
514
515#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
516#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
517
518#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
519#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
520
521#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
522#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
523
524#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
525#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
526
527#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
528#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
529
530#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
531#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
532
533#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
534#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
535
536#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
537#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
538
539#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
540#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
541
542#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
543#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
544
545#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
546#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
547
548#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
549#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
550
551#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
552#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
553
554/* SCB Configurable Fault Status Register Definitions */
555#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
556#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
557
558#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
559#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
560
561#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
562#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
563
564/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
565#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
566#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
567
568#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
569#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
570
571#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
572#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
573
574#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
575#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
576
577#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
578#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
579
580/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
581#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
582#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
583
584#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
585#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
586
587#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
588#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
589
590#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
591#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
592
593#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
594#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
595
596#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
597#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
598
599/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
600#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
601#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
602
603#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
604#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
605
606#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
607#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
608
609#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
610#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
611
612#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
613#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
614
615#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
616#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
617
618/* SCB Hard Fault Status Register Definitions */
619#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
620#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
621
622#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
623#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
624
625#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
626#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
627
628/* SCB Debug Fault Status Register Definitions */
629#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
630#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
631
632#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
633#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
634
635#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
636#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
637
638#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
639#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
640
641#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
642#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
643
644/*@} end of group CMSIS_SCB */
645
646
647/**
648 \ingroup CMSIS_core_register
649 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
650 \brief Type definitions for the System Control and ID Register not in the SCB
651 @{
652 */
653
654/**
655 \brief Structure type to access the System Control and ID Register not in the SCB.
656 */
657typedef struct
658{
659 uint32_t RESERVED0[1U];
660 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
661 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
662} SCnSCB_Type;
663
664/* Interrupt Controller Type Register Definitions */
665#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
666#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
667
668/* Auxiliary Control Register Definitions */
669#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
670#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
671
672#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
673#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
674
675#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
676#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
677
678/*@} end of group CMSIS_SCnotSCB */
679
680
681/**
682 \ingroup CMSIS_core_register
683 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
684 \brief Type definitions for the System Timer Registers.
685 @{
686 */
687
688/**
689 \brief Structure type to access the System Timer (SysTick).
690 */
691typedef struct
692{
693 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
694 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
695 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
696 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
697} SysTick_Type;
698
699/* SysTick Control / Status Register Definitions */
700#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
701#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
702
703#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
704#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
705
706#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
707#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
708
709#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
710#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
711
712/* SysTick Reload Register Definitions */
713#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
714#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
715
716/* SysTick Current Register Definitions */
717#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
718#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
719
720/* SysTick Calibration Register Definitions */
721#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
722#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
723
724#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
725#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
726
727#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
728#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
729
730/*@} end of group CMSIS_SysTick */
731
732
733/**
734 \ingroup CMSIS_core_register
735 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
736 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
737 @{
738 */
739
740/**
741 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
742 */
743typedef struct
744{
745 __OM union
746 {
747 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
748 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
749 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
750 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
751 uint32_t RESERVED0[864U];
752 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
753 uint32_t RESERVED1[15U];
754 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
755 uint32_t RESERVED2[15U];
756 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
757 uint32_t RESERVED3[32U];
758 uint32_t RESERVED4[43U];
759 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
760 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
761 uint32_t RESERVED5[6U];
762 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
763 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
764 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
765 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
766 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
767 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
768 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
769 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
770 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
771 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
772 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
773 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
774} ITM_Type;
775
776/* ITM Trace Privilege Register Definitions */
777#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
778#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
779
780/* ITM Trace Control Register Definitions */
781#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
782#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
783
784#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
785#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
786
787#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
788#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
789
790#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
791#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
792
793#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
794#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
795
796#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
797#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
798
799#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
800#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
801
802#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
803#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
804
805#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
806#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
807
808/* ITM Lock Status Register Definitions */
809#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
810#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
811
812#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
813#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
814
815#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
816#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
817
818/*@}*/ /* end of group CMSIS_ITM */
819
820
821/**
822 \ingroup CMSIS_core_register
823 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
824 \brief Type definitions for the Data Watchpoint and Trace (DWT)
825 @{
826 */
827
828/**
829 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
830 */
831typedef struct
832{
833 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
834 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
835 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
836 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
837 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
838 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
839 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
840 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
841 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
842 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
843 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
844 uint32_t RESERVED0[1U];
845 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
846 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
847 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
848 uint32_t RESERVED1[1U];
849 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
850 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
851 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
852 uint32_t RESERVED2[1U];
853 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
854 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
855 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
856} DWT_Type;
857
858/* DWT Control Register Definitions */
859#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
860#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
861
862#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
863#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
864
865#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
866#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
867
868#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
869#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
870
871#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
872#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
873
874#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
875#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
876
877#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
878#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
879
880#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
881#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
882
883#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
884#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
885
886#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
887#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
888
889#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
890#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
891
892#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
893#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
894
895#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
896#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
897
898#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
899#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
900
901#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
902#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
903
904#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
905#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
906
907#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
908#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
909
910#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
911#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
912
913/* DWT CPI Count Register Definitions */
914#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
915#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
916
917/* DWT Exception Overhead Count Register Definitions */
918#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
919#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
920
921/* DWT Sleep Count Register Definitions */
922#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
923#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
924
925/* DWT LSU Count Register Definitions */
926#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
927#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
928
929/* DWT Folded-instruction Count Register Definitions */
930#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
931#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
932
933/* DWT Comparator Mask Register Definitions */
934#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
935#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
936
937/* DWT Comparator Function Register Definitions */
938#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
939#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
940
941#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
942#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
943
944#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
945#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
946
947#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
948#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
949
950#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
951#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
952
953#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
954#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
955
956#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
957#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
958
959#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
960#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
961
962#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
963#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
964
965/*@}*/ /* end of group CMSIS_DWT */
966
967
968/**
969 \ingroup CMSIS_core_register
970 \defgroup CMSIS_TPI Trace Port Interface (TPI)
971 \brief Type definitions for the Trace Port Interface (TPI)
972 @{
973 */
974
975/**
976 \brief Structure type to access the Trace Port Interface Register (TPI).
977 */
978typedef struct
979{
980 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
981 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
982 uint32_t RESERVED0[2U];
983 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
984 uint32_t RESERVED1[55U];
985 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
986 uint32_t RESERVED2[131U];
987 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
988 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
989 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
990 uint32_t RESERVED3[759U];
991 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
992 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
993 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
994 uint32_t RESERVED4[1U];
995 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
996 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
997 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
998 uint32_t RESERVED5[39U];
999 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1000 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1001 uint32_t RESERVED7[8U];
1002 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1003 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
1004} TPI_Type;
1005
1006/* TPI Asynchronous Clock Prescaler Register Definitions */
1007#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
1008#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
1009
1010/* TPI Selected Pin Protocol Register Definitions */
1011#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
1012#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
1013
1014/* TPI Formatter and Flush Status Register Definitions */
1015#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
1016#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
1017
1018#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
1019#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
1020
1021#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
1022#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
1023
1024#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
1025#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
1026
1027/* TPI Formatter and Flush Control Register Definitions */
1028#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
1029#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
1030
1031#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
1032#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
1033
1034/* TPI TRIGGER Register Definitions */
1035#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
1036#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
1037
1038/* TPI Integration ETM Data Register Definitions (FIFO0) */
1039#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
1040#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
1041
1042#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
1043#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
1044
1045#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
1046#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
1047
1048#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
1049#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
1050
1051#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
1052#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
1053
1054#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
1055#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
1056
1057#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
1058#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
1059
1060/* TPI ITATBCTR2 Register Definitions */
1061#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
1062#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
1063
1064#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
1065#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
1066
1067/* TPI Integration ITM Data Register Definitions (FIFO1) */
1068#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
1069#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
1070
1071#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
1072#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
1073
1074#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
1075#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
1076
1077#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
1078#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
1079
1080#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
1081#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
1082
1083#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
1084#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
1085
1086#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
1087#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
1088
1089/* TPI ITATBCTR0 Register Definitions */
1090#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
1091#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
1092
1093#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
1094#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
1095
1096/* TPI Integration Mode Control Register Definitions */
1097#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
1098#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
1099
1100/* TPI DEVID Register Definitions */
1101#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
1102#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1103
1104#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
1105#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1106
1107#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
1108#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1109
1110#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
1111#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1112
1113#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
1114#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1115
1116#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
1117#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
1118
1119/* TPI DEVTYPE Register Definitions */
1120#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
1121#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
1122
1123#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
1124#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1125
1126/*@}*/ /* end of group CMSIS_TPI */
1127
1128
1129#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1130/**
1131 \ingroup CMSIS_core_register
1132 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1133 \brief Type definitions for the Memory Protection Unit (MPU)
1134 @{
1135 */
1136
1137/**
1138 \brief Structure type to access the Memory Protection Unit (MPU).
1139 */
1140typedef struct
1141{
1142 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1143 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1144 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1145 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1146 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1147 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1148 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1149 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1150 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1151 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1152 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1153} MPU_Type;
1154
1155/* MPU Type Register Definitions */
1156#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1157#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1158
1159#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1160#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1161
1162#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1163#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1164
1165/* MPU Control Register Definitions */
1166#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1167#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1168
1169#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1170#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1171
1172#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1173#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1174
1175/* MPU Region Number Register Definitions */
1176#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1177#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1178
1179/* MPU Region Base Address Register Definitions */
1180#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
1181#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1182
1183#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
1184#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1185
1186#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
1187#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
1188
1189/* MPU Region Attribute and Size Register Definitions */
1190#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
1191#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1192
1193#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
1194#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1195
1196#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
1197#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1198
1199#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
1200#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1201
1202#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
1203#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1204
1205#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
1206#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1207
1208#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
1209#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1210
1211#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
1212#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1213
1214#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
1215#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1216
1217#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
1218#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
1219
1220/*@} end of group CMSIS_MPU */
1221#endif
1222
1223
1224/**
1225 \ingroup CMSIS_core_register
1226 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1227 \brief Type definitions for the Core Debug Registers
1228 @{
1229 */
1230
1231/**
1232 \brief Structure type to access the Core Debug Register (CoreDebug).
1233 */
1234typedef struct
1235{
1236 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1237 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1238 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1239 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1240} CoreDebug_Type;
1241
1242/* Debug Halting Control and Status Register Definitions */
1243#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
1244#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1245
1246#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
1247#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1248
1249#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1250#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1251
1252#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
1253#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1254
1255#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
1256#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1257
1258#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
1259#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1260
1261#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
1262#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1263
1264#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1265#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1266
1267#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
1268#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1269
1270#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
1271#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1272
1273#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
1274#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1275
1276#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1277#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1278
1279/* Debug Core Register Selector Register Definitions */
1280#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
1281#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1282
1283#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
1284#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
1285
1286/* Debug Exception and Monitor Control Register Definitions */
1287#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
1288#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1289
1290#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
1291#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1292
1293#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
1294#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1295
1296#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
1297#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1298
1299#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
1300#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1301
1302#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
1303#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1304
1305#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
1306#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1307
1308#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
1309#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1310
1311#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
1312#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1313
1314#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
1315#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1316
1317#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1318#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1319
1320#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
1321#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1322
1323#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
1324#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1325
1326/*@} end of group CMSIS_CoreDebug */
1327
1328
1329/**
1330 \ingroup CMSIS_core_register
1331 \defgroup CMSIS_core_bitfield Core register bit field macros
1332 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1333 @{
1334 */
1335
1336/**
1337 \brief Mask and shift a bit field value for use in a register bit range.
1338 \param[in] field Name of the register bit field.
1339 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1340 \return Masked and shifted value.
1341*/
1342#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1343
1344/**
1345 \brief Mask and shift a register value to extract a bit filed value.
1346 \param[in] field Name of the register bit field.
1347 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
1348 \return Masked and shifted bit field value.
1349*/
1350#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1351
1352/*@} end of group CMSIS_core_bitfield */
1353
1354
1355/**
1356 \ingroup CMSIS_core_register
1357 \defgroup CMSIS_core_base Core Definitions
1358 \brief Definitions for base addresses, unions, and structures.
1359 @{
1360 */
1361
1362/* Memory mapping of Core Hardware */
1363#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1364#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1365#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1366#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1367#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1368#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1369#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1370#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1371
1372#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1373#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1374#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1375#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1376#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1377#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1378#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1379#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1380
1381#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1382 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1383 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1384#endif
1385
1386/*@} */
1387
1388
1389
1390/*******************************************************************************
1391 * Hardware Abstraction Layer
1392 Core Function Interface contains:
1393 - Core NVIC Functions
1394 - Core SysTick Functions
1395 - Core Debug Functions
1396 - Core Register Access Functions
1397 ******************************************************************************/
1398/**
1399 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1400*/
1401
1402
1403
1404/* ########################## NVIC functions #################################### */
1405/**
1406 \ingroup CMSIS_Core_FunctionInterface
1407 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1408 \brief Functions that manage interrupts and exceptions via the NVIC.
1409 @{
1410 */
1411
1412#ifdef CMSIS_NVIC_VIRTUAL
1413 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1414 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1415 #endif
1416 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1417#else
1418 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1419 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1420 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1421 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1422 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1423 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1424 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1425 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1426 #define NVIC_GetActive __NVIC_GetActive
1427 #define NVIC_SetPriority __NVIC_SetPriority
1428 #define NVIC_GetPriority __NVIC_GetPriority
1429 #define NVIC_SystemReset __NVIC_SystemReset
1430#endif /* CMSIS_NVIC_VIRTUAL */
1431
1432#ifdef CMSIS_VECTAB_VIRTUAL
1433 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1434 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1435 #endif
1436 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1437#else
1438 #define NVIC_SetVector __NVIC_SetVector
1439 #define NVIC_GetVector __NVIC_GetVector
1440#endif /* (CMSIS_VECTAB_VIRTUAL) */
1441
1442#define NVIC_USER_IRQ_OFFSET 16
1443
1444
1445/* The following EXC_RETURN values are saved the LR on exception entry */
1446#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
1447#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
1448#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
1449
1450
1451/**
1452 \brief Set Priority Grouping
1453 \details Sets the priority grouping field using the required unlock sequence.
1454 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1455 Only values from 0..7 are used.
1456 In case of a conflict between priority grouping and available
1457 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1458 \param [in] PriorityGroup Priority grouping field.
1459 */
1460__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1461{
1462 uint32_t reg_value;
1463 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1464
1465 reg_value = SCB->AIRCR; /* read old register configuration */
1466 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1467 reg_value = (reg_value |
1468 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1469 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
1470 SCB->AIRCR = reg_value;
1471}
1472
1473
1474/**
1475 \brief Get Priority Grouping
1476 \details Reads the priority grouping field from the NVIC Interrupt Controller.
1477 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1478 */
1479__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
1480{
1481 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1482}
1483
1484
1485/**
1486 \brief Enable Interrupt
1487 \details Enables a device specific interrupt in the NVIC interrupt controller.
1488 \param [in] IRQn Device specific interrupt number.
1489 \note IRQn must not be negative.
1490 */
1491__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1492{
1493 if ((int32_t)(IRQn) >= 0)
1494 {
1495 __COMPILER_BARRIER();
1496 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1497 __COMPILER_BARRIER();
1498 }
1499}
1500
1501
1502/**
1503 \brief Get Interrupt Enable status
1504 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
1505 \param [in] IRQn Device specific interrupt number.
1506 \return 0 Interrupt is not enabled.
1507 \return 1 Interrupt is enabled.
1508 \note IRQn must not be negative.
1509 */
1510__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1511{
1512 if ((int32_t)(IRQn) >= 0)
1513 {
1514 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1515 }
1516 else
1517 {
1518 return(0U);
1519 }
1520}
1521
1522
1523/**
1524 \brief Disable Interrupt
1525 \details Disables a device specific interrupt in the NVIC interrupt controller.
1526 \param [in] IRQn Device specific interrupt number.
1527 \note IRQn must not be negative.
1528 */
1529__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1530{
1531 if ((int32_t)(IRQn) >= 0)
1532 {
1533 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1534 __DSB();
1535 __ISB();
1536 }
1537}
1538
1539
1540/**
1541 \brief Get Pending Interrupt
1542 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
1543 \param [in] IRQn Device specific interrupt number.
1544 \return 0 Interrupt status is not pending.
1545 \return 1 Interrupt status is pending.
1546 \note IRQn must not be negative.
1547 */
1548__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1549{
1550 if ((int32_t)(IRQn) >= 0)
1551 {
1552 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1553 }
1554 else
1555 {
1556 return(0U);
1557 }
1558}
1559
1560
1561/**
1562 \brief Set Pending Interrupt
1563 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
1564 \param [in] IRQn Device specific interrupt number.
1565 \note IRQn must not be negative.
1566 */
1567__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1568{
1569 if ((int32_t)(IRQn) >= 0)
1570 {
1571 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1572 }
1573}
1574
1575
1576/**
1577 \brief Clear Pending Interrupt
1578 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
1579 \param [in] IRQn Device specific interrupt number.
1580 \note IRQn must not be negative.
1581 */
1582__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1583{
1584 if ((int32_t)(IRQn) >= 0)
1585 {
1586 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1587 }
1588}
1589
1590
1591/**
1592 \brief Get Active Interrupt
1593 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
1594 \param [in] IRQn Device specific interrupt number.
1595 \return 0 Interrupt status is not active.
1596 \return 1 Interrupt status is active.
1597 \note IRQn must not be negative.
1598 */
1599__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1600{
1601 if ((int32_t)(IRQn) >= 0)
1602 {
1603 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1604 }
1605 else
1606 {
1607 return(0U);
1608 }
1609}
1610
1611
1612/**
1613 \brief Set Interrupt Priority
1614 \details Sets the priority of a device specific interrupt or a processor exception.
1615 The interrupt number can be positive to specify a device specific interrupt,
1616 or negative to specify a processor exception.
1617 \param [in] IRQn Interrupt number.
1618 \param [in] priority Priority to set.
1619 \note The priority cannot be set for every processor exception.
1620 */
1621__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1622{
1623 if ((int32_t)(IRQn) >= 0)
1624 {
1625 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1626 }
1627 else
1628 {
1629 SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1630 }
1631}
1632
1633
1634/**
1635 \brief Get Interrupt Priority
1636 \details Reads the priority of a device specific interrupt or a processor exception.
1637 The interrupt number can be positive to specify a device specific interrupt,
1638 or negative to specify a processor exception.
1639 \param [in] IRQn Interrupt number.
1640 \return Interrupt Priority.
1641 Value is aligned automatically to the implemented priority bits of the microcontroller.
1642 */
1643__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1644{
1645
1646 if ((int32_t)(IRQn) >= 0)
1647 {
1648 return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
1649 }
1650 else
1651 {
1652 return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
1653 }
1654}
1655
1656
1657/**
1658 \brief Encode Priority
1659 \details Encodes the priority for an interrupt with the given priority group,
1660 preemptive priority value, and subpriority value.
1661 In case of a conflict between priority grouping and available
1662 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1663 \param [in] PriorityGroup Used priority group.
1664 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1665 \param [in] SubPriority Subpriority value (starting from 0).
1666 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1667 */
1668__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1669{
1670 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1671 uint32_t PreemptPriorityBits;
1672 uint32_t SubPriorityBits;
1673
1674 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1675 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1676
1677 return (
1678 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1679 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1680 );
1681}
1682
1683
1684/**
1685 \brief Decode Priority
1686 \details Decodes an interrupt priority value with a given priority group to
1687 preemptive priority value and subpriority value.
1688 In case of a conflict between priority grouping and available
1689 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1690 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1691 \param [in] PriorityGroup Used priority group.
1692 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1693 \param [out] pSubPriority Subpriority value (starting from 0).
1694 */
1695__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1696{
1697 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1698 uint32_t PreemptPriorityBits;
1699 uint32_t SubPriorityBits;
1700
1701 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1702 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1703
1704 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1705 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1706}
1707
1708
1709/**
1710 \brief Set Interrupt Vector
1711 \details Sets an interrupt vector in SRAM based interrupt vector table.
1712 The interrupt number can be positive to specify a device specific interrupt,
1713 or negative to specify a processor exception.
1714 VTOR must been relocated to SRAM before.
1715 \param [in] IRQn Interrupt number
1716 \param [in] vector Address of interrupt handler function
1717 */
1718__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1719{
1720 uint32_t *vectors = (uint32_t *)SCB->VTOR;
1721 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1722 /* ARM Application Note 321 states that the M3 does not require the architectural barrier */
1723}
1724
1725
1726/**
1727 \brief Get Interrupt Vector
1728 \details Reads an interrupt vector from interrupt vector table.
1729 The interrupt number can be positive to specify a device specific interrupt,
1730 or negative to specify a processor exception.
1731 \param [in] IRQn Interrupt number.
1732 \return Address of interrupt handler function
1733 */
1734__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1735{
1736 uint32_t *vectors = (uint32_t *)SCB->VTOR;
1737 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1738}
1739
1740
1741/**
1742 \brief System Reset
1743 \details Initiates a system reset request to reset the MCU.
1744 */
1745__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
1746{
1747 __DSB(); /* Ensure all outstanding memory accesses included
1748 buffered write are completed before reset */
1749 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1750 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1751 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
1752 __DSB(); /* Ensure completion of memory access */
1753
1754 for(;;) /* wait until reset */
1755 {
1756 __NOP();
1757 }
1758}
1759
1760/*@} end of CMSIS_Core_NVICFunctions */
1761
1762
1763/* ########################## FPU functions #################################### */
1764/**
1765 \ingroup CMSIS_Core_FunctionInterface
1766 \defgroup CMSIS_Core_FpuFunctions FPU Functions
1767 \brief Function that provides FPU type.
1768 @{
1769 */
1770
1771/**
1772 \brief get FPU type
1773 \details returns the FPU type
1774 \returns
1775 - \b 0: No FPU
1776 - \b 1: Single precision FPU
1777 - \b 2: Double + Single precision FPU
1778 */
1779__STATIC_INLINE uint32_t SCB_GetFPUType(void)
1780{
1781 return 0U; /* No FPU */
1782}
1783
1784
1785/*@} end of CMSIS_Core_FpuFunctions */
1786
1787
1788
1789/* ################################## SysTick function ############################################ */
1790/**
1791 \ingroup CMSIS_Core_FunctionInterface
1792 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1793 \brief Functions that configure the System.
1794 @{
1795 */
1796
1797#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1798
1799/**
1800 \brief System Tick Configuration
1801 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
1802 Counter is in free running mode to generate periodic interrupts.
1803 \param [in] ticks Number of ticks between two interrupts.
1804 \return 0 Function succeeded.
1805 \return 1 Function failed.
1806 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1807 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1808 must contain a vendor-specific implementation of this function.
1809 */
1810__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1811{
1812 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1813 {
1814 return (1UL); /* Reload value impossible */
1815 }
1816
1817 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1818 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1819 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1820 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1821 SysTick_CTRL_TICKINT_Msk |
1822 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1823 return (0UL); /* Function successful */
1824}
1825
1826#endif
1827
1828/*@} end of CMSIS_Core_SysTickFunctions */
1829
1830
1831
1832/* ##################################### Debug In/Output function ########################################### */
1833/**
1834 \ingroup CMSIS_Core_FunctionInterface
1835 \defgroup CMSIS_core_DebugFunctions ITM Functions
1836 \brief Functions that access the ITM debug interface.
1837 @{
1838 */
1839
1840extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
1841#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
1842
1843
1844/**
1845 \brief ITM Send Character
1846 \details Transmits a character via the ITM channel 0, and
1847 \li Just returns when no debugger is connected that has booked the output.
1848 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
1849 \param [in] ch Character to transmit.
1850 \returns Character to transmit.
1851 */
1852__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1853{
1854 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
1855 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
1856 {
1857 while (ITM->PORT[0U].u32 == 0UL)
1858 {
1859 __NOP();
1860 }
1861 ITM->PORT[0U].u8 = (uint8_t)ch;
1862 }
1863 return (ch);
1864}
1865
1866
1867/**
1868 \brief ITM Receive Character
1869 \details Inputs a character via the external variable \ref ITM_RxBuffer.
1870 \return Received character.
1871 \return -1 No character pending.
1872 */
1873__STATIC_INLINE int32_t ITM_ReceiveChar (void)
1874{
1875 int32_t ch = -1; /* no character available */
1876
1877 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
1878 {
1879 ch = ITM_RxBuffer;
1880 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1881 }
1882
1883 return (ch);
1884}
1885
1886
1887/**
1888 \brief ITM Check Character
1889 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
1890 \return 0 No character available.
1891 \return 1 Character available.
1892 */
1893__STATIC_INLINE int32_t ITM_CheckChar (void)
1894{
1895
1896 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
1897 {
1898 return (0); /* no character available */
1899 }
1900 else
1901 {
1902 return (1); /* character available */
1903 }
1904}
1905
1906/*@} end of CMSIS_core_DebugFunctions */
1907
1908
1909
1910
1911#ifdef __cplusplus
1912}
1913#endif
1914
1915#endif /* __CORE_SC300_H_DEPENDANT */
1916
1917#endif /* __CMSIS_GENERIC */
__NO_RETURN
#define __NO_RETURN
Definition cmsis_armcc.h:70
__COMPILER_BARRIER
#define __COMPILER_BARRIER()
Definition cmsis_armcc.h:109
__STATIC_INLINE
#define __STATIC_INLINE
Definition cmsis_armcc.h:64
cmsis_compiler.h
CMSIS compiler generic header file.
cmsis_version.h
CMSIS Core(M) Version definitions.
__OM
#define __OM
Definition core_armv81mml.h:294
__IM
#define __IM
Definition core_armv81mml.h:293
__IOM
#define __IOM
Definition core_armv81mml.h:295
__OM
#define __OM
Definition core_starmc1.h:293
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
SysTick CTRL: ENABLE Mask.
Definition core_armv81mml.h:1045
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
SysTick LOAD: RELOAD Mask.
Definition core_armv81mml.h:1049
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
ITM TCR: ITM Enable bit Mask.
Definition core_armv81mml.h:1154
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
SCB AIRCR: PRIGROUP Mask.
Definition core_armv81mml.h:639
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
SCB AIRCR: VECTKEY Mask.
Definition core_armv81mml.h:624
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
SysTick CTRL: TICKINT Mask.
Definition core_armv81mml.h:1042
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
SysTick CTRL: CLKSOURCE Mask.
Definition core_armv81mml.h:1039
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
SCB AIRCR: VECTKEY Position.
Definition core_armv81mml.h:623
SCB
#define SCB
SCB configuration struct.
Definition core_armv81mml.h:3106
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
SCB AIRCR: SYSRESETREQ Mask.
Definition core_armv81mml.h:651
ITM
#define ITM
ITM configuration struct.
Definition core_armv81mml.h:3109
NVIC
#define NVIC
NVIC configuration struct.
Definition core_armv81mml.h:3108
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
SCB AIRCR: PRIGROUP Position.
Definition core_armv81mml.h:638
SysTick
#define SysTick
SysTick configuration struct.
Definition core_armv81mml.h:3107
__NVIC_SetPriorityGrouping
#define __NVIC_SetPriorityGrouping(X)
Definition core_armv8mbl.h:1440
__NVIC_GetPriorityGrouping
#define __NVIC_GetPriorityGrouping()
Get Priority Grouping.
Definition core_armv8mbl.h:1441
__DSB
#define __DSB()
Data Synchronization Barrier.
Definition cmsis_armcc.h:182
__ISB
#define __ISB()
Instruction Synchronization Barrier.
Definition cmsis_armcc.h:175
__NOP
#define __NOP
No Operation.
Definition cmsis_armcc.h:144
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition core_armv81mml.h:3611
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition core_armv81mml.h:3584
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition core_armv81mml.h:3561
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition core_armv81mml.h:3600
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition core_armv81mml.h:3487
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition core_armv81mml.h:3381
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition core_armv81mml.h:3347
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition core_armv81mml.h:3862
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition core_armv81mml.h:3290
NVIC_USER_IRQ_OFFSET
#define NVIC_USER_IRQ_OFFSET
Definition core_armv81mml.h:3225
__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition core_armv81mml.h:3398
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition core_armv81mml.h:3366
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition core_armv81mml.h:3309
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition core_armv81mml.h:3534
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition core_armv81mml.h:3328
NVIC_SetPriority
#define NVIC_SetPriority
Definition core_sc300.h:1427
SysTick_Config
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Definition core_armv81mml.h:4091
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition core_armv81mml.h:3509
xPSR_Type::@244221304127174261110374135210036304371376321171::_reserved1
uint32_t _reserved1
bit: 16..23 Reserved
Definition core_sc300.h:270
xPSR_Type::@244221304127174261110374135210036304371376321171::_reserved0
uint32_t _reserved0
bit: 9 Reserved
Definition core_sc300.h:268
APSR_Type::@341032015064031271002321246151141077202014226010::C
uint32_t C
bit: 29 Carry condition code flag
Definition core_sc300.h:218
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
External variable to receive characters.
APSR_Type::@341032015064031271002321246151141077202014226010::N
uint32_t N
bit: 31 Negative condition code flag
Definition core_sc300.h:220
IPSR_Type::@123224240133024225314016131147003147162124327135::_reserved0
uint32_t _reserved0
bit: 9..31 Reserved
Definition core_sc300.h:250
xPSR_Type::@244221304127174261110374135210036304371376321171::ICI_IT_2
uint32_t ICI_IT_2
bit: 25..26 ICI/IT part 2
Definition core_sc300.h:272
xPSR_Type::@244221304127174261110374135210036304371376321171::ISR
uint32_t ISR
bit: 0.
Definition core_sc300.h:267
xPSR_Type::@244221304127174261110374135210036304371376321171::Q
uint32_t Q
bit: 27 Saturation condition flag
Definition core_sc300.h:273
xPSR_Type::@244221304127174261110374135210036304371376321171::C
uint32_t C
bit: 29 Carry condition code flag
Definition core_sc300.h:275
ITM_Type::@174024357201340225261211272351302322334176227371::u16
__OM uint16_t u16
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit.
Definition core_sc300.h:748
IPSR_Type::@123224240133024225314016131147003147162124327135::ISR
uint32_t ISR
bit: 0.
Definition core_sc300.h:249
xPSR_Type::@244221304127174261110374135210036304371376321171::ICI_IT_1
uint32_t ICI_IT_1
bit: 10..15 ICI/IT part 1
Definition core_sc300.h:269
ITM_Type::@174024357201340225261211272351302322334176227371::u32
__OM uint32_t u32
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit.
Definition core_sc300.h:749
APSR_Type::@341032015064031271002321246151141077202014226010::Q
uint32_t Q
bit: 27 Saturation condition flag
Definition core_sc300.h:216
ITM_Type::@174024357201340225261211272351302322334176227371::u8
__OM uint8_t u8
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit.
Definition core_sc300.h:747
xPSR_Type::@244221304127174261110374135210036304371376321171::N
uint32_t N
bit: 31 Negative condition code flag
Definition core_sc300.h:277
CONTROL_Type::@264116250335015102300022317301315003367214310221::nPRIV
uint32_t nPRIV
bit: 0 Execution privilege in Thread mode
Definition core_sc300.h:318
xPSR_Type::@244221304127174261110374135210036304371376321171::Z
uint32_t Z
bit: 30 Zero condition code flag
Definition core_sc300.h:276
APSR_Type::@341032015064031271002321246151141077202014226010::Z
uint32_t Z
bit: 30 Zero condition code flag
Definition core_sc300.h:219
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Value identifying ITM_RxBuffer is ready for next character.
Definition core_armv81mml.h:4152
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition core_armv81mml.h:4184
APSR_Type::@341032015064031271002321246151141077202014226010::V
uint32_t V
bit: 28 Overflow condition code flag
Definition core_sc300.h:217
ITM_SendChar
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
ITM Send Character.
Definition core_armv81mml.h:4163
CONTROL_Type::@264116250335015102300022317301315003367214310221::_reserved1
uint32_t _reserved1
bit: 2..31 Reserved
Definition core_sc300.h:320
xPSR_Type::@244221304127174261110374135210036304371376321171::T
uint32_t T
bit: 24 Thumb bit
Definition core_sc300.h:271
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition core_armv81mml.h:4204
APSR_Type::@341032015064031271002321246151141077202014226010::_reserved0
uint32_t _reserved0
bit: 0..26 Reserved
Definition core_sc300.h:215
CONTROL_Type::@264116250335015102300022317301315003367214310221::SPSEL
uint32_t SPSEL
bit: 1 Stack to be used
Definition core_sc300.h:319
xPSR_Type::@244221304127174261110374135210036304371376321171::V
uint32_t V
bit: 28 Overflow condition code flag
Definition core_sc300.h:274
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
CM7 uses 4 Bits for the Priority Levels.
Definition stm32h723xx.h:216
COMP2
#define COMP2
Definition stm32h723xx.h:2470
COMP1
#define COMP1
Definition stm32h723xx.h:2469
IRQn_Type
IRQn_Type
STM32H7XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32h723xx.h:49
SysTick_IRQn
@ SysTick_IRQn
15 Cortex-M System Tick Interrupt
Definition stm32h723xx.h:59
b
*brief create JSON pointer *sa reference_tokens const string_t const string_t & b
Definition json.hpp:13878
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition core_armv81mml.h:2624
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition core_armv81mml.h:1180
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition core_armv81mml.h:1079
MPU_Type
Structure type to access the Memory Protection Unit (MPU).
Definition core_armv81mml.h:2281
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition core_armv81mml.h:476
SCB_Type
Structure type to access the System Control Block (SCB).
Definition core_armv81mml.h:512
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition core_armv81mml.h:1002
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition core_armv81mml.h:1027
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition core_armv81mml.h:1366
ch
static std::string ch(int ain, const std::string &kind, const std::string &extra="", const std::string &board="lj")
Definition test_t7.cpp:98
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition core_armv81mml.h:329
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition core_armv81mml.h:437
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition core_armv81mml.h:368
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition core_armv81mml.h:386