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core_cm4.h
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1/**************************************************************************//**
2 * @file core_cm4.h
3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
4 * @version V5.1.2
5 * @date 04. June 2021
6 ******************************************************************************/
7/*
8 * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25#if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27#elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29#endif
30
31#ifndef __CORE_CM4_H_GENERIC
32#define __CORE_CM4_H_GENERIC
33
34#include <stdint.h>
35
36#ifdef __cplusplus
37 extern "C" {
38#endif
39
40/**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55/*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58/**
59 \ingroup Cortex_M4
60 @{
61 */
62
63#include "cmsis_version.h"
64
65/* CMSIS CM4 definitions */
66#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
67#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
68#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
69 __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
70
71#define __CORTEX_M (4U) /*!< Cortex-M Core */
72
73/** __FPU_USED indicates whether an FPU is used or not.
74 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
75*/
76#if defined ( __CC_ARM )
77 #if defined __TARGET_FPU_VFP
78 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
79 #define __FPU_USED 1U
80 #else
81 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
82 #define __FPU_USED 0U
83 #endif
84 #else
85 #define __FPU_USED 0U
86 #endif
87
88#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
89 #if defined __ARM_FP
90 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
91 #define __FPU_USED 1U
92 #else
93 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
94 #define __FPU_USED 0U
95 #endif
96 #else
97 #define __FPU_USED 0U
98 #endif
99
100#elif defined ( __GNUC__ )
101 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
102 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
103 #define __FPU_USED 1U
104 #else
105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106 #define __FPU_USED 0U
107 #endif
108 #else
109 #define __FPU_USED 0U
110 #endif
111
112#elif defined ( __ICCARM__ )
113 #if defined __ARMVFP__
114 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
115 #define __FPU_USED 1U
116 #else
117 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
118 #define __FPU_USED 0U
119 #endif
120 #else
121 #define __FPU_USED 0U
122 #endif
123
124#elif defined ( __TI_ARM__ )
125 #if defined __TI_VFP_SUPPORT__
126 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
127 #define __FPU_USED 1U
128 #else
129 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
130 #define __FPU_USED 0U
131 #endif
132 #else
133 #define __FPU_USED 0U
134 #endif
135
136#elif defined ( __TASKING__ )
137 #if defined __FPU_VFP__
138 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
139 #define __FPU_USED 1U
140 #else
141 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
142 #define __FPU_USED 0U
143 #endif
144 #else
145 #define __FPU_USED 0U
146 #endif
147
148#elif defined ( __CSMC__ )
149 #if ( __CSMC__ & 0x400U)
150 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
151 #define __FPU_USED 1U
152 #else
153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
154 #define __FPU_USED 0U
155 #endif
156 #else
157 #define __FPU_USED 0U
158 #endif
159
160#endif
161
162#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
163
164
165#ifdef __cplusplus
166}
167#endif
168
169#endif /* __CORE_CM4_H_GENERIC */
170
171#ifndef __CMSIS_GENERIC
172
173#ifndef __CORE_CM4_H_DEPENDANT
174#define __CORE_CM4_H_DEPENDANT
175
176#ifdef __cplusplus
177 extern "C" {
178#endif
179
180/* check device defines and use defaults */
181#if defined __CHECK_DEVICE_DEFINES
182 #ifndef __CM4_REV
183 #define __CM4_REV 0x0000U
184 #warning "__CM4_REV not defined in device header file; using default!"
185 #endif
186
187 #ifndef __FPU_PRESENT
188 #define __FPU_PRESENT 0U
189 #warning "__FPU_PRESENT not defined in device header file; using default!"
190 #endif
191
192 #ifndef __MPU_PRESENT
193 #define __MPU_PRESENT 0U
194 #warning "__MPU_PRESENT not defined in device header file; using default!"
195 #endif
196
197 #ifndef __VTOR_PRESENT
198 #define __VTOR_PRESENT 1U
199 #warning "__VTOR_PRESENT not defined in device header file; using default!"
200 #endif
201
202 #ifndef __NVIC_PRIO_BITS
203 #define __NVIC_PRIO_BITS 3U
204 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
205 #endif
206
207 #ifndef __Vendor_SysTickConfig
208 #define __Vendor_SysTickConfig 0U
209 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
210 #endif
211#endif
212
213/* IO definitions (access restrictions to peripheral registers) */
214/**
215 \defgroup CMSIS_glob_defs CMSIS Global Defines
216
217 <strong>IO Type Qualifiers</strong> are used
218 \li to specify the access to peripheral variables.
219 \li for automatic generation of peripheral register debug information.
220*/
221#ifdef __cplusplus
222 #define __I volatile /*!< Defines 'read only' permissions */
223#else
224 #define __I volatile const /*!< Defines 'read only' permissions */
225#endif
226#define __O volatile /*!< Defines 'write only' permissions */
227#define __IO volatile /*!< Defines 'read / write' permissions */
228
229/* following defines should be used for structure members */
230#define __IM volatile const /*! Defines 'read only' structure member permissions */
231#define __OM volatile /*! Defines 'write only' structure member permissions */
232#define __IOM volatile /*! Defines 'read / write' structure member permissions */
233
234/*@} end of group Cortex_M4 */
235
236
237
238/*******************************************************************************
239 * Register Abstraction
240 Core Register contain:
241 - Core Register
242 - Core NVIC Register
243 - Core SCB Register
244 - Core SysTick Register
245 - Core Debug Register
246 - Core MPU Register
247 - Core FPU Register
248 ******************************************************************************/
249/**
250 \defgroup CMSIS_core_register Defines and Type Definitions
251 \brief Type definitions and defines for Cortex-M processor based devices.
252*/
253
254/**
255 \ingroup CMSIS_core_register
256 \defgroup CMSIS_CORE Status and Control Registers
257 \brief Core Register type definitions.
258 @{
259 */
260
261/**
262 \brief Union type to access the Application Program Status Register (APSR).
263 */
264typedef union
265{
266 struct
267 {
268 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
269 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
270 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
271 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
272 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
273 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
274 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
275 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
276 } b; /*!< Structure used for bit access */
277 uint32_t w; /*!< Type used for word access */
278} APSR_Type;
279
280/* APSR Register Definitions */
281#define APSR_N_Pos 31U /*!< APSR: N Position */
282#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
283
284#define APSR_Z_Pos 30U /*!< APSR: Z Position */
285#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
286
287#define APSR_C_Pos 29U /*!< APSR: C Position */
288#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
289
290#define APSR_V_Pos 28U /*!< APSR: V Position */
291#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
292
293#define APSR_Q_Pos 27U /*!< APSR: Q Position */
294#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
295
296#define APSR_GE_Pos 16U /*!< APSR: GE Position */
297#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
298
299
300/**
301 \brief Union type to access the Interrupt Program Status Register (IPSR).
302 */
303typedef union
304{
305 struct
306 {
307 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
308 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
309 } b; /*!< Structure used for bit access */
310 uint32_t w; /*!< Type used for word access */
311} IPSR_Type;
312
313/* IPSR Register Definitions */
314#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
315#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
316
317
318/**
319 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
320 */
321typedef union
322{
323 struct
324 {
325 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
326 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
327 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
328 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
329 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
330 uint32_t T:1; /*!< bit: 24 Thumb bit */
331 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
332 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
333 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
334 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
335 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
336 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
337 } b; /*!< Structure used for bit access */
338 uint32_t w; /*!< Type used for word access */
339} xPSR_Type;
340
341/* xPSR Register Definitions */
342#define xPSR_N_Pos 31U /*!< xPSR: N Position */
343#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
344
345#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
346#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
347
348#define xPSR_C_Pos 29U /*!< xPSR: C Position */
349#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
350
351#define xPSR_V_Pos 28U /*!< xPSR: V Position */
352#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
353
354#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
355#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
356
357#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
358#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
359
360#define xPSR_T_Pos 24U /*!< xPSR: T Position */
361#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
362
363#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
364#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
365
366#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
367#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
368
369#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
370#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
371
372
373/**
374 \brief Union type to access the Control Registers (CONTROL).
375 */
376typedef union
377{
378 struct
379 {
380 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
381 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
382 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
383 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
384 } b; /*!< Structure used for bit access */
385 uint32_t w; /*!< Type used for word access */
386} CONTROL_Type;
387
388/* CONTROL Register Definitions */
389#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
390#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
391
392#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
393#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
394
395#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
396#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
397
398/*@} end of group CMSIS_CORE */
399
400
401/**
402 \ingroup CMSIS_core_register
403 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
404 \brief Type definitions for the NVIC Registers
405 @{
406 */
407
408/**
409 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
410 */
411typedef struct
412{
413 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
414 uint32_t RESERVED0[24U];
415 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
416 uint32_t RESERVED1[24U];
417 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
418 uint32_t RESERVED2[24U];
419 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
420 uint32_t RESERVED3[24U];
421 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
422 uint32_t RESERVED4[56U];
423 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
424 uint32_t RESERVED5[644U];
425 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
426} NVIC_Type;
427
428/* Software Triggered Interrupt Register Definitions */
429#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
430#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
431
432/*@} end of group CMSIS_NVIC */
433
434
435/**
436 \ingroup CMSIS_core_register
437 \defgroup CMSIS_SCB System Control Block (SCB)
438 \brief Type definitions for the System Control Block Registers
439 @{
440 */
441
442/**
443 \brief Structure type to access the System Control Block (SCB).
444 */
445typedef struct
446{
447 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
448 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
449 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
450 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
451 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
452 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
453 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
454 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
455 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
456 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
457 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
458 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
459 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
460 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
461 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
462 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
463 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
464 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
465 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
466 uint32_t RESERVED0[5U];
467 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
468} SCB_Type;
469
470/* SCB CPUID Register Definitions */
471#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
472#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
473
474#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
475#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
476
477#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
478#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
479
480#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
481#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
482
483#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
484#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
485
486/* SCB Interrupt Control State Register Definitions */
487#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
488#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
489
490#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
491#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
492
493#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
494#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
495
496#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
497#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
498
499#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
500#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
501
502#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
503#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
504
505#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
506#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
507
508#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
509#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
510
511#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
512#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
513
514#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
515#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
516
517/* SCB Vector Table Offset Register Definitions */
518#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
519#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
520
521/* SCB Application Interrupt and Reset Control Register Definitions */
522#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
523#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
524
525#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
526#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
527
528#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
529#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
530
531#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
532#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
533
534#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
535#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
536
537#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
538#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
539
540#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
541#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
542
543/* SCB System Control Register Definitions */
544#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
545#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
546
547#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
548#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
549
550#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
551#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
552
553/* SCB Configuration Control Register Definitions */
554#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
555#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
556
557#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
558#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
559
560#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
561#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
562
563#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
564#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
565
566#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
567#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
568
569#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
570#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
571
572/* SCB System Handler Control and State Register Definitions */
573#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
574#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
575
576#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
577#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
578
579#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
580#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
581
582#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
583#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
584
585#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
586#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
587
588#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
589#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
590
591#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
592#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
593
594#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
595#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
596
597#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
598#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
599
600#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
601#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
602
603#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
604#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
605
606#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
607#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
608
609#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
610#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
611
612#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
613#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
614
615/* SCB Configurable Fault Status Register Definitions */
616#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
617#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
618
619#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
620#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
621
622#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
623#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
624
625/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
626#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
627#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
628
629#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
630#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
631
632#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
633#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
634
635#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
636#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
637
638#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
639#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
640
641#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
642#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
643
644/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
645#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
646#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
647
648#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
649#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
650
651#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
652#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
653
654#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
655#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
656
657#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
658#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
659
660#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
661#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
662
663#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
664#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
665
666/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
667#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
668#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
669
670#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
671#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
672
673#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
674#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
675
676#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
677#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
678
679#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
680#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
681
682#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
683#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
684
685/* SCB Hard Fault Status Register Definitions */
686#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
687#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
688
689#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
690#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
691
692#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
693#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
694
695/* SCB Debug Fault Status Register Definitions */
696#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
697#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
698
699#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
700#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
701
702#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
703#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
704
705#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
706#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
707
708#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
709#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
710
711/*@} end of group CMSIS_SCB */
712
713
714/**
715 \ingroup CMSIS_core_register
716 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
717 \brief Type definitions for the System Control and ID Register not in the SCB
718 @{
719 */
720
721/**
722 \brief Structure type to access the System Control and ID Register not in the SCB.
723 */
724typedef struct
725{
726 uint32_t RESERVED0[1U];
727 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
728 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
729} SCnSCB_Type;
730
731/* Interrupt Controller Type Register Definitions */
732#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
733#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
734
735/* Auxiliary Control Register Definitions */
736#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
737#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
738
739#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
740#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
741
742#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
743#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
744
745#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
746#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
747
748#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
749#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
750
751/*@} end of group CMSIS_SCnotSCB */
752
753
754/**
755 \ingroup CMSIS_core_register
756 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
757 \brief Type definitions for the System Timer Registers.
758 @{
759 */
760
761/**
762 \brief Structure type to access the System Timer (SysTick).
763 */
764typedef struct
765{
766 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
767 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
768 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
769 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
770} SysTick_Type;
771
772/* SysTick Control / Status Register Definitions */
773#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
774#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
775
776#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
777#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
778
779#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
780#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
781
782#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
783#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
784
785/* SysTick Reload Register Definitions */
786#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
787#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
788
789/* SysTick Current Register Definitions */
790#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
791#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
792
793/* SysTick Calibration Register Definitions */
794#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
795#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
796
797#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
798#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
799
800#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
801#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
802
803/*@} end of group CMSIS_SysTick */
804
805
806/**
807 \ingroup CMSIS_core_register
808 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
809 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
810 @{
811 */
812
813/**
814 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
815 */
816typedef struct
817{
818 __OM union
819 {
820 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
821 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
822 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
823 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
824 uint32_t RESERVED0[864U];
825 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
826 uint32_t RESERVED1[15U];
827 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
828 uint32_t RESERVED2[15U];
829 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
830 uint32_t RESERVED3[32U];
831 uint32_t RESERVED4[43U];
832 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
833 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
834 uint32_t RESERVED5[6U];
835 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
836 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
837 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
838 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
839 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
840 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
841 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
842 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
843 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
844 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
845 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
846 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
847} ITM_Type;
848
849/* ITM Trace Privilege Register Definitions */
850#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
851#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
852
853/* ITM Trace Control Register Definitions */
854#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
855#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
856
857#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
858#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
859
860#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
861#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
862
863#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
864#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
865
866#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
867#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
868
869#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
870#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
871
872#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
873#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
874
875#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
876#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
877
878#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
879#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
880
881/* ITM Lock Status Register Definitions */
882#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
883#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
884
885#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
886#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
887
888#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
889#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
890
891/*@}*/ /* end of group CMSIS_ITM */
892
893
894/**
895 \ingroup CMSIS_core_register
896 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
897 \brief Type definitions for the Data Watchpoint and Trace (DWT)
898 @{
899 */
900
901/**
902 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
903 */
904typedef struct
905{
906 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
907 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
908 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
909 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
910 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
911 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
912 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
913 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
914 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
915 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
916 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
917 uint32_t RESERVED0[1U];
918 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
919 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
920 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
921 uint32_t RESERVED1[1U];
922 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
923 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
924 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
925 uint32_t RESERVED2[1U];
926 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
927 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
928 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
929} DWT_Type;
930
931/* DWT Control Register Definitions */
932#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
933#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
934
935#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
936#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
937
938#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
939#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
940
941#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
942#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
943
944#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
945#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
946
947#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
948#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
949
950#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
951#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
952
953#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
954#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
955
956#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
957#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
958
959#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
960#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
961
962#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
963#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
964
965#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
966#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
967
968#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
969#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
970
971#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
972#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
973
974#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
975#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
976
977#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
978#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
979
980#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
981#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
982
983#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
984#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
985
986/* DWT CPI Count Register Definitions */
987#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
988#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
989
990/* DWT Exception Overhead Count Register Definitions */
991#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
992#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
993
994/* DWT Sleep Count Register Definitions */
995#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
996#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
997
998/* DWT LSU Count Register Definitions */
999#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
1000#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
1001
1002/* DWT Folded-instruction Count Register Definitions */
1003#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
1004#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
1005
1006/* DWT Comparator Mask Register Definitions */
1007#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
1008#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
1009
1010/* DWT Comparator Function Register Definitions */
1011#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
1012#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
1013
1014#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
1015#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
1016
1017#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
1018#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
1019
1020#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
1021#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
1022
1023#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
1024#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
1025
1026#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
1027#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
1028
1029#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
1030#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
1031
1032#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
1033#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
1034
1035#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
1036#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
1037
1038/*@}*/ /* end of group CMSIS_DWT */
1039
1040
1041/**
1042 \ingroup CMSIS_core_register
1043 \defgroup CMSIS_TPI Trace Port Interface (TPI)
1044 \brief Type definitions for the Trace Port Interface (TPI)
1045 @{
1046 */
1047
1048/**
1049 \brief Structure type to access the Trace Port Interface Register (TPI).
1050 */
1051typedef struct
1052{
1053 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
1054 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
1055 uint32_t RESERVED0[2U];
1056 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1057 uint32_t RESERVED1[55U];
1058 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1059 uint32_t RESERVED2[131U];
1060 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1061 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1062 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
1063 uint32_t RESERVED3[759U];
1064 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1065 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1066 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1067 uint32_t RESERVED4[1U];
1068 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1069 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1070 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1071 uint32_t RESERVED5[39U];
1072 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1073 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1074 uint32_t RESERVED7[8U];
1075 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1076 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
1077} TPI_Type;
1078
1079/* TPI Asynchronous Clock Prescaler Register Definitions */
1080#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
1081#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
1082
1083/* TPI Selected Pin Protocol Register Definitions */
1084#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
1085#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
1086
1087/* TPI Formatter and Flush Status Register Definitions */
1088#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
1089#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
1090
1091#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
1092#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
1093
1094#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
1095#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
1096
1097#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
1098#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
1099
1100/* TPI Formatter and Flush Control Register Definitions */
1101#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
1102#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
1103
1104#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
1105#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
1106
1107/* TPI TRIGGER Register Definitions */
1108#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
1109#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
1110
1111/* TPI Integration ETM Data Register Definitions (FIFO0) */
1112#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
1113#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
1114
1115#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
1116#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
1117
1118#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
1119#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
1120
1121#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
1122#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
1123
1124#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
1125#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
1126
1127#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
1128#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
1129
1130#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
1131#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
1132
1133/* TPI ITATBCTR2 Register Definitions */
1134#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
1135#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
1136
1137#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
1138#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
1139
1140/* TPI Integration ITM Data Register Definitions (FIFO1) */
1141#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
1142#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
1143
1144#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
1145#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
1146
1147#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
1148#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
1149
1150#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
1151#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
1152
1153#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
1154#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
1155
1156#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
1157#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
1158
1159#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
1160#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
1161
1162/* TPI ITATBCTR0 Register Definitions */
1163#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
1164#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
1165
1166#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
1167#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
1168
1169/* TPI Integration Mode Control Register Definitions */
1170#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
1171#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
1172
1173/* TPI DEVID Register Definitions */
1174#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
1175#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1176
1177#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
1178#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1179
1180#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
1181#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1182
1183#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
1184#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1185
1186#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
1187#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1188
1189#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
1190#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
1191
1192/* TPI DEVTYPE Register Definitions */
1193#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
1194#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
1195
1196#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
1197#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1198
1199/*@}*/ /* end of group CMSIS_TPI */
1200
1201
1202#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1203/**
1204 \ingroup CMSIS_core_register
1205 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1206 \brief Type definitions for the Memory Protection Unit (MPU)
1207 @{
1208 */
1209
1210/**
1211 \brief Structure type to access the Memory Protection Unit (MPU).
1212 */
1213typedef struct
1214{
1215 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1216 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1217 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1218 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1219 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1220 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1221 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1222 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1223 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1224 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1225 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1226} MPU_Type;
1227
1228#define MPU_TYPE_RALIASES 4U
1229
1230/* MPU Type Register Definitions */
1231#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1232#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1233
1234#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1235#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1236
1237#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1238#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1239
1240/* MPU Control Register Definitions */
1241#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1242#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1243
1244#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1245#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1246
1247#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1248#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1249
1250/* MPU Region Number Register Definitions */
1251#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1252#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1253
1254/* MPU Region Base Address Register Definitions */
1255#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
1256#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1257
1258#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
1259#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1260
1261#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
1262#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
1263
1264/* MPU Region Attribute and Size Register Definitions */
1265#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
1266#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1267
1268#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
1269#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1270
1271#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
1272#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1273
1274#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
1275#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1276
1277#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
1278#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1279
1280#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
1281#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1282
1283#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
1284#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1285
1286#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
1287#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1288
1289#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
1290#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1291
1292#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
1293#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
1294
1295/*@} end of group CMSIS_MPU */
1296#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
1297
1298
1299/**
1300 \ingroup CMSIS_core_register
1301 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1302 \brief Type definitions for the Floating Point Unit (FPU)
1303 @{
1304 */
1305
1306/**
1307 \brief Structure type to access the Floating Point Unit (FPU).
1308 */
1309typedef struct
1310{
1311 uint32_t RESERVED0[1U];
1312 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1313 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1314 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1315 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
1316 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
1317 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
1318} FPU_Type;
1319
1320/* Floating-Point Context Control Register Definitions */
1321#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
1322#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1323
1324#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
1325#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1326
1327#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
1328#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1329
1330#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
1331#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1332
1333#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
1334#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1335
1336#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
1337#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1338
1339#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
1340#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1341
1342#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
1343#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1344
1345#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
1346#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
1347
1348/* Floating-Point Context Address Register Definitions */
1349#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
1350#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1351
1352/* Floating-Point Default Status Control Register Definitions */
1353#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
1354#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1355
1356#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
1357#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1358
1359#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
1360#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1361
1362#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
1363#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1364
1365/* Media and FP Feature Register 0 Definitions */
1366#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
1367#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
1368
1369#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
1370#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
1371
1372#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
1373#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
1374
1375#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
1376#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
1377
1378#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
1379#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
1380
1381#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
1382#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
1383
1384#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
1385#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
1386
1387#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
1388#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
1389
1390/* Media and FP Feature Register 1 Definitions */
1391#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
1392#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
1393
1394#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
1395#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1396
1397#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
1398#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1399
1400#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
1401#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
1402
1403/* Media and FP Feature Register 2 Definitions */
1404
1405#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
1406#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */
1407
1408/*@} end of group CMSIS_FPU */
1409
1410
1411/**
1412 \ingroup CMSIS_core_register
1413 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1414 \brief Type definitions for the Core Debug Registers
1415 @{
1416 */
1417
1418/**
1419 \brief Structure type to access the Core Debug Register (CoreDebug).
1420 */
1421typedef struct
1422{
1423 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1424 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1425 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1426 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1427} CoreDebug_Type;
1428
1429/* Debug Halting Control and Status Register Definitions */
1430#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
1431#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1432
1433#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
1434#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1435
1436#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1437#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1438
1439#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
1440#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1441
1442#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
1443#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1444
1445#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
1446#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1447
1448#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
1449#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1450
1451#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1452#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1453
1454#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
1455#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1456
1457#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
1458#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1459
1460#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
1461#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1462
1463#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1464#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1465
1466/* Debug Core Register Selector Register Definitions */
1467#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
1468#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1469
1470#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
1471#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
1472
1473/* Debug Exception and Monitor Control Register Definitions */
1474#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
1475#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1476
1477#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
1478#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1479
1480#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
1481#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1482
1483#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
1484#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1485
1486#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
1487#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1488
1489#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
1490#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1491
1492#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
1493#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1494
1495#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
1496#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1497
1498#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
1499#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1500
1501#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
1502#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1503
1504#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1505#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1506
1507#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
1508#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1509
1510#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
1511#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1512
1513/*@} end of group CMSIS_CoreDebug */
1514
1515
1516/**
1517 \ingroup CMSIS_core_register
1518 \defgroup CMSIS_core_bitfield Core register bit field macros
1519 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1520 @{
1521 */
1522
1523/**
1524 \brief Mask and shift a bit field value for use in a register bit range.
1525 \param[in] field Name of the register bit field.
1526 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1527 \return Masked and shifted value.
1528*/
1529#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1530
1531/**
1532 \brief Mask and shift a register value to extract a bit filed value.
1533 \param[in] field Name of the register bit field.
1534 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
1535 \return Masked and shifted bit field value.
1536*/
1537#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1538
1539/*@} end of group CMSIS_core_bitfield */
1540
1541
1542/**
1543 \ingroup CMSIS_core_register
1544 \defgroup CMSIS_core_base Core Definitions
1545 \brief Definitions for base addresses, unions, and structures.
1546 @{
1547 */
1548
1549/* Memory mapping of Core Hardware */
1550#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1551#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1552#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1553#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1554#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1555#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1556#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1557#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1558
1559#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1560#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1561#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1562#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1563#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1564#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1565#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1566#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1567
1568#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1569 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1570 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1571#endif
1572
1573#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
1574#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
1575
1576/*@} */
1577
1578
1579
1580/*******************************************************************************
1581 * Hardware Abstraction Layer
1582 Core Function Interface contains:
1583 - Core NVIC Functions
1584 - Core SysTick Functions
1585 - Core Debug Functions
1586 - Core Register Access Functions
1587 ******************************************************************************/
1588/**
1589 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1590*/
1591
1592
1593
1594/* ########################## NVIC functions #################################### */
1595/**
1596 \ingroup CMSIS_Core_FunctionInterface
1597 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1598 \brief Functions that manage interrupts and exceptions via the NVIC.
1599 @{
1600 */
1601
1602#ifdef CMSIS_NVIC_VIRTUAL
1603 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1604 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1605 #endif
1606 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1607#else
1608 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1609 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1610 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1611 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1612 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1613 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1614 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1615 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1616 #define NVIC_GetActive __NVIC_GetActive
1617 #define NVIC_SetPriority __NVIC_SetPriority
1618 #define NVIC_GetPriority __NVIC_GetPriority
1619 #define NVIC_SystemReset __NVIC_SystemReset
1620#endif /* CMSIS_NVIC_VIRTUAL */
1621
1622#ifdef CMSIS_VECTAB_VIRTUAL
1623 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1624 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1625 #endif
1626 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1627#else
1628 #define NVIC_SetVector __NVIC_SetVector
1629 #define NVIC_GetVector __NVIC_GetVector
1630#endif /* (CMSIS_VECTAB_VIRTUAL) */
1631
1632#define NVIC_USER_IRQ_OFFSET 16
1633
1634
1635/* The following EXC_RETURN values are saved the LR on exception entry */
1636#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
1637#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
1638#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
1639#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
1640#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
1641#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
1642
1643
1644/**
1645 \brief Set Priority Grouping
1646 \details Sets the priority grouping field using the required unlock sequence.
1647 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1648 Only values from 0..7 are used.
1649 In case of a conflict between priority grouping and available
1650 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1651 \param [in] PriorityGroup Priority grouping field.
1652 */
1653__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1654{
1655 uint32_t reg_value;
1656 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1657
1658 reg_value = SCB->AIRCR; /* read old register configuration */
1659 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1660 reg_value = (reg_value |
1661 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1662 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
1663 SCB->AIRCR = reg_value;
1664}
1665
1666
1667/**
1668 \brief Get Priority Grouping
1669 \details Reads the priority grouping field from the NVIC Interrupt Controller.
1670 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1671 */
1672__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
1673{
1674 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1675}
1676
1677
1678/**
1679 \brief Enable Interrupt
1680 \details Enables a device specific interrupt in the NVIC interrupt controller.
1681 \param [in] IRQn Device specific interrupt number.
1682 \note IRQn must not be negative.
1683 */
1684__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1685{
1686 if ((int32_t)(IRQn) >= 0)
1687 {
1688 __COMPILER_BARRIER();
1689 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1690 __COMPILER_BARRIER();
1691 }
1692}
1693
1694
1695/**
1696 \brief Get Interrupt Enable status
1697 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
1698 \param [in] IRQn Device specific interrupt number.
1699 \return 0 Interrupt is not enabled.
1700 \return 1 Interrupt is enabled.
1701 \note IRQn must not be negative.
1702 */
1703__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1704{
1705 if ((int32_t)(IRQn) >= 0)
1706 {
1707 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1708 }
1709 else
1710 {
1711 return(0U);
1712 }
1713}
1714
1715
1716/**
1717 \brief Disable Interrupt
1718 \details Disables a device specific interrupt in the NVIC interrupt controller.
1719 \param [in] IRQn Device specific interrupt number.
1720 \note IRQn must not be negative.
1721 */
1722__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1723{
1724 if ((int32_t)(IRQn) >= 0)
1725 {
1726 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1727 __DSB();
1728 __ISB();
1729 }
1730}
1731
1732
1733/**
1734 \brief Get Pending Interrupt
1735 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
1736 \param [in] IRQn Device specific interrupt number.
1737 \return 0 Interrupt status is not pending.
1738 \return 1 Interrupt status is pending.
1739 \note IRQn must not be negative.
1740 */
1741__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1742{
1743 if ((int32_t)(IRQn) >= 0)
1744 {
1745 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1746 }
1747 else
1748 {
1749 return(0U);
1750 }
1751}
1752
1753
1754/**
1755 \brief Set Pending Interrupt
1756 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
1757 \param [in] IRQn Device specific interrupt number.
1758 \note IRQn must not be negative.
1759 */
1760__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1761{
1762 if ((int32_t)(IRQn) >= 0)
1763 {
1764 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1765 }
1766}
1767
1768
1769/**
1770 \brief Clear Pending Interrupt
1771 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
1772 \param [in] IRQn Device specific interrupt number.
1773 \note IRQn must not be negative.
1774 */
1775__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1776{
1777 if ((int32_t)(IRQn) >= 0)
1778 {
1779 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1780 }
1781}
1782
1783
1784/**
1785 \brief Get Active Interrupt
1786 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
1787 \param [in] IRQn Device specific interrupt number.
1788 \return 0 Interrupt status is not active.
1789 \return 1 Interrupt status is active.
1790 \note IRQn must not be negative.
1791 */
1792__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1793{
1794 if ((int32_t)(IRQn) >= 0)
1795 {
1796 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1797 }
1798 else
1799 {
1800 return(0U);
1801 }
1802}
1803
1804
1805/**
1806 \brief Set Interrupt Priority
1807 \details Sets the priority of a device specific interrupt or a processor exception.
1808 The interrupt number can be positive to specify a device specific interrupt,
1809 or negative to specify a processor exception.
1810 \param [in] IRQn Interrupt number.
1811 \param [in] priority Priority to set.
1812 \note The priority cannot be set for every processor exception.
1813 */
1814__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1815{
1816 if ((int32_t)(IRQn) >= 0)
1817 {
1818 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1819 }
1820 else
1821 {
1822 SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1823 }
1824}
1825
1826
1827/**
1828 \brief Get Interrupt Priority
1829 \details Reads the priority of a device specific interrupt or a processor exception.
1830 The interrupt number can be positive to specify a device specific interrupt,
1831 or negative to specify a processor exception.
1832 \param [in] IRQn Interrupt number.
1833 \return Interrupt Priority.
1834 Value is aligned automatically to the implemented priority bits of the microcontroller.
1835 */
1836__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1837{
1838
1839 if ((int32_t)(IRQn) >= 0)
1840 {
1841 return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
1842 }
1843 else
1844 {
1845 return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
1846 }
1847}
1848
1849
1850/**
1851 \brief Encode Priority
1852 \details Encodes the priority for an interrupt with the given priority group,
1853 preemptive priority value, and subpriority value.
1854 In case of a conflict between priority grouping and available
1855 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1856 \param [in] PriorityGroup Used priority group.
1857 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1858 \param [in] SubPriority Subpriority value (starting from 0).
1859 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1860 */
1861__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1862{
1863 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1864 uint32_t PreemptPriorityBits;
1865 uint32_t SubPriorityBits;
1866
1867 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1868 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1869
1870 return (
1871 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1872 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1873 );
1874}
1875
1876
1877/**
1878 \brief Decode Priority
1879 \details Decodes an interrupt priority value with a given priority group to
1880 preemptive priority value and subpriority value.
1881 In case of a conflict between priority grouping and available
1882 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1883 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1884 \param [in] PriorityGroup Used priority group.
1885 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1886 \param [out] pSubPriority Subpriority value (starting from 0).
1887 */
1888__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1889{
1890 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1891 uint32_t PreemptPriorityBits;
1892 uint32_t SubPriorityBits;
1893
1894 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1895 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1896
1897 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1898 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1899}
1900
1901
1902/**
1903 \brief Set Interrupt Vector
1904 \details Sets an interrupt vector in SRAM based interrupt vector table.
1905 The interrupt number can be positive to specify a device specific interrupt,
1906 or negative to specify a processor exception.
1907 VTOR must been relocated to SRAM before.
1908 \param [in] IRQn Interrupt number
1909 \param [in] vector Address of interrupt handler function
1910 */
1911__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1912{
1913 uint32_t *vectors = (uint32_t *)SCB->VTOR;
1914 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1915 /* ARM Application Note 321 states that the M4 does not require the architectural barrier */
1916}
1917
1918
1919/**
1920 \brief Get Interrupt Vector
1921 \details Reads an interrupt vector from interrupt vector table.
1922 The interrupt number can be positive to specify a device specific interrupt,
1923 or negative to specify a processor exception.
1924 \param [in] IRQn Interrupt number.
1925 \return Address of interrupt handler function
1926 */
1927__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1928{
1929 uint32_t *vectors = (uint32_t *)SCB->VTOR;
1930 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1931}
1932
1933
1934/**
1935 \brief System Reset
1936 \details Initiates a system reset request to reset the MCU.
1937 */
1938__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
1939{
1940 __DSB(); /* Ensure all outstanding memory accesses included
1941 buffered write are completed before reset */
1942 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1943 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1944 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
1945 __DSB(); /* Ensure completion of memory access */
1946
1947 for(;;) /* wait until reset */
1948 {
1949 __NOP();
1950 }
1951}
1952
1953/*@} end of CMSIS_Core_NVICFunctions */
1954
1955
1956/* ########################## MPU functions #################################### */
1957
1958#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1959
1960#include "mpu_armv7.h"
1961
1962#endif
1963
1964
1965/* ########################## FPU functions #################################### */
1966/**
1967 \ingroup CMSIS_Core_FunctionInterface
1968 \defgroup CMSIS_Core_FpuFunctions FPU Functions
1969 \brief Function that provides FPU type.
1970 @{
1971 */
1972
1973/**
1974 \brief get FPU type
1975 \details returns the FPU type
1976 \returns
1977 - \b 0: No FPU
1978 - \b 1: Single precision FPU
1979 - \b 2: Double + Single precision FPU
1980 */
1981__STATIC_INLINE uint32_t SCB_GetFPUType(void)
1982{
1983 uint32_t mvfr0;
1984
1985 mvfr0 = FPU->MVFR0;
1986 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
1987 {
1988 return 1U; /* Single precision FPU */
1989 }
1990 else
1991 {
1992 return 0U; /* No FPU */
1993 }
1994}
1995
1996
1997/*@} end of CMSIS_Core_FpuFunctions */
1998
1999
2000
2001/* ################################## SysTick function ############################################ */
2002/**
2003 \ingroup CMSIS_Core_FunctionInterface
2004 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
2005 \brief Functions that configure the System.
2006 @{
2007 */
2008
2009#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2010
2011/**
2012 \brief System Tick Configuration
2013 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
2014 Counter is in free running mode to generate periodic interrupts.
2015 \param [in] ticks Number of ticks between two interrupts.
2016 \return 0 Function succeeded.
2017 \return 1 Function failed.
2018 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2019 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
2020 must contain a vendor-specific implementation of this function.
2021 */
2022__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2023{
2024 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2025 {
2026 return (1UL); /* Reload value impossible */
2027 }
2028
2029 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2030 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2031 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2032 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2033 SysTick_CTRL_TICKINT_Msk |
2034 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2035 return (0UL); /* Function successful */
2036}
2037
2038#endif
2039
2040/*@} end of CMSIS_Core_SysTickFunctions */
2041
2042
2043
2044/* ##################################### Debug In/Output function ########################################### */
2045/**
2046 \ingroup CMSIS_Core_FunctionInterface
2047 \defgroup CMSIS_core_DebugFunctions ITM Functions
2048 \brief Functions that access the ITM debug interface.
2049 @{
2050 */
2051
2052extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
2053#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
2054
2055
2056/**
2057 \brief ITM Send Character
2058 \details Transmits a character via the ITM channel 0, and
2059 \li Just returns when no debugger is connected that has booked the output.
2060 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
2061 \param [in] ch Character to transmit.
2062 \returns Character to transmit.
2063 */
2064__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2065{
2066 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2067 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2068 {
2069 while (ITM->PORT[0U].u32 == 0UL)
2070 {
2071 __NOP();
2072 }
2073 ITM->PORT[0U].u8 = (uint8_t)ch;
2074 }
2075 return (ch);
2076}
2077
2078
2079/**
2080 \brief ITM Receive Character
2081 \details Inputs a character via the external variable \ref ITM_RxBuffer.
2082 \return Received character.
2083 \return -1 No character pending.
2084 */
2085__STATIC_INLINE int32_t ITM_ReceiveChar (void)
2086{
2087 int32_t ch = -1; /* no character available */
2088
2089 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2090 {
2091 ch = ITM_RxBuffer;
2092 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2093 }
2094
2095 return (ch);
2096}
2097
2098
2099/**
2100 \brief ITM Check Character
2101 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
2102 \return 0 No character available.
2103 \return 1 Character available.
2104 */
2105__STATIC_INLINE int32_t ITM_CheckChar (void)
2106{
2107
2108 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2109 {
2110 return (0); /* no character available */
2111 }
2112 else
2113 {
2114 return (1); /* character available */
2115 }
2116}
2117
2118/*@} end of CMSIS_core_DebugFunctions */
2119
2120
2121
2122
2123#ifdef __cplusplus
2124}
2125#endif
2126
2127#endif /* __CORE_CM4_H_DEPENDANT */
2128
2129#endif /* __CMSIS_GENERIC */
__NO_RETURN
#define __NO_RETURN
Definition cmsis_armcc.h:70
__COMPILER_BARRIER
#define __COMPILER_BARRIER()
Definition cmsis_armcc.h:109
__STATIC_INLINE
#define __STATIC_INLINE
Definition cmsis_armcc.h:64
cmsis_compiler.h
CMSIS compiler generic header file.
cmsis_version.h
CMSIS Core(M) Version definitions.
__OM
#define __OM
Definition core_armv81mml.h:294
__IM
#define __IM
Definition core_armv81mml.h:293
__IOM
#define __IOM
Definition core_armv81mml.h:295
__OM
#define __OM
Definition core_starmc1.h:293
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
SysTick CTRL: ENABLE Mask.
Definition core_armv81mml.h:1045
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
SysTick LOAD: RELOAD Mask.
Definition core_armv81mml.h:1049
FPU_MVFR0_Double_precision_Msk
#define FPU_MVFR0_Double_precision_Msk
MVFR0: Double-precision bits Mask.
Definition core_armv8mml.h:1698
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
ITM TCR: ITM Enable bit Mask.
Definition core_armv81mml.h:1154
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
SCB AIRCR: PRIGROUP Mask.
Definition core_armv81mml.h:639
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
SCB AIRCR: VECTKEY Mask.
Definition core_armv81mml.h:624
FPU_MVFR0_Single_precision_Msk
#define FPU_MVFR0_Single_precision_Msk
MVFR0: Single-precision bits Mask.
Definition core_armv8mml.h:1701
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
SysTick CTRL: TICKINT Mask.
Definition core_armv81mml.h:1042
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
SysTick CTRL: CLKSOURCE Mask.
Definition core_armv81mml.h:1039
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
SCB AIRCR: VECTKEY Position.
Definition core_armv81mml.h:623
SCB
#define SCB
SCB configuration struct.
Definition core_armv81mml.h:3106
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
SCB AIRCR: SYSRESETREQ Mask.
Definition core_armv81mml.h:651
ITM
#define ITM
ITM configuration struct.
Definition core_armv81mml.h:3109
FPU
#define FPU
Floating Point Unit.
Definition core_armv81mml.h:3132
NVIC
#define NVIC
NVIC configuration struct.
Definition core_armv81mml.h:3108
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
SCB AIRCR: PRIGROUP Position.
Definition core_armv81mml.h:638
SysTick
#define SysTick
SysTick configuration struct.
Definition core_armv81mml.h:3107
__NVIC_SetPriorityGrouping
#define __NVIC_SetPriorityGrouping(X)
Definition core_armv8mbl.h:1440
__NVIC_GetPriorityGrouping
#define __NVIC_GetPriorityGrouping()
Get Priority Grouping.
Definition core_armv8mbl.h:1441
__DSB
#define __DSB()
Data Synchronization Barrier.
Definition cmsis_armcc.h:182
__ISB
#define __ISB()
Instruction Synchronization Barrier.
Definition cmsis_armcc.h:175
__NOP
#define __NOP
No Operation.
Definition cmsis_armcc.h:144
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition core_armv81mml.h:3611
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition core_armv81mml.h:3584
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition core_armv81mml.h:3561
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition core_armv81mml.h:3600
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition core_armv81mml.h:3487
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition core_armv81mml.h:3381
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition core_armv81mml.h:3347
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition core_armv81mml.h:3862
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition core_armv81mml.h:3290
NVIC_USER_IRQ_OFFSET
#define NVIC_USER_IRQ_OFFSET
Definition core_armv81mml.h:3225
__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition core_armv81mml.h:3398
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition core_armv81mml.h:3366
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition core_armv81mml.h:3309
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition core_armv81mml.h:3534
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition core_armv81mml.h:3328
NVIC_SetPriority
#define NVIC_SetPriority
Definition core_cm4.h:1617
SysTick_Config
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Definition core_armv81mml.h:4091
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition core_armv81mml.h:3509
CONTROL_Type::@376065120377227036210154270074010325013015000222::FPCA
uint32_t FPCA
bit: 2 FP extension active flag
Definition core_cm4.h:382
xPSR_Type::@234250120244346044234251003105331241335324323200::V
uint32_t V
bit: 28 Overflow condition code flag
Definition core_cm4.h:333
xPSR_Type::@234250120244346044234251003105331241335324323200::Z
uint32_t Z
bit: 30 Zero condition code flag
Definition core_cm4.h:335
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
External variable to receive characters.
xPSR_Type::@234250120244346044234251003105331241335324323200::ICI_IT_1
uint32_t ICI_IT_1
bit: 10..15 ICI/IT part 1
Definition core_cm4.h:327
ITM_Type::@003257127012074045320030126073143333266333337354::u8
__OM uint8_t u8
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit.
Definition core_cm4.h:820
APSR_Type::@071212370340345021171336265214357066234256200137::Q
uint32_t Q
bit: 27 Saturation condition flag
Definition core_cm4.h:271
IPSR_Type::@143025336042161333275316170130117330351315234334::ISR
uint32_t ISR
bit: 0.
Definition core_cm4.h:307
APSR_Type::@071212370340345021171336265214357066234256200137::GE
uint32_t GE
bit: 16..19 Greater than or Equal flags
Definition core_cm4.h:269
CONTROL_Type::@376065120377227036210154270074010325013015000222::_reserved0
uint32_t _reserved0
bit: 3..31 Reserved
Definition core_cm4.h:383
APSR_Type::@071212370340345021171336265214357066234256200137::Z
uint32_t Z
bit: 30 Zero condition code flag
Definition core_cm4.h:274
APSR_Type::@071212370340345021171336265214357066234256200137::_reserved0
uint32_t _reserved0
bit: 0..15 Reserved
Definition core_cm4.h:268
ITM_Type::@003257127012074045320030126073143333266333337354::u32
__OM uint32_t u32
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit.
Definition core_cm4.h:822
xPSR_Type::@234250120244346044234251003105331241335324323200::GE
uint32_t GE
bit: 16..19 Greater than or Equal flags
Definition core_cm4.h:328
IPSR_Type::@143025336042161333275316170130117330351315234334::_reserved0
uint32_t _reserved0
bit: 9..31 Reserved
Definition core_cm4.h:308
xPSR_Type::@234250120244346044234251003105331241335324323200::N
uint32_t N
bit: 31 Negative condition code flag
Definition core_cm4.h:336
APSR_Type::@071212370340345021171336265214357066234256200137::_reserved1
uint32_t _reserved1
bit: 20..26 Reserved
Definition core_cm4.h:270
CONTROL_Type::@376065120377227036210154270074010325013015000222::nPRIV
uint32_t nPRIV
bit: 0 Execution privilege in Thread mode
Definition core_cm4.h:380
xPSR_Type::@234250120244346044234251003105331241335324323200::_reserved1
uint32_t _reserved1
bit: 20..23 Reserved
Definition core_cm4.h:329
xPSR_Type::@234250120244346044234251003105331241335324323200::C
uint32_t C
bit: 29 Carry condition code flag
Definition core_cm4.h:334
CONTROL_Type::@376065120377227036210154270074010325013015000222::SPSEL
uint32_t SPSEL
bit: 1 Stack to be used
Definition core_cm4.h:381
ITM_Type::@003257127012074045320030126073143333266333337354::u16
__OM uint16_t u16
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit.
Definition core_cm4.h:821
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Value identifying ITM_RxBuffer is ready for next character.
Definition core_armv81mml.h:4152
xPSR_Type::@234250120244346044234251003105331241335324323200::Q
uint32_t Q
bit: 27 Saturation condition flag
Definition core_cm4.h:332
APSR_Type::@071212370340345021171336265214357066234256200137::V
uint32_t V
bit: 28 Overflow condition code flag
Definition core_cm4.h:272
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition core_armv81mml.h:4184
APSR_Type::@071212370340345021171336265214357066234256200137::C
uint32_t C
bit: 29 Carry condition code flag
Definition core_cm4.h:273
ITM_SendChar
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
ITM Send Character.
Definition core_armv81mml.h:4163
xPSR_Type::@234250120244346044234251003105331241335324323200::ISR
uint32_t ISR
bit: 0.
Definition core_cm4.h:325
xPSR_Type::@234250120244346044234251003105331241335324323200::ICI_IT_2
uint32_t ICI_IT_2
bit: 25..26 ICI/IT part 2
Definition core_cm4.h:331
APSR_Type::@071212370340345021171336265214357066234256200137::N
uint32_t N
bit: 31 Negative condition code flag
Definition core_cm4.h:275
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition core_armv81mml.h:4204
xPSR_Type::@234250120244346044234251003105331241335324323200::_reserved0
uint32_t _reserved0
bit: 9 Reserved
Definition core_cm4.h:326
xPSR_Type::@234250120244346044234251003105331241335324323200::T
uint32_t T
bit: 24 Thumb bit
Definition core_cm4.h:330
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
CM7 uses 4 Bits for the Priority Levels.
Definition stm32h723xx.h:216
COMP2
#define COMP2
Definition stm32h723xx.h:2470
COMP1
#define COMP1
Definition stm32h723xx.h:2469
IRQn_Type
IRQn_Type
STM32H7XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32h723xx.h:49
SysTick_IRQn
@ SysTick_IRQn
15 Cortex-M System Tick Interrupt
Definition stm32h723xx.h:59
b
*brief create JSON pointer *sa reference_tokens const string_t const string_t & b
Definition json.hpp:13878
mpu_armv7.h
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition core_armv81mml.h:2624
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition core_armv81mml.h:1180
FPU_Type
Structure type to access the Floating Point Unit (FPU).
Definition core_armv81mml.h:2483
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition core_armv81mml.h:1079
MPU_Type
Structure type to access the Memory Protection Unit (MPU).
Definition core_armv81mml.h:2281
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition core_armv81mml.h:476
SCB_Type
Structure type to access the System Control Block (SCB).
Definition core_armv81mml.h:512
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition core_armv81mml.h:1002
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition core_armv81mml.h:1027
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition core_armv81mml.h:1366
ch
static std::string ch(int ain, const std::string &kind, const std::string &extra="", const std::string &board="lj")
Definition test_t7.cpp:98
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition core_armv81mml.h:329
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition core_armv81mml.h:437
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition core_armv81mml.h:368
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition core_armv81mml.h:386