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Memory System Control Registers (IMPLEMENTATION DEFINED)
Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » Implementation Control Block register (ICB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT)

Type definitions for the Memory System Control Registers (MEMSYSCTL). More...

Collaboration diagram for Memory System Control Registers (IMPLEMENTATION DEFINED):

Topics

 Power Mode Control Registers
 Type definitions for the Power Mode Control Registers (PWRMODCTL).

Classes

struct  MemSysCtl_Type
 Structure type to access the Memory System Control Registers (MEMSYSCTL). More...
#define MEMSYSCTL_MSCR_CPWRDN_Pos   17U
 MEMSYSCTL MSCR: CPWRDN Position.
#define MEMSYSCTL_MSCR_CPWRDN_Msk   (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos)
 MEMSYSCTL MSCR: CPWRDN Mask.
#define MEMSYSCTL_MSCR_DCCLEAN_Pos   16U
 MEMSYSCTL MSCR: DCCLEAN Position.
#define MEMSYSCTL_MSCR_DCCLEAN_Msk   (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos)
 MEMSYSCTL MSCR: DCCLEAN Mask.
#define MEMSYSCTL_MSCR_ICACTIVE_Pos   13U
 MEMSYSCTL MSCR: ICACTIVE Position.
#define MEMSYSCTL_MSCR_ICACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos)
 MEMSYSCTL MSCR: ICACTIVE Mask.
#define MEMSYSCTL_MSCR_DCACTIVE_Pos   12U
 MEMSYSCTL MSCR: DCACTIVE Position.
#define MEMSYSCTL_MSCR_DCACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos)
 MEMSYSCTL MSCR: DCACTIVE Mask.
#define MEMSYSCTL_MSCR_EVECCFAULT_Pos   3U
 MEMSYSCTL MSCR: EVECCFAULT Position.
#define MEMSYSCTL_MSCR_EVECCFAULT_Msk   (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos)
 MEMSYSCTL MSCR: EVECCFAULT Mask.
#define MEMSYSCTL_MSCR_FORCEWT_Pos   2U
 MEMSYSCTL MSCR: FORCEWT Position.
#define MEMSYSCTL_MSCR_FORCEWT_Msk   (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos)
 MEMSYSCTL MSCR: FORCEWT Mask.
#define MEMSYSCTL_MSCR_ECCEN_Pos   1U
 MEMSYSCTL MSCR: ECCEN Position.
#define MEMSYSCTL_MSCR_ECCEN_Msk   (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos)
 MEMSYSCTL MSCR: ECCEN Mask.
#define MEMSYSCTL_PFCR_ENABLE_Pos   0U
 MEMSYSCTL PFCR: ENABLE Position.
#define MEMSYSCTL_PFCR_ENABLE_Msk   (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/)
 MEMSYSCTL PFCR: ENABLE Mask.
#define MEMSYSCTL_ITCMCR_SZ_Pos   3U
 MEMSYSCTL ITCMCR: SZ Position.
#define MEMSYSCTL_ITCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos)
 MEMSYSCTL ITCMCR: SZ Mask.
#define MEMSYSCTL_ITCMCR_EN_Pos   0U
 MEMSYSCTL ITCMCR: EN Position.
#define MEMSYSCTL_ITCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/)
 MEMSYSCTL ITCMCR: EN Mask.
#define MEMSYSCTL_DTCMCR_SZ_Pos   3U
 MEMSYSCTL DTCMCR: SZ Position.
#define MEMSYSCTL_DTCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos)
 MEMSYSCTL DTCMCR: SZ Mask.
#define MEMSYSCTL_DTCMCR_EN_Pos   0U
 MEMSYSCTL DTCMCR: EN Position.
#define MEMSYSCTL_DTCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/)
 MEMSYSCTL DTCMCR: EN Mask.
#define MEMSYSCTL_PAHBCR_SZ_Pos   1U
 MEMSYSCTL PAHBCR: SZ Position.
#define MEMSYSCTL_PAHBCR_SZ_Msk   (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos)
 MEMSYSCTL PAHBCR: SZ Mask.
#define MEMSYSCTL_PAHBCR_EN_Pos   0U
 MEMSYSCTL PAHBCR: EN Position.
#define MEMSYSCTL_PAHBCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/)
 MEMSYSCTL PAHBCR: EN Mask.
#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos   1U
 MEMSYSCTL ITGU_CTRL: DEREN Position.
#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos)
 MEMSYSCTL ITGU_CTRL: DEREN Mask.
#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos   0U
 MEMSYSCTL ITGU_CTRL: DBFEN Position.
#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/)
 MEMSYSCTL ITGU_CTRL: DBFEN Mask.
#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos   31U
 MEMSYSCTL ITGU_CFG: PRESENT Position.
#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos)
 MEMSYSCTL ITGU_CFG: PRESENT Mask.
#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos   8U
 MEMSYSCTL ITGU_CFG: NUMBLKS Position.
#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos)
 MEMSYSCTL ITGU_CFG: NUMBLKS Mask.
#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos   0U
 MEMSYSCTL ITGU_CFG: BLKSZ Position.
#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/)
 MEMSYSCTL ITGU_CFG: BLKSZ Mask.
#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos   1U
 MEMSYSCTL DTGU_CTRL: DEREN Position.
#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos)
 MEMSYSCTL DTGU_CTRL: DEREN Mask.
#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos   0U
 MEMSYSCTL DTGU_CTRL: DBFEN Position.
#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/)
 MEMSYSCTL DTGU_CTRL: DBFEN Mask.
#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos   31U
 MEMSYSCTL DTGU_CFG: PRESENT Position.
#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos)
 MEMSYSCTL DTGU_CFG: PRESENT Mask.
#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos   8U
 MEMSYSCTL DTGU_CFG: NUMBLKS Position.
#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos)
 MEMSYSCTL DTGU_CFG: NUMBLKS Mask.
#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos   0U
 MEMSYSCTL DTGU_CFG: BLKSZ Position.
#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/)
 MEMSYSCTL DTGU_CFG: BLKSZ Mask.
#define MEMSYSCTL_MSCR_CPWRDN_Pos   17U
 MEMSYSCTL MSCR: CPWRDN Position.
#define MEMSYSCTL_MSCR_CPWRDN_Msk   (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos)
 MEMSYSCTL MSCR: CPWRDN Mask.
#define MEMSYSCTL_MSCR_DCCLEAN_Pos   16U
 MEMSYSCTL MSCR: DCCLEAN Position.
#define MEMSYSCTL_MSCR_DCCLEAN_Msk   (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos)
 MEMSYSCTL MSCR: DCCLEAN Mask.
#define MEMSYSCTL_MSCR_ICACTIVE_Pos   13U
 MEMSYSCTL MSCR: ICACTIVE Position.
#define MEMSYSCTL_MSCR_ICACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos)
 MEMSYSCTL MSCR: ICACTIVE Mask.
#define MEMSYSCTL_MSCR_DCACTIVE_Pos   12U
 MEMSYSCTL MSCR: DCACTIVE Position.
#define MEMSYSCTL_MSCR_DCACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos)
 MEMSYSCTL MSCR: DCACTIVE Mask.
#define MEMSYSCTL_MSCR_EVECCFAULT_Pos   3U
 MEMSYSCTL MSCR: EVECCFAULT Position.
#define MEMSYSCTL_MSCR_EVECCFAULT_Msk   (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos)
 MEMSYSCTL MSCR: EVECCFAULT Mask.
#define MEMSYSCTL_MSCR_FORCEWT_Pos   2U
 MEMSYSCTL MSCR: FORCEWT Position.
#define MEMSYSCTL_MSCR_FORCEWT_Msk   (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos)
 MEMSYSCTL MSCR: FORCEWT Mask.
#define MEMSYSCTL_MSCR_ECCEN_Pos   1U
 MEMSYSCTL MSCR: ECCEN Position.
#define MEMSYSCTL_MSCR_ECCEN_Msk   (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos)
 MEMSYSCTL MSCR: ECCEN Mask.
#define MEMSYSCTL_PFCR_DIS_NLP_Pos   7U
 MEMSYSCTL PFCR: DIS_NLP Position.
#define MEMSYSCTL_PFCR_DIS_NLP_Msk   (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos)
 MEMSYSCTL PFCR: DIS_NLP Mask.
#define MEMSYSCTL_PFCR_ENABLE_Pos   0U
 MEMSYSCTL PFCR: ENABLE Position.
#define MEMSYSCTL_PFCR_ENABLE_Msk   (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/)
 MEMSYSCTL PFCR: ENABLE Mask.
#define MEMSYSCTL_ITCMCR_SZ_Pos   3U
 MEMSYSCTL ITCMCR: SZ Position.
#define MEMSYSCTL_ITCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos)
 MEMSYSCTL ITCMCR: SZ Mask.
#define MEMSYSCTL_ITCMCR_EN_Pos   0U
 MEMSYSCTL ITCMCR: EN Position.
#define MEMSYSCTL_ITCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/)
 MEMSYSCTL ITCMCR: EN Mask.
#define MEMSYSCTL_DTCMCR_SZ_Pos   3U
 MEMSYSCTL DTCMCR: SZ Position.
#define MEMSYSCTL_DTCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos)
 MEMSYSCTL DTCMCR: SZ Mask.
#define MEMSYSCTL_DTCMCR_EN_Pos   0U
 MEMSYSCTL DTCMCR: EN Position.
#define MEMSYSCTL_DTCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/)
 MEMSYSCTL DTCMCR: EN Mask.
#define MEMSYSCTL_PAHBCR_SZ_Pos   1U
 MEMSYSCTL PAHBCR: SZ Position.
#define MEMSYSCTL_PAHBCR_SZ_Msk   (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos)
 MEMSYSCTL PAHBCR: SZ Mask.
#define MEMSYSCTL_PAHBCR_EN_Pos   0U
 MEMSYSCTL PAHBCR: EN Position.
#define MEMSYSCTL_PAHBCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/)
 MEMSYSCTL PAHBCR: EN Mask.
#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos   1U
 MEMSYSCTL ITGU_CTRL: DEREN Position.
#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos)
 MEMSYSCTL ITGU_CTRL: DEREN Mask.
#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos   0U
 MEMSYSCTL ITGU_CTRL: DBFEN Position.
#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/)
 MEMSYSCTL ITGU_CTRL: DBFEN Mask.
#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos   31U
 MEMSYSCTL ITGU_CFG: PRESENT Position.
#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos)
 MEMSYSCTL ITGU_CFG: PRESENT Mask.
#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos   8U
 MEMSYSCTL ITGU_CFG: NUMBLKS Position.
#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos)
 MEMSYSCTL ITGU_CFG: NUMBLKS Mask.
#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos   0U
 MEMSYSCTL ITGU_CFG: BLKSZ Position.
#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/)
 MEMSYSCTL ITGU_CFG: BLKSZ Mask.
#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos   1U
 MEMSYSCTL DTGU_CTRL: DEREN Position.
#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos)
 MEMSYSCTL DTGU_CTRL: DEREN Mask.
#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos   0U
 MEMSYSCTL DTGU_CTRL: DBFEN Position.
#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/)
 MEMSYSCTL DTGU_CTRL: DBFEN Mask.
#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos   31U
 MEMSYSCTL DTGU_CFG: PRESENT Position.
#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos)
 MEMSYSCTL DTGU_CFG: PRESENT Mask.
#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos   8U
 MEMSYSCTL DTGU_CFG: NUMBLKS Position.
#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos)
 MEMSYSCTL DTGU_CFG: NUMBLKS Mask.
#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos   0U
 MEMSYSCTL DTGU_CFG: BLKSZ Position.
#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/)
 MEMSYSCTL DTGU_CFG: BLKSZ Mask.
#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos   4U
 MEMSYSCTL MSCR: TECCCHKDIS Position.
#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk   (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos)
 MEMSYSCTL MSCR: TECCCHKDIS Mask.
#define MEMSYSCTL_PFCR_MAX_OS_Pos   7U
 MEMSYSCTL PFCR: MAX_OS Position.
#define MEMSYSCTL_PFCR_MAX_OS_Msk   (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos)
 MEMSYSCTL PFCR: MAX_OS Mask.
#define MEMSYSCTL_PFCR_MAX_LA_Pos   4U
 MEMSYSCTL PFCR: MAX_LA Position.
#define MEMSYSCTL_PFCR_MAX_LA_Msk   (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos)
 MEMSYSCTL PFCR: MAX_LA Mask.
#define MEMSYSCTL_PFCR_MIN_LA_Pos   1U
 MEMSYSCTL PFCR: MIN_LA Position.
#define MEMSYSCTL_PFCR_MIN_LA_Msk   (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos)
 MEMSYSCTL PFCR: MIN_LA Mask.

Detailed Description

Type definitions for the Memory System Control Registers (MEMSYSCTL).

Macro Definition Documentation

◆ MEMSYSCTL_DTCMCR_EN_Msk [1/2]

#define MEMSYSCTL_DTCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/)

MEMSYSCTL DTCMCR: EN Mask.

Definition at line 1480 of file core_cm55.h.

◆ MEMSYSCTL_DTCMCR_EN_Msk [2/2]

#define MEMSYSCTL_DTCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/)

MEMSYSCTL DTCMCR: EN Mask.

Definition at line 1467 of file core_cm85.h.

◆ MEMSYSCTL_DTCMCR_EN_Pos [1/2]

#define MEMSYSCTL_DTCMCR_EN_Pos   0U

MEMSYSCTL DTCMCR: EN Position.

Definition at line 1479 of file core_cm55.h.

◆ MEMSYSCTL_DTCMCR_EN_Pos [2/2]

#define MEMSYSCTL_DTCMCR_EN_Pos   0U

MEMSYSCTL DTCMCR: EN Position.

Definition at line 1466 of file core_cm85.h.

◆ MEMSYSCTL_DTCMCR_SZ_Msk [1/2]

#define MEMSYSCTL_DTCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos)

MEMSYSCTL DTCMCR: SZ Mask.

Definition at line 1477 of file core_cm55.h.

◆ MEMSYSCTL_DTCMCR_SZ_Msk [2/2]

#define MEMSYSCTL_DTCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos)

MEMSYSCTL DTCMCR: SZ Mask.

Definition at line 1464 of file core_cm85.h.

◆ MEMSYSCTL_DTCMCR_SZ_Pos [1/2]

#define MEMSYSCTL_DTCMCR_SZ_Pos   3U

MEMSYSCTL DTCMCR: SZ Position.

Definition at line 1476 of file core_cm55.h.

◆ MEMSYSCTL_DTCMCR_SZ_Pos [2/2]

#define MEMSYSCTL_DTCMCR_SZ_Pos   3U

MEMSYSCTL DTCMCR: SZ Position.

Definition at line 1463 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CFG_BLKSZ_Msk [1/2]

#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/)

MEMSYSCTL DTGU_CFG: BLKSZ Mask.

Definition at line 1521 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CFG_BLKSZ_Msk [2/2]

#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/)

MEMSYSCTL DTGU_CFG: BLKSZ Mask.

Definition at line 1508 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CFG_BLKSZ_Pos [1/2]

#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos   0U

MEMSYSCTL DTGU_CFG: BLKSZ Position.

Definition at line 1520 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CFG_BLKSZ_Pos [2/2]

#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos   0U

MEMSYSCTL DTGU_CFG: BLKSZ Position.

Definition at line 1507 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk [1/2]

#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos)

MEMSYSCTL DTGU_CFG: NUMBLKS Mask.

Definition at line 1518 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk [2/2]

#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos)

MEMSYSCTL DTGU_CFG: NUMBLKS Mask.

Definition at line 1505 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos [1/2]

#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos   8U

MEMSYSCTL DTGU_CFG: NUMBLKS Position.

Definition at line 1517 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos [2/2]

#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos   8U

MEMSYSCTL DTGU_CFG: NUMBLKS Position.

Definition at line 1504 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CFG_PRESENT_Msk [1/2]

#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos)

MEMSYSCTL DTGU_CFG: PRESENT Mask.

Definition at line 1515 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CFG_PRESENT_Msk [2/2]

#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos)

MEMSYSCTL DTGU_CFG: PRESENT Mask.

Definition at line 1502 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CFG_PRESENT_Pos [1/2]

#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos   31U

MEMSYSCTL DTGU_CFG: PRESENT Position.

Definition at line 1514 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CFG_PRESENT_Pos [2/2]

#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos   31U

MEMSYSCTL DTGU_CFG: PRESENT Position.

Definition at line 1501 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CTRL_DBFEN_Msk [1/2]

#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/)

MEMSYSCTL DTGU_CTRL: DBFEN Mask.

Definition at line 1511 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CTRL_DBFEN_Msk [2/2]

#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/)

MEMSYSCTL DTGU_CTRL: DBFEN Mask.

Definition at line 1498 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CTRL_DBFEN_Pos [1/2]

#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos   0U

MEMSYSCTL DTGU_CTRL: DBFEN Position.

Definition at line 1510 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CTRL_DBFEN_Pos [2/2]

#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos   0U

MEMSYSCTL DTGU_CTRL: DBFEN Position.

Definition at line 1497 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CTRL_DEREN_Msk [1/2]

#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos)

MEMSYSCTL DTGU_CTRL: DEREN Mask.

Definition at line 1508 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CTRL_DEREN_Msk [2/2]

#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos)

MEMSYSCTL DTGU_CTRL: DEREN Mask.

Definition at line 1495 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CTRL_DEREN_Pos [1/2]

#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos   1U

MEMSYSCTL DTGU_CTRL: DEREN Position.

Definition at line 1507 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CTRL_DEREN_Pos [2/2]

#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos   1U

MEMSYSCTL DTGU_CTRL: DEREN Position.

Definition at line 1494 of file core_cm85.h.

◆ MEMSYSCTL_ITCMCR_EN_Msk [1/2]

#define MEMSYSCTL_ITCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/)

MEMSYSCTL ITCMCR: EN Mask.

Definition at line 1473 of file core_cm55.h.

◆ MEMSYSCTL_ITCMCR_EN_Msk [2/2]

#define MEMSYSCTL_ITCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/)

MEMSYSCTL ITCMCR: EN Mask.

Definition at line 1460 of file core_cm85.h.

◆ MEMSYSCTL_ITCMCR_EN_Pos [1/2]

#define MEMSYSCTL_ITCMCR_EN_Pos   0U

MEMSYSCTL ITCMCR: EN Position.

Definition at line 1472 of file core_cm55.h.

◆ MEMSYSCTL_ITCMCR_EN_Pos [2/2]

#define MEMSYSCTL_ITCMCR_EN_Pos   0U

MEMSYSCTL ITCMCR: EN Position.

Definition at line 1459 of file core_cm85.h.

◆ MEMSYSCTL_ITCMCR_SZ_Msk [1/2]

#define MEMSYSCTL_ITCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos)

MEMSYSCTL ITCMCR: SZ Mask.

Definition at line 1470 of file core_cm55.h.

◆ MEMSYSCTL_ITCMCR_SZ_Msk [2/2]

#define MEMSYSCTL_ITCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos)

MEMSYSCTL ITCMCR: SZ Mask.

Definition at line 1457 of file core_cm85.h.

◆ MEMSYSCTL_ITCMCR_SZ_Pos [1/2]

#define MEMSYSCTL_ITCMCR_SZ_Pos   3U

MEMSYSCTL ITCMCR: SZ Position.

Definition at line 1469 of file core_cm55.h.

◆ MEMSYSCTL_ITCMCR_SZ_Pos [2/2]

#define MEMSYSCTL_ITCMCR_SZ_Pos   3U

MEMSYSCTL ITCMCR: SZ Position.

Definition at line 1456 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CFG_BLKSZ_Msk [1/2]

#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/)

MEMSYSCTL ITGU_CFG: BLKSZ Mask.

Definition at line 1504 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CFG_BLKSZ_Msk [2/2]

#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/)

MEMSYSCTL ITGU_CFG: BLKSZ Mask.

Definition at line 1491 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CFG_BLKSZ_Pos [1/2]

#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos   0U

MEMSYSCTL ITGU_CFG: BLKSZ Position.

Definition at line 1503 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CFG_BLKSZ_Pos [2/2]

#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos   0U

MEMSYSCTL ITGU_CFG: BLKSZ Position.

Definition at line 1490 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk [1/2]

#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos)

MEMSYSCTL ITGU_CFG: NUMBLKS Mask.

Definition at line 1501 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk [2/2]

#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos)

MEMSYSCTL ITGU_CFG: NUMBLKS Mask.

Definition at line 1488 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos [1/2]

#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos   8U

MEMSYSCTL ITGU_CFG: NUMBLKS Position.

Definition at line 1500 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos [2/2]

#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos   8U

MEMSYSCTL ITGU_CFG: NUMBLKS Position.

Definition at line 1487 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CFG_PRESENT_Msk [1/2]

#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos)

MEMSYSCTL ITGU_CFG: PRESENT Mask.

Definition at line 1498 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CFG_PRESENT_Msk [2/2]

#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos)

MEMSYSCTL ITGU_CFG: PRESENT Mask.

Definition at line 1485 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CFG_PRESENT_Pos [1/2]

#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos   31U

MEMSYSCTL ITGU_CFG: PRESENT Position.

Definition at line 1497 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CFG_PRESENT_Pos [2/2]

#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos   31U

MEMSYSCTL ITGU_CFG: PRESENT Position.

Definition at line 1484 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CTRL_DBFEN_Msk [1/2]

#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/)

MEMSYSCTL ITGU_CTRL: DBFEN Mask.

Definition at line 1494 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CTRL_DBFEN_Msk [2/2]

#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/)

MEMSYSCTL ITGU_CTRL: DBFEN Mask.

Definition at line 1481 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CTRL_DBFEN_Pos [1/2]

#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos   0U

MEMSYSCTL ITGU_CTRL: DBFEN Position.

Definition at line 1493 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CTRL_DBFEN_Pos [2/2]

#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos   0U

MEMSYSCTL ITGU_CTRL: DBFEN Position.

Definition at line 1480 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CTRL_DEREN_Msk [1/2]

#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos)

MEMSYSCTL ITGU_CTRL: DEREN Mask.

Definition at line 1491 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CTRL_DEREN_Msk [2/2]

#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos)

MEMSYSCTL ITGU_CTRL: DEREN Mask.

Definition at line 1478 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CTRL_DEREN_Pos [1/2]

#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos   1U

MEMSYSCTL ITGU_CTRL: DEREN Position.

Definition at line 1490 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CTRL_DEREN_Pos [2/2]

#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos   1U

MEMSYSCTL ITGU_CTRL: DEREN Position.

Definition at line 1477 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_CPWRDN_Msk [1/2]

#define MEMSYSCTL_MSCR_CPWRDN_Msk   (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos)

MEMSYSCTL MSCR: CPWRDN Mask.

Definition at line 1432 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_CPWRDN_Msk [2/2]

#define MEMSYSCTL_MSCR_CPWRDN_Msk   (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos)

MEMSYSCTL MSCR: CPWRDN Mask.

Definition at line 1428 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_CPWRDN_Pos [1/2]

#define MEMSYSCTL_MSCR_CPWRDN_Pos   17U

MEMSYSCTL MSCR: CPWRDN Position.

Definition at line 1431 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_CPWRDN_Pos [2/2]

#define MEMSYSCTL_MSCR_CPWRDN_Pos   17U

MEMSYSCTL MSCR: CPWRDN Position.

Definition at line 1427 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_DCACTIVE_Msk [1/2]

#define MEMSYSCTL_MSCR_DCACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos)

MEMSYSCTL MSCR: DCACTIVE Mask.

Definition at line 1441 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_DCACTIVE_Msk [2/2]

#define MEMSYSCTL_MSCR_DCACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos)

MEMSYSCTL MSCR: DCACTIVE Mask.

Definition at line 1437 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_DCACTIVE_Pos [1/2]

#define MEMSYSCTL_MSCR_DCACTIVE_Pos   12U

MEMSYSCTL MSCR: DCACTIVE Position.

Definition at line 1440 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_DCACTIVE_Pos [2/2]

#define MEMSYSCTL_MSCR_DCACTIVE_Pos   12U

MEMSYSCTL MSCR: DCACTIVE Position.

Definition at line 1436 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_DCCLEAN_Msk [1/2]

#define MEMSYSCTL_MSCR_DCCLEAN_Msk   (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos)

MEMSYSCTL MSCR: DCCLEAN Mask.

Definition at line 1435 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_DCCLEAN_Msk [2/2]

#define MEMSYSCTL_MSCR_DCCLEAN_Msk   (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos)

MEMSYSCTL MSCR: DCCLEAN Mask.

Definition at line 1431 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_DCCLEAN_Pos [1/2]

#define MEMSYSCTL_MSCR_DCCLEAN_Pos   16U

MEMSYSCTL MSCR: DCCLEAN Position.

Definition at line 1434 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_DCCLEAN_Pos [2/2]

#define MEMSYSCTL_MSCR_DCCLEAN_Pos   16U

MEMSYSCTL MSCR: DCCLEAN Position.

Definition at line 1430 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_ECCEN_Msk [1/2]

#define MEMSYSCTL_MSCR_ECCEN_Msk   (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos)

MEMSYSCTL MSCR: ECCEN Mask.

Definition at line 1453 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_ECCEN_Msk [2/2]

#define MEMSYSCTL_MSCR_ECCEN_Msk   (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos)

MEMSYSCTL MSCR: ECCEN Mask.

Definition at line 1446 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_ECCEN_Pos [1/2]

#define MEMSYSCTL_MSCR_ECCEN_Pos   1U

MEMSYSCTL MSCR: ECCEN Position.

Definition at line 1452 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_ECCEN_Pos [2/2]

#define MEMSYSCTL_MSCR_ECCEN_Pos   1U

MEMSYSCTL MSCR: ECCEN Position.

Definition at line 1445 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_EVECCFAULT_Msk [1/2]

#define MEMSYSCTL_MSCR_EVECCFAULT_Msk   (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos)

MEMSYSCTL MSCR: EVECCFAULT Mask.

Definition at line 1447 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_EVECCFAULT_Msk [2/2]

#define MEMSYSCTL_MSCR_EVECCFAULT_Msk   (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos)

MEMSYSCTL MSCR: EVECCFAULT Mask.

Definition at line 1440 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_EVECCFAULT_Pos [1/2]

#define MEMSYSCTL_MSCR_EVECCFAULT_Pos   3U

MEMSYSCTL MSCR: EVECCFAULT Position.

Definition at line 1446 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_EVECCFAULT_Pos [2/2]

#define MEMSYSCTL_MSCR_EVECCFAULT_Pos   3U

MEMSYSCTL MSCR: EVECCFAULT Position.

Definition at line 1439 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_FORCEWT_Msk [1/2]

#define MEMSYSCTL_MSCR_FORCEWT_Msk   (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos)

MEMSYSCTL MSCR: FORCEWT Mask.

Definition at line 1450 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_FORCEWT_Msk [2/2]

#define MEMSYSCTL_MSCR_FORCEWT_Msk   (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos)

MEMSYSCTL MSCR: FORCEWT Mask.

Definition at line 1443 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_FORCEWT_Pos [1/2]

#define MEMSYSCTL_MSCR_FORCEWT_Pos   2U

MEMSYSCTL MSCR: FORCEWT Position.

Definition at line 1449 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_FORCEWT_Pos [2/2]

#define MEMSYSCTL_MSCR_FORCEWT_Pos   2U

MEMSYSCTL MSCR: FORCEWT Position.

Definition at line 1442 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_ICACTIVE_Msk [1/2]

#define MEMSYSCTL_MSCR_ICACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos)

MEMSYSCTL MSCR: ICACTIVE Mask.

Definition at line 1438 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_ICACTIVE_Msk [2/2]

#define MEMSYSCTL_MSCR_ICACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos)

MEMSYSCTL MSCR: ICACTIVE Mask.

Definition at line 1434 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_ICACTIVE_Pos [1/2]

#define MEMSYSCTL_MSCR_ICACTIVE_Pos   13U

MEMSYSCTL MSCR: ICACTIVE Position.

Definition at line 1437 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_ICACTIVE_Pos [2/2]

#define MEMSYSCTL_MSCR_ICACTIVE_Pos   13U

MEMSYSCTL MSCR: ICACTIVE Position.

Definition at line 1433 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_TECCCHKDIS_Msk

#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk   (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos)

MEMSYSCTL MSCR: TECCCHKDIS Mask.

Definition at line 1444 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_TECCCHKDIS_Pos

#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos   4U

MEMSYSCTL MSCR: TECCCHKDIS Position.

Definition at line 1443 of file core_cm55.h.

◆ MEMSYSCTL_PAHBCR_EN_Msk [1/2]

#define MEMSYSCTL_PAHBCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/)

MEMSYSCTL PAHBCR: EN Mask.

Definition at line 1487 of file core_cm55.h.

◆ MEMSYSCTL_PAHBCR_EN_Msk [2/2]

#define MEMSYSCTL_PAHBCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/)

MEMSYSCTL PAHBCR: EN Mask.

Definition at line 1474 of file core_cm85.h.

◆ MEMSYSCTL_PAHBCR_EN_Pos [1/2]

#define MEMSYSCTL_PAHBCR_EN_Pos   0U

MEMSYSCTL PAHBCR: EN Position.

Definition at line 1486 of file core_cm55.h.

◆ MEMSYSCTL_PAHBCR_EN_Pos [2/2]

#define MEMSYSCTL_PAHBCR_EN_Pos   0U

MEMSYSCTL PAHBCR: EN Position.

Definition at line 1473 of file core_cm85.h.

◆ MEMSYSCTL_PAHBCR_SZ_Msk [1/2]

#define MEMSYSCTL_PAHBCR_SZ_Msk   (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos)

MEMSYSCTL PAHBCR: SZ Mask.

Definition at line 1484 of file core_cm55.h.

◆ MEMSYSCTL_PAHBCR_SZ_Msk [2/2]

#define MEMSYSCTL_PAHBCR_SZ_Msk   (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos)

MEMSYSCTL PAHBCR: SZ Mask.

Definition at line 1471 of file core_cm85.h.

◆ MEMSYSCTL_PAHBCR_SZ_Pos [1/2]

#define MEMSYSCTL_PAHBCR_SZ_Pos   1U

MEMSYSCTL PAHBCR: SZ Position.

Definition at line 1483 of file core_cm55.h.

◆ MEMSYSCTL_PAHBCR_SZ_Pos [2/2]

#define MEMSYSCTL_PAHBCR_SZ_Pos   1U

MEMSYSCTL PAHBCR: SZ Position.

Definition at line 1470 of file core_cm85.h.

◆ MEMSYSCTL_PFCR_DIS_NLP_Msk

#define MEMSYSCTL_PFCR_DIS_NLP_Msk   (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos)

MEMSYSCTL PFCR: DIS_NLP Mask.

Definition at line 1450 of file core_cm85.h.

◆ MEMSYSCTL_PFCR_DIS_NLP_Pos

#define MEMSYSCTL_PFCR_DIS_NLP_Pos   7U

MEMSYSCTL PFCR: DIS_NLP Position.

Definition at line 1449 of file core_cm85.h.

◆ MEMSYSCTL_PFCR_ENABLE_Msk [1/2]

#define MEMSYSCTL_PFCR_ENABLE_Msk   (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/)

MEMSYSCTL PFCR: ENABLE Mask.

Definition at line 1466 of file core_cm55.h.

◆ MEMSYSCTL_PFCR_ENABLE_Msk [2/2]

#define MEMSYSCTL_PFCR_ENABLE_Msk   (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/)

MEMSYSCTL PFCR: ENABLE Mask.

Definition at line 1453 of file core_cm85.h.

◆ MEMSYSCTL_PFCR_ENABLE_Pos [1/2]

#define MEMSYSCTL_PFCR_ENABLE_Pos   0U

MEMSYSCTL PFCR: ENABLE Position.

Definition at line 1465 of file core_cm55.h.

◆ MEMSYSCTL_PFCR_ENABLE_Pos [2/2]

#define MEMSYSCTL_PFCR_ENABLE_Pos   0U

MEMSYSCTL PFCR: ENABLE Position.

Definition at line 1452 of file core_cm85.h.

◆ MEMSYSCTL_PFCR_MAX_LA_Msk

#define MEMSYSCTL_PFCR_MAX_LA_Msk   (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos)

MEMSYSCTL PFCR: MAX_LA Mask.

Definition at line 1460 of file core_cm55.h.

◆ MEMSYSCTL_PFCR_MAX_LA_Pos

#define MEMSYSCTL_PFCR_MAX_LA_Pos   4U

MEMSYSCTL PFCR: MAX_LA Position.

Definition at line 1459 of file core_cm55.h.

◆ MEMSYSCTL_PFCR_MAX_OS_Msk

#define MEMSYSCTL_PFCR_MAX_OS_Msk   (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos)

MEMSYSCTL PFCR: MAX_OS Mask.

Definition at line 1457 of file core_cm55.h.

◆ MEMSYSCTL_PFCR_MAX_OS_Pos

#define MEMSYSCTL_PFCR_MAX_OS_Pos   7U

MEMSYSCTL PFCR: MAX_OS Position.

Definition at line 1456 of file core_cm55.h.

◆ MEMSYSCTL_PFCR_MIN_LA_Msk

#define MEMSYSCTL_PFCR_MIN_LA_Msk   (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos)

MEMSYSCTL PFCR: MIN_LA Mask.

Definition at line 1463 of file core_cm55.h.

◆ MEMSYSCTL_PFCR_MIN_LA_Pos

#define MEMSYSCTL_PFCR_MIN_LA_Pos   1U

MEMSYSCTL PFCR: MIN_LA Position.

Definition at line 1462 of file core_cm55.h.