Instrumentation Trace Macrocell (ITM)

Type definitions for the Instrumentation Trace Macrocell (ITM). More...

Collaboration diagram for Instrumentation Trace Macrocell (ITM):

Topics
	Data Watchpoint and Trace (DWT)
	Type definitions for the Data Watchpoint and Trace (DWT).

Classes
struct	ITM_Type
	Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...
#define	ITM_STIM_DISABLED_Pos   1U
	ITM STIM: DISABLED Position.
#define	ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)
	ITM STIM: DISABLED Mask.
#define	ITM_STIM_FIFOREADY_Pos   0U
	ITM STIM: FIFOREADY Position.
#define	ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
	ITM STIM: FIFOREADY Mask.
#define	ITM_TPR_PRIVMASK_Pos   0U
	ITM TPR: PRIVMASK Position.
#define	ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
	ITM TPR: PRIVMASK Mask.
#define	ITM_TCR_BUSY_Pos   23U
	ITM TCR: BUSY Position.
#define	ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
	ITM TCR: BUSY Mask.
#define	ITM_TCR_TRACEBUSID_Pos   16U
	ITM TCR: ATBID Position.
#define	ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
	ITM TCR: ATBID Mask.
#define	ITM_TCR_GTSFREQ_Pos   10U
	ITM TCR: Global timestamp frequency Position.
#define	ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
	ITM TCR: Global timestamp frequency Mask.
#define	ITM_TCR_TSPRESCALE_Pos   8U
	ITM TCR: TSPRESCALE Position.
#define	ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
	ITM TCR: TSPRESCALE Mask.
#define	ITM_TCR_STALLENA_Pos   5U
	ITM TCR: STALLENA Position.
#define	ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)
	ITM TCR: STALLENA Mask.
#define	ITM_TCR_SWOENA_Pos   4U
	ITM TCR: SWOENA Position.
#define	ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
	ITM TCR: SWOENA Mask.
#define	ITM_TCR_DWTENA_Pos   3U
	ITM TCR: DWTENA Position.
#define	ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
	ITM TCR: DWTENA Mask.
#define	ITM_TCR_SYNCENA_Pos   2U
	ITM TCR: SYNCENA Position.
#define	ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
	ITM TCR: SYNCENA Mask.
#define	ITM_TCR_TSENA_Pos   1U
	ITM TCR: TSENA Position.
#define	ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
	ITM TCR: TSENA Mask.
#define	ITM_TCR_ITMENA_Pos   0U
	ITM TCR: ITM Enable bit Position.
#define	ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
	ITM TCR: ITM Enable bit Mask.
#define	ITM_LSR_ByteAcc_Pos   2U
	ITM LSR: ByteAcc Position.
#define	ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
	ITM LSR: ByteAcc Mask.
#define	ITM_LSR_Access_Pos   1U
	ITM LSR: Access Position.
#define	ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
	ITM LSR: Access Mask.
#define	ITM_LSR_Present_Pos   0U
	ITM LSR: Present Position.
#define	ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
	ITM LSR: Present Mask.
#define	ITM_STIM_DISABLED_Pos   1U
	ITM STIM: DISABLED Position.
#define	ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)
	ITM STIM: DISABLED Mask.
#define	ITM_STIM_FIFOREADY_Pos   0U
	ITM STIM: FIFOREADY Position.
#define	ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
	ITM STIM: FIFOREADY Mask.
#define	ITM_TPR_PRIVMASK_Pos   0U
	ITM TPR: PRIVMASK Position.
#define	ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
	ITM TPR: PRIVMASK Mask.
#define	ITM_TCR_BUSY_Pos   23U
	ITM TCR: BUSY Position.
#define	ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
	ITM TCR: BUSY Mask.
#define	ITM_TCR_TRACEBUSID_Pos   16U
	ITM TCR: ATBID Position.
#define	ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
	ITM TCR: ATBID Mask.
#define	ITM_TCR_GTSFREQ_Pos   10U
	ITM TCR: Global timestamp frequency Position.
#define	ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
	ITM TCR: Global timestamp frequency Mask.
#define	ITM_TCR_TSPRESCALE_Pos   8U
	ITM TCR: TSPRESCALE Position.
#define	ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
	ITM TCR: TSPRESCALE Mask.
#define	ITM_TCR_STALLENA_Pos   5U
	ITM TCR: STALLENA Position.
#define	ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)
	ITM TCR: STALLENA Mask.
#define	ITM_TCR_SWOENA_Pos   4U
	ITM TCR: SWOENA Position.
#define	ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
	ITM TCR: SWOENA Mask.
#define	ITM_TCR_DWTENA_Pos   3U
	ITM TCR: DWTENA Position.
#define	ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
	ITM TCR: DWTENA Mask.
#define	ITM_TCR_SYNCENA_Pos   2U
	ITM TCR: SYNCENA Position.
#define	ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
	ITM TCR: SYNCENA Mask.
#define	ITM_TCR_TSENA_Pos   1U
	ITM TCR: TSENA Position.
#define	ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
	ITM TCR: TSENA Mask.
#define	ITM_TCR_ITMENA_Pos   0U
	ITM TCR: ITM Enable bit Position.
#define	ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
	ITM TCR: ITM Enable bit Mask.
#define	ITM_LSR_ByteAcc_Pos   2U
	ITM LSR: ByteAcc Position.
#define	ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
	ITM LSR: ByteAcc Mask.
#define	ITM_LSR_Access_Pos   1U
	ITM LSR: Access Position.
#define	ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
	ITM LSR: Access Mask.
#define	ITM_LSR_Present_Pos   0U
	ITM LSR: Present Position.
#define	ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
	ITM LSR: Present Mask.
#define	ITM_TPR_PRIVMASK_Pos   0U
	ITM TPR: PRIVMASK Position.
#define	ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
	ITM TPR: PRIVMASK Mask.
#define	ITM_TCR_BUSY_Pos   23U
	ITM TCR: BUSY Position.
#define	ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
	ITM TCR: BUSY Mask.
#define	ITM_TCR_GTSFREQ_Pos   10U
	ITM TCR: Global timestamp frequency Position.
#define	ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
	ITM TCR: Global timestamp frequency Mask.
#define	ITM_TCR_SWOENA_Pos   4U
	ITM TCR: SWOENA Position.
#define	ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
	ITM TCR: SWOENA Mask.
#define	ITM_TCR_DWTENA_Pos   3U
	ITM TCR: DWTENA Position.
#define	ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
	ITM TCR: DWTENA Mask.
#define	ITM_TCR_SYNCENA_Pos   2U
	ITM TCR: SYNCENA Position.
#define	ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
	ITM TCR: SYNCENA Mask.
#define	ITM_TCR_TSENA_Pos   1U
	ITM TCR: TSENA Position.
#define	ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
	ITM TCR: TSENA Mask.
#define	ITM_TCR_ITMENA_Pos   0U
	ITM TCR: ITM Enable bit Position.
#define	ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
	ITM TCR: ITM Enable bit Mask.
#define	ITM_LSR_ByteAcc_Pos   2U
	ITM LSR: ByteAcc Position.
#define	ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
	ITM LSR: ByteAcc Mask.
#define	ITM_LSR_Access_Pos   1U
	ITM LSR: Access Position.
#define	ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
	ITM LSR: Access Mask.
#define	ITM_LSR_Present_Pos   0U
	ITM LSR: Present Position.
#define	ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
	ITM LSR: Present Mask.
#define	ITM_STIM_DISABLED_Pos   1U
	ITM STIM: DISABLED Position.
#define	ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)
	ITM STIM: DISABLED Mask.
#define	ITM_STIM_FIFOREADY_Pos   0U
	ITM STIM: FIFOREADY Position.
#define	ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
	ITM STIM: FIFOREADY Mask.
#define	ITM_TPR_PRIVMASK_Pos   0U
	ITM TPR: PRIVMASK Position.
#define	ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
	ITM TPR: PRIVMASK Mask.
#define	ITM_TCR_BUSY_Pos   23U
	ITM TCR: BUSY Position.
#define	ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
	ITM TCR: BUSY Mask.
#define	ITM_TCR_TRACEBUSID_Pos   16U
	ITM TCR: ATBID Position.
#define	ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
	ITM TCR: ATBID Mask.
#define	ITM_TCR_GTSFREQ_Pos   10U
	ITM TCR: Global timestamp frequency Position.
#define	ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
	ITM TCR: Global timestamp frequency Mask.
#define	ITM_TCR_TSPRESCALE_Pos   8U
	ITM TCR: TSPRESCALE Position.
#define	ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
	ITM TCR: TSPRESCALE Mask.
#define	ITM_TCR_STALLENA_Pos   5U
	ITM TCR: STALLENA Position.
#define	ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)
	ITM TCR: STALLENA Mask.
#define	ITM_TCR_SWOENA_Pos   4U
	ITM TCR: SWOENA Position.
#define	ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
	ITM TCR: SWOENA Mask.
#define	ITM_TCR_DWTENA_Pos   3U
	ITM TCR: DWTENA Position.
#define	ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
	ITM TCR: DWTENA Mask.
#define	ITM_TCR_SYNCENA_Pos   2U
	ITM TCR: SYNCENA Position.
#define	ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
	ITM TCR: SYNCENA Mask.
#define	ITM_TCR_TSENA_Pos   1U
	ITM TCR: TSENA Position.
#define	ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
	ITM TCR: TSENA Mask.
#define	ITM_TCR_ITMENA_Pos   0U
	ITM TCR: ITM Enable bit Position.
#define	ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
	ITM TCR: ITM Enable bit Mask.
#define	ITM_LSR_ByteAcc_Pos   2U
	ITM LSR: ByteAcc Position.
#define	ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
	ITM LSR: ByteAcc Mask.
#define	ITM_LSR_Access_Pos   1U
	ITM LSR: Access Position.
#define	ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
	ITM LSR: Access Mask.
#define	ITM_LSR_Present_Pos   0U
	ITM LSR: Present Position.
#define	ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
	ITM LSR: Present Mask.
#define	ITM_STIM_DISABLED_Pos   1U
	ITM STIM: DISABLED Position.
#define	ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)
	ITM STIM: DISABLED Mask.
#define	ITM_STIM_FIFOREADY_Pos   0U
	ITM STIM: FIFOREADY Position.
#define	ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
	ITM STIM: FIFOREADY Mask.
#define	ITM_TPR_PRIVMASK_Pos   0U
	ITM TPR: PRIVMASK Position.
#define	ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
	ITM TPR: PRIVMASK Mask.
#define	ITM_TCR_BUSY_Pos   23U
	ITM TCR: BUSY Position.
#define	ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
	ITM TCR: BUSY Mask.
#define	ITM_TCR_TRACEBUSID_Pos   16U
	ITM TCR: ATBID Position.
#define	ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
	ITM TCR: ATBID Mask.
#define	ITM_TCR_GTSFREQ_Pos   10U
	ITM TCR: Global timestamp frequency Position.
#define	ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
	ITM TCR: Global timestamp frequency Mask.
#define	ITM_TCR_TSPRESCALE_Pos   8U
	ITM TCR: TSPRESCALE Position.
#define	ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
	ITM TCR: TSPRESCALE Mask.
#define	ITM_TCR_STALLENA_Pos   5U
	ITM TCR: STALLENA Position.
#define	ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)
	ITM TCR: STALLENA Mask.
#define	ITM_TCR_SWOENA_Pos   4U
	ITM TCR: SWOENA Position.
#define	ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
	ITM TCR: SWOENA Mask.
#define	ITM_TCR_DWTENA_Pos   3U
	ITM TCR: DWTENA Position.
#define	ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
	ITM TCR: DWTENA Mask.
#define	ITM_TCR_SYNCENA_Pos   2U
	ITM TCR: SYNCENA Position.
#define	ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
	ITM TCR: SYNCENA Mask.
#define	ITM_TCR_TSENA_Pos   1U
	ITM TCR: TSENA Position.
#define	ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
	ITM TCR: TSENA Mask.
#define	ITM_TCR_ITMENA_Pos   0U
	ITM TCR: ITM Enable bit Position.
#define	ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
	ITM TCR: ITM Enable bit Mask.
#define	ITM_LSR_ByteAcc_Pos   2U
	ITM LSR: ByteAcc Position.
#define	ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
	ITM LSR: ByteAcc Mask.
#define	ITM_LSR_Access_Pos   1U
	ITM LSR: Access Position.
#define	ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
	ITM LSR: Access Mask.
#define	ITM_LSR_Present_Pos   0U
	ITM LSR: Present Position.
#define	ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
	ITM LSR: Present Mask.
#define	ITM_TPR_PRIVMASK_Pos   0U
	ITM TPR: PRIVMASK Position.
#define	ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
	ITM TPR: PRIVMASK Mask.
#define	ITM_TCR_BUSY_Pos   23U
	ITM TCR: BUSY Position.
#define	ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
	ITM TCR: BUSY Mask.
#define	ITM_TCR_GTSFREQ_Pos   10U
	ITM TCR: Global timestamp frequency Position.
#define	ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
	ITM TCR: Global timestamp frequency Mask.
#define	ITM_TCR_SWOENA_Pos   4U
	ITM TCR: SWOENA Position.
#define	ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
	ITM TCR: SWOENA Mask.
#define	ITM_TCR_DWTENA_Pos   3U
	ITM TCR: DWTENA Position.
#define	ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
	ITM TCR: DWTENA Mask.
#define	ITM_TCR_SYNCENA_Pos   2U
	ITM TCR: SYNCENA Position.
#define	ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
	ITM TCR: SYNCENA Mask.
#define	ITM_TCR_TSENA_Pos   1U
	ITM TCR: TSENA Position.
#define	ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
	ITM TCR: TSENA Mask.
#define	ITM_TCR_ITMENA_Pos   0U
	ITM TCR: ITM Enable bit Position.
#define	ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
	ITM TCR: ITM Enable bit Mask.
#define	ITM_LSR_ByteAcc_Pos   2U
	ITM LSR: ByteAcc Position.
#define	ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
	ITM LSR: ByteAcc Mask.
#define	ITM_LSR_Access_Pos   1U
	ITM LSR: Access Position.
#define	ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
	ITM LSR: Access Mask.
#define	ITM_LSR_Present_Pos   0U
	ITM LSR: Present Position.
#define	ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
	ITM LSR: Present Mask.
#define	ITM_STIM_DISABLED_Pos   1U
	ITM STIM: DISABLED Position.
#define	ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)
	ITM STIM: DISABLED Mask.
#define	ITM_STIM_FIFOREADY_Pos   0U
	ITM STIM: FIFOREADY Position.
#define	ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
	ITM STIM: FIFOREADY Mask.
#define	ITM_TPR_PRIVMASK_Pos   0U
	ITM TPR: PRIVMASK Position.
#define	ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
	ITM TPR: PRIVMASK Mask.
#define	ITM_TCR_BUSY_Pos   23U
	ITM TCR: BUSY Position.
#define	ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
	ITM TCR: BUSY Mask.
#define	ITM_TCR_TRACEBUSID_Pos   16U
	ITM TCR: ATBID Position.
#define	ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
	ITM TCR: ATBID Mask.
#define	ITM_TCR_GTSFREQ_Pos   10U
	ITM TCR: Global timestamp frequency Position.
#define	ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
	ITM TCR: Global timestamp frequency Mask.
#define	ITM_TCR_TSPRESCALE_Pos   8U
	ITM TCR: TSPRESCALE Position.
#define	ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
	ITM TCR: TSPRESCALE Mask.
#define	ITM_TCR_STALLENA_Pos   5U
	ITM TCR: STALLENA Position.
#define	ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)
	ITM TCR: STALLENA Mask.
#define	ITM_TCR_SWOENA_Pos   4U
	ITM TCR: SWOENA Position.
#define	ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
	ITM TCR: SWOENA Mask.
#define	ITM_TCR_DWTENA_Pos   3U
	ITM TCR: DWTENA Position.
#define	ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
	ITM TCR: DWTENA Mask.
#define	ITM_TCR_SYNCENA_Pos   2U
	ITM TCR: SYNCENA Position.
#define	ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
	ITM TCR: SYNCENA Mask.
#define	ITM_TCR_TSENA_Pos   1U
	ITM TCR: TSENA Position.
#define	ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
	ITM TCR: TSENA Mask.
#define	ITM_TCR_ITMENA_Pos   0U
	ITM TCR: ITM Enable bit Position.
#define	ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
	ITM TCR: ITM Enable bit Mask.
#define	ITM_LSR_ByteAcc_Pos   2U
	ITM LSR: ByteAcc Position.
#define	ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
	ITM LSR: ByteAcc Mask.
#define	ITM_LSR_Access_Pos   1U
	ITM LSR: Access Position.
#define	ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
	ITM LSR: Access Mask.
#define	ITM_LSR_Present_Pos   0U
	ITM LSR: Present Position.
#define	ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
	ITM LSR: Present Mask.
#define	ITM_TPR_PRIVMASK_Pos   0U
	ITM TPR: PRIVMASK Position.
#define	ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
	ITM TPR: PRIVMASK Mask.
#define	ITM_TCR_BUSY_Pos   23U
	ITM TCR: BUSY Position.
#define	ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
	ITM TCR: BUSY Mask.
#define	ITM_TCR_GTSFREQ_Pos   10U
	ITM TCR: Global timestamp frequency Position.
#define	ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
	ITM TCR: Global timestamp frequency Mask.
#define	ITM_TCR_SWOENA_Pos   4U
	ITM TCR: SWOENA Position.
#define	ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
	ITM TCR: SWOENA Mask.
#define	ITM_TCR_DWTENA_Pos   3U
	ITM TCR: DWTENA Position.
#define	ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
	ITM TCR: DWTENA Mask.
#define	ITM_TCR_SYNCENA_Pos   2U
	ITM TCR: SYNCENA Position.
#define	ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
	ITM TCR: SYNCENA Mask.
#define	ITM_TCR_TSENA_Pos   1U
	ITM TCR: TSENA Position.
#define	ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
	ITM TCR: TSENA Mask.
#define	ITM_TCR_ITMENA_Pos   0U
	ITM TCR: ITM Enable bit Position.
#define	ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
	ITM TCR: ITM Enable bit Mask.
#define	ITM_LSR_ByteAcc_Pos   2U
	ITM LSR: ByteAcc Position.
#define	ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
	ITM LSR: ByteAcc Mask.
#define	ITM_LSR_Access_Pos   1U
	ITM LSR: Access Position.
#define	ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
	ITM LSR: Access Mask.
#define	ITM_LSR_Present_Pos   0U
	ITM LSR: Present Position.
#define	ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
	ITM LSR: Present Mask.
#define	ITM_STIM_DISABLED_Pos   1U
	ITM STIM: DISABLED Position.
#define	ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)
	ITM STIM: DISABLED Mask.
#define	ITM_STIM_FIFOREADY_Pos   0U
	ITM STIM: FIFOREADY Position.
#define	ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
	ITM STIM: FIFOREADY Mask.
#define	ITM_TPR_PRIVMASK_Pos   0U
	ITM TPR: PRIVMASK Position.
#define	ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
	ITM TPR: PRIVMASK Mask.
#define	ITM_TCR_BUSY_Pos   23U
	ITM TCR: BUSY Position.
#define	ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
	ITM TCR: BUSY Mask.
#define	ITM_TCR_TRACEBUSID_Pos   16U
	ITM TCR: ATBID Position.
#define	ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
	ITM TCR: ATBID Mask.
#define	ITM_TCR_GTSFREQ_Pos   10U
	ITM TCR: Global timestamp frequency Position.
#define	ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
	ITM TCR: Global timestamp frequency Mask.
#define	ITM_TCR_TSPRESCALE_Pos   8U
	ITM TCR: TSPRESCALE Position.
#define	ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
	ITM TCR: TSPRESCALE Mask.
#define	ITM_TCR_STALLENA_Pos   5U
	ITM TCR: STALLENA Position.
#define	ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)
	ITM TCR: STALLENA Mask.
#define	ITM_TCR_SWOENA_Pos   4U
	ITM TCR: SWOENA Position.
#define	ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
	ITM TCR: SWOENA Mask.
#define	ITM_TCR_DWTENA_Pos   3U
	ITM TCR: DWTENA Position.
#define	ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
	ITM TCR: DWTENA Mask.
#define	ITM_TCR_SYNCENA_Pos   2U
	ITM TCR: SYNCENA Position.
#define	ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
	ITM TCR: SYNCENA Mask.
#define	ITM_TCR_TSENA_Pos   1U
	ITM TCR: TSENA Position.
#define	ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
	ITM TCR: TSENA Mask.
#define	ITM_TCR_ITMENA_Pos   0U
	ITM TCR: ITM Enable bit Position.
#define	ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
	ITM TCR: ITM Enable bit Mask.
#define	ITM_LSR_ByteAcc_Pos   2U
	ITM LSR: ByteAcc Position.
#define	ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
	ITM LSR: ByteAcc Mask.
#define	ITM_LSR_Access_Pos   1U
	ITM LSR: Access Position.
#define	ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
	ITM LSR: Access Mask.
#define	ITM_LSR_Present_Pos   0U
	ITM LSR: Present Position.
#define	ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
	ITM LSR: Present Mask.
#define	ITM_TPR_PRIVMASK_Pos   0U
	ITM TPR: PRIVMASK Position.
#define	ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
	ITM TPR: PRIVMASK Mask.
#define	ITM_TCR_BUSY_Pos   23U
	ITM TCR: BUSY Position.
#define	ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
	ITM TCR: BUSY Mask.
#define	ITM_TCR_GTSFREQ_Pos   10U
	ITM TCR: Global timestamp frequency Position.
#define	ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
	ITM TCR: Global timestamp frequency Mask.
#define	ITM_TCR_SWOENA_Pos   4U
	ITM TCR: SWOENA Position.
#define	ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
	ITM TCR: SWOENA Mask.
#define	ITM_TCR_DWTENA_Pos   3U
	ITM TCR: DWTENA Position.
#define	ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
	ITM TCR: DWTENA Mask.
#define	ITM_TCR_SYNCENA_Pos   2U
	ITM TCR: SYNCENA Position.
#define	ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
	ITM TCR: SYNCENA Mask.
#define	ITM_TCR_TSENA_Pos   1U
	ITM TCR: TSENA Position.
#define	ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
	ITM TCR: TSENA Mask.
#define	ITM_TCR_ITMENA_Pos   0U
	ITM TCR: ITM Enable bit Position.
#define	ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
	ITM TCR: ITM Enable bit Mask.
#define	ITM_LSR_ByteAcc_Pos   2U
	ITM LSR: ByteAcc Position.
#define	ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
	ITM LSR: ByteAcc Mask.
#define	ITM_LSR_Access_Pos   1U
	ITM LSR: Access Position.
#define	ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
	ITM LSR: Access Mask.
#define	ITM_LSR_Present_Pos   0U
	ITM LSR: Present Position.
#define	ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
	ITM LSR: Present Mask.
#define	ITM_STIM_DISABLED_Pos   1U
	ITM STIM: DISABLED Position.
#define	ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)
	ITM STIM: DISABLED Mask.
#define	ITM_STIM_FIFOREADY_Pos   0U
	ITM STIM: FIFOREADY Position.
#define	ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
	ITM STIM: FIFOREADY Mask.
#define	ITM_TPR_PRIVMASK_Pos   0U
	ITM TPR: PRIVMASK Position.
#define	ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
	ITM TPR: PRIVMASK Mask.
#define	ITM_TCR_BUSY_Pos   23U
	ITM TCR: BUSY Position.
#define	ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
	ITM TCR: BUSY Mask.
#define	ITM_TCR_TRACEBUSID_Pos   16U
	ITM TCR: ATBID Position.
#define	ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
	ITM TCR: ATBID Mask.
#define	ITM_TCR_GTSFREQ_Pos   10U
	ITM TCR: Global timestamp frequency Position.
#define	ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
	ITM TCR: Global timestamp frequency Mask.
#define	ITM_TCR_TSPRESCALE_Pos   8U
	ITM TCR: TSPRESCALE Position.
#define	ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)
	ITM TCR: TSPRESCALE Mask.
#define	ITM_TCR_STALLENA_Pos   5U
	ITM TCR: STALLENA Position.
#define	ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)
	ITM TCR: STALLENA Mask.
#define	ITM_TCR_SWOENA_Pos   4U
	ITM TCR: SWOENA Position.
#define	ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
	ITM TCR: SWOENA Mask.
#define	ITM_TCR_DWTENA_Pos   3U
	ITM TCR: DWTENA Position.
#define	ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
	ITM TCR: DWTENA Mask.
#define	ITM_TCR_SYNCENA_Pos   2U
	ITM TCR: SYNCENA Position.
#define	ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
	ITM TCR: SYNCENA Mask.
#define	ITM_TCR_TSENA_Pos   1U
	ITM TCR: TSENA Position.
#define	ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
	ITM TCR: TSENA Mask.
#define	ITM_TCR_ITMENA_Pos   0U
	ITM TCR: ITM Enable bit Position.
#define	ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
	ITM TCR: ITM Enable bit Mask.
#define	ITM_LSR_ByteAcc_Pos   2U
	ITM LSR: ByteAcc Position.
#define	ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
	ITM LSR: ByteAcc Mask.
#define	ITM_LSR_Access_Pos   1U
	ITM LSR: Access Position.
#define	ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
	ITM LSR: Access Mask.
#define	ITM_LSR_Present_Pos   0U
	ITM LSR: Present Position.
#define	ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
	ITM LSR: Present Mask.
#define	ITM_TCR_TraceBusID_Pos   16U
	ITM TCR: ATBID Position.
#define	ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
	ITM TCR: ATBID Mask.
#define	ITM_TCR_TSPrescale_Pos   8U
	ITM TCR: TSPrescale Position.
#define	ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
	ITM TCR: TSPrescale Mask.
#define	ITM_TCR_TraceBusID_Pos   16U
	ITM TCR: ATBID Position.
#define	ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
	ITM TCR: ATBID Mask.
#define	ITM_TCR_TSPrescale_Pos   8U
	ITM TCR: TSPrescale Position.
#define	ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
	ITM TCR: TSPrescale Mask.
#define	ITM_TCR_TraceBusID_Pos   16U
	ITM TCR: ATBID Position.
#define	ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
	ITM TCR: ATBID Mask.
#define	ITM_TCR_TSPrescale_Pos   8U
	ITM TCR: TSPrescale Position.
#define	ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
	ITM TCR: TSPrescale Mask.
#define	ITM_TCR_TraceBusID_Pos   16U
	ITM TCR: ATBID Position.
#define	ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
	ITM TCR: ATBID Mask.
#define	ITM_TCR_TSPrescale_Pos   8U
	ITM TCR: TSPrescale Position.
#define	ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
	ITM TCR: TSPrescale Mask.

Detailed Description

Type definitions for the Instrumentation Trace Macrocell (ITM).

Macro Definition Documentation

ITM_LSR_Access_Msk [1/11]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask.

Definition at line 1161 of file core_armv81mml.h.

ITM_LSR_Access_Msk [2/11]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask.

Definition at line 1099 of file core_armv8mml.h.

ITM_LSR_Access_Msk [3/11]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask.

Definition at line 828 of file core_cm3.h.

ITM_LSR_Access_Msk [4/11]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask.

Definition at line 1099 of file core_cm33.h.

ITM_LSR_Access_Msk [5/11]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask.

Definition at line 1099 of file core_cm35p.h.

ITM_LSR_Access_Msk [6/11]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask.

Definition at line 886 of file core_cm4.h.

ITM_LSR_Access_Msk [7/11]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask.

Definition at line 1206 of file core_cm55.h.

ITM_LSR_Access_Msk [8/11]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask.

Definition at line 1110 of file core_cm7.h.

ITM_LSR_Access_Msk [9/11]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask.

Definition at line 1202 of file core_cm85.h.

ITM_LSR_Access_Msk [10/11]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask.

Definition at line 813 of file core_sc300.h.

ITM_LSR_Access_Msk [11/11]

#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask.

Definition at line 1157 of file core_starmc1.h.

ITM_LSR_Access_Pos [1/11]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position.

Definition at line 1160 of file core_armv81mml.h.

ITM_LSR_Access_Pos [2/11]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position.

Definition at line 1098 of file core_armv8mml.h.

ITM_LSR_Access_Pos [3/11]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position.

Definition at line 827 of file core_cm3.h.

ITM_LSR_Access_Pos [4/11]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position.

Definition at line 1098 of file core_cm33.h.

ITM_LSR_Access_Pos [5/11]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position.

Definition at line 1098 of file core_cm35p.h.

ITM_LSR_Access_Pos [6/11]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position.

Definition at line 885 of file core_cm4.h.

ITM_LSR_Access_Pos [7/11]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position.

Definition at line 1205 of file core_cm55.h.

ITM_LSR_Access_Pos [8/11]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position.

Definition at line 1109 of file core_cm7.h.

ITM_LSR_Access_Pos [9/11]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position.

Definition at line 1201 of file core_cm85.h.

ITM_LSR_Access_Pos [10/11]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position.

Definition at line 812 of file core_sc300.h.

ITM_LSR_Access_Pos [11/11]

#define ITM_LSR_Access_Pos   1U

ITM LSR: Access Position.

Definition at line 1156 of file core_starmc1.h.

ITM_LSR_ByteAcc_Msk [1/11]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask.

Definition at line 1158 of file core_armv81mml.h.

ITM_LSR_ByteAcc_Msk [2/11]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask.

Definition at line 1096 of file core_armv8mml.h.

ITM_LSR_ByteAcc_Msk [3/11]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask.

Definition at line 825 of file core_cm3.h.

ITM_LSR_ByteAcc_Msk [4/11]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask.

Definition at line 1096 of file core_cm33.h.

ITM_LSR_ByteAcc_Msk [5/11]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask.

Definition at line 1096 of file core_cm35p.h.

ITM_LSR_ByteAcc_Msk [6/11]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask.

Definition at line 883 of file core_cm4.h.

ITM_LSR_ByteAcc_Msk [7/11]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask.

Definition at line 1203 of file core_cm55.h.

ITM_LSR_ByteAcc_Msk [8/11]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask.

Definition at line 1107 of file core_cm7.h.

ITM_LSR_ByteAcc_Msk [9/11]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask.

Definition at line 1199 of file core_cm85.h.

ITM_LSR_ByteAcc_Msk [10/11]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask.

Definition at line 810 of file core_sc300.h.

ITM_LSR_ByteAcc_Msk [11/11]

#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask.

Definition at line 1154 of file core_starmc1.h.

ITM_LSR_ByteAcc_Pos [1/11]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position.

Definition at line 1157 of file core_armv81mml.h.

ITM_LSR_ByteAcc_Pos [2/11]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position.

Definition at line 1095 of file core_armv8mml.h.

ITM_LSR_ByteAcc_Pos [3/11]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position.

Definition at line 824 of file core_cm3.h.

ITM_LSR_ByteAcc_Pos [4/11]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position.

Definition at line 1095 of file core_cm33.h.

ITM_LSR_ByteAcc_Pos [5/11]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position.

Definition at line 1095 of file core_cm35p.h.

ITM_LSR_ByteAcc_Pos [6/11]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position.

Definition at line 882 of file core_cm4.h.

ITM_LSR_ByteAcc_Pos [7/11]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position.

Definition at line 1202 of file core_cm55.h.

ITM_LSR_ByteAcc_Pos [8/11]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position.

Definition at line 1106 of file core_cm7.h.

ITM_LSR_ByteAcc_Pos [9/11]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position.

Definition at line 1198 of file core_cm85.h.

ITM_LSR_ByteAcc_Pos [10/11]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position.

Definition at line 809 of file core_sc300.h.

ITM_LSR_ByteAcc_Pos [11/11]

#define ITM_LSR_ByteAcc_Pos   2U

ITM LSR: ByteAcc Position.

Definition at line 1153 of file core_starmc1.h.

ITM_LSR_Present_Msk [1/11]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask.

Definition at line 1164 of file core_armv81mml.h.

ITM_LSR_Present_Msk [2/11]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask.

Definition at line 1102 of file core_armv8mml.h.

ITM_LSR_Present_Msk [3/11]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask.

Definition at line 831 of file core_cm3.h.

ITM_LSR_Present_Msk [4/11]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask.

Definition at line 1102 of file core_cm33.h.

ITM_LSR_Present_Msk [5/11]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask.

Definition at line 1102 of file core_cm35p.h.

ITM_LSR_Present_Msk [6/11]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask.

Definition at line 889 of file core_cm4.h.

ITM_LSR_Present_Msk [7/11]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask.

Definition at line 1209 of file core_cm55.h.

ITM_LSR_Present_Msk [8/11]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask.

Definition at line 1113 of file core_cm7.h.

ITM_LSR_Present_Msk [9/11]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask.

Definition at line 1205 of file core_cm85.h.

ITM_LSR_Present_Msk [10/11]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask.

Definition at line 816 of file core_sc300.h.

ITM_LSR_Present_Msk [11/11]

#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask.

Definition at line 1160 of file core_starmc1.h.

ITM_LSR_Present_Pos [1/11]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position.

Definition at line 1163 of file core_armv81mml.h.

ITM_LSR_Present_Pos [2/11]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position.

Definition at line 1101 of file core_armv8mml.h.

ITM_LSR_Present_Pos [3/11]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position.

Definition at line 830 of file core_cm3.h.

ITM_LSR_Present_Pos [4/11]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position.

Definition at line 1101 of file core_cm33.h.

ITM_LSR_Present_Pos [5/11]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position.

Definition at line 1101 of file core_cm35p.h.

ITM_LSR_Present_Pos [6/11]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position.

Definition at line 888 of file core_cm4.h.

ITM_LSR_Present_Pos [7/11]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position.

Definition at line 1208 of file core_cm55.h.

ITM_LSR_Present_Pos [8/11]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position.

Definition at line 1112 of file core_cm7.h.

ITM_LSR_Present_Pos [9/11]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position.

Definition at line 1204 of file core_cm85.h.

ITM_LSR_Present_Pos [10/11]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position.

Definition at line 815 of file core_sc300.h.

ITM_LSR_Present_Pos [11/11]

#define ITM_LSR_Present_Pos   0U

ITM LSR: Present Position.

Definition at line 1159 of file core_starmc1.h.

ITM_STIM_DISABLED_Msk [1/7]

#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask.

Definition at line 1116 of file core_armv81mml.h.

ITM_STIM_DISABLED_Msk [2/7]

#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask.

Definition at line 1054 of file core_armv8mml.h.

ITM_STIM_DISABLED_Msk [3/7]

#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask.

Definition at line 1054 of file core_cm33.h.

ITM_STIM_DISABLED_Msk [4/7]

#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask.

Definition at line 1054 of file core_cm35p.h.

ITM_STIM_DISABLED_Msk [5/7]

#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask.

Definition at line 1161 of file core_cm55.h.

ITM_STIM_DISABLED_Msk [6/7]

#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask.

Definition at line 1157 of file core_cm85.h.

ITM_STIM_DISABLED_Msk [7/7]

#define ITM_STIM_DISABLED_Msk   (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask.

Definition at line 1112 of file core_starmc1.h.

ITM_STIM_DISABLED_Pos [1/7]

#define ITM_STIM_DISABLED_Pos   1U

ITM STIM: DISABLED Position.

Definition at line 1115 of file core_armv81mml.h.

ITM_STIM_DISABLED_Pos [2/7]

#define ITM_STIM_DISABLED_Pos   1U

ITM STIM: DISABLED Position.

Definition at line 1053 of file core_armv8mml.h.

ITM_STIM_DISABLED_Pos [3/7]

#define ITM_STIM_DISABLED_Pos   1U

ITM STIM: DISABLED Position.

Definition at line 1053 of file core_cm33.h.

ITM_STIM_DISABLED_Pos [4/7]

#define ITM_STIM_DISABLED_Pos   1U

ITM STIM: DISABLED Position.

Definition at line 1053 of file core_cm35p.h.

ITM_STIM_DISABLED_Pos [5/7]

#define ITM_STIM_DISABLED_Pos   1U

ITM STIM: DISABLED Position.

Definition at line 1160 of file core_cm55.h.

ITM_STIM_DISABLED_Pos [6/7]

#define ITM_STIM_DISABLED_Pos   1U

ITM STIM: DISABLED Position.

Definition at line 1156 of file core_cm85.h.

ITM_STIM_DISABLED_Pos [7/7]

#define ITM_STIM_DISABLED_Pos   1U

ITM STIM: DISABLED Position.

Definition at line 1111 of file core_starmc1.h.

ITM_STIM_FIFOREADY_Msk [1/7]

#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask.

Definition at line 1119 of file core_armv81mml.h.

ITM_STIM_FIFOREADY_Msk [2/7]

#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask.

Definition at line 1057 of file core_armv8mml.h.

ITM_STIM_FIFOREADY_Msk [3/7]

#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask.

Definition at line 1057 of file core_cm33.h.

ITM_STIM_FIFOREADY_Msk [4/7]

#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask.

Definition at line 1057 of file core_cm35p.h.

ITM_STIM_FIFOREADY_Msk [5/7]

#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask.

Definition at line 1164 of file core_cm55.h.

ITM_STIM_FIFOREADY_Msk [6/7]

#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask.

Definition at line 1160 of file core_cm85.h.

ITM_STIM_FIFOREADY_Msk [7/7]

#define ITM_STIM_FIFOREADY_Msk   (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask.

Definition at line 1115 of file core_starmc1.h.

ITM_STIM_FIFOREADY_Pos [1/7]

#define ITM_STIM_FIFOREADY_Pos   0U

ITM STIM: FIFOREADY Position.

Definition at line 1118 of file core_armv81mml.h.

ITM_STIM_FIFOREADY_Pos [2/7]

#define ITM_STIM_FIFOREADY_Pos   0U

ITM STIM: FIFOREADY Position.

Definition at line 1056 of file core_armv8mml.h.

ITM_STIM_FIFOREADY_Pos [3/7]

#define ITM_STIM_FIFOREADY_Pos   0U

ITM STIM: FIFOREADY Position.

Definition at line 1056 of file core_cm33.h.

ITM_STIM_FIFOREADY_Pos [4/7]

#define ITM_STIM_FIFOREADY_Pos   0U

ITM STIM: FIFOREADY Position.

Definition at line 1056 of file core_cm35p.h.

ITM_STIM_FIFOREADY_Pos [5/7]

#define ITM_STIM_FIFOREADY_Pos   0U

ITM STIM: FIFOREADY Position.

Definition at line 1163 of file core_cm55.h.

ITM_STIM_FIFOREADY_Pos [6/7]

#define ITM_STIM_FIFOREADY_Pos   0U

ITM STIM: FIFOREADY Position.

Definition at line 1159 of file core_cm85.h.

ITM_STIM_FIFOREADY_Pos [7/7]

#define ITM_STIM_FIFOREADY_Pos   0U

ITM STIM: FIFOREADY Position.

Definition at line 1114 of file core_starmc1.h.

ITM_TCR_BUSY_Msk [1/11]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask.

Definition at line 1127 of file core_armv81mml.h.

ITM_TCR_BUSY_Msk [2/11]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask.

Definition at line 1065 of file core_armv8mml.h.

ITM_TCR_BUSY_Msk [3/11]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask.

Definition at line 797 of file core_cm3.h.

ITM_TCR_BUSY_Msk [4/11]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask.

Definition at line 1065 of file core_cm33.h.

ITM_TCR_BUSY_Msk [5/11]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask.

Definition at line 1065 of file core_cm35p.h.

ITM_TCR_BUSY_Msk [6/11]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask.

Definition at line 855 of file core_cm4.h.

ITM_TCR_BUSY_Msk [7/11]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask.

Definition at line 1172 of file core_cm55.h.

ITM_TCR_BUSY_Msk [8/11]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask.

Definition at line 1079 of file core_cm7.h.

ITM_TCR_BUSY_Msk [9/11]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask.

Definition at line 1168 of file core_cm85.h.

ITM_TCR_BUSY_Msk [10/11]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask.

Definition at line 782 of file core_sc300.h.

ITM_TCR_BUSY_Msk [11/11]

#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask.

Definition at line 1123 of file core_starmc1.h.

ITM_TCR_BUSY_Pos [1/11]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position.

Definition at line 1126 of file core_armv81mml.h.

ITM_TCR_BUSY_Pos [2/11]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position.

Definition at line 1064 of file core_armv8mml.h.

ITM_TCR_BUSY_Pos [3/11]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position.

Definition at line 796 of file core_cm3.h.

ITM_TCR_BUSY_Pos [4/11]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position.

Definition at line 1064 of file core_cm33.h.

ITM_TCR_BUSY_Pos [5/11]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position.

Definition at line 1064 of file core_cm35p.h.

ITM_TCR_BUSY_Pos [6/11]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position.

Definition at line 854 of file core_cm4.h.

ITM_TCR_BUSY_Pos [7/11]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position.

Definition at line 1171 of file core_cm55.h.

ITM_TCR_BUSY_Pos [8/11]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position.

Definition at line 1078 of file core_cm7.h.

ITM_TCR_BUSY_Pos [9/11]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position.

Definition at line 1167 of file core_cm85.h.

ITM_TCR_BUSY_Pos [10/11]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position.

Definition at line 781 of file core_sc300.h.

ITM_TCR_BUSY_Pos [11/11]

#define ITM_TCR_BUSY_Pos   23U

ITM TCR: BUSY Position.

Definition at line 1122 of file core_starmc1.h.

ITM_TCR_DWTENA_Msk [1/11]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask.

Definition at line 1145 of file core_armv81mml.h.

ITM_TCR_DWTENA_Msk [2/11]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask.

Definition at line 1083 of file core_armv8mml.h.

ITM_TCR_DWTENA_Msk [3/11]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask.

Definition at line 812 of file core_cm3.h.

ITM_TCR_DWTENA_Msk [4/11]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask.

Definition at line 1083 of file core_cm33.h.

ITM_TCR_DWTENA_Msk [5/11]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask.

Definition at line 1083 of file core_cm35p.h.

ITM_TCR_DWTENA_Msk [6/11]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask.

Definition at line 870 of file core_cm4.h.

ITM_TCR_DWTENA_Msk [7/11]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask.

Definition at line 1190 of file core_cm55.h.

ITM_TCR_DWTENA_Msk [8/11]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask.

Definition at line 1094 of file core_cm7.h.

ITM_TCR_DWTENA_Msk [9/11]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask.

Definition at line 1186 of file core_cm85.h.

ITM_TCR_DWTENA_Msk [10/11]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask.

Definition at line 797 of file core_sc300.h.

ITM_TCR_DWTENA_Msk [11/11]

#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask.

Definition at line 1141 of file core_starmc1.h.

ITM_TCR_DWTENA_Pos [1/11]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position.

Definition at line 1144 of file core_armv81mml.h.

ITM_TCR_DWTENA_Pos [2/11]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position.

Definition at line 1082 of file core_armv8mml.h.

ITM_TCR_DWTENA_Pos [3/11]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position.

Definition at line 811 of file core_cm3.h.

ITM_TCR_DWTENA_Pos [4/11]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position.

Definition at line 1082 of file core_cm33.h.

ITM_TCR_DWTENA_Pos [5/11]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position.

Definition at line 1082 of file core_cm35p.h.

ITM_TCR_DWTENA_Pos [6/11]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position.

Definition at line 869 of file core_cm4.h.

ITM_TCR_DWTENA_Pos [7/11]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position.

Definition at line 1189 of file core_cm55.h.

ITM_TCR_DWTENA_Pos [8/11]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position.

Definition at line 1093 of file core_cm7.h.

ITM_TCR_DWTENA_Pos [9/11]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position.

Definition at line 1185 of file core_cm85.h.

ITM_TCR_DWTENA_Pos [10/11]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position.

Definition at line 796 of file core_sc300.h.

ITM_TCR_DWTENA_Pos [11/11]

#define ITM_TCR_DWTENA_Pos   3U

ITM TCR: DWTENA Position.

Definition at line 1140 of file core_starmc1.h.

ITM_TCR_GTSFREQ_Msk [1/11]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask.

Definition at line 1133 of file core_armv81mml.h.

ITM_TCR_GTSFREQ_Msk [2/11]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask.

Definition at line 1071 of file core_armv8mml.h.

ITM_TCR_GTSFREQ_Msk [3/11]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask.

Definition at line 803 of file core_cm3.h.

ITM_TCR_GTSFREQ_Msk [4/11]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask.

Definition at line 1071 of file core_cm33.h.

ITM_TCR_GTSFREQ_Msk [5/11]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask.

Definition at line 1071 of file core_cm35p.h.

ITM_TCR_GTSFREQ_Msk [6/11]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask.

Definition at line 861 of file core_cm4.h.

ITM_TCR_GTSFREQ_Msk [7/11]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask.

Definition at line 1178 of file core_cm55.h.

ITM_TCR_GTSFREQ_Msk [8/11]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask.

Definition at line 1085 of file core_cm7.h.

ITM_TCR_GTSFREQ_Msk [9/11]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask.

Definition at line 1174 of file core_cm85.h.

ITM_TCR_GTSFREQ_Msk [10/11]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask.

Definition at line 788 of file core_sc300.h.

ITM_TCR_GTSFREQ_Msk [11/11]

#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask.

Definition at line 1129 of file core_starmc1.h.

ITM_TCR_GTSFREQ_Pos [1/11]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position.

Definition at line 1132 of file core_armv81mml.h.

ITM_TCR_GTSFREQ_Pos [2/11]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position.

Definition at line 1070 of file core_armv8mml.h.

ITM_TCR_GTSFREQ_Pos [3/11]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position.

Definition at line 802 of file core_cm3.h.

ITM_TCR_GTSFREQ_Pos [4/11]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position.

Definition at line 1070 of file core_cm33.h.

ITM_TCR_GTSFREQ_Pos [5/11]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position.

Definition at line 1070 of file core_cm35p.h.

ITM_TCR_GTSFREQ_Pos [6/11]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position.

Definition at line 860 of file core_cm4.h.

ITM_TCR_GTSFREQ_Pos [7/11]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position.

Definition at line 1177 of file core_cm55.h.

ITM_TCR_GTSFREQ_Pos [8/11]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position.

Definition at line 1084 of file core_cm7.h.

ITM_TCR_GTSFREQ_Pos [9/11]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position.

Definition at line 1173 of file core_cm85.h.

ITM_TCR_GTSFREQ_Pos [10/11]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position.

Definition at line 787 of file core_sc300.h.

ITM_TCR_GTSFREQ_Pos [11/11]

#define ITM_TCR_GTSFREQ_Pos   10U

ITM TCR: Global timestamp frequency Position.

Definition at line 1128 of file core_starmc1.h.

ITM_TCR_ITMENA_Msk [1/11]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask.

Definition at line 1154 of file core_armv81mml.h.

Referenced by ITM_SendChar().

ITM_TCR_ITMENA_Msk [2/11]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask.

Definition at line 1092 of file core_armv8mml.h.

ITM_TCR_ITMENA_Msk [3/11]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask.

Definition at line 821 of file core_cm3.h.

ITM_TCR_ITMENA_Msk [4/11]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask.

Definition at line 1092 of file core_cm33.h.

ITM_TCR_ITMENA_Msk [5/11]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask.

Definition at line 1092 of file core_cm35p.h.

ITM_TCR_ITMENA_Msk [6/11]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask.

Definition at line 879 of file core_cm4.h.

ITM_TCR_ITMENA_Msk [7/11]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask.

Definition at line 1199 of file core_cm55.h.

ITM_TCR_ITMENA_Msk [8/11]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask.

Definition at line 1103 of file core_cm7.h.

ITM_TCR_ITMENA_Msk [9/11]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask.

Definition at line 1195 of file core_cm85.h.

ITM_TCR_ITMENA_Msk [10/11]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask.

Definition at line 806 of file core_sc300.h.

ITM_TCR_ITMENA_Msk [11/11]

#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask.

Definition at line 1150 of file core_starmc1.h.

ITM_TCR_ITMENA_Pos [1/11]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position.

Definition at line 1153 of file core_armv81mml.h.

ITM_TCR_ITMENA_Pos [2/11]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position.

Definition at line 1091 of file core_armv8mml.h.

ITM_TCR_ITMENA_Pos [3/11]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position.

Definition at line 820 of file core_cm3.h.

ITM_TCR_ITMENA_Pos [4/11]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position.

Definition at line 1091 of file core_cm33.h.

ITM_TCR_ITMENA_Pos [5/11]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position.

Definition at line 1091 of file core_cm35p.h.

ITM_TCR_ITMENA_Pos [6/11]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position.

Definition at line 878 of file core_cm4.h.

ITM_TCR_ITMENA_Pos [7/11]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position.

Definition at line 1198 of file core_cm55.h.

ITM_TCR_ITMENA_Pos [8/11]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position.

Definition at line 1102 of file core_cm7.h.

ITM_TCR_ITMENA_Pos [9/11]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position.

Definition at line 1194 of file core_cm85.h.

ITM_TCR_ITMENA_Pos [10/11]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position.

Definition at line 805 of file core_sc300.h.

ITM_TCR_ITMENA_Pos [11/11]

#define ITM_TCR_ITMENA_Pos   0U

ITM TCR: ITM Enable bit Position.

Definition at line 1149 of file core_starmc1.h.

ITM_TCR_STALLENA_Msk [1/7]

#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask.

Definition at line 1139 of file core_armv81mml.h.

ITM_TCR_STALLENA_Msk [2/7]

#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask.

Definition at line 1077 of file core_armv8mml.h.

ITM_TCR_STALLENA_Msk [3/7]

#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask.

Definition at line 1077 of file core_cm33.h.

ITM_TCR_STALLENA_Msk [4/7]

#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask.

Definition at line 1077 of file core_cm35p.h.

ITM_TCR_STALLENA_Msk [5/7]

#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask.

Definition at line 1184 of file core_cm55.h.

ITM_TCR_STALLENA_Msk [6/7]

#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask.

Definition at line 1180 of file core_cm85.h.

ITM_TCR_STALLENA_Msk [7/7]

#define ITM_TCR_STALLENA_Msk   (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask.

Definition at line 1135 of file core_starmc1.h.

ITM_TCR_STALLENA_Pos [1/7]

#define ITM_TCR_STALLENA_Pos   5U

ITM TCR: STALLENA Position.

Definition at line 1138 of file core_armv81mml.h.

ITM_TCR_STALLENA_Pos [2/7]

#define ITM_TCR_STALLENA_Pos   5U

ITM TCR: STALLENA Position.

Definition at line 1076 of file core_armv8mml.h.

ITM_TCR_STALLENA_Pos [3/7]

#define ITM_TCR_STALLENA_Pos   5U

ITM TCR: STALLENA Position.

Definition at line 1076 of file core_cm33.h.

ITM_TCR_STALLENA_Pos [4/7]

#define ITM_TCR_STALLENA_Pos   5U

ITM TCR: STALLENA Position.

Definition at line 1076 of file core_cm35p.h.

ITM_TCR_STALLENA_Pos [5/7]

#define ITM_TCR_STALLENA_Pos   5U

ITM TCR: STALLENA Position.

Definition at line 1183 of file core_cm55.h.

ITM_TCR_STALLENA_Pos [6/7]

#define ITM_TCR_STALLENA_Pos   5U

ITM TCR: STALLENA Position.

Definition at line 1179 of file core_cm85.h.

ITM_TCR_STALLENA_Pos [7/7]

#define ITM_TCR_STALLENA_Pos   5U

ITM TCR: STALLENA Position.

Definition at line 1134 of file core_starmc1.h.

ITM_TCR_SWOENA_Msk [1/11]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask.

Definition at line 1142 of file core_armv81mml.h.

ITM_TCR_SWOENA_Msk [2/11]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask.

Definition at line 1080 of file core_armv8mml.h.

ITM_TCR_SWOENA_Msk [3/11]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask.

Definition at line 809 of file core_cm3.h.

ITM_TCR_SWOENA_Msk [4/11]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask.

Definition at line 1080 of file core_cm33.h.

ITM_TCR_SWOENA_Msk [5/11]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask.

Definition at line 1080 of file core_cm35p.h.

ITM_TCR_SWOENA_Msk [6/11]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask.

Definition at line 867 of file core_cm4.h.

ITM_TCR_SWOENA_Msk [7/11]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask.

Definition at line 1187 of file core_cm55.h.

ITM_TCR_SWOENA_Msk [8/11]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask.

Definition at line 1091 of file core_cm7.h.

ITM_TCR_SWOENA_Msk [9/11]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask.

Definition at line 1183 of file core_cm85.h.

ITM_TCR_SWOENA_Msk [10/11]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask.

Definition at line 794 of file core_sc300.h.

ITM_TCR_SWOENA_Msk [11/11]

#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask.

Definition at line 1138 of file core_starmc1.h.

ITM_TCR_SWOENA_Pos [1/11]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position.

Definition at line 1141 of file core_armv81mml.h.

ITM_TCR_SWOENA_Pos [2/11]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position.

Definition at line 1079 of file core_armv8mml.h.

ITM_TCR_SWOENA_Pos [3/11]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position.

Definition at line 808 of file core_cm3.h.

ITM_TCR_SWOENA_Pos [4/11]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position.

Definition at line 1079 of file core_cm33.h.

ITM_TCR_SWOENA_Pos [5/11]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position.

Definition at line 1079 of file core_cm35p.h.

ITM_TCR_SWOENA_Pos [6/11]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position.

Definition at line 866 of file core_cm4.h.

ITM_TCR_SWOENA_Pos [7/11]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position.

Definition at line 1186 of file core_cm55.h.

ITM_TCR_SWOENA_Pos [8/11]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position.

Definition at line 1090 of file core_cm7.h.

ITM_TCR_SWOENA_Pos [9/11]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position.

Definition at line 1182 of file core_cm85.h.

ITM_TCR_SWOENA_Pos [10/11]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position.

Definition at line 793 of file core_sc300.h.

ITM_TCR_SWOENA_Pos [11/11]

#define ITM_TCR_SWOENA_Pos   4U

ITM TCR: SWOENA Position.

Definition at line 1137 of file core_starmc1.h.

ITM_TCR_SYNCENA_Msk [1/11]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask.

Definition at line 1148 of file core_armv81mml.h.

ITM_TCR_SYNCENA_Msk [2/11]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask.

Definition at line 1086 of file core_armv8mml.h.

ITM_TCR_SYNCENA_Msk [3/11]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask.

Definition at line 815 of file core_cm3.h.

ITM_TCR_SYNCENA_Msk [4/11]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask.

Definition at line 1086 of file core_cm33.h.

ITM_TCR_SYNCENA_Msk [5/11]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask.

Definition at line 1086 of file core_cm35p.h.

ITM_TCR_SYNCENA_Msk [6/11]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask.

Definition at line 873 of file core_cm4.h.

ITM_TCR_SYNCENA_Msk [7/11]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask.

Definition at line 1193 of file core_cm55.h.

ITM_TCR_SYNCENA_Msk [8/11]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask.

Definition at line 1097 of file core_cm7.h.

ITM_TCR_SYNCENA_Msk [9/11]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask.

Definition at line 1189 of file core_cm85.h.

ITM_TCR_SYNCENA_Msk [10/11]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask.

Definition at line 800 of file core_sc300.h.

ITM_TCR_SYNCENA_Msk [11/11]

#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask.

Definition at line 1144 of file core_starmc1.h.

ITM_TCR_SYNCENA_Pos [1/11]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position.

Definition at line 1147 of file core_armv81mml.h.

ITM_TCR_SYNCENA_Pos [2/11]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position.

Definition at line 1085 of file core_armv8mml.h.

ITM_TCR_SYNCENA_Pos [3/11]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position.

Definition at line 814 of file core_cm3.h.

ITM_TCR_SYNCENA_Pos [4/11]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position.

Definition at line 1085 of file core_cm33.h.

ITM_TCR_SYNCENA_Pos [5/11]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position.

Definition at line 1085 of file core_cm35p.h.

ITM_TCR_SYNCENA_Pos [6/11]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position.

Definition at line 872 of file core_cm4.h.

ITM_TCR_SYNCENA_Pos [7/11]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position.

Definition at line 1192 of file core_cm55.h.

ITM_TCR_SYNCENA_Pos [8/11]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position.

Definition at line 1096 of file core_cm7.h.

ITM_TCR_SYNCENA_Pos [9/11]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position.

Definition at line 1188 of file core_cm85.h.

ITM_TCR_SYNCENA_Pos [10/11]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position.

Definition at line 799 of file core_sc300.h.

ITM_TCR_SYNCENA_Pos [11/11]

#define ITM_TCR_SYNCENA_Pos   2U

ITM TCR: SYNCENA Position.

Definition at line 1143 of file core_starmc1.h.

ITM_TCR_TRACEBUSID_Msk [1/7]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask.

Definition at line 1130 of file core_armv81mml.h.

ITM_TCR_TRACEBUSID_Msk [2/7]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask.

Definition at line 1068 of file core_armv8mml.h.

ITM_TCR_TRACEBUSID_Msk [3/7]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask.

Definition at line 1068 of file core_cm33.h.

ITM_TCR_TRACEBUSID_Msk [4/7]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask.

Definition at line 1068 of file core_cm35p.h.

ITM_TCR_TRACEBUSID_Msk [5/7]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask.

Definition at line 1175 of file core_cm55.h.

ITM_TCR_TRACEBUSID_Msk [6/7]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask.

Definition at line 1171 of file core_cm85.h.

ITM_TCR_TRACEBUSID_Msk [7/7]

#define ITM_TCR_TRACEBUSID_Msk   (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask.

Definition at line 1126 of file core_starmc1.h.

ITM_TCR_TraceBusID_Msk [1/4]

#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask.

Definition at line 800 of file core_cm3.h.

ITM_TCR_TraceBusID_Msk [2/4]

#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask.

Definition at line 858 of file core_cm4.h.

ITM_TCR_TraceBusID_Msk [3/4]

#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask.

Definition at line 1082 of file core_cm7.h.

ITM_TCR_TraceBusID_Msk [4/4]

#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask.

Definition at line 785 of file core_sc300.h.

ITM_TCR_TRACEBUSID_Pos [1/7]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position.

Definition at line 1129 of file core_armv81mml.h.

ITM_TCR_TRACEBUSID_Pos [2/7]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position.

Definition at line 1067 of file core_armv8mml.h.

ITM_TCR_TRACEBUSID_Pos [3/7]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position.

Definition at line 1067 of file core_cm33.h.

ITM_TCR_TRACEBUSID_Pos [4/7]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position.

Definition at line 1067 of file core_cm35p.h.

ITM_TCR_TRACEBUSID_Pos [5/7]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position.

Definition at line 1174 of file core_cm55.h.

ITM_TCR_TRACEBUSID_Pos [6/7]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position.

Definition at line 1170 of file core_cm85.h.

ITM_TCR_TRACEBUSID_Pos [7/7]

#define ITM_TCR_TRACEBUSID_Pos   16U

ITM TCR: ATBID Position.

Definition at line 1125 of file core_starmc1.h.

ITM_TCR_TraceBusID_Pos [1/4]

#define ITM_TCR_TraceBusID_Pos   16U

ITM TCR: ATBID Position.

Definition at line 799 of file core_cm3.h.

ITM_TCR_TraceBusID_Pos [2/4]

#define ITM_TCR_TraceBusID_Pos   16U

ITM TCR: ATBID Position.

Definition at line 857 of file core_cm4.h.

ITM_TCR_TraceBusID_Pos [3/4]

#define ITM_TCR_TraceBusID_Pos   16U

ITM TCR: ATBID Position.

Definition at line 1081 of file core_cm7.h.

ITM_TCR_TraceBusID_Pos [4/4]

#define ITM_TCR_TraceBusID_Pos   16U

ITM TCR: ATBID Position.

Definition at line 784 of file core_sc300.h.

ITM_TCR_TSENA_Msk [1/11]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask.

Definition at line 1151 of file core_armv81mml.h.

ITM_TCR_TSENA_Msk [2/11]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask.

Definition at line 1089 of file core_armv8mml.h.

ITM_TCR_TSENA_Msk [3/11]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask.

Definition at line 818 of file core_cm3.h.

ITM_TCR_TSENA_Msk [4/11]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask.

Definition at line 1089 of file core_cm33.h.

ITM_TCR_TSENA_Msk [5/11]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask.

Definition at line 1089 of file core_cm35p.h.

ITM_TCR_TSENA_Msk [6/11]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask.

Definition at line 876 of file core_cm4.h.

ITM_TCR_TSENA_Msk [7/11]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask.

Definition at line 1196 of file core_cm55.h.

ITM_TCR_TSENA_Msk [8/11]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask.

Definition at line 1100 of file core_cm7.h.

ITM_TCR_TSENA_Msk [9/11]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask.

Definition at line 1192 of file core_cm85.h.

ITM_TCR_TSENA_Msk [10/11]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask.

Definition at line 803 of file core_sc300.h.

ITM_TCR_TSENA_Msk [11/11]

#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask.

Definition at line 1147 of file core_starmc1.h.

ITM_TCR_TSENA_Pos [1/11]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position.

Definition at line 1150 of file core_armv81mml.h.

ITM_TCR_TSENA_Pos [2/11]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position.

Definition at line 1088 of file core_armv8mml.h.

ITM_TCR_TSENA_Pos [3/11]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position.

Definition at line 817 of file core_cm3.h.

ITM_TCR_TSENA_Pos [4/11]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position.

Definition at line 1088 of file core_cm33.h.

ITM_TCR_TSENA_Pos [5/11]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position.

Definition at line 1088 of file core_cm35p.h.

ITM_TCR_TSENA_Pos [6/11]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position.

Definition at line 875 of file core_cm4.h.

ITM_TCR_TSENA_Pos [7/11]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position.

Definition at line 1195 of file core_cm55.h.

ITM_TCR_TSENA_Pos [8/11]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position.

Definition at line 1099 of file core_cm7.h.

ITM_TCR_TSENA_Pos [9/11]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position.

Definition at line 1191 of file core_cm85.h.

ITM_TCR_TSENA_Pos [10/11]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position.

Definition at line 802 of file core_sc300.h.

ITM_TCR_TSENA_Pos [11/11]

#define ITM_TCR_TSENA_Pos   1U

ITM TCR: TSENA Position.

Definition at line 1146 of file core_starmc1.h.

ITM_TCR_TSPRESCALE_Msk [1/7]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask.

Definition at line 1136 of file core_armv81mml.h.

ITM_TCR_TSPRESCALE_Msk [2/7]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask.

Definition at line 1074 of file core_armv8mml.h.

ITM_TCR_TSPRESCALE_Msk [3/7]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask.

Definition at line 1074 of file core_cm33.h.

ITM_TCR_TSPRESCALE_Msk [4/7]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask.

Definition at line 1074 of file core_cm35p.h.

ITM_TCR_TSPRESCALE_Msk [5/7]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask.

Definition at line 1181 of file core_cm55.h.

ITM_TCR_TSPRESCALE_Msk [6/7]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask.

Definition at line 1177 of file core_cm85.h.

ITM_TCR_TSPRESCALE_Msk [7/7]

#define ITM_TCR_TSPRESCALE_Msk   (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask.

Definition at line 1132 of file core_starmc1.h.

ITM_TCR_TSPrescale_Msk [1/4]

#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask.

Definition at line 806 of file core_cm3.h.

ITM_TCR_TSPrescale_Msk [2/4]

#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask.

Definition at line 864 of file core_cm4.h.

ITM_TCR_TSPrescale_Msk [3/4]

#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask.

Definition at line 1088 of file core_cm7.h.

ITM_TCR_TSPrescale_Msk [4/4]

#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask.

Definition at line 791 of file core_sc300.h.

ITM_TCR_TSPRESCALE_Pos [1/7]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPRESCALE Position.

Definition at line 1135 of file core_armv81mml.h.

ITM_TCR_TSPRESCALE_Pos [2/7]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPRESCALE Position.

Definition at line 1073 of file core_armv8mml.h.

ITM_TCR_TSPRESCALE_Pos [3/7]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPRESCALE Position.

Definition at line 1073 of file core_cm33.h.

ITM_TCR_TSPRESCALE_Pos [4/7]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPRESCALE Position.

Definition at line 1073 of file core_cm35p.h.

ITM_TCR_TSPRESCALE_Pos [5/7]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPRESCALE Position.

Definition at line 1180 of file core_cm55.h.

ITM_TCR_TSPRESCALE_Pos [6/7]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPRESCALE Position.

Definition at line 1176 of file core_cm85.h.

ITM_TCR_TSPRESCALE_Pos [7/7]

#define ITM_TCR_TSPRESCALE_Pos   8U

ITM TCR: TSPRESCALE Position.

Definition at line 1131 of file core_starmc1.h.

ITM_TCR_TSPrescale_Pos [1/4]

#define ITM_TCR_TSPrescale_Pos   8U

ITM TCR: TSPrescale Position.

Definition at line 805 of file core_cm3.h.

ITM_TCR_TSPrescale_Pos [2/4]

#define ITM_TCR_TSPrescale_Pos   8U

ITM TCR: TSPrescale Position.

Definition at line 863 of file core_cm4.h.

ITM_TCR_TSPrescale_Pos [3/4]

#define ITM_TCR_TSPrescale_Pos   8U

ITM TCR: TSPrescale Position.

Definition at line 1087 of file core_cm7.h.

ITM_TCR_TSPrescale_Pos [4/4]

#define ITM_TCR_TSPrescale_Pos   8U

ITM TCR: TSPrescale Position.

Definition at line 790 of file core_sc300.h.

ITM_TPR_PRIVMASK_Msk [1/11]

#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask.

Definition at line 1123 of file core_armv81mml.h.

ITM_TPR_PRIVMASK_Msk [2/11]

#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask.

Definition at line 1061 of file core_armv8mml.h.

ITM_TPR_PRIVMASK_Msk [3/11]

#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask.

Definition at line 793 of file core_cm3.h.

ITM_TPR_PRIVMASK_Msk [4/11]

#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask.

Definition at line 1061 of file core_cm33.h.

ITM_TPR_PRIVMASK_Msk [5/11]

#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask.

Definition at line 1061 of file core_cm35p.h.

ITM_TPR_PRIVMASK_Msk [6/11]

#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask.

Definition at line 851 of file core_cm4.h.

ITM_TPR_PRIVMASK_Msk [7/11]

#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask.

Definition at line 1168 of file core_cm55.h.

ITM_TPR_PRIVMASK_Msk [8/11]

#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask.

Definition at line 1075 of file core_cm7.h.

ITM_TPR_PRIVMASK_Msk [9/11]

#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask.

Definition at line 1164 of file core_cm85.h.

ITM_TPR_PRIVMASK_Msk [10/11]

#define ITM_TPR_PRIVMASK_Msk   (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask.

Definition at line 778 of file core_sc300.h.

ITM_TPR_PRIVMASK_Msk [11/11]

#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask.

Definition at line 1119 of file core_starmc1.h.

ITM_TPR_PRIVMASK_Pos [1/11]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position.

Definition at line 1122 of file core_armv81mml.h.

ITM_TPR_PRIVMASK_Pos [2/11]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position.

Definition at line 1060 of file core_armv8mml.h.

ITM_TPR_PRIVMASK_Pos [3/11]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position.

Definition at line 792 of file core_cm3.h.

ITM_TPR_PRIVMASK_Pos [4/11]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position.

Definition at line 1060 of file core_cm33.h.

ITM_TPR_PRIVMASK_Pos [5/11]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position.

Definition at line 1060 of file core_cm35p.h.

ITM_TPR_PRIVMASK_Pos [6/11]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position.

Definition at line 850 of file core_cm4.h.

ITM_TPR_PRIVMASK_Pos [7/11]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position.

Definition at line 1167 of file core_cm55.h.

ITM_TPR_PRIVMASK_Pos [8/11]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position.

Definition at line 1074 of file core_cm7.h.

ITM_TPR_PRIVMASK_Pos [9/11]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position.

Definition at line 1163 of file core_cm85.h.

ITM_TPR_PRIVMASK_Pos [10/11]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position.

Definition at line 777 of file core_sc300.h.

ITM_TPR_PRIVMASK_Pos [11/11]

#define ITM_TPR_PRIVMASK_Pos   0U

ITM TPR: PRIVMASK Position.

Definition at line 1118 of file core_starmc1.h.