Structure type to access the Memory System Control Registers (MEMSYSCTL). More...

#include <core_cm55.h>

Public Attributes
__IOM uint32_t	MSCR
	Offset: 0x000 (R/W) Memory System Control Register.
__IOM uint32_t	PFCR
	Offset: 0x004 (R/W) Prefetcher Control Register.
uint32_t	RESERVED1 [2U]
__IOM uint32_t	ITCMCR
	Offset: 0x010 (R/W) ITCM Control Register.
__IOM uint32_t	DTCMCR
	Offset: 0x014 (R/W) DTCM Control Register.
__IOM uint32_t	PAHBCR
	Offset: 0x018 (R/W) P-AHB Control Register.
uint32_t	RESERVED2 [313U]
__IOM uint32_t	ITGU_CTRL
	Offset: 0x500 (R/W) ITGU Control Register.
__IOM uint32_t	ITGU_CFG
	Offset: 0x504 (R/W) ITGU Configuration Register.
uint32_t	RESERVED3 [2U]
__IOM uint32_t	ITGU_LUT [16U]
	Offset: 0x510 (R/W) ITGU Look Up Table Register.
uint32_t	RESERVED4 [44U]
__IOM uint32_t	DTGU_CTRL
	Offset: 0x600 (R/W) DTGU Control Registers.
__IOM uint32_t	DTGU_CFG
	Offset: 0x604 (R/W) DTGU Configuration Register.
uint32_t	RESERVED5 [2U]
__IOM uint32_t	DTGU_LUT [16U]
	Offset: 0x610 (R/W) DTGU Look Up Table Register.

Detailed Description

Structure type to access the Memory System Control Registers (MEMSYSCTL).

Definition at line 1410 of file core_cm55.h.

The documentation for this struct was generated from the following files:

Public Attributes