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stm32h7xx_hal_rcc_ex.c
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1/**
2 ******************************************************************************
3 * @file stm32h7xx_hal_rcc_ex.c
4 * @author MCD Application Team
5 * @brief Extended RCC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities RCC extension peripheral:
8 * + Extended Peripheral Control functions
9 *
10 ******************************************************************************
11 * @attention
12 *
13 * Copyright (c) 2017 STMicroelectronics.
14 * All rights reserved.
15 *
16 * This software is licensed under terms that can be found in the LICENSE file in
17 * the root directory of this software component.
18 * If no LICENSE file comes with this software, it is provided AS-IS.
19 ******************************************************************************
20 */
21
22/* Includes ------------------------------------------------------------------*/
23#include "stm32h7xx_hal.h"
24
25/** @addtogroup STM32H7xx_HAL_Driver
26 * @{
27 */
28
29/** @defgroup RCCEx RCCEx
30 * @brief RCC HAL module driver
31 * @{
32 */
33
34#ifdef HAL_RCC_MODULE_ENABLED
35
36/* Private typedef -----------------------------------------------------------*/
37/* Private defines -----------------------------------------------------------*/
38/** @defgroup RCCEx_Private_defines RCCEx Private Defines
39 * @{
40 */
41#define PLL2_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */
42#define PLL3_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */
43
44#define DIVIDER_P_UPDATE 0U
45#define DIVIDER_Q_UPDATE 1U
46#define DIVIDER_R_UPDATE 2U
47/**
48 * @}
49 */
50
51/* Private macros ------------------------------------------------------------*/
52/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
53 * @{
54 */
55/**
56 * @}
57 */
58
59/* Private variables ---------------------------------------------------------*/
60/* Private function prototypes -----------------------------------------------*/
61static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2, uint32_t Divider);
62static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3, uint32_t Divider);
63
64/* Exported functions --------------------------------------------------------*/
65/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
66 * @{
67 */
68
69/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
70 * @brief Extended Peripheral Control functions
71 *
72@verbatim
73 ===============================================================================
74 ##### Extended Peripheral Control functions #####
75 ===============================================================================
76 [..]
77 This subsection provides a set of functions allowing to control the RCC Clocks
78 frequencies.
79 [..]
80 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
81 select the RTC clock source; in this case the Backup domain will be reset in
82 order to modify the RTC Clock source, as consequence RTC registers (including
83 the backup registers) and RCC_BDCR register are set to their reset values.
84
85@endverbatim
86 * @{
87 */
88/**
89 * @brief Initializes the RCC extended peripherals clocks according to the specified
90 * parameters in the RCC_PeriphCLKInitTypeDef.
91 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
92 * contains the configuration information for the Extended Peripherals
93 * clocks (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*,SAI2A*, SAI2B*, SAI1, SPI123,
94 * USART234578, USART16 (USART16910*), RNG, HRTIM1*, I2C123 (I2C1235*), USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC,
95 * SAI4A*, SAI4B*, SPI6, RTC).
96 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
97 * the RTC clock source; in this case the Backup domain will be reset in
98 * order to modify the RTC Clock source, as consequence RTC registers (including
99 * the backup registers) are set to their reset values.
100 *
101 * (*) : Available on some STM32H7 lines only.
102 *
103 * @retval HAL status
104 */
105HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
106{
107 uint32_t tmpreg;
108 uint32_t tickstart;
109 HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
110 HAL_StatusTypeDef status = HAL_OK; /* Final status */
111
112 /*---------------------------- SPDIFRX configuration -------------------------------*/
113
114 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
115 {
116
117 switch (PeriphClkInit->SpdifrxClockSelection)
118 {
119 case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/
120 /* Enable PLL1Q Clock output generated form System PLL . */
121 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
122
123 /* SPDIFRX clock source configuration done later after clock selection check */
124 break;
125
126 case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/
127
128 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
129
130 /* SPDIFRX clock source configuration done later after clock selection check */
131 break;
132
133 case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/
134 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
135
136 /* SPDIFRX clock source configuration done later after clock selection check */
137 break;
138
139 case RCC_SPDIFRXCLKSOURCE_HSI:
140 /* Internal OSC clock is used as source of SPDIFRX clock*/
141 /* SPDIFRX clock source configuration done later after clock selection check */
142 break;
143
144 default:
145 ret = HAL_ERROR;
146 break;
147 }
148
149 if (ret == HAL_OK)
150 {
151 /* Set the source of SPDIFRX clock*/
152 __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
153 }
154 else
155 {
156 /* set overall return value */
157 status = ret;
158 }
159 }
160
161 /*---------------------------- SAI1 configuration -------------------------------*/
162 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
163 {
164 switch (PeriphClkInit->Sai1ClockSelection)
165 {
166 case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/
167 /* Enable SAI Clock output generated form System PLL . */
168 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
169
170 /* SAI1 clock source configuration done later after clock selection check */
171 break;
172
173 case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/
174
175 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
176
177 /* SAI1 clock source configuration done later after clock selection check */
178 break;
179
180 case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/
181 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
182
183 /* SAI1 clock source configuration done later after clock selection check */
184 break;
185
186 case RCC_SAI1CLKSOURCE_PIN:
187 /* External clock is used as source of SAI1 clock*/
188 /* SAI1 clock source configuration done later after clock selection check */
189 break;
190
191 case RCC_SAI1CLKSOURCE_CLKP:
192 /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */
193 /* SAI1 clock source configuration done later after clock selection check */
194 break;
195
196 default:
197 ret = HAL_ERROR;
198 break;
199 }
200
201 if (ret == HAL_OK)
202 {
203 /* Set the source of SAI1 clock*/
204 __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
205 }
206 else
207 {
208 /* set overall return value */
209 status = ret;
210 }
211 }
212
213#if defined(SAI3)
214 /*---------------------------- SAI2/3 configuration -------------------------------*/
215 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23)
216 {
217 switch (PeriphClkInit->Sai23ClockSelection)
218 {
219 case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */
220 /* Enable SAI Clock output generated form System PLL . */
221 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
222
223 /* SAI2/3 clock source configuration done later after clock selection check */
224 break;
225
226 case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */
227
228 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
229
230 /* SAI2/3 clock source configuration done later after clock selection check */
231 break;
232
233 case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */
234 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
235
236 /* SAI2/3 clock source configuration done later after clock selection check */
237 break;
238
239 case RCC_SAI23CLKSOURCE_PIN:
240 /* External clock is used as source of SAI2/3 clock*/
241 /* SAI2/3 clock source configuration done later after clock selection check */
242 break;
243
244 case RCC_SAI23CLKSOURCE_CLKP:
245 /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */
246 /* SAI2/3 clock source configuration done later after clock selection check */
247 break;
248
249 default:
250 ret = HAL_ERROR;
251 break;
252 }
253
254 if (ret == HAL_OK)
255 {
256 /* Set the source of SAI2/3 clock*/
257 __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection);
258 }
259 else
260 {
261 /* set overall return value */
262 status = ret;
263 }
264 }
265
266#endif /* SAI3 */
267
268#if defined(RCC_CDCCIP1R_SAI2ASEL)
269 /*---------------------------- SAI2A configuration -------------------------------*/
270 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A)
271 {
272 switch (PeriphClkInit->Sai2AClockSelection)
273 {
274 case RCC_SAI2ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2A */
275 /* Enable SAI2A Clock output generated form System PLL . */
276 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
277
278 /* SAI2A clock source configuration done later after clock selection check */
279 break;
280
281 case RCC_SAI2ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2A */
282
283 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
284
285 /* SAI2A clock source configuration done later after clock selection check */
286 break;
287
288 case RCC_SAI2ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2A */
289 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
290
291 /* SAI2A clock source configuration done later after clock selection check */
292 break;
293
294 case RCC_SAI2ACLKSOURCE_PIN:
295 /* External clock is used as source of SAI2A clock*/
296 /* SAI2A clock source configuration done later after clock selection check */
297 break;
298
299 case RCC_SAI2ACLKSOURCE_CLKP:
300 /* HSI, HSE, or CSI oscillator is used as source of SAI2A clock */
301 /* SAI2A clock source configuration done later after clock selection check */
302 break;
303
304 case RCC_SAI2ACLKSOURCE_SPDIF:
305 /* SPDIF clock is used as source of SAI2A clock */
306 /* SAI2A clock source configuration done later after clock selection check */
307 break;
308
309 default:
310 ret = HAL_ERROR;
311 break;
312 }
313
314 if (ret == HAL_OK)
315 {
316 /* Set the source of SAI2A clock*/
317 __HAL_RCC_SAI2A_CONFIG(PeriphClkInit->Sai2AClockSelection);
318 }
319 else
320 {
321 /* set overall return value */
322 status = ret;
323 }
324 }
325#endif /*SAI2A*/
326
327#if defined(RCC_CDCCIP1R_SAI2BSEL)
328
329 /*---------------------------- SAI2B configuration -------------------------------*/
330 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B)
331 {
332 switch (PeriphClkInit->Sai2BClockSelection)
333 {
334 case RCC_SAI2BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2B */
335 /* Enable SAI Clock output generated form System PLL . */
336 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
337
338 /* SAI2B clock source configuration done later after clock selection check */
339 break;
340
341 case RCC_SAI2BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2B */
342
343 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
344
345 /* SAI2B clock source configuration done later after clock selection check */
346 break;
347
348 case RCC_SAI2BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2B */
349 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
350
351 /* SAI2B clock source configuration done later after clock selection check */
352 break;
353
354 case RCC_SAI2BCLKSOURCE_PIN:
355 /* External clock is used as source of SAI2B clock*/
356 /* SAI2B clock source configuration done later after clock selection check */
357 break;
358
359 case RCC_SAI2BCLKSOURCE_CLKP:
360 /* HSI, HSE, or CSI oscillator is used as source of SAI2B clock */
361 /* SAI2B clock source configuration done later after clock selection check */
362 break;
363
364 case RCC_SAI2BCLKSOURCE_SPDIF:
365 /* SPDIF clock is used as source of SAI2B clock */
366 /* SAI2B clock source configuration done later after clock selection check */
367 break;
368
369 default:
370 ret = HAL_ERROR;
371 break;
372 }
373
374 if (ret == HAL_OK)
375 {
376 /* Set the source of SAI2B clock*/
377 __HAL_RCC_SAI2B_CONFIG(PeriphClkInit->Sai2BClockSelection);
378 }
379 else
380 {
381 /* set overall return value */
382 status = ret;
383 }
384 }
385#endif /*SAI2B*/
386
387#if defined(SAI4)
388 /*---------------------------- SAI4A configuration -------------------------------*/
389 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)
390 {
391 switch (PeriphClkInit->Sai4AClockSelection)
392 {
393 case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
394 /* Enable SAI Clock output generated form System PLL . */
395 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
396
397 /* SAI1 clock source configuration done later after clock selection check */
398 break;
399
400 case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
401
402 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
403
404 /* SAI2 clock source configuration done later after clock selection check */
405 break;
406
407 case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/
408 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
409
410 /* SAI1 clock source configuration done later after clock selection check */
411 break;
412
413 case RCC_SAI4ACLKSOURCE_PIN:
414 /* External clock is used as source of SAI2 clock*/
415 /* SAI2 clock source configuration done later after clock selection check */
416 break;
417
418 case RCC_SAI4ACLKSOURCE_CLKP:
419 /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
420 /* SAI1 clock source configuration done later after clock selection check */
421 break;
422
423#if defined(RCC_VER_3_0)
424 case RCC_SAI4ACLKSOURCE_SPDIF:
425 /* SPDIF clock is used as source of SAI4A clock */
426 /* SAI4A clock source configuration done later after clock selection check */
427 break;
428#endif /* RCC_VER_3_0 */
429
430 default:
431 ret = HAL_ERROR;
432 break;
433 }
434
435 if (ret == HAL_OK)
436 {
437 /* Set the source of SAI4A clock*/
438 __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection);
439 }
440 else
441 {
442 /* set overall return value */
443 status = ret;
444 }
445 }
446 /*---------------------------- SAI4B configuration -------------------------------*/
447 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)
448 {
449 switch (PeriphClkInit->Sai4BClockSelection)
450 {
451 case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
452 /* Enable SAI Clock output generated form System PLL . */
453 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
454
455 /* SAI1 clock source configuration done later after clock selection check */
456 break;
457
458 case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
459
460 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
461
462 /* SAI2 clock source configuration done later after clock selection check */
463 break;
464
465 case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/
466 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
467
468 /* SAI1 clock source configuration done later after clock selection check */
469 break;
470
471 case RCC_SAI4BCLKSOURCE_PIN:
472 /* External clock is used as source of SAI2 clock*/
473 /* SAI2 clock source configuration done later after clock selection check */
474 break;
475
476 case RCC_SAI4BCLKSOURCE_CLKP:
477 /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
478 /* SAI1 clock source configuration done later after clock selection check */
479 break;
480
481#if defined(RCC_VER_3_0)
482 case RCC_SAI4BCLKSOURCE_SPDIF:
483 /* SPDIF clock is used as source of SAI4B clock */
484 /* SAI4B clock source configuration done later after clock selection check */
485 break;
486#endif /* RCC_VER_3_0 */
487
488 default:
489 ret = HAL_ERROR;
490 break;
491 }
492
493 if (ret == HAL_OK)
494 {
495 /* Set the source of SAI4B clock*/
496 __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection);
497 }
498 else
499 {
500 /* set overall return value */
501 status = ret;
502 }
503 }
504#endif /*SAI4*/
505
506#if defined(QUADSPI)
507 /*---------------------------- QSPI configuration -------------------------------*/
508 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
509 {
510 switch (PeriphClkInit->QspiClockSelection)
511 {
512 case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/
513 /* Enable QSPI Clock output generated form System PLL . */
514 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
515
516 /* QSPI clock source configuration done later after clock selection check */
517 break;
518
519 case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/
520
521 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
522
523 /* QSPI clock source configuration done later after clock selection check */
524 break;
525
526
527 case RCC_QSPICLKSOURCE_CLKP:
528 /* HSI, HSE, or CSI oscillator is used as source of QSPI clock */
529 /* QSPI clock source configuration done later after clock selection check */
530 break;
531
532 case RCC_QSPICLKSOURCE_D1HCLK:
533 /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */
534 break;
535
536 default:
537 ret = HAL_ERROR;
538 break;
539 }
540
541 if (ret == HAL_OK)
542 {
543 /* Set the source of QSPI clock*/
544 __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
545 }
546 else
547 {
548 /* set overall return value */
549 status = ret;
550 }
551 }
552#endif /*QUADSPI*/
553
554#if defined(OCTOSPI1) || defined(OCTOSPI2)
555 /*---------------------------- OCTOSPI configuration -------------------------------*/
556 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
557 {
558 switch (PeriphClkInit->OspiClockSelection)
559 {
560 case RCC_OSPICLKSOURCE_PLL: /* PLL is used as clock source for OSPI*/
561 /* Enable OSPI Clock output generated form System PLL . */
562 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
563
564 /* OSPI clock source configuration done later after clock selection check */
565 break;
566
567 case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/
568
569 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
570
571 /* OSPI clock source configuration done later after clock selection check */
572 break;
573
574
575 case RCC_OSPICLKSOURCE_CLKP:
576 /* HSI, HSE, or CSI oscillator is used as source of OSPI clock */
577 /* OSPI clock source configuration done later after clock selection check */
578 break;
579
580 case RCC_OSPICLKSOURCE_HCLK:
581 /* HCLK clock selected as OSPI kernel peripheral clock */
582 break;
583
584 default:
585 ret = HAL_ERROR;
586 break;
587 }
588
589 if (ret == HAL_OK)
590 {
591 /* Set the source of OSPI clock*/
592 __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection);
593 }
594 else
595 {
596 /* set overall return value */
597 status = ret;
598 }
599 }
600#endif /*OCTOSPI*/
601
602 /*---------------------------- SPI1/2/3 configuration -------------------------------*/
603 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123)
604 {
605 switch (PeriphClkInit->Spi123ClockSelection)
606 {
607 case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */
608 /* Enable SPI Clock output generated form System PLL . */
609 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
610
611 /* SPI1/2/3 clock source configuration done later after clock selection check */
612 break;
613
614 case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */
615 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
616
617 /* SPI1/2/3 clock source configuration done later after clock selection check */
618 break;
619
620 case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */
621 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
622
623 /* SPI1/2/3 clock source configuration done later after clock selection check */
624 break;
625
626 case RCC_SPI123CLKSOURCE_PIN:
627 /* External clock is used as source of SPI1/2/3 clock*/
628 /* SPI1/2/3 clock source configuration done later after clock selection check */
629 break;
630
631 case RCC_SPI123CLKSOURCE_CLKP:
632 /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */
633 /* SPI1/2/3 clock source configuration done later after clock selection check */
634 break;
635
636 default:
637 ret = HAL_ERROR;
638 break;
639 }
640
641 if (ret == HAL_OK)
642 {
643 /* Set the source of SPI1/2/3 clock*/
644 __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection);
645 }
646 else
647 {
648 /* set overall return value */
649 status = ret;
650 }
651 }
652
653 /*---------------------------- SPI4/5 configuration -------------------------------*/
654 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
655 {
656 switch (PeriphClkInit->Spi45ClockSelection)
657 {
658 case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for SPI4/5 */
659 /* SPI4/5 clock source configuration done later after clock selection check */
660 break;
661
662 case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */
663
664 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
665
666 /* SPI4/5 clock source configuration done later after clock selection check */
667 break;
668 case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */
669 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
670 /* SPI4/5 clock source configuration done later after clock selection check */
671 break;
672
673 case RCC_SPI45CLKSOURCE_HSI:
674 /* HSI oscillator clock is used as source of SPI4/5 clock*/
675 /* SPI4/5 clock source configuration done later after clock selection check */
676 break;
677
678 case RCC_SPI45CLKSOURCE_CSI:
679 /* CSI oscillator clock is used as source of SPI4/5 clock */
680 /* SPI4/5 clock source configuration done later after clock selection check */
681 break;
682
683 case RCC_SPI45CLKSOURCE_HSE:
684 /* HSE, oscillator is used as source of SPI4/5 clock */
685 /* SPI4/5 clock source configuration done later after clock selection check */
686 break;
687
688 default:
689 ret = HAL_ERROR;
690 break;
691 }
692
693 if (ret == HAL_OK)
694 {
695 /* Set the source of SPI4/5 clock*/
696 __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);
697 }
698 else
699 {
700 /* set overall return value */
701 status = ret;
702 }
703 }
704
705 /*---------------------------- SPI6 configuration -------------------------------*/
706 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
707 {
708 switch (PeriphClkInit->Spi6ClockSelection)
709 {
710 case RCC_SPI6CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for SPI6*/
711 /* SPI6 clock source configuration done later after clock selection check */
712 break;
713
714 case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/
715
716 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
717
718 /* SPI6 clock source configuration done later after clock selection check */
719 break;
720 case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/
721 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
722 /* SPI6 clock source configuration done later after clock selection check */
723 break;
724
725 case RCC_SPI6CLKSOURCE_HSI:
726 /* HSI oscillator clock is used as source of SPI6 clock*/
727 /* SPI6 clock source configuration done later after clock selection check */
728 break;
729
730 case RCC_SPI6CLKSOURCE_CSI:
731 /* CSI oscillator clock is used as source of SPI6 clock */
732 /* SPI6 clock source configuration done later after clock selection check */
733 break;
734
735 case RCC_SPI6CLKSOURCE_HSE:
736 /* HSE, oscillator is used as source of SPI6 clock */
737 /* SPI6 clock source configuration done later after clock selection check */
738 break;
739#if defined(RCC_SPI6CLKSOURCE_PIN)
740 case RCC_SPI6CLKSOURCE_PIN:
741 /* 2S_CKIN is used as source of SPI6 clock */
742 /* SPI6 clock source configuration done later after clock selection check */
743 break;
744#endif
745
746 default:
747 ret = HAL_ERROR;
748 break;
749 }
750
751 if (ret == HAL_OK)
752 {
753 /* Set the source of SPI6 clock*/
754 __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
755 }
756 else
757 {
758 /* set overall return value */
759 status = ret;
760 }
761 }
762
763#if defined(DSI)
764 /*---------------------------- DSI configuration -------------------------------*/
765 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)
766 {
767 switch (PeriphClkInit->DsiClockSelection)
768 {
769
770 case RCC_DSICLKSOURCE_PLL2: /* PLL2 is used as clock source for DSI*/
771
772 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
773
774 /* DSI clock source configuration done later after clock selection check */
775 break;
776
777 case RCC_DSICLKSOURCE_PHY:
778 /* PHY is used as clock source for DSI*/
779 /* DSI clock source configuration done later after clock selection check */
780 break;
781
782 default:
783 ret = HAL_ERROR;
784 break;
785 }
786
787 if (ret == HAL_OK)
788 {
789 /* Set the source of DSI clock*/
790 __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection);
791 }
792 else
793 {
794 /* set overall return value */
795 status = ret;
796 }
797 }
798#endif /*DSI*/
799
800#if defined(FDCAN1) || defined(FDCAN2)
801 /*---------------------------- FDCAN configuration -------------------------------*/
802 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
803 {
804 switch (PeriphClkInit->FdcanClockSelection)
805 {
806 case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/
807 /* Enable FDCAN Clock output generated form System PLL . */
808 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
809
810 /* FDCAN clock source configuration done later after clock selection check */
811 break;
812
813 case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/
814
815 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
816
817 /* FDCAN clock source configuration done later after clock selection check */
818 break;
819
820 case RCC_FDCANCLKSOURCE_HSE:
821 /* HSE is used as clock source for FDCAN*/
822 /* FDCAN clock source configuration done later after clock selection check */
823 break;
824
825 default:
826 ret = HAL_ERROR;
827 break;
828 }
829
830 if (ret == HAL_OK)
831 {
832 /* Set the source of FDCAN clock*/
833 __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
834 }
835 else
836 {
837 /* set overall return value */
838 status = ret;
839 }
840 }
841#endif /*FDCAN1 || FDCAN2*/
842
843 /*---------------------------- FMC configuration -------------------------------*/
844 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
845 {
846 switch (PeriphClkInit->FmcClockSelection)
847 {
848 case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/
849 /* Enable FMC Clock output generated form System PLL . */
850 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
851
852 /* FMC clock source configuration done later after clock selection check */
853 break;
854
855 case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/
856
857 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
858
859 /* FMC clock source configuration done later after clock selection check */
860 break;
861
862
863 case RCC_FMCCLKSOURCE_CLKP:
864 /* HSI, HSE, or CSI oscillator is used as source of FMC clock */
865 /* FMC clock source configuration done later after clock selection check */
866 break;
867
868 case RCC_FMCCLKSOURCE_HCLK:
869 /* D1/CD HCLK clock selected as FMC kernel peripheral clock */
870 break;
871
872 default:
873 ret = HAL_ERROR;
874 break;
875 }
876
877 if (ret == HAL_OK)
878 {
879 /* Set the source of FMC clock*/
880 __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
881 }
882 else
883 {
884 /* set overall return value */
885 status = ret;
886 }
887 }
888
889 /*---------------------------- RTC configuration -------------------------------*/
890 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
891 {
892 /* check for RTC Parameters used to output RTCCLK */
893 assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
894
895 /* Enable write access to Backup domain */
896 SET_BIT(PWR->CR1, PWR_CR1_DBP);
897
898 /* Wait for Backup domain Write protection disable */
899 tickstart = HAL_GetTick();
900
901 while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
902 {
903 if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
904 {
905 ret = HAL_TIMEOUT;
906 break;
907 }
908 }
909
910 if (ret == HAL_OK)
911 {
912 /* Reset the Backup domain only if the RTC Clock source selection is modified */
913 if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
914 {
915 /* Store the content of BDCR register before the reset of Backup Domain */
916 tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
917 /* RTC Clock selection can be changed only if the Backup Domain is reset */
918 __HAL_RCC_BACKUPRESET_FORCE();
919 __HAL_RCC_BACKUPRESET_RELEASE();
920 /* Restore the Content of BDCR register */
921 RCC->BDCR = tmpreg;
922 }
923
924 /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */
925 if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
926 {
927 /* Get Start Tick*/
928 tickstart = HAL_GetTick();
929
930 /* Wait till LSE is ready */
931 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
932 {
933 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
934 {
935 ret = HAL_TIMEOUT;
936 break;
937 }
938 }
939 }
940
941 if (ret == HAL_OK)
942 {
943 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
944 }
945 else
946 {
947 /* set overall return value */
948 status = ret;
949 }
950 }
951 else
952 {
953 /* set overall return value */
954 status = ret;
955 }
956 }
957
958
959 /*-------------------------- USART1/6 configuration --------------------------*/
960 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
961 {
962 switch (PeriphClkInit->Usart16ClockSelection)
963 {
964 case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */
965 /* USART1/6 clock source configuration done later after clock selection check */
966 break;
967
968 case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */
969 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
970 /* USART1/6 clock source configuration done later after clock selection check */
971 break;
972
973 case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */
974 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
975 /* USART1/6 clock source configuration done later after clock selection check */
976 break;
977
978 case RCC_USART16CLKSOURCE_HSI:
979 /* HSI oscillator clock is used as source of USART1/6 clock */
980 /* USART1/6 clock source configuration done later after clock selection check */
981 break;
982
983 case RCC_USART16CLKSOURCE_CSI:
984 /* CSI oscillator clock is used as source of USART1/6 clock */
985 /* USART1/6 clock source configuration done later after clock selection check */
986 break;
987
988 case RCC_USART16CLKSOURCE_LSE:
989 /* LSE, oscillator is used as source of USART1/6 clock */
990 /* USART1/6 clock source configuration done later after clock selection check */
991 break;
992
993 default:
994 ret = HAL_ERROR;
995 break;
996 }
997
998 if (ret == HAL_OK)
999 {
1000 /* Set the source of USART1/6 clock */
1001 __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection);
1002 }
1003 else
1004 {
1005 /* set overall return value */
1006 status = ret;
1007 }
1008 }
1009
1010 /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/
1011 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
1012 {
1013 switch (PeriphClkInit->Usart234578ClockSelection)
1014 {
1015 case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */
1016 /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
1017 break;
1018
1019 case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */
1020 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
1021 /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
1022 break;
1023
1024 case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */
1025 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
1026 /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
1027 break;
1028
1029 case RCC_USART234578CLKSOURCE_HSI:
1030 /* HSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */
1031 /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
1032 break;
1033
1034 case RCC_USART234578CLKSOURCE_CSI:
1035 /* CSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */
1036 /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
1037 break;
1038
1039 case RCC_USART234578CLKSOURCE_LSE:
1040 /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */
1041 /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
1042 break;
1043
1044 default:
1045 ret = HAL_ERROR;
1046 break;
1047 }
1048
1049 if (ret == HAL_OK)
1050 {
1051 /* Set the source of USART2/3/4/5/7/8 clock */
1052 __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection);
1053 }
1054 else
1055 {
1056 /* set overall return value */
1057 status = ret;
1058 }
1059 }
1060
1061 /*-------------------------- LPUART1 Configuration -------------------------*/
1062 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
1063 {
1064 switch (PeriphClkInit->Lpuart1ClockSelection)
1065 {
1066 case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */
1067 /* LPUART1 clock source configuration done later after clock selection check */
1068 break;
1069
1070 case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */
1071 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
1072 /* LPUART1 clock source configuration done later after clock selection check */
1073 break;
1074
1075 case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */
1076 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
1077 /* LPUART1 clock source configuration done later after clock selection check */
1078 break;
1079
1080 case RCC_LPUART1CLKSOURCE_HSI:
1081 /* HSI oscillator clock is used as source of LPUART1 clock */
1082 /* LPUART1 clock source configuration done later after clock selection check */
1083 break;
1084
1085 case RCC_LPUART1CLKSOURCE_CSI:
1086 /* CSI oscillator clock is used as source of LPUART1 clock */
1087 /* LPUART1 clock source configuration done later after clock selection check */
1088 break;
1089
1090 case RCC_LPUART1CLKSOURCE_LSE:
1091 /* LSE, oscillator is used as source of LPUART1 clock */
1092 /* LPUART1 clock source configuration done later after clock selection check */
1093 break;
1094
1095 default:
1096 ret = HAL_ERROR;
1097 break;
1098 }
1099
1100 if (ret == HAL_OK)
1101 {
1102 /* Set the source of LPUART1 clock */
1103 __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
1104 }
1105 else
1106 {
1107 /* set overall return value */
1108 status = ret;
1109 }
1110 }
1111
1112 /*---------------------------- LPTIM1 configuration -------------------------------*/
1113 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
1114 {
1115 switch (PeriphClkInit->Lptim1ClockSelection)
1116 {
1117 case RCC_LPTIM1CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for LPTIM1*/
1118 /* LPTIM1 clock source configuration done later after clock selection check */
1119 break;
1120
1121 case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/
1122
1123 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
1124
1125 /* LPTIM1 clock source configuration done later after clock selection check */
1126 break;
1127
1128 case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/
1129 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
1130
1131 /* LPTIM1 clock source configuration done later after clock selection check */
1132 break;
1133
1134 case RCC_LPTIM1CLKSOURCE_LSE:
1135 /* External low speed OSC clock is used as source of LPTIM1 clock*/
1136 /* LPTIM1 clock source configuration done later after clock selection check */
1137 break;
1138
1139 case RCC_LPTIM1CLKSOURCE_LSI:
1140 /* Internal low speed OSC clock is used as source of LPTIM1 clock*/
1141 /* LPTIM1 clock source configuration done later after clock selection check */
1142 break;
1143 case RCC_LPTIM1CLKSOURCE_CLKP:
1144 /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */
1145 /* LPTIM1 clock source configuration done later after clock selection check */
1146 break;
1147
1148 default:
1149 ret = HAL_ERROR;
1150 break;
1151 }
1152
1153 if (ret == HAL_OK)
1154 {
1155 /* Set the source of LPTIM1 clock*/
1156 __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
1157 }
1158 else
1159 {
1160 /* set overall return value */
1161 status = ret;
1162 }
1163 }
1164
1165 /*---------------------------- LPTIM2 configuration -------------------------------*/
1166 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
1167 {
1168 switch (PeriphClkInit->Lptim2ClockSelection)
1169 {
1170 case RCC_LPTIM2CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM2*/
1171 /* LPTIM2 clock source configuration done later after clock selection check */
1172 break;
1173
1174 case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/
1175
1176 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
1177
1178 /* LPTIM2 clock source configuration done later after clock selection check */
1179 break;
1180
1181 case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/
1182 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
1183
1184 /* LPTIM2 clock source configuration done later after clock selection check */
1185 break;
1186
1187 case RCC_LPTIM2CLKSOURCE_LSE:
1188 /* External low speed OSC clock is used as source of LPTIM2 clock*/
1189 /* LPTIM2 clock source configuration done later after clock selection check */
1190 break;
1191
1192 case RCC_LPTIM2CLKSOURCE_LSI:
1193 /* Internal low speed OSC clock is used as source of LPTIM2 clock*/
1194 /* LPTIM2 clock source configuration done later after clock selection check */
1195 break;
1196 case RCC_LPTIM2CLKSOURCE_CLKP:
1197 /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */
1198 /* LPTIM2 clock source configuration done later after clock selection check */
1199 break;
1200
1201 default:
1202 ret = HAL_ERROR;
1203 break;
1204 }
1205
1206 if (ret == HAL_OK)
1207 {
1208 /* Set the source of LPTIM2 clock*/
1209 __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
1210 }
1211 else
1212 {
1213 /* set overall return value */
1214 status = ret;
1215 }
1216 }
1217
1218 /*---------------------------- LPTIM345 configuration -------------------------------*/
1219 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)
1220 {
1221 switch (PeriphClkInit->Lptim345ClockSelection)
1222 {
1223
1224 case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */
1225 /* LPTIM3/4/5 clock source configuration done later after clock selection check */
1226 break;
1227
1228 case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */
1229 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
1230
1231 /* LPTIM3/4/5 clock source configuration done later after clock selection check */
1232 break;
1233
1234 case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */
1235 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
1236
1237 /* LPTIM3/4/5 clock source configuration done later after clock selection check */
1238 break;
1239
1240 case RCC_LPTIM345CLKSOURCE_LSE:
1241 /* External low speed OSC clock is used as source of LPTIM3/4/5 clock */
1242 /* LPTIM3/4/5 clock source configuration done later after clock selection check */
1243 break;
1244
1245 case RCC_LPTIM345CLKSOURCE_LSI:
1246 /* Internal low speed OSC clock is used as source of LPTIM3/4/5 clock */
1247 /* LPTIM3/4/5 clock source configuration done later after clock selection check */
1248 break;
1249 case RCC_LPTIM345CLKSOURCE_CLKP:
1250 /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */
1251 /* LPTIM3/4/5 clock source configuration done later after clock selection check */
1252 break;
1253
1254 default:
1255 ret = HAL_ERROR;
1256 break;
1257 }
1258
1259 if (ret == HAL_OK)
1260 {
1261 /* Set the source of LPTIM3/4/5 clock */
1262 __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection);
1263 }
1264 else
1265 {
1266 /* set overall return value */
1267 status = ret;
1268 }
1269 }
1270
1271 /*------------------------------ I2C1/2/3/5* Configuration ------------------------*/
1272#if defined(I2C5)
1273 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1235) == RCC_PERIPHCLK_I2C1235)
1274 {
1275 /* Check the parameters */
1276 assert_param(IS_RCC_I2C1235CLKSOURCE(PeriphClkInit->I2c1235ClockSelection));
1277
1278 if ((PeriphClkInit->I2c1235ClockSelection) == RCC_I2C1235CLKSOURCE_PLL3)
1279 {
1280 if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
1281 {
1282 status = HAL_ERROR;
1283 }
1284 }
1285
1286 __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection);
1287
1288 }
1289#else
1290 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123)
1291 {
1292 /* Check the parameters */
1293 assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection));
1294
1295 if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3)
1296 {
1297 if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
1298 {
1299 status = HAL_ERROR;
1300 }
1301 }
1302
1303 __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection);
1304
1305 }
1306#endif /* I2C5 */
1307
1308 /*------------------------------ I2C4 Configuration ------------------------*/
1309 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
1310 {
1311 /* Check the parameters */
1312 assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
1313
1314 if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3)
1315 {
1316 if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
1317 {
1318 status = HAL_ERROR;
1319 }
1320 }
1321
1322 __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
1323
1324 }
1325
1326 /*---------------------------- ADC configuration -------------------------------*/
1327 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
1328 {
1329 switch (PeriphClkInit->AdcClockSelection)
1330 {
1331
1332 case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/
1333
1334 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
1335
1336 /* ADC clock source configuration done later after clock selection check */
1337 break;
1338
1339 case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/
1340 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
1341
1342 /* ADC clock source configuration done later after clock selection check */
1343 break;
1344
1345 case RCC_ADCCLKSOURCE_CLKP:
1346 /* HSI, HSE, or CSI oscillator is used as source of ADC clock */
1347 /* ADC clock source configuration done later after clock selection check */
1348 break;
1349
1350 default:
1351 ret = HAL_ERROR;
1352 break;
1353 }
1354
1355 if (ret == HAL_OK)
1356 {
1357 /* Set the source of ADC clock*/
1358 __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
1359 }
1360 else
1361 {
1362 /* set overall return value */
1363 status = ret;
1364 }
1365 }
1366
1367 /*------------------------------ USB Configuration -------------------------*/
1368 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
1369 {
1370
1371 switch (PeriphClkInit->UsbClockSelection)
1372 {
1373 case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/
1374 /* Enable USB Clock output generated form System USB . */
1375 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
1376
1377 /* USB clock source configuration done later after clock selection check */
1378 break;
1379
1380 case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/
1381
1382 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
1383
1384 /* USB clock source configuration done later after clock selection check */
1385 break;
1386
1387 case RCC_USBCLKSOURCE_HSI48:
1388 /* HSI48 oscillator is used as source of USB clock */
1389 /* USB clock source configuration done later after clock selection check */
1390 break;
1391
1392 default:
1393 ret = HAL_ERROR;
1394 break;
1395 }
1396
1397 if (ret == HAL_OK)
1398 {
1399 /* Set the source of USB clock*/
1400 __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
1401 }
1402 else
1403 {
1404 /* set overall return value */
1405 status = ret;
1406 }
1407
1408 }
1409
1410 /*------------------------------------- SDMMC Configuration ------------------------------------*/
1411 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC)
1412 {
1413 /* Check the parameters */
1414 assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection));
1415
1416 switch (PeriphClkInit->SdmmcClockSelection)
1417 {
1418 case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/
1419 /* Enable SDMMC Clock output generated form System PLL . */
1420 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
1421
1422 /* SDMMC clock source configuration done later after clock selection check */
1423 break;
1424
1425 case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/
1426
1427 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
1428
1429 /* SDMMC clock source configuration done later after clock selection check */
1430 break;
1431
1432 default:
1433 ret = HAL_ERROR;
1434 break;
1435 }
1436
1437 if (ret == HAL_OK)
1438 {
1439 /* Set the source of SDMMC clock*/
1440 __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection);
1441 }
1442 else
1443 {
1444 /* set overall return value */
1445 status = ret;
1446 }
1447 }
1448
1449#if defined(LTDC)
1450 /*-------------------------------------- LTDC Configuration -----------------------------------*/
1451 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
1452 {
1453 if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
1454 {
1455 status = HAL_ERROR;
1456 }
1457 }
1458#endif /* LTDC */
1459
1460 /*------------------------------ RNG Configuration -------------------------*/
1461 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
1462 {
1463
1464 switch (PeriphClkInit->RngClockSelection)
1465 {
1466 case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/
1467 /* Enable RNG Clock output generated form System RNG . */
1468 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
1469
1470 /* RNG clock source configuration done later after clock selection check */
1471 break;
1472
1473 case RCC_RNGCLKSOURCE_LSE: /* LSE is used as clock source for RNG*/
1474
1475 /* RNG clock source configuration done later after clock selection check */
1476 break;
1477
1478 case RCC_RNGCLKSOURCE_LSI: /* LSI is used as clock source for RNG*/
1479
1480 /* RNG clock source configuration done later after clock selection check */
1481 break;
1482 case RCC_RNGCLKSOURCE_HSI48:
1483 /* HSI48 oscillator is used as source of RNG clock */
1484 /* RNG clock source configuration done later after clock selection check */
1485 break;
1486
1487 default:
1488 ret = HAL_ERROR;
1489 break;
1490 }
1491
1492 if (ret == HAL_OK)
1493 {
1494 /* Set the source of RNG clock*/
1495 __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
1496 }
1497 else
1498 {
1499 /* set overall return value */
1500 status = ret;
1501 }
1502
1503 }
1504
1505 /*------------------------------ SWPMI1 Configuration ------------------------*/
1506 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
1507 {
1508 /* Check the parameters */
1509 assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
1510
1511 /* Configure the SWPMI1 interface clock source */
1512 __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
1513 }
1514#if defined(HRTIM1)
1515 /*------------------------------ HRTIM1 clock Configuration ----------------*/
1516 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
1517 {
1518 /* Check the parameters */
1519 assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));
1520
1521 /* Configure the HRTIM1 clock source */
1522 __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
1523 }
1524#endif /*HRTIM1*/
1525 /*------------------------------ DFSDM1 Configuration ------------------------*/
1526 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
1527 {
1528 /* Check the parameters */
1529 assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
1530
1531 /* Configure the DFSDM1 interface clock source */
1532 __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
1533 }
1534
1535#if defined(DFSDM2_BASE)
1536 /*------------------------------ DFSDM2 Configuration ------------------------*/
1537 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2)
1538 {
1539 /* Check the parameters */
1540 assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection));
1541
1542 /* Configure the DFSDM2 interface clock source */
1543 __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection);
1544 }
1545#endif /* DFSDM2 */
1546
1547 /*------------------------------------ TIM configuration --------------------------------------*/
1548 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
1549 {
1550 /* Check the parameters */
1551 assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
1552
1553 /* Configure Timer Prescaler */
1554 __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
1555 }
1556
1557 /*------------------------------------ CKPER configuration --------------------------------------*/
1558 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
1559 {
1560 /* Check the parameters */
1561 assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection));
1562
1563 /* Configure the CKPER clock source */
1564 __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection);
1565 }
1566
1567 /*------------------------------ CEC Configuration ------------------------*/
1568 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
1569 {
1570 /* Check the parameters */
1571 assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
1572
1573 /* Configure the CEC interface clock source */
1574 __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
1575 }
1576
1577 /*---------------------------- PLL2 configuration -------------------------------*/
1578 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP)
1579 {
1580 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
1581
1582 if (ret == HAL_OK)
1583 {
1584 /*Nothing to do*/
1585 }
1586 else
1587 {
1588 /* set overall return value */
1589 status = ret;
1590 }
1591 }
1592
1593
1594 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ)
1595 {
1596 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
1597
1598 if (ret == HAL_OK)
1599 {
1600 /*Nothing to do*/
1601 }
1602 else
1603 {
1604 /* set overall return value */
1605 status = ret;
1606 }
1607 }
1608
1609
1610 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR)
1611 {
1612 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
1613
1614 if (ret == HAL_OK)
1615 {
1616 /*Nothing to do*/
1617 }
1618 else
1619 {
1620 /* set overall return value */
1621 status = ret;
1622 }
1623 }
1624
1625
1626 /*---------------------------- PLL3 configuration -------------------------------*/
1627 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP)
1628 {
1629 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
1630
1631 if (ret == HAL_OK)
1632 {
1633 /*Nothing to do*/
1634 }
1635 else
1636 {
1637 /* set overall return value */
1638 status = ret;
1639 }
1640 }
1641
1642
1643 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ)
1644 {
1645 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
1646
1647 if (ret == HAL_OK)
1648 {
1649 /*Nothing to do*/
1650 }
1651 else
1652 {
1653 /* set overall return value */
1654 status = ret;
1655 }
1656 }
1657
1658
1659 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR)
1660 {
1661 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
1662
1663 if (ret == HAL_OK)
1664 {
1665 /*Nothing to do*/
1666 }
1667 else
1668 {
1669 /* set overall return value */
1670 status = ret;
1671 }
1672 }
1673
1674 if (status == HAL_OK)
1675 {
1676 return HAL_OK;
1677 }
1678 return HAL_ERROR;
1679}
1680
1681/**
1682 * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
1683 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
1684 * returns the configuration information for the Extended Peripherals clocks :
1685 * (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI*, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*, SAI1, SPI123,
1686 * USART234578, USART16, RNG, HRTIM1*, I2C123 (I2C1235*), USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC.
1687 * SAI4A*, SAI4B*, SPI6, RTC, TIM).
1688 * @retval None
1689 *
1690 * (*) : Available on some STM32H7 lines only.
1691 */
1692void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
1693{
1694 /* Set all possible values for the extended clock type parameter------------*/
1695 PeriphClkInit->PeriphClockSelection =
1696 RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 |
1697 RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM345 |
1698 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SPI123 | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6 |
1699 RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB |
1700 RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_RTC |
1701 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_SPDIFRX | RCC_PERIPHCLK_TIM |
1702 RCC_PERIPHCLK_CKPER;
1703
1704#if defined(I2C5)
1705 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C1235;
1706#else
1707 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C123;
1708#endif /*I2C5*/
1709#if defined(RCC_CDCCIP1R_SAI2ASEL)
1710 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2A;
1711#endif /* RCC_CDCCIP1R_SAI2ASEL */
1712#if defined(RCC_CDCCIP1R_SAI2BSEL)
1713 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2B;
1714#endif /* RCC_CDCCIP1R_SAI2BSEL */
1715#if defined(SAI3)
1716 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI23;
1717#endif /* SAI3 */
1718#if defined(SAI4)
1719 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4A;
1720 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4B;
1721#endif /* SAI4 */
1722#if defined(DFSDM2_BASE)
1723 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DFSDM2;
1724#endif /* DFSDM2 */
1725#if defined(QUADSPI)
1726 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_QSPI;
1727#endif /* QUADSPI */
1728#if defined(OCTOSPI1) || defined(OCTOSPI2)
1729 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_OSPI;
1730#endif /* OCTOSPI1 || OCTOSPI2 */
1731#if defined(HRTIM1)
1732 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1;
1733#endif /* HRTIM1 */
1734#if defined(LTDC)
1735 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LTDC;
1736#endif /* LTDC */
1737#if defined(DSI)
1738 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DSI;
1739#endif /* DSI */
1740
1741 /* Get the PLL3 Clock configuration -----------------------------------------------*/
1742 PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos);
1743 PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos) + 1U;
1744 PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos) + 1U;
1745 PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos) + 1U;
1746 PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos) + 1U;
1747 PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> RCC_PLLCFGR_PLL3RGE_Pos);
1748 PeriphClkInit->PLL3.PLL3VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3VCOSEL) >> RCC_PLLCFGR_PLL3VCOSEL_Pos);
1749
1750 /* Get the PLL2 Clock configuration -----------------------------------------------*/
1751 PeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> RCC_PLLCKSELR_DIVM2_Pos);
1752 PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos) + 1U;
1753 PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos) + 1U;
1754 PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos) + 1U;
1755 PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos) + 1U;
1756 PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> RCC_PLLCFGR_PLL2RGE_Pos);
1757 PeriphClkInit->PLL2.PLL2VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2VCOSEL) >> RCC_PLLCFGR_PLL2VCOSEL_Pos);
1758
1759 /* Get the USART1 configuration --------------------------------------------*/
1760 PeriphClkInit->Usart16ClockSelection = __HAL_RCC_GET_USART16_SOURCE();
1761 /* Get the USART2/3/4/5/7/8 clock source -----------------------------------*/
1762 PeriphClkInit->Usart234578ClockSelection = __HAL_RCC_GET_USART234578_SOURCE();
1763 /* Get the LPUART1 clock source --------------------------------------------*/
1764 PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
1765#if defined(I2C5)
1766 /* Get the I2C1/2/3/5 clock source -----------------------------------------*/
1767 PeriphClkInit->I2c1235ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
1768#else
1769 /* Get the I2C1/2/3 clock source -------------------------------------------*/
1770 PeriphClkInit->I2c123ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
1771#endif /*I2C5*/
1772 /* Get the LPTIM1 clock source ---------------------------------------------*/
1773 PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
1774 /* Get the LPTIM2 clock source ---------------------------------------------*/
1775 PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE();
1776 /* Get the LPTIM3/4/5 clock source -----------------------------------------*/
1777 PeriphClkInit->Lptim345ClockSelection = __HAL_RCC_GET_LPTIM345_SOURCE();
1778 /* Get the SAI1 clock source -----------------------------------------------*/
1779 PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
1780#if defined(SAI3)
1781 /* Get the SAI2/3 clock source ---------------------------------------------*/
1782 PeriphClkInit->Sai23ClockSelection = __HAL_RCC_GET_SAI23_SOURCE();
1783#endif /*SAI3*/
1784#if defined(RCC_CDCCIP1R_SAI2ASEL_0)
1785 /* Get the SAI2A clock source ---------------------------------------------*/
1786 PeriphClkInit->Sai2AClockSelection = __HAL_RCC_GET_SAI2A_SOURCE();
1787#endif /*SAI2A*/
1788#if defined(RCC_CDCCIP1R_SAI2BSEL_0)
1789 /* Get the SAI2B clock source ---------------------------------------------*/
1790 PeriphClkInit->Sai2BClockSelection = __HAL_RCC_GET_SAI2B_SOURCE();
1791#endif /*SAI2B*/
1792#if defined(SAI4)
1793 /* Get the SAI4A clock source ----------------------------------------------*/
1794 PeriphClkInit->Sai4AClockSelection = __HAL_RCC_GET_SAI4A_SOURCE();
1795 /* Get the SAI4B clock source ----------------------------------------------*/
1796 PeriphClkInit->Sai4BClockSelection = __HAL_RCC_GET_SAI4B_SOURCE();
1797#endif /*SAI4*/
1798 /* Get the RTC clock source ------------------------------------------------*/
1799 PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
1800 /* Get the USB clock source ------------------------------------------------*/
1801 PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
1802 /* Get the SDMMC clock source ----------------------------------------------*/
1803 PeriphClkInit->SdmmcClockSelection = __HAL_RCC_GET_SDMMC_SOURCE();
1804 /* Get the RNG clock source ------------------------------------------------*/
1805 PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE();
1806#if defined(HRTIM1)
1807 /* Get the HRTIM1 clock source ---------------------------------------------*/
1808 PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE();
1809#endif /* HRTIM1 */
1810 /* Get the ADC clock source ------------------------------------------------*/
1811 PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
1812 /* Get the SWPMI1 clock source ---------------------------------------------*/
1813 PeriphClkInit->Swpmi1ClockSelection = __HAL_RCC_GET_SWPMI1_SOURCE();
1814 /* Get the DFSDM1 clock source ---------------------------------------------*/
1815 PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();
1816#if defined(DFSDM2_BASE)
1817 /* Get the DFSDM2 clock source ---------------------------------------------*/
1818 PeriphClkInit->Dfsdm2ClockSelection = __HAL_RCC_GET_DFSDM2_SOURCE();
1819#endif /* DFSDM2 */
1820 /* Get the SPDIFRX clock source --------------------------------------------*/
1821 PeriphClkInit->SpdifrxClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();
1822 /* Get the SPI1/2/3 clock source -------------------------------------------*/
1823 PeriphClkInit->Spi123ClockSelection = __HAL_RCC_GET_SPI123_SOURCE();
1824 /* Get the SPI4/5 clock source ---------------------------------------------*/
1825 PeriphClkInit->Spi45ClockSelection = __HAL_RCC_GET_SPI45_SOURCE();
1826 /* Get the SPI6 clock source -----------------------------------------------*/
1827 PeriphClkInit->Spi6ClockSelection = __HAL_RCC_GET_SPI6_SOURCE();
1828 /* Get the FDCAN clock source ----------------------------------------------*/
1829 PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE();
1830 /* Get the CEC clock source ------------------------------------------------*/
1831 PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
1832 /* Get the FMC clock source ------------------------------------------------*/
1833 PeriphClkInit->FmcClockSelection = __HAL_RCC_GET_FMC_SOURCE();
1834#if defined(QUADSPI)
1835 /* Get the QSPI clock source -----------------------------------------------*/
1836 PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE();
1837#endif /* QUADSPI */
1838#if defined(OCTOSPI1) || defined(OCTOSPI2)
1839 /* Get the OSPI clock source -----------------------------------------------*/
1840 PeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE();
1841#endif /* OCTOSPI1 || OCTOSPI2 */
1842
1843#if defined(DSI)
1844 /* Get the DSI clock source ------------------------------------------------*/
1845 PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE();
1846#endif /*DSI*/
1847
1848 /* Get the CKPER clock source ----------------------------------------------*/
1849 PeriphClkInit->CkperClockSelection = __HAL_RCC_GET_CLKP_SOURCE();
1850
1851 /* Get the TIM Prescaler configuration -------------------------------------*/
1852 if ((RCC->CFGR & RCC_CFGR_TIMPRE) == 0U)
1853 {
1854 PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
1855 }
1856 else
1857 {
1858 PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
1859 }
1860}
1861
1862/**
1863 * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
1864 * @note Return 0 if peripheral clock identifier not managed by this API
1865 * @param PeriphClk: Peripheral clock identifier
1866 * This parameter can be one of the following values:
1867 * @arg RCC_PERIPHCLK_SAI1 : SAI1 peripheral clock
1868 * @arg RCC_PERIPHCLK_SAI23 : SAI2/3 peripheral clock (*)
1869 * @arg RCC_PERIPHCLK_SAI2A : SAI2A peripheral clock (*)
1870 * @arg RCC_PERIPHCLK_SAI2B : SAI2B peripheral clock (*)
1871 * @arg RCC_PERIPHCLK_SAI4A : SAI4A peripheral clock (*)
1872 * @arg RCC_PERIPHCLK_SAI4B : SAI4B peripheral clock (*)
1873 * @arg RCC_PERIPHCLK_SPI123: SPI1/2/3 peripheral clock
1874 * @arg RCC_PERIPHCLK_ADC : ADC peripheral clock
1875 * @arg RCC_PERIPHCLK_SDMMC : SDMMC peripheral clock
1876 * @arg RCC_PERIPHCLK_SPI6 : SPI6 peripheral clock
1877 * @retval Frequency in KHz
1878 *
1879 * (*) : Available on some STM32H7 lines only.
1880 */
1881uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)
1882{
1883 PLL1_ClocksTypeDef pll1_clocks;
1884 PLL2_ClocksTypeDef pll2_clocks;
1885 PLL3_ClocksTypeDef pll3_clocks;
1886
1887 /* This variable is used to store the clock frequency (value in Hz) */
1888 uint32_t frequency;
1889 /* This variable is used to store the SAI and CKP clock source */
1890 uint32_t saiclocksource;
1891 uint32_t ckpclocksource;
1892 uint32_t srcclk;
1893
1894 if (PeriphClk == RCC_PERIPHCLK_SAI1)
1895 {
1896
1897 saiclocksource = __HAL_RCC_GET_SAI1_SOURCE();
1898
1899 switch (saiclocksource)
1900 {
1901 case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */
1902 {
1903 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
1904 {
1905 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
1906 frequency = pll1_clocks.PLL1_Q_Frequency;
1907 }
1908 else
1909 {
1910 frequency = 0;
1911 }
1912 break;
1913 }
1914 case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */
1915 {
1916 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
1917 {
1918 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
1919 frequency = pll2_clocks.PLL2_P_Frequency;
1920 }
1921 else
1922 {
1923 frequency = 0;
1924 }
1925 break;
1926 }
1927
1928 case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */
1929 {
1930 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
1931 {
1932 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
1933 frequency = pll3_clocks.PLL3_P_Frequency;
1934 }
1935 else
1936 {
1937 frequency = 0;
1938 }
1939 break;
1940 }
1941
1942 case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/
1943 {
1944
1945 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
1946
1947 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
1948 {
1949 /* In Case the CKPER Source is HSI */
1950 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
1951 }
1952
1953 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
1954 {
1955 /* In Case the CKPER Source is CSI */
1956 frequency = CSI_VALUE;
1957 }
1958
1959 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
1960 {
1961 /* In Case the CKPER Source is HSE */
1962 frequency = HSE_VALUE;
1963 }
1964
1965 else
1966 {
1967 /* In Case the CKPER is disabled*/
1968 frequency = 0;
1969 }
1970
1971 break;
1972 }
1973
1974 case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */
1975 {
1976 frequency = EXTERNAL_CLOCK_VALUE;
1977 break;
1978 }
1979 default :
1980 {
1981 frequency = 0;
1982 break;
1983 }
1984 }
1985 }
1986
1987#if defined(SAI3)
1988 else if (PeriphClk == RCC_PERIPHCLK_SAI23)
1989 {
1990
1991 saiclocksource = __HAL_RCC_GET_SAI23_SOURCE();
1992
1993 switch (saiclocksource)
1994 {
1995 case RCC_SAI23CLKSOURCE_PLL: /* PLL1 is the clock source for SAI2/3 */
1996 {
1997 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
1998 {
1999 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2000 frequency = pll1_clocks.PLL1_Q_Frequency;
2001 }
2002 else
2003 {
2004 frequency = 0;
2005 }
2006 break;
2007 }
2008 case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */
2009 {
2010 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2011 {
2012 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2013 frequency = pll2_clocks.PLL2_P_Frequency;
2014 }
2015 else
2016 {
2017 frequency = 0;
2018 }
2019 break;
2020 }
2021
2022 case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */
2023 {
2024 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2025 {
2026 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2027 frequency = pll3_clocks.PLL3_P_Frequency;
2028 }
2029 else
2030 {
2031 frequency = 0;
2032 }
2033 break;
2034 }
2035
2036 case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */
2037 {
2038
2039 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
2040
2041 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
2042 {
2043 /* In Case the CKPER Source is HSI */
2044 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
2045 }
2046
2047 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
2048 {
2049 /* In Case the CKPER Source is CSI */
2050 frequency = CSI_VALUE;
2051 }
2052
2053 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
2054 {
2055 /* In Case the CKPER Source is HSE */
2056 frequency = HSE_VALUE;
2057 }
2058
2059 else
2060 {
2061 /* In Case the CKPER is disabled*/
2062 frequency = 0;
2063 }
2064
2065 break;
2066 }
2067
2068 case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */
2069 {
2070 frequency = EXTERNAL_CLOCK_VALUE;
2071 break;
2072 }
2073 default :
2074 {
2075 frequency = 0;
2076 break;
2077 }
2078 }
2079 }
2080#endif /* SAI3 */
2081
2082#if defined(RCC_CDCCIP1R_SAI2ASEL)
2083
2084 else if (PeriphClk == RCC_PERIPHCLK_SAI2A)
2085 {
2086 saiclocksource = __HAL_RCC_GET_SAI2A_SOURCE();
2087
2088 switch (saiclocksource)
2089 {
2090 case RCC_SAI2ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI2A */
2091 {
2092 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2093 {
2094 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2095 frequency = pll1_clocks.PLL1_Q_Frequency;
2096 }
2097 else
2098 {
2099 frequency = 0;
2100 }
2101 break;
2102 }
2103 case RCC_SAI2ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2A */
2104 {
2105 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2106 {
2107 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2108 frequency = pll2_clocks.PLL2_P_Frequency;
2109 }
2110 else
2111 {
2112 frequency = 0;
2113 }
2114 break;
2115 }
2116
2117 case RCC_SAI2ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2A */
2118 {
2119 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2120 {
2121 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2122 frequency = pll3_clocks.PLL3_P_Frequency;
2123 }
2124 else
2125 {
2126 frequency = 0;
2127 }
2128 break;
2129 }
2130
2131 case RCC_SAI2ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI2A */
2132 {
2133
2134 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
2135
2136 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
2137 {
2138 /* In Case the CKPER Source is HSI */
2139 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
2140 }
2141
2142 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
2143 {
2144 /* In Case the CKPER Source is CSI */
2145 frequency = CSI_VALUE;
2146 }
2147
2148 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
2149 {
2150 /* In Case the CKPER Source is HSE */
2151 frequency = HSE_VALUE;
2152 }
2153
2154 else
2155 {
2156 /* In Case the CKPER is disabled*/
2157 frequency = 0;
2158 }
2159
2160 break;
2161 }
2162
2163 case (RCC_SAI2ACLKSOURCE_PIN): /* External clock is the clock source for SAI2A */
2164 {
2165 frequency = EXTERNAL_CLOCK_VALUE;
2166 break;
2167 }
2168
2169 default :
2170 {
2171 frequency = 0;
2172 break;
2173 }
2174 }
2175
2176 }
2177#endif
2178
2179#if defined(RCC_CDCCIP1R_SAI2BSEL_0)
2180 else if (PeriphClk == RCC_PERIPHCLK_SAI2B)
2181 {
2182
2183 saiclocksource = __HAL_RCC_GET_SAI2B_SOURCE();
2184
2185 switch (saiclocksource)
2186 {
2187 case RCC_SAI2BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI2B */
2188 {
2189 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2190 {
2191 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2192 frequency = pll1_clocks.PLL1_Q_Frequency;
2193 }
2194 else
2195 {
2196 frequency = 0;
2197 }
2198 break;
2199 }
2200 case RCC_SAI2BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2B */
2201 {
2202 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2203 {
2204 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2205 frequency = pll2_clocks.PLL2_P_Frequency;
2206 }
2207 else
2208 {
2209 frequency = 0;
2210 }
2211 break;
2212 }
2213
2214 case RCC_SAI2BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2B */
2215 {
2216 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2217 {
2218 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2219 frequency = pll3_clocks.PLL3_P_Frequency;
2220 }
2221 else
2222 {
2223 frequency = 0;
2224 }
2225 break;
2226 }
2227
2228 case RCC_SAI2BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI2B*/
2229 {
2230
2231 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
2232
2233 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
2234 {
2235 /* In Case the CKPER Source is HSI */
2236 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
2237 }
2238
2239 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
2240 {
2241 /* In Case the CKPER Source is CSI */
2242 frequency = CSI_VALUE;
2243 }
2244
2245 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
2246 {
2247 /* In Case the CKPER Source is HSE */
2248 frequency = HSE_VALUE;
2249 }
2250
2251 else
2252 {
2253 /* In Case the CKPER is disabled*/
2254 frequency = 0;
2255 }
2256 break;
2257 }
2258
2259 case (RCC_SAI2BCLKSOURCE_PIN): /* External clock is the clock source for SAI2B */
2260 {
2261 frequency = EXTERNAL_CLOCK_VALUE;
2262 break;
2263 }
2264
2265 default :
2266 {
2267 frequency = 0;
2268 break;
2269 }
2270 }
2271 }
2272#endif
2273
2274#if defined(SAI4)
2275 else if (PeriphClk == RCC_PERIPHCLK_SAI4A)
2276 {
2277
2278 saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE();
2279
2280 switch (saiclocksource)
2281 {
2282 case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */
2283 {
2284 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2285 {
2286 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2287 frequency = pll1_clocks.PLL1_Q_Frequency;
2288 }
2289 else
2290 {
2291 frequency = 0;
2292 }
2293 break;
2294 }
2295 case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */
2296 {
2297 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2298 {
2299 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2300 frequency = pll2_clocks.PLL2_P_Frequency;
2301 }
2302 else
2303 {
2304 frequency = 0;
2305 }
2306 break;
2307 }
2308
2309 case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */
2310 {
2311 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2312 {
2313 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2314 frequency = pll3_clocks.PLL3_P_Frequency;
2315 }
2316 else
2317 {
2318 frequency = 0;
2319 }
2320 break;
2321 }
2322
2323 case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/
2324 {
2325
2326 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
2327
2328 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
2329 {
2330 /* In Case the CKPER Source is HSI */
2331 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
2332 }
2333
2334 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
2335 {
2336 /* In Case the CKPER Source is CSI */
2337 frequency = CSI_VALUE;
2338 }
2339
2340 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
2341 {
2342 /* In Case the CKPER Source is HSE */
2343 frequency = HSE_VALUE;
2344 }
2345
2346 else
2347 {
2348 /* In Case the CKPER is disabled*/
2349 frequency = 0;
2350 }
2351
2352 break;
2353 }
2354
2355 case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */
2356 {
2357 frequency = EXTERNAL_CLOCK_VALUE;
2358 break;
2359 }
2360
2361 default :
2362 {
2363 frequency = 0;
2364 break;
2365 }
2366 }
2367 }
2368
2369 else if (PeriphClk == RCC_PERIPHCLK_SAI4B)
2370 {
2371
2372 saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE();
2373
2374 switch (saiclocksource)
2375 {
2376 case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */
2377 {
2378 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2379 {
2380 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2381 frequency = pll1_clocks.PLL1_Q_Frequency;
2382 }
2383 else
2384 {
2385 frequency = 0;
2386 }
2387 break;
2388 }
2389 case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */
2390 {
2391 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2392 {
2393 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2394 frequency = pll2_clocks.PLL2_P_Frequency;
2395 }
2396 else
2397 {
2398 frequency = 0;
2399 }
2400 break;
2401 }
2402
2403 case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */
2404 {
2405 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2406 {
2407 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2408 frequency = pll3_clocks.PLL3_P_Frequency;
2409 }
2410 else
2411 {
2412 frequency = 0;
2413 }
2414 break;
2415 }
2416
2417 case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/
2418 {
2419
2420 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
2421
2422 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
2423 {
2424 /* In Case the CKPER Source is HSI */
2425 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
2426 }
2427
2428 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
2429 {
2430 /* In Case the CKPER Source is CSI */
2431 frequency = CSI_VALUE;
2432 }
2433
2434 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
2435 {
2436 /* In Case the CKPER Source is HSE */
2437 frequency = HSE_VALUE;
2438 }
2439
2440 else
2441 {
2442 /* In Case the CKPER is disabled*/
2443 frequency = 0;
2444 }
2445
2446 break;
2447 }
2448
2449 case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */
2450 {
2451 frequency = EXTERNAL_CLOCK_VALUE;
2452 break;
2453 }
2454
2455 default :
2456 {
2457 frequency = 0;
2458 break;
2459 }
2460 }
2461 }
2462#endif /*SAI4*/
2463 else if (PeriphClk == RCC_PERIPHCLK_SPI123)
2464 {
2465 /* Get SPI1/2/3 clock source */
2466 srcclk = __HAL_RCC_GET_SPI123_SOURCE();
2467
2468 switch (srcclk)
2469 {
2470 case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */
2471 {
2472 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2473 {
2474 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2475 frequency = pll1_clocks.PLL1_Q_Frequency;
2476 }
2477 else
2478 {
2479 frequency = 0;
2480 }
2481 break;
2482 }
2483 case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */
2484 {
2485 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2486 {
2487 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2488 frequency = pll2_clocks.PLL2_P_Frequency;
2489 }
2490 else
2491 {
2492 frequency = 0;
2493 }
2494 break;
2495 }
2496
2497 case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */
2498 {
2499 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2500 {
2501 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2502 frequency = pll3_clocks.PLL3_P_Frequency;
2503 }
2504 else
2505 {
2506 frequency = 0;
2507 }
2508 break;
2509 }
2510
2511 case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */
2512 {
2513
2514 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
2515
2516 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
2517 {
2518 /* In Case the CKPER Source is HSI */
2519 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
2520 }
2521
2522 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
2523 {
2524 /* In Case the CKPER Source is CSI */
2525 frequency = CSI_VALUE;
2526 }
2527
2528 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
2529 {
2530 /* In Case the CKPER Source is HSE */
2531 frequency = HSE_VALUE;
2532 }
2533
2534 else
2535 {
2536 /* In Case the CKPER is disabled*/
2537 frequency = 0;
2538 }
2539
2540 break;
2541 }
2542
2543 case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */
2544 {
2545 frequency = EXTERNAL_CLOCK_VALUE;
2546 break;
2547 }
2548 default :
2549 {
2550 frequency = 0;
2551 break;
2552 }
2553 }
2554 }
2555 else if (PeriphClk == RCC_PERIPHCLK_SPI45)
2556 {
2557 /* Get SPI45 clock source */
2558 srcclk = __HAL_RCC_GET_SPI45_SOURCE();
2559 switch (srcclk)
2560 {
2561 case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 is the clock source for SPI4/5 */
2562 {
2563 frequency = HAL_RCC_GetPCLK1Freq();
2564 break;
2565 }
2566 case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI45 */
2567 {
2568 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2569 {
2570 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2571 frequency = pll2_clocks.PLL2_Q_Frequency;
2572 }
2573 else
2574 {
2575 frequency = 0;
2576 }
2577 break;
2578 }
2579 case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI45 */
2580 {
2581 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2582 {
2583 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2584 frequency = pll3_clocks.PLL3_Q_Frequency;
2585 }
2586 else
2587 {
2588 frequency = 0;
2589 }
2590 break;
2591 }
2592 case RCC_SPI45CLKSOURCE_HSI: /* HSI is the clock source for SPI45 */
2593 {
2594 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
2595 {
2596 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
2597 }
2598 else
2599 {
2600 frequency = 0;
2601 }
2602 break;
2603 }
2604 case RCC_SPI45CLKSOURCE_CSI: /* CSI is the clock source for SPI45 */
2605 {
2606 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY))
2607 {
2608 frequency = CSI_VALUE;
2609 }
2610 else
2611 {
2612 frequency = 0;
2613 }
2614 break;
2615 }
2616 case RCC_SPI45CLKSOURCE_HSE: /* HSE is the clock source for SPI45 */
2617 {
2618 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
2619 {
2620 frequency = HSE_VALUE;
2621 }
2622 else
2623 {
2624 frequency = 0;
2625 }
2626 break;
2627 }
2628 default :
2629 {
2630 frequency = 0;
2631 break;
2632 }
2633 }
2634 }
2635 else if (PeriphClk == RCC_PERIPHCLK_ADC)
2636 {
2637 /* Get ADC clock source */
2638 srcclk = __HAL_RCC_GET_ADC_SOURCE();
2639
2640 switch (srcclk)
2641 {
2642 case RCC_ADCCLKSOURCE_PLL2:
2643 {
2644 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2645 {
2646 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2647 frequency = pll2_clocks.PLL2_P_Frequency;
2648 }
2649 else
2650 {
2651 frequency = 0;
2652 }
2653 break;
2654 }
2655 case RCC_ADCCLKSOURCE_PLL3:
2656 {
2657 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2658 {
2659 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2660 frequency = pll3_clocks.PLL3_R_Frequency;
2661 }
2662 else
2663 {
2664 frequency = 0;
2665 }
2666 break;
2667 }
2668
2669 case RCC_ADCCLKSOURCE_CLKP:
2670 {
2671
2672 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
2673
2674 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
2675 {
2676 /* In Case the CKPER Source is HSI */
2677 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
2678 }
2679
2680 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
2681 {
2682 /* In Case the CKPER Source is CSI */
2683 frequency = CSI_VALUE;
2684 }
2685
2686 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
2687 {
2688 /* In Case the CKPER Source is HSE */
2689 frequency = HSE_VALUE;
2690 }
2691
2692 else
2693 {
2694 /* In Case the CKPER is disabled*/
2695 frequency = 0;
2696 }
2697
2698 break;
2699 }
2700
2701 default :
2702 {
2703 frequency = 0;
2704 break;
2705 }
2706 }
2707 }
2708 else if (PeriphClk == RCC_PERIPHCLK_SDMMC)
2709 {
2710 /* Get SDMMC clock source */
2711 srcclk = __HAL_RCC_GET_SDMMC_SOURCE();
2712
2713 switch (srcclk)
2714 {
2715 case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */
2716 {
2717 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2718 {
2719 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2720 frequency = pll1_clocks.PLL1_Q_Frequency;
2721 }
2722 else
2723 {
2724 frequency = 0;
2725 }
2726 break;
2727 }
2728 case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */
2729 {
2730 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2731 {
2732 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2733 frequency = pll2_clocks.PLL2_R_Frequency;
2734 }
2735 else
2736 {
2737 frequency = 0;
2738 }
2739 break;
2740 }
2741
2742 default :
2743 {
2744 frequency = 0;
2745 break;
2746 }
2747 }
2748 }
2749 else if (PeriphClk == RCC_PERIPHCLK_SPI6)
2750 {
2751 /* Get SPI6 clock source */
2752 srcclk = __HAL_RCC_GET_SPI6_SOURCE();
2753
2754 switch (srcclk)
2755 {
2756 case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */
2757 {
2758 frequency = HAL_RCCEx_GetD3PCLK1Freq();
2759 break;
2760 }
2761 case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */
2762 {
2763 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2764 {
2765 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2766 frequency = pll2_clocks.PLL2_Q_Frequency;
2767 }
2768 else
2769 {
2770 frequency = 0;
2771 }
2772 break;
2773 }
2774 case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */
2775 {
2776 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
2777 {
2778 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2779 frequency = pll3_clocks.PLL3_Q_Frequency;
2780 }
2781 else
2782 {
2783 frequency = 0;
2784 }
2785 break;
2786 }
2787 case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */
2788 {
2789 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
2790 {
2791 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
2792 }
2793 else
2794 {
2795 frequency = 0;
2796 }
2797 break;
2798 }
2799 case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */
2800 {
2801 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY))
2802 {
2803 frequency = CSI_VALUE;
2804 }
2805 else
2806 {
2807 frequency = 0;
2808 }
2809 break;
2810 }
2811 case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */
2812 {
2813 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
2814 {
2815 frequency = HSE_VALUE;
2816 }
2817 else
2818 {
2819 frequency = 0;
2820 }
2821 break;
2822 }
2823#if defined(RCC_SPI6CLKSOURCE_PIN)
2824 case RCC_SPI6CLKSOURCE_PIN: /* External clock is the clock source for SPI6 */
2825 {
2826 frequency = EXTERNAL_CLOCK_VALUE;
2827 break;
2828 }
2829#endif /* RCC_SPI6CLKSOURCE_PIN */
2830 default :
2831 {
2832 frequency = 0;
2833 break;
2834 }
2835 }
2836 }
2837 else if (PeriphClk == RCC_PERIPHCLK_FDCAN)
2838 {
2839 /* Get FDCAN clock source */
2840 srcclk = __HAL_RCC_GET_FDCAN_SOURCE();
2841
2842 switch (srcclk)
2843 {
2844 case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */
2845 {
2846 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
2847 {
2848 frequency = HSE_VALUE;
2849 }
2850 else
2851 {
2852 frequency = 0;
2853 }
2854 break;
2855 }
2856 case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */
2857 {
2858 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2859 {
2860 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2861 frequency = pll1_clocks.PLL1_Q_Frequency;
2862 }
2863 else
2864 {
2865 frequency = 0;
2866 }
2867 break;
2868 }
2869 case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */
2870 {
2871 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2872 {
2873 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2874 frequency = pll2_clocks.PLL2_Q_Frequency;
2875 }
2876 else
2877 {
2878 frequency = 0;
2879 }
2880 break;
2881 }
2882 default :
2883 {
2884 frequency = 0;
2885 break;
2886 }
2887 }
2888 }
2889 else
2890 {
2891 frequency = 0;
2892 }
2893
2894 return frequency;
2895}
2896
2897
2898/**
2899 * @brief Returns the D1PCLK1 frequency
2900 * @note Each time D1PCLK1 changes, this function must be called to update the
2901 * right D1PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
2902 * @retval D1PCLK1 frequency
2903 */
2904uint32_t HAL_RCCEx_GetD1PCLK1Freq(void)
2905{
2906#if defined(RCC_D1CFGR_D1PPRE)
2907 /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/
2908 return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR_D1PPRE_Pos] & 0x1FU));
2909#else
2910 /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/
2911 return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos] & 0x1FU));
2912#endif
2913}
2914
2915/**
2916 * @brief Returns the D3PCLK1 frequency
2917 * @note Each time D3PCLK1 changes, this function must be called to update the
2918 * right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
2919 * @retval D3PCLK1 frequency
2920 */
2921uint32_t HAL_RCCEx_GetD3PCLK1Freq(void)
2922{
2923#if defined(RCC_D3CFGR_D3PPRE)
2924 /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
2925 return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU));
2926#else
2927 /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
2928 return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU));
2929#endif
2930}
2931/**
2932* @brief Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency
2933 * @note The PLL2 clock frequencies computed by this function is not the real
2934 * frequency in the chip. It is calculated based on the predefined
2935 * constant and the selected clock source:
2936 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
2937 * @note This function can be used by the user application to compute the
2938 * baud-rate for the communication peripherals or configure other parameters.
2939 *
2940 * @note Each time PLL2CLK changes, this function must be called to update the
2941 * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
2942 * @param PLL2_Clocks structure.
2943 * @retval None
2944 */
2945void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks)
2946{
2947 uint32_t pllsource, pll2m, pll2fracen, hsivalue;
2948 float_t fracn2, pll2vco;
2949
2950 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N
2951 PLL2xCLK = PLL2_VCO / PLL2x
2952 */
2953 pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
2954 pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12);
2955 pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos;
2956 fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3));
2957
2958 if (pll2m != 0U)
2959 {
2960 switch (pllsource)
2961 {
2962
2963 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
2964
2965 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
2966 {
2967 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
2968 pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
2969 }
2970 else
2971 {
2972 pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
2973 }
2974 break;
2975
2976 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */
2977 pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
2978 break;
2979
2980 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
2981 pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
2982 break;
2983
2984 default:
2985 pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
2986 break;
2987 }
2988 PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ;
2989 PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ;
2990 PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ;
2991 }
2992 else
2993 {
2994 PLL2_Clocks->PLL2_P_Frequency = 0U;
2995 PLL2_Clocks->PLL2_Q_Frequency = 0U;
2996 PLL2_Clocks->PLL2_R_Frequency = 0U;
2997 }
2998}
2999
3000/**
3001* @brief Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency
3002 * @note The PLL3 clock frequencies computed by this function is not the real
3003 * frequency in the chip. It is calculated based on the predefined
3004 * constant and the selected clock source:
3005 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
3006 * @note This function can be used by the user application to compute the
3007 * baud-rate for the communication peripherals or configure other parameters.
3008 *
3009 * @note Each time PLL3CLK changes, this function must be called to update the
3010 * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
3011 * @param PLL3_Clocks structure.
3012 * @retval None
3013 */
3014void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks)
3015{
3016 uint32_t pllsource, pll3m, pll3fracen, hsivalue;
3017 float_t fracn3, pll3vco;
3018
3019 /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N
3020 PLL3xCLK = PLL3_VCO / PLLxR
3021 */
3022 pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
3023 pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ;
3024 pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos;
3025 fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3));
3026
3027 if (pll3m != 0U)
3028 {
3029 switch (pllsource)
3030 {
3031 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
3032
3033 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
3034 {
3035 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
3036 pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
3037 }
3038 else
3039 {
3040 pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
3041 }
3042 break;
3043 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */
3044 pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
3045 break;
3046
3047 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
3048 pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
3049 break;
3050
3051 default:
3052 pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
3053 break;
3054 }
3055 PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ;
3056 PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ;
3057 PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ;
3058 }
3059 else
3060 {
3061 PLL3_Clocks->PLL3_P_Frequency = 0U;
3062 PLL3_Clocks->PLL3_Q_Frequency = 0U;
3063 PLL3_Clocks->PLL3_R_Frequency = 0U;
3064 }
3065
3066}
3067
3068/**
3069* @brief Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency
3070 * @note The PLL1 clock frequencies computed by this function is not the real
3071 * frequency in the chip. It is calculated based on the predefined
3072 * constant and the selected clock source:
3073 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
3074 * @note This function can be used by the user application to compute the
3075 * baud-rate for the communication peripherals or configure other parameters.
3076 *
3077 * @note Each time PLL1CLK changes, this function must be called to update the
3078 * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
3079 * @param PLL1_Clocks structure.
3080 * @retval None
3081 */
3082void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks)
3083{
3084 uint32_t pllsource, pll1m, pll1fracen, hsivalue;
3085 float_t fracn1, pll1vco;
3086
3087 pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
3088 pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4);
3089 pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
3090 fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
3091
3092 if (pll1m != 0U)
3093 {
3094 switch (pllsource)
3095 {
3096
3097 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
3098
3099 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
3100 {
3101 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
3102 pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
3103 }
3104 else
3105 {
3106 pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
3107 }
3108 break;
3109 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */
3110 pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
3111 break;
3112
3113 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
3114 pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
3115 break;
3116
3117 default:
3118 pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
3119 break;
3120 }
3121
3122 PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (float_t)1)) ;
3123 PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ;
3124 PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ;
3125 }
3126 else
3127 {
3128 PLL1_Clocks->PLL1_P_Frequency = 0U;
3129 PLL1_Clocks->PLL1_Q_Frequency = 0U;
3130 PLL1_Clocks->PLL1_R_Frequency = 0U;
3131 }
3132
3133}
3134
3135/**
3136 * @brief Returns the main System frequency
3137 * @note Each time System clock changes, this function must be called to update the
3138 * right core clock value. Otherwise, any configuration based on this function will be incorrect.
3139 * @note The SystemCoreClock CMSIS variable is used to store System current Core Clock Frequency
3140 * and updated within this function
3141 * @retval HCLK frequency
3142 */
3143uint32_t HAL_RCCEx_GetD1SysClockFreq(void)
3144{
3145 uint32_t common_system_clock;
3146
3147#if defined(RCC_D1CFGR_D1CPRE)
3148 common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
3149#else
3150 common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
3151#endif
3152
3153 /* Update the SystemD2Clock global variable */
3154#if defined(RCC_D1CFGR_HPRE)
3155 SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
3156#else
3157 SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
3158#endif
3159
3160#if defined(DUAL_CORE) && defined(CORE_CM4)
3161 SystemCoreClock = SystemD2Clock;
3162#else
3163 SystemCoreClock = common_system_clock;
3164#endif /* DUAL_CORE && CORE_CM4 */
3165
3166 return common_system_clock;
3167}
3168/**
3169 * @}
3170 */
3171
3172/** @defgroup RCCEx_Exported_Functions_Group2 Extended System Control functions
3173 * @brief Extended Peripheral Control functions
3174 * @{
3175 */
3176/**
3177 * @brief Enables the LSE Clock Security System.
3178 * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
3179 * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
3180 * clock with HAL_RCCEx_PeriphCLKConfig().
3181 * @retval None
3182 */
3183void HAL_RCCEx_EnableLSECSS(void)
3184{
3185 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
3186}
3187
3188/**
3189 * @brief Disables the LSE Clock Security System.
3190 * @note LSE Clock Security System can only be disabled after a LSE failure detection.
3191 * @retval None
3192 */
3193void HAL_RCCEx_DisableLSECSS(void)
3194{
3195 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
3196 /* Disable LSE CSS IT if any */
3197 __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
3198}
3199
3200/**
3201 * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
3202 * @note LSE Clock Security System Interrupt is mapped on EXTI line 18
3203 * @retval None
3204 */
3205void HAL_RCCEx_EnableLSECSS_IT(void)
3206{
3207 /* Enable LSE CSS */
3208 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
3209
3210 /* Enable LSE CSS IT */
3211 __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
3212
3213 /* Enable IT on EXTI Line 18 */
3214#if defined(DUAL_CORE) && defined(CORE_CM4)
3215 __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT();
3216#else
3217 __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
3218#endif /* DUAL_CORE && CORE_CM4 */
3219 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
3220}
3221
3222/**
3223 * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock
3224 * @param WakeUpClk: Wakeup clock
3225 * This parameter can be one of the following values:
3226 * @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI oscillator selection
3227 * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection
3228 * @note This function shall not be called after the Clock Security System on HSE has been
3229 * enabled.
3230 * @retval None
3231 */
3232void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
3233{
3234 assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
3235
3236 __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
3237}
3238
3239/**
3240 * @brief Configure the oscillator Kernel clock source for wakeup from Stop
3241 * @param WakeUpClk: Kernel Wakeup clock
3242 * This parameter can be one of the following values:
3243 * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection
3244 * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection
3245 * @retval None
3246 */
3247void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
3248{
3249 assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk));
3250
3251 __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk);
3252}
3253
3254#if defined(DUAL_CORE)
3255/**
3256 * @brief Enable COREx boot independently of CMx_B option byte value
3257 * @param RCC_BootCx: Boot Core to be enabled
3258 * This parameter can be one of the following values:
3259 * @arg RCC_BOOT_C1: CM7 core selection
3260 * @arg RCC_BOOT_C2: CM4 core selection
3261 * @note This bit can be set by software but is cleared by hardware after a system reset or STANDBY
3262 *
3263 * @retval None
3264 */
3265void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx)
3266{
3267 assert_param(IS_RCC_BOOT_CORE(RCC_BootCx));
3268 SET_BIT(RCC->GCR, RCC_BootCx) ;
3269}
3270
3271#endif /*DUAL_CORE*/
3272
3273#if defined(DUAL_CORE)
3274/**
3275 * @brief Configure WWDGx to generate a system reset not only CPUx reset(default) when a time-out occurs
3276 * @param RCC_WWDGx: WWDGx to be configured
3277 * This parameter can be one of the following values:
3278 * @arg RCC_WWDG1: WWDG1 generates system reset
3279 * @arg RCC_WWDG2: WWDG2 generates system reset
3280 * @note This bit can be set by software but is cleared by hardware during a system reset
3281 *
3282 * @retval None
3283 */
3284void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
3285{
3286 assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx));
3287 SET_BIT(RCC->GCR, RCC_WWDGx) ;
3288}
3289
3290#else
3291#if defined(RCC_GCR_WW1RSC)
3292/**
3293 * @brief Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out occurs
3294 * @param RCC_WWDGx: WWDGx to be configured
3295 * This parameter can be one of the following values:
3296 * @arg RCC_WWDG1: WWDG1 generates system reset
3297 * @note This bit can be set by software but is cleared by hardware during a system reset
3298 *
3299 * @retval None
3300 */
3301void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
3302{
3303 assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx));
3304 SET_BIT(RCC->GCR, RCC_WWDGx) ;
3305}
3306#endif
3307#endif /*DUAL_CORE*/
3308
3309/**
3310 * @}
3311 */
3312
3313/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
3314 * @brief Extended Clock Recovery System Control functions
3315 *
3316@verbatim
3317 ===============================================================================
3318 ##### Extended Clock Recovery System Control functions #####
3319 ===============================================================================
3320 [..]
3321 For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
3322
3323 (#) In System clock config, HSI48 needs to be enabled
3324
3325 (#) Enable CRS clock in IP MSP init which will use CRS functions
3326
3327 (#) Call CRS functions as follows:
3328 (##) Prepare synchronization configuration necessary for HSI48 calibration
3329 (+++) Default values can be set for frequency Error Measurement (reload and error limit)
3330 and also HSI48 oscillator smooth trimming.
3331 (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
3332 directly reload value with target and synchronization frequencies values
3333 (##) Call function HAL_RCCEx_CRSConfig which
3334 (+++) Resets CRS registers to their default values.
3335 (+++) Configures CRS registers with synchronization configuration
3336 (+++) Enables automatic calibration and frequency error counter feature
3337 Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
3338 periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
3339 provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
3340 precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
3341 should be used as SYNC signal.
3342
3343 (##) A polling function is provided to wait for complete synchronization
3344 (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
3345 (+++) According to CRS status, user can decide to adjust again the calibration or continue
3346 application if synchronization is OK
3347
3348 (#) User can retrieve information related to synchronization in calling function
3349 HAL_RCCEx_CRSGetSynchronizationInfo()
3350
3351 (#) Regarding synchronization status and synchronization information, user can try a new calibration
3352 in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
3353 Note: When the SYNC event is detected during the down-counting phase (before reaching the zero value),
3354 it means that the actual frequency is lower than the target (and so, that the TRIM value should be
3355 incremented), while when it is detected during the up-counting phase it means that the actual frequency
3356 is higher (and that the TRIM value should be decremented).
3357
3358 (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
3359 through CRS Handler (CRS_IRQn/CRS_IRQHandler)
3360 (++) Call function HAL_RCCEx_CRSConfig()
3361 (++) Enable CRS_IRQn (thanks to NVIC functions)
3362 (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
3363 (++) Implement CRS status management in the following user callbacks called from
3364 HAL_RCCEx_CRS_IRQHandler():
3365 (+++) HAL_RCCEx_CRS_SyncOkCallback()
3366 (+++) HAL_RCCEx_CRS_SyncWarnCallback()
3367 (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
3368 (+++) HAL_RCCEx_CRS_ErrorCallback()
3369
3370 (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
3371 This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
3372
3373@endverbatim
3374 * @{
3375 */
3376
3377/**
3378 * @brief Start automatic synchronization for polling mode
3379 * @param pInit Pointer on RCC_CRSInitTypeDef structure
3380 * @retval None
3381 */
3382void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *pInit)
3383{
3384 uint32_t value;
3385
3386 /* Check the parameters */
3387 assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
3388 assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
3389 assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
3390 assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
3391 assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
3392 assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
3393
3394 /* CONFIGURATION */
3395
3396 /* Before configuration, reset CRS registers to their default values*/
3397 __HAL_RCC_CRS_FORCE_RESET();
3398 __HAL_RCC_CRS_RELEASE_RESET();
3399
3400 /* Set the SYNCDIV[2:0] bits according to Pre-scaler value */
3401 /* Set the SYNCSRC[1:0] bits according to Source value */
3402 /* Set the SYNCSPOL bit according to Polarity value */
3403 if ((HAL_GetREVID() <= REV_ID_Y) && (pInit->Source == RCC_CRS_SYNC_SOURCE_USB2))
3404 {
3405 /* Use Rev.Y value of USB2 */
3406 value = (pInit->Prescaler | RCC_CRS_SYNC_SOURCE_PIN | pInit->Polarity);
3407 }
3408 else
3409 {
3410 value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
3411 }
3412 /* Set the RELOAD[15:0] bits according to ReloadValue value */
3413 value |= pInit->ReloadValue;
3414 /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
3415 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
3416 WRITE_REG(CRS->CFGR, value);
3417
3418 /* Adjust HSI48 oscillator smooth trimming */
3419 /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
3420 MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
3421
3422 /* START AUTOMATIC SYNCHRONIZATION*/
3423
3424 /* Enable Automatic trimming & Frequency error counter */
3425 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
3426}
3427
3428/**
3429 * @brief Generate the software synchronization event
3430 * @retval None
3431 */
3432void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
3433{
3434 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
3435}
3436
3437/**
3438 * @brief Return synchronization info
3439 * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
3440 * @retval None
3441 */
3442void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
3443{
3444 /* Check the parameter */
3445 assert_param(pSynchroInfo != (void *)NULL);
3446
3447 /* Get the reload value */
3448 pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
3449
3450 /* Get HSI48 oscillator smooth trimming */
3451 pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
3452
3453 /* Get Frequency error capture */
3454 pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
3455
3456 /* Get Frequency error direction */
3457 pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
3458}
3459
3460/**
3461* @brief Wait for CRS Synchronization status.
3462* @param Timeout Duration of the time-out
3463* @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
3464* frequency.
3465* @note If Time-out set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
3466* @retval Combination of Synchronization status
3467* This parameter can be a combination of the following values:
3468* @arg @ref RCC_CRS_TIMEOUT
3469* @arg @ref RCC_CRS_SYNCOK
3470* @arg @ref RCC_CRS_SYNCWARN
3471* @arg @ref RCC_CRS_SYNCERR
3472* @arg @ref RCC_CRS_SYNCMISS
3473* @arg @ref RCC_CRS_TRIMOVF
3474*/
3475uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
3476{
3477 uint32_t crsstatus = RCC_CRS_NONE;
3478 uint32_t tickstart;
3479
3480 /* Get time-out */
3481 tickstart = HAL_GetTick();
3482
3483 /* Wait for CRS flag or time-out detection */
3484 do
3485 {
3486 if (Timeout != HAL_MAX_DELAY)
3487 {
3488 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3489 {
3490 crsstatus = RCC_CRS_TIMEOUT;
3491 }
3492 }
3493 /* Check CRS SYNCOK flag */
3494 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
3495 {
3496 /* CRS SYNC event OK */
3497 crsstatus |= RCC_CRS_SYNCOK;
3498
3499 /* Clear CRS SYNC event OK bit */
3500 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
3501 }
3502
3503 /* Check CRS SYNCWARN flag */
3504 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
3505 {
3506 /* CRS SYNC warning */
3507 crsstatus |= RCC_CRS_SYNCWARN;
3508
3509 /* Clear CRS SYNCWARN bit */
3510 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
3511 }
3512
3513 /* Check CRS TRIM overflow flag */
3514 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
3515 {
3516 /* CRS SYNC Error */
3517 crsstatus |= RCC_CRS_TRIMOVF;
3518
3519 /* Clear CRS Error bit */
3520 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
3521 }
3522
3523 /* Check CRS Error flag */
3524 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
3525 {
3526 /* CRS SYNC Error */
3527 crsstatus |= RCC_CRS_SYNCERR;
3528
3529 /* Clear CRS Error bit */
3530 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
3531 }
3532
3533 /* Check CRS SYNC Missed flag */
3534 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
3535 {
3536 /* CRS SYNC Missed */
3537 crsstatus |= RCC_CRS_SYNCMISS;
3538
3539 /* Clear CRS SYNC Missed bit */
3540 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
3541 }
3542
3543 /* Check CRS Expected SYNC flag */
3544 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
3545 {
3546 /* frequency error counter reached a zero value */
3547 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
3548 }
3549 }
3550 while (RCC_CRS_NONE == crsstatus);
3551
3552 return crsstatus;
3553}
3554
3555/**
3556 * @brief Handle the Clock Recovery System interrupt request.
3557 * @retval None
3558 */
3559void HAL_RCCEx_CRS_IRQHandler(void)
3560{
3561 uint32_t crserror = RCC_CRS_NONE;
3562 /* Get current IT flags and IT sources values */
3563 uint32_t itflags = READ_REG(CRS->ISR);
3564 uint32_t itsources = READ_REG(CRS->CR);
3565
3566 /* Check CRS SYNCOK flag */
3567 if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
3568 {
3569 /* Clear CRS SYNC event OK flag */
3570 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
3571
3572 /* user callback */
3573 HAL_RCCEx_CRS_SyncOkCallback();
3574 }
3575 /* Check CRS SYNCWARN flag */
3576 else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
3577 {
3578 /* Clear CRS SYNCWARN flag */
3579 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
3580
3581 /* user callback */
3582 HAL_RCCEx_CRS_SyncWarnCallback();
3583 }
3584 /* Check CRS Expected SYNC flag */
3585 else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
3586 {
3587 /* frequency error counter reached a zero value */
3588 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
3589
3590 /* user callback */
3591 HAL_RCCEx_CRS_ExpectedSyncCallback();
3592 }
3593 /* Check CRS Error flags */
3594 else
3595 {
3596 if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
3597 {
3598 if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
3599 {
3600 crserror |= RCC_CRS_SYNCERR;
3601 }
3602 if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
3603 {
3604 crserror |= RCC_CRS_SYNCMISS;
3605 }
3606 if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
3607 {
3608 crserror |= RCC_CRS_TRIMOVF;
3609 }
3610
3611 /* Clear CRS Error flags */
3612 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
3613
3614 /* user error callback */
3615 HAL_RCCEx_CRS_ErrorCallback(crserror);
3616 }
3617 }
3618}
3619
3620/**
3621 * @brief RCCEx Clock Recovery System SYNCOK interrupt callback.
3622 * @retval none
3623 */
3624__weak void HAL_RCCEx_CRS_SyncOkCallback(void)
3625{
3626 /* NOTE : This function should not be modified, when the callback is needed,
3627 the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
3628 */
3629}
3630
3631/**
3632 * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback.
3633 * @retval none
3634 */
3635__weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
3636{
3637 /* NOTE : This function should not be modified, when the callback is needed,
3638 the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
3639 */
3640}
3641
3642/**
3643 * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback.
3644 * @retval none
3645 */
3646__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
3647{
3648 /* NOTE : This function should not be modified, when the callback is needed,
3649 the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
3650 */
3651}
3652
3653/**
3654 * @brief RCCEx Clock Recovery System Error interrupt callback.
3655 * @param Error Combination of Error status.
3656 * This parameter can be a combination of the following values:
3657 * @arg @ref RCC_CRS_SYNCERR
3658 * @arg @ref RCC_CRS_SYNCMISS
3659 * @arg @ref RCC_CRS_TRIMOVF
3660 * @retval none
3661 */
3662__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
3663{
3664 /* Prevent unused argument(s) compilation warning */
3665 UNUSED(Error);
3666
3667 /* NOTE : This function should not be modified, when the callback is needed,
3668 the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
3669 */
3670}
3671
3672
3673/**
3674 * @}
3675 */
3676
3677/**
3678 * @}
3679 */
3680
3681/** @defgroup RCCEx_Private_functions RCCEx Private Functions
3682 * @{
3683 */
3684/**
3685 * @brief Configure the PLL2 VCI,VCO ranges, multiplication and division factors and enable it
3686 * @param pll2: Pointer to an RCC_PLL2InitTypeDef structure that
3687 * contains the configuration parameters as well as VCI, VCO clock ranges.
3688 * @param Divider divider parameter to be updated
3689 * @note PLL2 is temporary disabled to apply new parameters
3690 *
3691 * @retval HAL status
3692 */
3693static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2, uint32_t Divider)
3694{
3695
3696 uint32_t tickstart;
3697 HAL_StatusTypeDef status = HAL_OK;
3698 assert_param(IS_RCC_PLL2M_VALUE(pll2->PLL2M));
3699 assert_param(IS_RCC_PLL2N_VALUE(pll2->PLL2N));
3700 assert_param(IS_RCC_PLL2P_VALUE(pll2->PLL2P));
3701 assert_param(IS_RCC_PLL2R_VALUE(pll2->PLL2R));
3702 assert_param(IS_RCC_PLL2Q_VALUE(pll2->PLL2Q));
3703 assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE));
3704 assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL));
3705 assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN));
3706
3707 /* Check that PLL2 OSC clock source is already set */
3708 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
3709 {
3710 return HAL_ERROR;
3711 }
3712
3713
3714 else
3715 {
3716 /* Disable PLL2. */
3717 __HAL_RCC_PLL2_DISABLE();
3718
3719 /* Get Start Tick*/
3720 tickstart = HAL_GetTick();
3721
3722 /* Wait till PLL is disabled */
3723 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
3724 {
3725 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
3726 {
3727 return HAL_TIMEOUT;
3728 }
3729 }
3730
3731 /* Configure PLL2 multiplication and division factors. */
3732 __HAL_RCC_PLL2_CONFIG(pll2->PLL2M,
3733 pll2->PLL2N,
3734 pll2->PLL2P,
3735 pll2->PLL2Q,
3736 pll2->PLL2R);
3737
3738 /* Select PLL2 input reference frequency range: VCI */
3739 __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ;
3740
3741 /* Select PLL2 output frequency range : VCO */
3742 __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ;
3743
3744 /* Disable PLL2FRACN . */
3745 __HAL_RCC_PLL2FRACN_DISABLE();
3746
3747 /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */
3748 __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);
3749
3750 /* Enable PLL2FRACN . */
3751 __HAL_RCC_PLL2FRACN_ENABLE();
3752
3753 /* Enable the PLL2 clock output */
3754 if (Divider == DIVIDER_P_UPDATE)
3755 {
3756 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
3757 }
3758 else if (Divider == DIVIDER_Q_UPDATE)
3759 {
3760 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
3761 }
3762 else
3763 {
3764 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR);
3765 }
3766
3767 /* Enable PLL2. */
3768 __HAL_RCC_PLL2_ENABLE();
3769
3770 /* Get Start Tick*/
3771 tickstart = HAL_GetTick();
3772
3773 /* Wait till PLL2 is ready */
3774 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
3775 {
3776 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
3777 {
3778 return HAL_TIMEOUT;
3779 }
3780 }
3781
3782 }
3783
3784
3785 return status;
3786}
3787
3788
3789/**
3790 * @brief Configure the PLL3 VCI,VCO ranges, multiplication and division factors and enable it
3791 * @param pll3: Pointer to an RCC_PLL3InitTypeDef structure that
3792 * contains the configuration parameters as well as VCI, VCO clock ranges.
3793 * @param Divider divider parameter to be updated
3794 * @note PLL3 is temporary disabled to apply new parameters
3795 *
3796 * @retval HAL status
3797 */
3798static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3, uint32_t Divider)
3799{
3800 uint32_t tickstart;
3801 HAL_StatusTypeDef status = HAL_OK;
3802 assert_param(IS_RCC_PLL3M_VALUE(pll3->PLL3M));
3803 assert_param(IS_RCC_PLL3N_VALUE(pll3->PLL3N));
3804 assert_param(IS_RCC_PLL3P_VALUE(pll3->PLL3P));
3805 assert_param(IS_RCC_PLL3R_VALUE(pll3->PLL3R));
3806 assert_param(IS_RCC_PLL3Q_VALUE(pll3->PLL3Q));
3807 assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE));
3808 assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL));
3809 assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN));
3810
3811 /* Check that PLL3 OSC clock source is already set */
3812 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
3813 {
3814 return HAL_ERROR;
3815 }
3816
3817
3818 else
3819 {
3820 /* Disable PLL3. */
3821 __HAL_RCC_PLL3_DISABLE();
3822
3823 /* Get Start Tick*/
3824 tickstart = HAL_GetTick();
3825 /* Wait till PLL3 is ready */
3826 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
3827 {
3828 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
3829 {
3830 return HAL_TIMEOUT;
3831 }
3832 }
3833
3834 /* Configure the PLL3 multiplication and division factors. */
3835 __HAL_RCC_PLL3_CONFIG(pll3->PLL3M,
3836 pll3->PLL3N,
3837 pll3->PLL3P,
3838 pll3->PLL3Q,
3839 pll3->PLL3R);
3840
3841 /* Select PLL3 input reference frequency range: VCI */
3842 __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ;
3843
3844 /* Select PLL3 output frequency range : VCO */
3845 __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ;
3846
3847 /* Disable PLL3FRACN . */
3848 __HAL_RCC_PLL3FRACN_DISABLE();
3849
3850 /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */
3851 __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);
3852
3853 /* Enable PLL3FRACN . */
3854 __HAL_RCC_PLL3FRACN_ENABLE();
3855
3856 /* Enable the PLL3 clock output */
3857 if (Divider == DIVIDER_P_UPDATE)
3858 {
3859 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
3860 }
3861 else if (Divider == DIVIDER_Q_UPDATE)
3862 {
3863 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
3864 }
3865 else
3866 {
3867 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
3868 }
3869
3870 /* Enable PLL3. */
3871 __HAL_RCC_PLL3_ENABLE();
3872
3873 /* Get Start Tick*/
3874 tickstart = HAL_GetTick();
3875
3876 /* Wait till PLL3 is ready */
3877 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
3878 {
3879 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
3880 {
3881 return HAL_TIMEOUT;
3882 }
3883 }
3884
3885 }
3886
3887
3888 return status;
3889}
3890
3891/**
3892 * @brief Handle the RCC LSE Clock Security System interrupt request.
3893 * @retval None
3894 */
3895void HAL_RCCEx_LSECSS_IRQHandler(void)
3896{
3897 /* Check RCC LSE CSSF flag */
3898 if (__HAL_RCC_GET_IT(RCC_IT_LSECSS))
3899 {
3900
3901 /* Clear RCC LSE CSS pending bit */
3902 __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
3903
3904 /* RCC LSE Clock Security System interrupt user callback */
3905 HAL_RCCEx_LSECSS_Callback();
3906
3907 }
3908}
3909
3910/**
3911 * @brief RCCEx LSE Clock Security System interrupt callback.
3912 * @retval none
3913 */
3914__weak void HAL_RCCEx_LSECSS_Callback(void)
3915{
3916 /* NOTE : This function should not be modified, when the callback is needed,
3917 the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
3918 */
3919}
3920
3921
3922
3923/**
3924 * @}
3925 */
3926
3927#endif /* HAL_RCC_MODULE_ENABLED */
3928/**
3929 * @}
3930 */
3931
3932/**
3933 * @}
3934 */
3935
CLEAR_BIT
#define CLEAR_BIT(REG, BIT)
Definition stm32h7xx.h:209
SET_BIT
#define SET_BIT(REG, BIT)
Definition stm32h7xx.h:207
WRITE_REG
#define WRITE_REG(REG, VAL)
Definition stm32h7xx.h:215
MODIFY_REG
#define MODIFY_REG(REG, CLEARMASK, SETMASK)
Definition stm32h7xx.h:219
READ_BIT
#define READ_BIT(REG, BIT)
Definition stm32h7xx.h:211
READ_REG
#define READ_REG(REG)
Definition stm32h7xx.h:217
HAL_GetREVID
uint32_t HAL_GetREVID(void)
Returns the device revision identifier.
Definition stm32h7xx_hal.c:466
HAL_GetTick
uint32_t HAL_GetTick(void)
Provides a tick value in millisecond.
Definition stm32h7xx_hal.c:338
RCC_PLL3DIVR_N3_Pos
#define RCC_PLL3DIVR_N3_Pos
Definition stm32h723xx.h:15012
RCC_PLLCFGR_PLL2RGE_Pos
#define RCC_PLLCFGR_PLL2RGE_Pos
Definition stm32h723xx.h:14920
RCC_PLL2DIVR_Q2
#define RCC_PLL2DIVR_Q2
Definition stm32h723xx.h:15001
PWR_CR1_DBP
#define PWR_CR1_DBP
Disable Back-up domain Protection.
Definition stm32h723xx.h:14208
RCC_CR_CSIRDY
#define RCC_CR_CSIRDY
The Internal RC 4MHz oscillator clock ready.
Definition stm32h723xx.h:14474
RCC_D1CFGR_D1PPRE_Pos
#define RCC_D1CFGR_D1PPRE_Pos
Definition stm32h723xx.h:14728
RCC_D1CFGR_D1PPRE
#define RCC_D1CFGR_D1PPRE
D1PRE[2:0] bits (APB3 prescaler).
Definition stm32h723xx.h:14730
RCC_PLL3DIVR_P3
#define RCC_PLL3DIVR_P3
Definition stm32h723xx.h:15017
RCC_PLL1DIVR_N1
#define RCC_PLL1DIVR_N1
Definition stm32h723xx.h:14976
RCC_PLL2DIVR_N2_Pos
#define RCC_PLL2DIVR_N2_Pos
Definition stm32h723xx.h:14993
RCC_CR_PLL2RDY
#define RCC_CR_PLL2RDY
System PLL2 clock ready.
Definition stm32h723xx.h:14517
RCC_PLL1DIVR_P1
#define RCC_PLL1DIVR_P1
Definition stm32h723xx.h:14979
RCC_D1CFGR_D1CPRE
#define RCC_D1CFGR_D1CPRE
D1CPRE[2:0] bits (Domain 1 Core prescaler).
Definition stm32h723xx.h:14751
RCC_CR_PLL1RDY
#define RCC_CR_PLL1RDY
System PLL1 clock ready.
Definition stm32h723xx.h:14511
RCC_PLLCFGR_PLL2FRACEN
#define RCC_PLLCFGR_PLL2FRACEN
Definition stm32h723xx.h:14916
RCC_CR_PLL3RDY
#define RCC_CR_PLL3RDY
System PLL3 clock ready.
Definition stm32h723xx.h:14523
RCC_PLLCFGR_PLL2RGE
#define RCC_PLLCFGR_PLL2RGE
Definition stm32h723xx.h:14922
CRS_ISR_FECAP_Pos
#define CRS_ISR_FECAP_Pos
Definition stm32h723xx.h:5884
CRS_CR_SWSYNC
#define CRS_CR_SWSYNC
Generate software SYNC event.
Definition stm32h723xx.h:5829
RCC_PLLCKSELR_PLLSRC
#define RCC_PLLCKSELR_PLLSRC
Definition stm32h723xx.h:14855
RCC_PLLCKSELR_DIVM2
#define RCC_PLLCKSELR_DIVM2
Definition stm32h723xx.h:14880
RCC_PLL2DIVR_N2
#define RCC_PLL2DIVR_N2
Definition stm32h723xx.h:14995
CRS_CFGR_FELIM_Pos
#define CRS_CFGR_FELIM_Pos
Definition stm32h723xx.h:5838
RCC_PLLCFGR_PLL2FRACEN_Pos
#define RCC_PLLCFGR_PLL2FRACEN_Pos
Definition stm32h723xx.h:14914
RCC_PLL3FRACR_FRACN3
#define RCC_PLL3FRACR_FRACN3
Definition stm32h723xx.h:15028
RCC_PLLCKSELR_DIVM1
#define RCC_PLLCKSELR_DIVM1
Definition stm32h723xx.h:14870
RCC_CFGR_TIMPRE
#define RCC_CFGR_TIMPRE
0x00008000
Definition stm32h723xx.h:14657
RCC_PLLCKSELR_DIVM3
#define RCC_PLLCKSELR_DIVM3
Definition stm32h723xx.h:14890
RCC_PLL3DIVR_R3
#define RCC_PLL3DIVR_R3
Definition stm32h723xx.h:15023
RCC_BDCR_LSECSSON
#define RCC_BDCR_LSECSSON
Definition stm32h723xx.h:15314
CRS_CR_TRIM
#define CRS_CR_TRIM
HSI48 oscillator smooth trimming.
Definition stm32h723xx.h:5832
RCC_PLLCKSELR_DIVM2_Pos
#define RCC_PLLCKSELR_DIVM2_Pos
Definition stm32h723xx.h:14878
RCC_PLL2FRACR_FRACN2
#define RCC_PLL2FRACR_FRACN2
Definition stm32h723xx.h:15009
RCC_PLLCFGR_PLL2VCOSEL_Pos
#define RCC_PLLCFGR_PLL2VCOSEL_Pos
Definition stm32h723xx.h:14917
RCC_PLLCFGR_PLL3VCOSEL
#define RCC_PLLCFGR_PLL3VCOSEL
Definition stm32h723xx.h:14933
CRS_CFGR_RELOAD
#define CRS_CFGR_RELOAD
Counter reload value.
Definition stm32h723xx.h:5837
RCC_PLL1DIVR_R1
#define RCC_PLL1DIVR_R1
Definition stm32h723xx.h:14985
CRS_CR_TRIM_Pos
#define CRS_CR_TRIM_Pos
Definition stm32h723xx.h:5830
RCC_PLL3DIVR_Q3_Pos
#define RCC_PLL3DIVR_Q3_Pos
Definition stm32h723xx.h:15018
RCC_CR_HSERDY
#define RCC_CR_HSERDY
External High Speed clock ready.
Definition stm32h723xx.h:14497
RCC_PLL3DIVR_P3_Pos
#define RCC_PLL3DIVR_P3_Pos
Definition stm32h723xx.h:15015
RCC_D3CFGR_D3PPRE
#define RCC_D3CFGR_D3PPRE
D3PPRE1[2:0] bits (APB4 prescaler).
Definition stm32h723xx.h:14832
RCC_PLLCFGR_PLL3RGE_Pos
#define RCC_PLLCFGR_PLL3RGE_Pos
Definition stm32h723xx.h:14934
CRS_ISR_FEDIR
#define CRS_ISR_FEDIR
Frequency error direction.
Definition stm32h723xx.h:5883
RCC_D1CFGR_HPRE
#define RCC_D1CFGR_HPRE
HPRE[3:0] bits (AHB3 prescaler).
Definition stm32h723xx.h:14694
RCC_PLL3DIVR_Q3
#define RCC_PLL3DIVR_Q3
Definition stm32h723xx.h:15020
RCC_PLL2DIVR_Q2_Pos
#define RCC_PLL2DIVR_Q2_Pos
Definition stm32h723xx.h:14999
RCC_PLLCFGR_PLL3VCOSEL_Pos
#define RCC_PLLCFGR_PLL3VCOSEL_Pos
Definition stm32h723xx.h:14931
RCC_CR_HSIRDY
#define RCC_CR_HSIRDY
Internal High Speed clock ready flag.
Definition stm32h723xx.h:14457
CRS_ICR_SYNCOKC
#define CRS_ICR_SYNCOKC
SYNC event OK clear flag.
Definition stm32h723xx.h:5891
RCC_PLL3DIVR_N3
#define RCC_PLL3DIVR_N3
Definition stm32h723xx.h:15014
RCC_PLLCKSELR_DIVM3_Pos
#define RCC_PLLCKSELR_DIVM3_Pos
Definition stm32h723xx.h:14888
RCC_PLL2DIVR_R2
#define RCC_PLL2DIVR_R2
Definition stm32h723xx.h:15004
CRS_ICR_SYNCWARNC
#define CRS_ICR_SYNCWARNC
SYNC warning clear flag.
Definition stm32h723xx.h:5894
RCC_D3CFGR_D3PPRE_Pos
#define RCC_D3CFGR_D3PPRE_Pos
< D3PPRE configuration
Definition stm32h723xx.h:14830
RCC_PLLCFGR_PLL3FRACEN
#define RCC_PLLCFGR_PLL3FRACEN
Definition stm32h723xx.h:14930
RCC_BDCR_RTCSEL
#define RCC_BDCR_RTCSEL
Definition stm32h723xx.h:15321
RCC_PLLCFGR_PLL3RGE
#define RCC_PLLCFGR_PLL3RGE
Definition stm32h723xx.h:14936
RCC_PLL1DIVR_Q1
#define RCC_PLL1DIVR_Q1
Definition stm32h723xx.h:14982
RCC_PLLCFGR_PLL1FRACEN
#define RCC_PLLCFGR_PLL1FRACEN
Definition stm32h723xx.h:14902
CRS_CR_CEN
#define CRS_CR_CEN
Frequency error counter enable.
Definition stm32h723xx.h:5823
RCC_PLL2DIVR_R2_Pos
#define RCC_PLL2DIVR_R2_Pos
Definition stm32h723xx.h:15002
CRS_ICR_ESYNCC
#define CRS_ICR_ESYNCC
Expected SYNC clear flag.
Definition stm32h723xx.h:5900
RCC_PLLCFGR_PLL3FRACEN_Pos
#define RCC_PLLCFGR_PLL3FRACEN_Pos
Definition stm32h723xx.h:14928
RCC_PLL3DIVR_R3_Pos
#define RCC_PLL3DIVR_R3_Pos
Definition stm32h723xx.h:15021
CRS_ICR_ERRC
#define CRS_ICR_ERRC
Error clear flag.
Definition stm32h723xx.h:5897
RCC_PLL1FRACR_FRACN1
#define RCC_PLL1FRACR_FRACN1
Definition stm32h723xx.h:14990
RCC_D1CFGR_D1CPRE_Pos
#define RCC_D1CFGR_D1CPRE_Pos
Definition stm32h723xx.h:14749
CRS_ISR_FECAP
#define CRS_ISR_FECAP
Frequency error capture.
Definition stm32h723xx.h:5886
RCC_PLL2DIVR_P2_Pos
#define RCC_PLL2DIVR_P2_Pos
Definition stm32h723xx.h:14996
RCC_D1CFGR_HPRE_Pos
#define RCC_D1CFGR_HPRE_Pos
< D1HPRE configuration
Definition stm32h723xx.h:14692
CRS_CR_AUTOTRIMEN
#define CRS_CR_AUTOTRIMEN
Automatic trimming enable.
Definition stm32h723xx.h:5826
RCC_PLL2DIVR_P2
#define RCC_PLL2DIVR_P2
Definition stm32h723xx.h:14998
RCC_PLLCFGR_PLL2VCOSEL
#define RCC_PLLCFGR_PLL2VCOSEL
Definition stm32h723xx.h:14919
PWR
#define PWR
Definition stm32h723xx.h:2457
RCC
#define RCC
Definition stm32h723xx.h:2511
CRS
#define CRS
Definition stm32h723xx.h:2441
RCC_ADCCLKSOURCE_CLKP
#define RCC_ADCCLKSOURCE_CLKP
Definition stm32h7xx_hal_rcc_ex.h:1481
RCC_ADCCLKSOURCE_PLL2
#define RCC_ADCCLKSOURCE_PLL2
Definition stm32h7xx_hal_rcc_ex.h:1479
RCC_ADCCLKSOURCE_PLL3
#define RCC_ADCCLKSOURCE_PLL3
Definition stm32h7xx_hal_rcc_ex.h:1480
RCC_CLKPSOURCE_CSI
#define RCC_CLKPSOURCE_CSI
Definition stm32h7xx_hal_rcc_ex.h:1576
RCC_CLKPSOURCE_HSI
#define RCC_CLKPSOURCE_HSI
Definition stm32h7xx_hal_rcc_ex.h:1575
RCC_CLKPSOURCE_HSE
#define RCC_CLKPSOURCE_HSE
Definition stm32h7xx_hal_rcc_ex.h:1577
RCC_CRS_FLAG_ESYNC
#define RCC_CRS_FLAG_ESYNC
Expected SYNC flag.
Definition stm32h7xx_hal_rcc_ex.h:1746
RCC_CRS_FLAG_SYNCWARN
#define RCC_CRS_FLAG_SYNCWARN
SYNC warning flag.
Definition stm32h7xx_hal_rcc_ex.h:1744
RCC_CRS_FLAG_SYNCOK
#define RCC_CRS_FLAG_SYNCOK
SYNC event OK flag.
Definition stm32h7xx_hal_rcc_ex.h:1743
RCC_CRS_FLAG_TRIMOVF
#define RCC_CRS_FLAG_TRIMOVF
Trimming overflow or underflow.
Definition stm32h7xx_hal_rcc_ex.h:1749
RCC_CRS_FLAG_SYNCMISS
#define RCC_CRS_FLAG_SYNCMISS
SYNC missed.
Definition stm32h7xx_hal_rcc_ex.h:1748
RCC_CRS_FLAG_ERR
#define RCC_CRS_FLAG_ERR
Error flag.
Definition stm32h7xx_hal_rcc_ex.h:1745
RCC_CRS_FLAG_SYNCERR
#define RCC_CRS_FLAG_SYNCERR
SYNC error.
Definition stm32h7xx_hal_rcc_ex.h:1747
RCC_CRS_IT_ERR
#define RCC_CRS_IT_ERR
Error.
Definition stm32h7xx_hal_rcc_ex.h:1730
RCC_CRS_IT_SYNCOK
#define RCC_CRS_IT_SYNCOK
SYNC event OK.
Definition stm32h7xx_hal_rcc_ex.h:1728
RCC_CRS_IT_SYNCWARN
#define RCC_CRS_IT_SYNCWARN
SYNC warning.
Definition stm32h7xx_hal_rcc_ex.h:1729
RCC_CRS_IT_ESYNC
#define RCC_CRS_IT_ESYNC
Expected SYNC.
Definition stm32h7xx_hal_rcc_ex.h:1731
RCC_CRS_SYNCWARN
#define RCC_CRS_SYNCWARN
Definition stm32h7xx_hal_rcc_ex.h:1644
RCC_CRS_SYNCERR
#define RCC_CRS_SYNCERR
Definition stm32h7xx_hal_rcc_ex.h:1645
RCC_CRS_NONE
#define RCC_CRS_NONE
Definition stm32h7xx_hal_rcc_ex.h:1641
RCC_CRS_TRIMOVF
#define RCC_CRS_TRIMOVF
Definition stm32h7xx_hal_rcc_ex.h:1647
RCC_CRS_SYNCOK
#define RCC_CRS_SYNCOK
Definition stm32h7xx_hal_rcc_ex.h:1643
RCC_CRS_TIMEOUT
#define RCC_CRS_TIMEOUT
Definition stm32h7xx_hal_rcc_ex.h:1642
RCC_CRS_SYNCMISS
#define RCC_CRS_SYNCMISS
Definition stm32h7xx_hal_rcc_ex.h:1646
RCC_CRS_SYNC_SOURCE_USB2
#define RCC_CRS_SYNC_SOURCE_USB2
Synchro Signal source USB2 SOF.
Definition stm32h7xx_hal_rcc_ex.h:1658
RCC_CRS_SYNC_SOURCE_PIN
#define RCC_CRS_SYNC_SOURCE_PIN
Synchro Signal source external pin, Available on STM32H7 Rev.B and above devices only.
Definition stm32h7xx_hal_rcc_ex.h:1655
HAL_RCCEx_PeriphCLKConfig
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
HAL_RCCEx_GetD3PCLK1Freq
uint32_t HAL_RCCEx_GetD3PCLK1Freq(void)
HAL_RCCEx_GetPeriphCLKConfig
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
HAL_RCCEx_GetD1PCLK1Freq
uint32_t HAL_RCCEx_GetD1PCLK1Freq(void)
HAL_RCCEx_GetPLL3ClockFreq
void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks)
HAL_RCCEx_GetPLL1ClockFreq
void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks)
HAL_RCCEx_GetPeriphCLKFreq
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)
HAL_RCCEx_GetD1SysClockFreq
uint32_t HAL_RCCEx_GetD1SysClockFreq(void)
HAL_RCCEx_GetPLL2ClockFreq
void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks)
HAL_RCCEx_KerWakeUpStopCLKConfig
void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
HAL_RCCEx_LSECSS_Callback
void HAL_RCCEx_LSECSS_Callback(void)
HAL_RCCEx_EnableLSECSS
void HAL_RCCEx_EnableLSECSS(void)
HAL_RCCEx_LSECSS_IRQHandler
void HAL_RCCEx_LSECSS_IRQHandler(void)
HAL_RCCEx_EnableLSECSS_IT
void HAL_RCCEx_EnableLSECSS_IT(void)
HAL_RCCEx_WakeUpStopCLKConfig
void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
HAL_RCCEx_DisableLSECSS
void HAL_RCCEx_DisableLSECSS(void)
HAL_RCCEx_CRS_SyncWarnCallback
void HAL_RCCEx_CRS_SyncWarnCallback(void)
HAL_RCCEx_CRS_IRQHandler
void HAL_RCCEx_CRS_IRQHandler(void)
HAL_RCCEx_CRS_ExpectedSyncCallback
void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
HAL_RCCEx_CRS_ErrorCallback
void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
HAL_RCCEx_CRSWaitSynchronization
uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
HAL_RCCEx_CRSSoftwareSynchronizationGenerate
void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
HAL_RCCEx_CRSGetSynchronizationInfo
void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
HAL_RCCEx_CRS_SyncOkCallback
void HAL_RCCEx_CRS_SyncOkCallback(void)
HAL_RCCEx_CRSConfig
void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *pInit)
__HAL_RCC_ADC_CONFIG
#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__)
Macro to configure the ADC clock.
Definition stm32h7xx_hal_rcc_ex.h:3121
__HAL_RCC_SAI1_CONFIG
#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__)
Macro to Configure the SAI1 clock source.
Definition stm32h7xx_hal_rcc_ex.h:2025
__HAL_RCC_SPI6_CONFIG
#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__)
Macro to Configure the SPI6 clock source.
Definition stm32h7xx_hal_rcc_ex.h:3506
__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE
#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()
Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
Definition stm32h7xx_hal_rcc_ex.h:3678
__HAL_RCC_FMC_CONFIG
#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__)
macro to configure the FMC clock source.
Definition stm32h7xx_hal_rcc_ex.h:3066
__HAL_RCC_GET_LPUART1_SOURCE
#define __HAL_RCC_GET_LPUART1_SOURCE()
macro to get the LPUART1 clock source.
Definition stm32h7xx_hal_rcc_ex.h:2801
__HAL_RCC_PLL2_CONFIG
#define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__, __PLL2R__)
Macro to configures the PLL2 multiplication and division factors.
Definition stm32h7xx_hal_rcc_ex.h:1836
__HAL_RCC_I2C123_CONFIG
#define __HAL_RCC_I2C123_CONFIG
Definition stm32h7xx_hal_rcc_ex.h:2281
__HAL_RCC_USB_CONFIG
#define __HAL_RCC_USB_CONFIG(__USBCLKSource__)
Macro to configure the USB clock (USBCLK).
Definition stm32h7xx_hal_rcc_ex.h:3094
__HAL_RCC_PLL2_DISABLE
#define __HAL_RCC_PLL2_DISABLE()
Definition stm32h7xx_hal_rcc_ex.h:1773
__HAL_RCC_PLL2FRACN_ENABLE
#define __HAL_RCC_PLL2FRACN_ENABLE()
Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO.
Definition stm32h7xx_hal_rcc_ex.h:1800
__HAL_RCC_LPUART1_CONFIG
#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__)
macro to configure the LPUART1 clock (LPUART1CLK).
Definition stm32h7xx_hal_rcc_ex.h:2785
__HAL_RCC_GET_SPI123_SOURCE
#define __HAL_RCC_GET_SPI123_SOURCE()
Macro to get the SPI1/2/3 clock source.
Definition stm32h7xx_hal_rcc_ex.h:3321
__HAL_RCC_TIMCLKPRESCALER
#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__)
Macro to configure the Timers clocks prescalers.
Definition stm32h7xx_hal_rcc_ex.h:3606
__HAL_RCC_GET_USB_SOURCE
#define __HAL_RCC_GET_USB_SOURCE()
Macro to get the USB clock source.
Definition stm32h7xx_hal_rcc_ex.h:3107
__HAL_RCC_GET_USART234578_SOURCE
#define __HAL_RCC_GET_USART234578_SOURCE()
macro to get the USART2/3/4/5/7/8 clock source.
Definition stm32h7xx_hal_rcc_ex.h:2523
__HAL_RCC_GET_ADC_SOURCE
#define __HAL_RCC_GET_ADC_SOURCE()
Macro to get the ADC clock source.
Definition stm32h7xx_hal_rcc_ex.h:3134
__HAL_RCC_PLL2FRACN_DISABLE
#define __HAL_RCC_PLL2FRACN_DISABLE()
Definition stm32h7xx_hal_rcc_ex.h:1802
__HAL_RCC_PLL3FRACN_ENABLE
#define __HAL_RCC_PLL3FRACN_ENABLE()
Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO.
Definition stm32h7xx_hal_rcc_ex.h:1902
__HAL_RCC_PLL3FRACN_CONFIG
#define __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__)
Macro to configures PLL3 clock Fractional Part of The Multiplication Factor.
Definition stm32h7xx_hal_rcc_ex.h:1982
__HAL_RCC_GET_SWPMI1_SOURCE
#define __HAL_RCC_GET_SWPMI1_SOURCE()
Macro to get the SWPMI1 clock source.
Definition stm32h7xx_hal_rcc_ex.h:3159
__HAL_RCC_LPTIM1_CONFIG
#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__)
macro to configure the LPTIM1 clock source.
Definition stm32h7xx_hal_rcc_ex.h:2819
__HAL_RCC_PLL3CLKOUT_ENABLE
#define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__)
Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK).
Definition stm32h7xx_hal_rcc_ex.h:1922
__HAL_RCC_GET_FMC_SOURCE
#define __HAL_RCC_GET_FMC_SOURCE()
macro to get the FMC clock source.
Definition stm32h7xx_hal_rcc_ex.h:3080
__HAL_RCC_PLL3FRACN_DISABLE
#define __HAL_RCC_PLL3FRACN_DISABLE()
Definition stm32h7xx_hal_rcc_ex.h:1904
__HAL_RCC_PLL3_VCIRANGE
#define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__)
Macro to select the PLL3 reference frequency range.
Definition stm32h7xx_hal_rcc_ex.h:1993
__HAL_RCC_PLL2_VCORANGE
#define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__)
Macro to select the PLL2 reference frequency range.
Definition stm32h7xx_hal_rcc_ex.h:1885
__HAL_RCC_GET_DFSDM1_SOURCE
#define __HAL_RCC_GET_DFSDM1_SOURCE()
Macro to get the DFSDM1 clock source.
Definition stm32h7xx_hal_rcc_ex.h:3184
__HAL_RCC_GET_CLKP_SOURCE
#define __HAL_RCC_GET_CLKP_SOURCE()
Macro to get the Oscillator clock for peripheral source.
Definition stm32h7xx_hal_rcc_ex.h:3257
__HAL_RCC_USART234578_CONFIG
#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__)
macro to configure the USART234578 clock (USART234578CLK).
Definition stm32h7xx_hal_rcc_ex.h:2507
__HAL_RCC_GET_LPTIM345_SOURCE
#define __HAL_RCC_GET_LPTIM345_SOURCE()
macro to get the LPTIM3/4/5 clock source.
Definition stm32h7xx_hal_rcc_ex.h:2902
__HAL_RCC_SPDIFRX_CONFIG
#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__)
Macro to Configure the SPDIFRX clock source.
Definition stm32h7xx_hal_rcc_ex.h:2058
__HAL_RCC_SDMMC_CONFIG
#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__)
Macro to configure the SDMMC clock.
Definition stm32h7xx_hal_rcc_ex.h:3536
__HAL_RCC_DFSDM1_CONFIG
#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__)
Macro to configure the DFSDM1 clock.
Definition stm32h7xx_hal_rcc_ex.h:3172
__HAL_RCC_GET_CEC_SOURCE
#define __HAL_RCC_GET_CEC_SOURCE()
macro to get the CEC clock source.
Definition stm32h7xx_hal_rcc_ex.h:3230
__HAL_RCC_CEC_CONFIG
#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__)
macro to configure the CEC clock (CECCLK).
Definition stm32h7xx_hal_rcc_ex.h:3217
__HAL_RCC_PLL3_VCORANGE
#define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__)
Macro to select the PLL3 reference frequency range.
Definition stm32h7xx_hal_rcc_ex.h:2007
__HAL_RCC_GET_LPTIM2_SOURCE
#define __HAL_RCC_GET_LPTIM2_SOURCE()
macro to get the LPTIM2 clock source.
Definition stm32h7xx_hal_rcc_ex.h:2869
__HAL_RCC_PLL2_VCIRANGE
#define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__)
Macro to select the PLL2 reference frequency range.
Definition stm32h7xx_hal_rcc_ex.h:1871
__HAL_RCC_SPI123_CONFIG
#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__)
Macro to Configure the SPI1/2/3 clock source.
Definition stm32h7xx_hal_rcc_ex.h:3306
__HAL_RCC_GET_SPI6_SOURCE
#define __HAL_RCC_GET_SPI6_SOURCE()
Macro to get the SPI6 clock source.
Definition stm32h7xx_hal_rcc_ex.h:3523
__HAL_RCC_GET_SAI1_SOURCE
#define __HAL_RCC_GET_SAI1_SOURCE()
Macro to get the SAI1 clock source.
Definition stm32h7xx_hal_rcc_ex.h:2040
__HAL_RCC_PLL3_DISABLE
#define __HAL_RCC_PLL3_DISABLE()
Definition stm32h7xx_hal_rcc_ex.h:1895
__HAL_RCC_CLKP_CONFIG
#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__)
Macro to configure the CLKP : Oscillator clock for peripheral.
Definition stm32h7xx_hal_rcc_ex.h:3244
__HAL_RCC_GET_I2C1_SOURCE
#define __HAL_RCC_GET_I2C1_SOURCE
macro to get the I2C1 clock source.
Definition stm32h7xx_hal_rcc_ex.h:2328
__HAL_RCC_LPTIM2_CONFIG
#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__)
macro to configure the LPTIM2 clock source.
Definition stm32h7xx_hal_rcc_ex.h:2853
__HAL_RCC_LPTIM345_CONFIG
#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__)
macro to configure the LPTIM3/4/5 clock source.
Definition stm32h7xx_hal_rcc_ex.h:2886
__HAL_RCC_SWPMI1_CONFIG
#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__)
Macro to configure the SWPMI1 clock.
Definition stm32h7xx_hal_rcc_ex.h:3147
__HAL_RCC_PLL2FRACN_CONFIG
#define __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__)
Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor.
Definition stm32h7xx_hal_rcc_ex.h:1859
__HAL_RCC_PLL3_CONFIG
#define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__, __PLL3R__)
Macro to configures the PLL3 multiplication and division factors.
Definition stm32h7xx_hal_rcc_ex.h:1958
__HAL_RCC_I2C4_CONFIG
#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__)
macro to configure the I2C4 clock (I2C4CLK).
Definition stm32h7xx_hal_rcc_ex.h:2400
__HAL_RCC_PLL3_ENABLE
#define __HAL_RCC_PLL3_ENABLE()
Macros to enable or disable the main PLL3.
Definition stm32h7xx_hal_rcc_ex.h:1894
__HAL_RCC_PLL2_ENABLE
#define __HAL_RCC_PLL2_ENABLE()
Macros to enable or disable PLL2.
Definition stm32h7xx_hal_rcc_ex.h:1772
__HAL_RCC_USART16_CONFIG
#define __HAL_RCC_USART16_CONFIG
Definition stm32h7xx_hal_rcc_ex.h:2466
__HAL_RCC_GET_SDMMC_SOURCE
#define __HAL_RCC_GET_SDMMC_SOURCE()
Macro to get the SDMMC clock.
Definition stm32h7xx_hal_rcc_ex.h:3545
__HAL_RCC_GET_SPDIFRX_SOURCE
#define __HAL_RCC_GET_SPDIFRX_SOURCE()
Macro to get the SPDIFRX clock source.
Definition stm32h7xx_hal_rcc_ex.h:2069
__HAL_RCC_CRS_GET_FLAG
#define __HAL_RCC_CRS_GET_FLAG(__FLAG__)
Check whether the specified CRS flag is set or not.
Definition stm32h7xx_hal_rcc_ex.h:3810
__HAL_RCC_GET_USART16_SOURCE
#define __HAL_RCC_GET_USART16_SOURCE
Definition stm32h7xx_hal_rcc_ex.h:2489
__HAL_RCC_GET_LPTIM1_SOURCE
#define __HAL_RCC_GET_LPTIM1_SOURCE()
macro to get the LPTIM1 clock source.
Definition stm32h7xx_hal_rcc_ex.h:2835
__HAL_RCC_GET_RNG_SOURCE
#define __HAL_RCC_GET_RNG_SOURCE()
macro to get the RNG clock source.
Definition stm32h7xx_hal_rcc_ex.h:3575
__HAL_RCC_PLL2CLKOUT_ENABLE
#define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__)
Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK).
Definition stm32h7xx_hal_rcc_ex.h:1791
__HAL_RCC_RNG_CONFIG
#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__)
macro to configure the RNG clock (RNGCLK).
Definition stm32h7xx_hal_rcc_ex.h:3561
__HAL_RCC_SPI45_CONFIG
#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__)
Macro to Configure the SPI4/5 clock source.
Definition stm32h7xx_hal_rcc_ex.h:3413
__HAL_RCC_CRS_CLEAR_FLAG
#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)
Definition stm32h7xx_hal_rcc_ex.h:3830
__HAL_RCC_LSECSS_EXTI_ENABLE_IT
#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()
Enable the RCC LSE CSS Extended Interrupt Line.
Definition stm32h7xx_hal_rcc_ex.h:3614
__HAL_RCC_I2C1235_CONFIG
#define __HAL_RCC_I2C1235_CONFIG(__I2C1235CLKSource__)
macro to configure the I2C1/2/3/5* clock (I2C123CLK).
Definition stm32h7xx_hal_rcc_ex.h:2278
__HAL_RCC_GET_SPI45_SOURCE
#define __HAL_RCC_GET_SPI45_SOURCE()
Macro to get the SPI4/5 clock source.
Definition stm32h7xx_hal_rcc_ex.h:3429
RCC_FMCCLKSOURCE_HCLK
#define RCC_FMCCLKSOURCE_HCLK
Definition stm32h7xx_hal_rcc_ex.h:1426
RCC_FMCCLKSOURCE_PLL
#define RCC_FMCCLKSOURCE_PLL
Definition stm32h7xx_hal_rcc_ex.h:1429
RCC_FMCCLKSOURCE_PLL2
#define RCC_FMCCLKSOURCE_PLL2
Definition stm32h7xx_hal_rcc_ex.h:1430
RCC_FMCCLKSOURCE_CLKP
#define RCC_FMCCLKSOURCE_CLKP
Definition stm32h7xx_hal_rcc_ex.h:1431
RCC_I2C4CLKSOURCE_PLL3
#define RCC_I2C4CLKSOURCE_PLL3
Definition stm32h7xx_hal_rcc_ex.h:894
IS_RCC_CECCLKSOURCE
#define IS_RCC_CECCLKSOURCE(SOURCE)
Definition stm32h7xx_hal_rcc_ex.h:4416
IS_RCC_SCOPE_WWDG
#define IS_RCC_SCOPE_WWDG(WWDG)
Definition stm32h7xx_hal_rcc_ex.h:4436
IS_RCC_CRS_HSI48CALIBRATION
#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__)
Definition stm32h7xx_hal_rcc_ex.h:4457
IS_RCC_CRS_SYNC_SOURCE
#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__)
Definition stm32h7xx_hal_rcc_ex.h:4440
IS_RCC_PLL3RGE_VALUE
#define IS_RCC_PLL3RGE_VALUE(VALUE)
Definition stm32h7xx_hal_rcc_ex.h:4300
IS_RCC_CLKPSOURCE
#define IS_RCC_CLKPSOURCE(SOURCE)
Definition stm32h7xx_hal_rcc_ex.h:4420
IS_RCC_SDMMC
#define IS_RCC_SDMMC(__SOURCE__)
Definition stm32h7xx_hal_rcc_ex.h:4392
IS_RCC_PLL3N_VALUE
#define IS_RCC_PLL3N_VALUE(VALUE)
Definition stm32h7xx_hal_rcc_ex.h:4284
IS_RCC_PLL3Q_VALUE
#define IS_RCC_PLL3Q_VALUE(VALUE)
Definition stm32h7xx_hal_rcc_ex.h:4286
IS_RCC_I2C123CLKSOURCE
#define IS_RCC_I2C123CLKSOURCE(SOURCE)
Definition stm32h7xx_hal_rcc_ex.h:4098
IS_RCC_PLL2P_VALUE
#define IS_RCC_PLL2P_VALUE(VALUE)
Definition stm32h7xx_hal_rcc_ex.h:4291
IS_RCC_PLL2M_VALUE
#define IS_RCC_PLL2M_VALUE(VALUE)
Definition stm32h7xx_hal_rcc_ex.h:4289
IS_RCC_PLL2VCO_VALUE
#define IS_RCC_PLL2VCO_VALUE(VALUE)
Definition stm32h7xx_hal_rcc_ex.h:4305
IS_RCC_DFSDM1CLKSOURCE
#define IS_RCC_DFSDM1CLKSOURCE(SOURCE)
Definition stm32h7xx_hal_rcc_ex.h:4403
IS_RCC_PLL3R_VALUE
#define IS_RCC_PLL3R_VALUE(VALUE)
Definition stm32h7xx_hal_rcc_ex.h:4287
IS_RCC_SWPMI1CLKSOURCE
#define IS_RCC_SWPMI1CLKSOURCE(SOURCE)
Definition stm32h7xx_hal_rcc_ex.h:4400
IS_RCC_PLL3VCO_VALUE
#define IS_RCC_PLL3VCO_VALUE(VALUE)
Definition stm32h7xx_hal_rcc_ex.h:4308
IS_RCC_PLL3P_VALUE
#define IS_RCC_PLL3P_VALUE(VALUE)
Definition stm32h7xx_hal_rcc_ex.h:4285
IS_RCC_PLL2Q_VALUE
#define IS_RCC_PLL2Q_VALUE(VALUE)
Definition stm32h7xx_hal_rcc_ex.h:4292
IS_RCC_PLL2N_VALUE
#define IS_RCC_PLL2N_VALUE(VALUE)
Definition stm32h7xx_hal_rcc_ex.h:4290
IS_RCC_CRS_SYNC_POLARITY
#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__)
Definition stm32h7xx_hal_rcc_ex.h:4450
IS_RCC_CRS_ERRORLIMIT
#define IS_RCC_CRS_ERRORLIMIT(__VALUE__)
Definition stm32h7xx_hal_rcc_ex.h:4455
IS_RCC_PLL2RGE_VALUE
#define IS_RCC_PLL2RGE_VALUE(VALUE)
Definition stm32h7xx_hal_rcc_ex.h:4295
IS_RCC_CRS_RELOADVALUE
#define IS_RCC_CRS_RELOADVALUE(__VALUE__)
Definition stm32h7xx_hal_rcc_ex.h:4453
IS_RCC_I2C4CLKSOURCE
#define IS_RCC_I2C4CLKSOURCE(SOURCE)
Definition stm32h7xx_hal_rcc_ex.h:4119
IS_RCC_TIMPRES
#define IS_RCC_TIMPRES(VALUE)
Definition stm32h7xx_hal_rcc_ex.h:4423
IS_RCC_PLL3M_VALUE
#define IS_RCC_PLL3M_VALUE(VALUE)
Definition stm32h7xx_hal_rcc_ex.h:4283
IS_RCC_CRS_SYNC_DIV
#define IS_RCC_CRS_SYNC_DIV(__DIV__)
Definition stm32h7xx_hal_rcc_ex.h:4445
IS_RCC_PLL2R_VALUE
#define IS_RCC_PLL2R_VALUE(VALUE)
Definition stm32h7xx_hal_rcc_ex.h:4293
RCC_LPTIM1CLKSOURCE_CLKP
#define RCC_LPTIM1CLKSOURCE_CLKP
Definition stm32h7xx_hal_rcc_ex.h:1256
RCC_LPTIM1CLKSOURCE_PLL3
#define RCC_LPTIM1CLKSOURCE_PLL3
Definition stm32h7xx_hal_rcc_ex.h:1253
RCC_LPTIM1CLKSOURCE_PCLK1
#define RCC_LPTIM1CLKSOURCE_PCLK1
Definition stm32h7xx_hal_rcc_ex.h:1250
RCC_LPTIM1CLKSOURCE_PLL2
#define RCC_LPTIM1CLKSOURCE_PLL2
Definition stm32h7xx_hal_rcc_ex.h:1252
RCC_LPTIM1CLKSOURCE_LSE
#define RCC_LPTIM1CLKSOURCE_LSE
Definition stm32h7xx_hal_rcc_ex.h:1254
RCC_LPTIM1CLKSOURCE_LSI
#define RCC_LPTIM1CLKSOURCE_LSI
Definition stm32h7xx_hal_rcc_ex.h:1255
RCC_LPTIM2CLKSOURCE_CLKP
#define RCC_LPTIM2CLKSOURCE_CLKP
Definition stm32h7xx_hal_rcc_ex.h:1284
RCC_LPTIM2CLKSOURCE_LSI
#define RCC_LPTIM2CLKSOURCE_LSI
Definition stm32h7xx_hal_rcc_ex.h:1283
RCC_LPTIM2CLKSOURCE_LSE
#define RCC_LPTIM2CLKSOURCE_LSE
Definition stm32h7xx_hal_rcc_ex.h:1282
RCC_LPTIM2CLKSOURCE_PLL3
#define RCC_LPTIM2CLKSOURCE_PLL3
Definition stm32h7xx_hal_rcc_ex.h:1281
RCC_LPTIM2CLKSOURCE_PCLK4
#define RCC_LPTIM2CLKSOURCE_PCLK4
Definition stm32h7xx_hal_rcc_ex.h:1278
RCC_LPTIM2CLKSOURCE_PLL2
#define RCC_LPTIM2CLKSOURCE_PLL2
Definition stm32h7xx_hal_rcc_ex.h:1280
RCC_LPTIM345CLKSOURCE_PLL2
#define RCC_LPTIM345CLKSOURCE_PLL2
Definition stm32h7xx_hal_rcc_ex.h:1307
RCC_LPTIM345CLKSOURCE_CLKP
#define RCC_LPTIM345CLKSOURCE_CLKP
Definition stm32h7xx_hal_rcc_ex.h:1311
RCC_LPTIM345CLKSOURCE_PCLK4
#define RCC_LPTIM345CLKSOURCE_PCLK4
Definition stm32h7xx_hal_rcc_ex.h:1305
RCC_LPTIM345CLKSOURCE_LSI
#define RCC_LPTIM345CLKSOURCE_LSI
Definition stm32h7xx_hal_rcc_ex.h:1310
RCC_LPTIM345CLKSOURCE_PLL3
#define RCC_LPTIM345CLKSOURCE_PLL3
Definition stm32h7xx_hal_rcc_ex.h:1308
RCC_LPTIM345CLKSOURCE_LSE
#define RCC_LPTIM345CLKSOURCE_LSE
Definition stm32h7xx_hal_rcc_ex.h:1309
RCC_LPUART1CLKSOURCE_PLL3
#define RCC_LPUART1CLKSOURCE_PLL3
Definition stm32h7xx_hal_rcc_ex.h:776
RCC_LPUART1CLKSOURCE_CSI
#define RCC_LPUART1CLKSOURCE_CSI
Definition stm32h7xx_hal_rcc_ex.h:778
RCC_LPUART1CLKSOURCE_PLL2
#define RCC_LPUART1CLKSOURCE_PLL2
Definition stm32h7xx_hal_rcc_ex.h:775
RCC_LPUART1CLKSOURCE_PCLK4
#define RCC_LPUART1CLKSOURCE_PCLK4
Definition stm32h7xx_hal_rcc_ex.h:773
RCC_LPUART1CLKSOURCE_HSI
#define RCC_LPUART1CLKSOURCE_HSI
Definition stm32h7xx_hal_rcc_ex.h:777
RCC_LPUART1CLKSOURCE_LSE
#define RCC_LPUART1CLKSOURCE_LSE
Definition stm32h7xx_hal_rcc_ex.h:779
RCC_PERIPHCLK_RNG
#define RCC_PERIPHCLK_RNG
Definition stm32h7xx_hal_rcc_ex.h:428
RCC_PERIPHCLK_LPTIM345
#define RCC_PERIPHCLK_LPTIM345
Definition stm32h7xx_hal_rcc_ex.h:394
RCC_PERIPHCLK_LPUART1
#define RCC_PERIPHCLK_LPUART1
Definition stm32h7xx_hal_rcc_ex.h:374
RCC_PERIPHCLK_I2C123
#define RCC_PERIPHCLK_I2C123
Definition stm32h7xx_hal_rcc_ex.h:383
RCC_PERIPHCLK_PLL3_DIVP
#define RCC_PERIPHCLK_PLL3_DIVP
Definition stm32h7xx_hal_rcc_ex.h:459
RCC_PERIPHCLK_I2C4
#define RCC_PERIPHCLK_I2C4
Definition stm32h7xx_hal_rcc_ex.h:388
RCC_PERIPHCLK_CKPER
#define RCC_PERIPHCLK_CKPER
Definition stm32h7xx_hal_rcc_ex.h:454
RCC_PERIPHCLK_USART16
#define RCC_PERIPHCLK_USART16
Definition stm32h7xx_hal_rcc_ex.h:361
RCC_PERIPHCLK_LPTIM2
#define RCC_PERIPHCLK_LPTIM2
Definition stm32h7xx_hal_rcc_ex.h:393
RCC_PERIPHCLK_LPTIM1
#define RCC_PERIPHCLK_LPTIM1
Definition stm32h7xx_hal_rcc_ex.h:392
RCC_PERIPHCLK_PLL3_DIVR
#define RCC_PERIPHCLK_PLL3_DIVR
Definition stm32h7xx_hal_rcc_ex.h:461
RCC_PERIPHCLK_USART234578
#define RCC_PERIPHCLK_USART234578
Definition stm32h7xx_hal_rcc_ex.h:367
RCC_PERIPHCLK_PLL2_DIVQ
#define RCC_PERIPHCLK_PLL2_DIVQ
Definition stm32h7xx_hal_rcc_ex.h:457
RCC_PERIPHCLK_TIM
#define RCC_PERIPHCLK_TIM
Definition stm32h7xx_hal_rcc_ex.h:453
RCC_PERIPHCLK_PLL2_DIVR
#define RCC_PERIPHCLK_PLL2_DIVR
Definition stm32h7xx_hal_rcc_ex.h:458
RCC_PERIPHCLK_SWPMI1
#define RCC_PERIPHCLK_SWPMI1
Definition stm32h7xx_hal_rcc_ex.h:431
RCC_PERIPHCLK_SPI45
#define RCC_PERIPHCLK_SPI45
Definition stm32h7xx_hal_rcc_ex.h:422
RCC_PERIPHCLK_PLL3_DIVQ
#define RCC_PERIPHCLK_PLL3_DIVQ
Definition stm32h7xx_hal_rcc_ex.h:460
RCC_PERIPHCLK_SAI1
#define RCC_PERIPHCLK_SAI1
Definition stm32h7xx_hal_rcc_ex.h:402
RCC_PERIPHCLK_ADC
#define RCC_PERIPHCLK_ADC
Definition stm32h7xx_hal_rcc_ex.h:430
RCC_PERIPHCLK_SPI6
#define RCC_PERIPHCLK_SPI6
Definition stm32h7xx_hal_rcc_ex.h:425
RCC_PERIPHCLK_FMC
#define RCC_PERIPHCLK_FMC
Definition stm32h7xx_hal_rcc_ex.h:438
RCC_PERIPHCLK_PLL2_DIVP
#define RCC_PERIPHCLK_PLL2_DIVP
Definition stm32h7xx_hal_rcc_ex.h:456
RCC_PERIPHCLK_USB
#define RCC_PERIPHCLK_USB
Definition stm32h7xx_hal_rcc_ex.h:429
RCC_PERIPHCLK_SPDIFRX
#define RCC_PERIPHCLK_SPDIFRX
Definition stm32h7xx_hal_rcc_ex.h:446
RCC_PERIPHCLK_DFSDM1
#define RCC_PERIPHCLK_DFSDM1
Definition stm32h7xx_hal_rcc_ex.h:432
RCC_PERIPHCLK_CEC
#define RCC_PERIPHCLK_CEC
Definition stm32h7xx_hal_rcc_ex.h:437
RCC_PERIPHCLK_RTC
#define RCC_PERIPHCLK_RTC
Definition stm32h7xx_hal_rcc_ex.h:436
RCC_PERIPHCLK_DSI
#define RCC_PERIPHCLK_DSI
Definition stm32h7xx_hal_rcc_ex.h:445
RCC_PERIPHCLK_SDMMC
#define RCC_PERIPHCLK_SDMMC
Definition stm32h7xx_hal_rcc_ex.h:427
RCC_PERIPHCLK_FDCAN
#define RCC_PERIPHCLK_FDCAN
Definition stm32h7xx_hal_rcc_ex.h:426
RCC_PERIPHCLK_SPI123
#define RCC_PERIPHCLK_SPI123
Definition stm32h7xx_hal_rcc_ex.h:418
RCC_RNGCLKSOURCE_HSI48
#define RCC_RNGCLKSOURCE_HSI48
Definition stm32h7xx_hal_rcc_ex.h:925
RCC_RNGCLKSOURCE_LSI
#define RCC_RNGCLKSOURCE_LSI
Definition stm32h7xx_hal_rcc_ex.h:928
RCC_RNGCLKSOURCE_PLL
#define RCC_RNGCLKSOURCE_PLL
Definition stm32h7xx_hal_rcc_ex.h:926
RCC_RNGCLKSOURCE_LSE
#define RCC_RNGCLKSOURCE_LSE
Definition stm32h7xx_hal_rcc_ex.h:927
RCC_SAI1CLKSOURCE_CLKP
#define RCC_SAI1CLKSOURCE_CLKP
Definition stm32h7xx_hal_rcc_ex.h:978
RCC_SAI1CLKSOURCE_PLL2
#define RCC_SAI1CLKSOURCE_PLL2
Definition stm32h7xx_hal_rcc_ex.h:975
RCC_SAI1CLKSOURCE_PIN
#define RCC_SAI1CLKSOURCE_PIN
Definition stm32h7xx_hal_rcc_ex.h:977
RCC_SAI1CLKSOURCE_PLL3
#define RCC_SAI1CLKSOURCE_PLL3
Definition stm32h7xx_hal_rcc_ex.h:976
RCC_SAI1CLKSOURCE_PLL
#define RCC_SAI1CLKSOURCE_PLL
Definition stm32h7xx_hal_rcc_ex.h:974
RCC_SDMMCCLKSOURCE_PLL
#define RCC_SDMMCCLKSOURCE_PLL
Definition stm32h7xx_hal_rcc_ex.h:1463
RCC_SDMMCCLKSOURCE_PLL2
#define RCC_SDMMCCLKSOURCE_PLL2
Definition stm32h7xx_hal_rcc_ex.h:1464
RCC_SPDIFRXCLKSOURCE_PLL
#define RCC_SPDIFRXCLKSOURCE_PLL
Definition stm32h7xx_hal_rcc_ex.h:1541
RCC_SPDIFRXCLKSOURCE_HSI
#define RCC_SPDIFRXCLKSOURCE_HSI
Definition stm32h7xx_hal_rcc_ex.h:1544
RCC_SPDIFRXCLKSOURCE_PLL2
#define RCC_SPDIFRXCLKSOURCE_PLL2
Definition stm32h7xx_hal_rcc_ex.h:1542
RCC_SPDIFRXCLKSOURCE_PLL3
#define RCC_SPDIFRXCLKSOURCE_PLL3
Definition stm32h7xx_hal_rcc_ex.h:1543
RCC_SPI123CLKSOURCE_PIN
#define RCC_SPI123CLKSOURCE_PIN
Definition stm32h7xx_hal_rcc_ex.h:1067
RCC_SPI123CLKSOURCE_CLKP
#define RCC_SPI123CLKSOURCE_CLKP
Definition stm32h7xx_hal_rcc_ex.h:1068
RCC_SPI123CLKSOURCE_PLL3
#define RCC_SPI123CLKSOURCE_PLL3
Definition stm32h7xx_hal_rcc_ex.h:1066
RCC_SPI123CLKSOURCE_PLL
#define RCC_SPI123CLKSOURCE_PLL
Definition stm32h7xx_hal_rcc_ex.h:1064
RCC_SPI123CLKSOURCE_PLL2
#define RCC_SPI123CLKSOURCE_PLL2
Definition stm32h7xx_hal_rcc_ex.h:1065
RCC_SPI45CLKSOURCE_PCLK2
#define RCC_SPI45CLKSOURCE_PCLK2
Definition stm32h7xx_hal_rcc_ex.h:1128
RCC_SPI45CLKSOURCE_PLL2
#define RCC_SPI45CLKSOURCE_PLL2
Definition stm32h7xx_hal_rcc_ex.h:1129
RCC_SPI45CLKSOURCE_HSE
#define RCC_SPI45CLKSOURCE_HSE
Definition stm32h7xx_hal_rcc_ex.h:1133
RCC_SPI45CLKSOURCE_PLL3
#define RCC_SPI45CLKSOURCE_PLL3
Definition stm32h7xx_hal_rcc_ex.h:1130
RCC_SPI45CLKSOURCE_HSI
#define RCC_SPI45CLKSOURCE_HSI
Definition stm32h7xx_hal_rcc_ex.h:1131
RCC_SPI45CLKSOURCE_CSI
#define RCC_SPI45CLKSOURCE_CSI
Definition stm32h7xx_hal_rcc_ex.h:1132
RCC_SPI6CLKSOURCE_PIN
#define RCC_SPI6CLKSOURCE_PIN
Definition stm32h7xx_hal_rcc_ex.h:1188
RCC_SPI6CLKSOURCE_PLL3
#define RCC_SPI6CLKSOURCE_PLL3
Definition stm32h7xx_hal_rcc_ex.h:1184
RCC_SPI6CLKSOURCE_HSE
#define RCC_SPI6CLKSOURCE_HSE
Definition stm32h7xx_hal_rcc_ex.h:1187
RCC_SPI6CLKSOURCE_CSI
#define RCC_SPI6CLKSOURCE_CSI
Definition stm32h7xx_hal_rcc_ex.h:1186
RCC_SPI6CLKSOURCE_PLL2
#define RCC_SPI6CLKSOURCE_PLL2
Definition stm32h7xx_hal_rcc_ex.h:1183
RCC_SPI6CLKSOURCE_PCLK4
#define RCC_SPI6CLKSOURCE_PCLK4
Definition stm32h7xx_hal_rcc_ex.h:1182
RCC_SPI6CLKSOURCE_HSI
#define RCC_SPI6CLKSOURCE_HSI
Definition stm32h7xx_hal_rcc_ex.h:1185
RCC_SPI6CLKSOURCE_D3PCLK1
#define RCC_SPI6CLKSOURCE_D3PCLK1
Definition stm32h7xx_hal_rcc_ex.h:1181
RCC_TIMPRES_DESACTIVATED
#define RCC_TIMPRES_DESACTIVATED
Definition stm32h7xx_hal_rcc_ex.h:1586
RCC_TIMPRES_ACTIVATED
#define RCC_TIMPRES_ACTIVATED
Definition stm32h7xx_hal_rcc_ex.h:1587
RCC_USART16CLKSOURCE_CSI
#define RCC_USART16CLKSOURCE_CSI
Definition stm32h7xx_hal_rcc_ex.h:583
RCC_USART16CLKSOURCE_LSE
#define RCC_USART16CLKSOURCE_LSE
Definition stm32h7xx_hal_rcc_ex.h:584
RCC_USART16CLKSOURCE_PLL3
#define RCC_USART16CLKSOURCE_PLL3
Definition stm32h7xx_hal_rcc_ex.h:581
RCC_USART16CLKSOURCE_PLL2
#define RCC_USART16CLKSOURCE_PLL2
Definition stm32h7xx_hal_rcc_ex.h:580
RCC_USART16CLKSOURCE_HSI
#define RCC_USART16CLKSOURCE_HSI
Definition stm32h7xx_hal_rcc_ex.h:582
RCC_USART16CLKSOURCE_PCLK2
#define RCC_USART16CLKSOURCE_PCLK2
Definition stm32h7xx_hal_rcc_ex.h:579
RCC_USART234578CLKSOURCE_PCLK1
#define RCC_USART234578CLKSOURCE_PCLK1
Definition stm32h7xx_hal_rcc_ex.h:662
RCC_USART234578CLKSOURCE_PLL3
#define RCC_USART234578CLKSOURCE_PLL3
Definition stm32h7xx_hal_rcc_ex.h:665
RCC_USART234578CLKSOURCE_CSI
#define RCC_USART234578CLKSOURCE_CSI
Definition stm32h7xx_hal_rcc_ex.h:667
RCC_USART234578CLKSOURCE_HSI
#define RCC_USART234578CLKSOURCE_HSI
Definition stm32h7xx_hal_rcc_ex.h:666
RCC_USART234578CLKSOURCE_LSE
#define RCC_USART234578CLKSOURCE_LSE
Definition stm32h7xx_hal_rcc_ex.h:668
RCC_USART234578CLKSOURCE_PLL2
#define RCC_USART234578CLKSOURCE_PLL2
Definition stm32h7xx_hal_rcc_ex.h:664
RCC_USBCLKSOURCE_PLL3
#define RCC_USBCLKSOURCE_PLL3
Definition stm32h7xx_hal_rcc_ex.h:956
RCC_USBCLKSOURCE_PLL
#define RCC_USBCLKSOURCE_PLL
Definition stm32h7xx_hal_rcc_ex.h:955
RCC_USBCLKSOURCE_HSI48
#define RCC_USBCLKSOURCE_HSI48
Definition stm32h7xx_hal_rcc_ex.h:957
HAL_RCC_GetHCLKFreq
uint32_t HAL_RCC_GetHCLKFreq(void)
HAL_RCC_GetSysClockFreq
uint32_t HAL_RCC_GetSysClockFreq(void)
HAL_RCC_GetPCLK1Freq
uint32_t HAL_RCC_GetPCLK1Freq(void)
__HAL_RCC_CRS_FORCE_RESET
#define __HAL_RCC_CRS_FORCE_RESET()
Definition stm32h7xx_hal_rcc.h:4969
__HAL_RCC_BACKUPRESET_RELEASE
#define __HAL_RCC_BACKUPRESET_RELEASE()
Definition stm32h7xx_hal_rcc.h:7506
__HAL_RCC_CRS_RELEASE_RESET
#define __HAL_RCC_CRS_RELEASE_RESET()
Definition stm32h7xx_hal_rcc.h:5010
__HAL_RCC_RTC_CONFIG
#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__)
Definition stm32h7xx_hal_rcc.h:7493
__HAL_RCC_PLLCLKOUT_ENABLE
#define __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__)
Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK).
Definition stm32h7xx_hal_rcc.h:7535
__HAL_RCC_BACKUPRESET_FORCE
#define __HAL_RCC_BACKUPRESET_FORCE()
Macros to force or release the Backup domain reset.
Definition stm32h7xx_hal_rcc.h:7505
__HAL_RCC_GET_PLL_OSCSOURCE
#define __HAL_RCC_GET_PLL_OSCSOURCE()
Macro to get the oscillator used as PLL clock source.
Definition stm32h7xx_hal_rcc.h:7687
__HAL_RCC_GET_HSI_DIVIDER
#define __HAL_RCC_GET_HSI_DIVIDER()
Macro to get the HSI divider.
Definition stm32h7xx_hal_rcc.h:7143
__HAL_RCC_GET_RTC_SOURCE
#define __HAL_RCC_GET_RTC_SOURCE()
Definition stm32h7xx_hal_rcc.h:7497
__HAL_RCC_WAKEUPSTOP_CLK_CONFIG
#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__)
Macro to configure the wake up from stop clock.
Definition stm32h7xx_hal_rcc.h:7767
__HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG
#define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__)
Macro to configure the Kernel wake up from stop clock.
Definition stm32h7xx_hal_rcc.h:7778
RCC_FLAG_PLL3RDY
#define RCC_FLAG_PLL3RDY
Definition stm32h7xx_hal_rcc.h:668
RCC_FLAG_PLL2RDY
#define RCC_FLAG_PLL2RDY
Definition stm32h7xx_hal_rcc.h:667
RCC_FLAG_HSIDIV
#define RCC_FLAG_HSIDIV
Definition stm32h7xx_hal_rcc.h:650
RCC_FLAG_LSERDY
#define RCC_FLAG_LSERDY
Definition stm32h7xx_hal_rcc.h:670
__HAL_RCC_GET_IT
#define __HAL_RCC_GET_IT(__INTERRUPT__)
Check the RCC's interrupt has occurred or not.
Definition stm32h7xx_hal_rcc.h:7850
__HAL_RCC_ENABLE_IT
#define __HAL_RCC_ENABLE_IT(__INTERRUPT__)
Enable RCC interrupt.
Definition stm32h7xx_hal_rcc.h:7799
__HAL_RCC_CLEAR_IT
#define __HAL_RCC_CLEAR_IT(__INTERRUPT__)
Clear the RCC's interrupt pending bits.
Definition stm32h7xx_hal_rcc.h:7832
__HAL_RCC_GET_FLAG
#define __HAL_RCC_GET_FLAG(__FLAG__)
Definition stm32h7xx_hal_rcc.h:7943
__HAL_RCC_DISABLE_IT
#define __HAL_RCC_DISABLE_IT(__INTERRUPT__)
Disable RCC interrupt.
Definition stm32h7xx_hal_rcc.h:7815
IS_RCC_PLLFRACN_VALUE
#define IS_RCC_PLLFRACN_VALUE(VALUE)
Definition stm32h7xx_hal_rcc.h:8083
IS_RCC_STOP_WAKEUPCLOCK
#define IS_RCC_STOP_WAKEUPCLOCK(SOURCE)
Definition stm32h7xx_hal_rcc.h:8241
IS_RCC_STOP_KERWAKEUPCLOCK
#define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE)
Definition stm32h7xx_hal_rcc.h:8244
IS_RCC_RTCCLKSOURCE
#define IS_RCC_RTCCLKSOURCE(SOURCE)
Definition stm32h7xx_hal_rcc.h:8139
RCC_IT_LSECSS
#define RCC_IT_LSECSS
Definition stm32h7xx_hal_rcc.h:632
RCC_PLL2_DIVQ
#define RCC_PLL2_DIVQ
Definition stm32h7xx_hal_rcc_ex.h:472
RCC_PLL2_DIVR
#define RCC_PLL2_DIVR
Definition stm32h7xx_hal_rcc_ex.h:473
RCC_PLL2_DIVP
#define RCC_PLL2_DIVP
Definition stm32h7xx_hal_rcc_ex.h:471
RCC_PLL3_DIVQ
#define RCC_PLL3_DIVQ
Definition stm32h7xx_hal_rcc_ex.h:483
RCC_PLL3_DIVP
#define RCC_PLL3_DIVP
Definition stm32h7xx_hal_rcc_ex.h:482
RCC_PLL3_DIVR
#define RCC_PLL3_DIVR
Definition stm32h7xx_hal_rcc_ex.h:484
RCC_PLL1_DIVQ
#define RCC_PLL1_DIVQ
Definition stm32h7xx_hal_rcc.h:275
RCC_PLLSOURCE_HSI
#define RCC_PLLSOURCE_HSI
Definition stm32h7xx_hal_rcc.h:263
RCC_PLLSOURCE_HSE
#define RCC_PLLSOURCE_HSE
Definition stm32h7xx_hal_rcc.h:265
RCC_PLLSOURCE_NONE
#define RCC_PLLSOURCE_NONE
Definition stm32h7xx_hal_rcc.h:266
RCC_PLLSOURCE_CSI
#define RCC_PLLSOURCE_CSI
Definition stm32h7xx_hal_rcc.h:264
RCC_DBP_TIMEOUT_VALUE
#define RCC_DBP_TIMEOUT_VALUE
Definition stm32h7xx_hal_rcc.h:8018
RCC_LSE_TIMEOUT_VALUE
#define RCC_LSE_TIMEOUT_VALUE
Definition stm32h7xx_hal_rcc.h:8019
RCC_RTCCLKSOURCE_LSE
#define RCC_RTCCLKSOURCE_LSE
Definition stm32h7xx_hal_rcc.h:488
REV_ID_Y
#define REV_ID_Y
STM32H7 rev.Y.
Definition stm32h7xx_hal.h:61
SystemD2Clock
uint32_t SystemD2Clock
System Domain2 Clock Frequency.
Definition system_stm32h7xx.c:152
SystemCoreClock
uint32_t SystemCoreClock
System Domain1 Clock Frequency.
Definition system_stm32h7xx.c:151
D1CorePrescTable
const uint8_t D1CorePrescTable[16]
D1CorePrescTable prescalers table values.
Definition system_stm32h7xx.c:153
NULL
#define NULL
Definition usbd_def.h:44
anonymous_namespace{radio_task.cpp}::status
radio_status_t status
Definition radio_task.cpp:83
stm32h7xx_hal.h
This file contains all the functions prototypes for the HAL module driver.
CSI_VALUE
#define CSI_VALUE
Internal oscillator (CSI) default value.
Definition stm32h7xx_hal_conf.h:121
assert_param
#define assert_param(expr)
Uncomment the line below to expanse the "assert_param" macro in the HAL drivers code.
Definition stm32h7xx_hal_conf.h:507
EXTERNAL_CLOCK_VALUE
#define EXTERNAL_CLOCK_VALUE
< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variation...
Definition stm32h7xx_hal_conf.h:157
HSI_VALUE
#define HSI_VALUE
Internal High Speed oscillator (HSI) value.
Definition stm32h7xx_hal_conf.h:130
HSE_VALUE
#define HSE_VALUE
Adjust the value of External High Speed oscillator (HSE) used in your application.
Definition stm32h7xx_hal_conf.h:109
HAL_IS_BIT_SET
#define HAL_IS_BIT_SET(REG, BIT)
Definition stm32h7xx_hal_def.h:60
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition stm32h7xx_hal_def.h:40
HAL_TIMEOUT
@ HAL_TIMEOUT
Definition stm32h7xx_hal_def.h:44
HAL_ERROR
@ HAL_ERROR
Definition stm32h7xx_hal_def.h:42
HAL_OK
@ HAL_OK
Definition stm32h7xx_hal_def.h:41
UNUSED
#define UNUSED(x)
Definition stm32h7xx_hal_def.h:70
HAL_MAX_DELAY
#define HAL_MAX_DELAY
Definition stm32h7xx_hal_def.h:58
PLL1_ClocksTypeDef
RCC PLL1 Clocks structure definition.
Definition stm32h7xx_hal_rcc_ex.h:110
PLL1_ClocksTypeDef::PLL1_R_Frequency
uint32_t PLL1_R_Frequency
Definition stm32h7xx_hal_rcc_ex.h:113
PLL1_ClocksTypeDef::PLL1_Q_Frequency
uint32_t PLL1_Q_Frequency
Definition stm32h7xx_hal_rcc_ex.h:112
PLL1_ClocksTypeDef::PLL1_P_Frequency
uint32_t PLL1_P_Frequency
Definition stm32h7xx_hal_rcc_ex.h:111
PLL2_ClocksTypeDef
RCC PLL2 Clocks structure definition.
Definition stm32h7xx_hal_rcc_ex.h:120
PLL2_ClocksTypeDef::PLL2_Q_Frequency
uint32_t PLL2_Q_Frequency
Definition stm32h7xx_hal_rcc_ex.h:122
PLL2_ClocksTypeDef::PLL2_P_Frequency
uint32_t PLL2_P_Frequency
Definition stm32h7xx_hal_rcc_ex.h:121
PLL2_ClocksTypeDef::PLL2_R_Frequency
uint32_t PLL2_R_Frequency
Definition stm32h7xx_hal_rcc_ex.h:123
PLL3_ClocksTypeDef
RCC PLL3 Clocks structure definition.
Definition stm32h7xx_hal_rcc_ex.h:130
PLL3_ClocksTypeDef::PLL3_P_Frequency
uint32_t PLL3_P_Frequency
Definition stm32h7xx_hal_rcc_ex.h:131
PLL3_ClocksTypeDef::PLL3_R_Frequency
uint32_t PLL3_R_Frequency
Definition stm32h7xx_hal_rcc_ex.h:133
PLL3_ClocksTypeDef::PLL3_Q_Frequency
uint32_t PLL3_Q_Frequency
Definition stm32h7xx_hal_rcc_ex.h:132
RCC_CRSInitTypeDef
RCC_CRS Init structure definition.
Definition stm32h7xx_hal_rcc_ex.h:294
RCC_CRSInitTypeDef::Polarity
uint32_t Polarity
Specifies the input polarity for the SYNC signal source.
Definition stm32h7xx_hal_rcc_ex.h:301
RCC_CRSInitTypeDef::HSI48CalibrationValue
uint32_t HSI48CalibrationValue
Specifies a user-programmable trimming value to the HSI48 oscillator.
Definition stm32h7xx_hal_rcc_ex.h:311
RCC_CRSInitTypeDef::Prescaler
uint32_t Prescaler
Specifies the division factor of the SYNC signal.
Definition stm32h7xx_hal_rcc_ex.h:295
RCC_CRSInitTypeDef::ReloadValue
uint32_t ReloadValue
Specifies the value to be loaded in the frequency error counter with each SYNC event.
Definition stm32h7xx_hal_rcc_ex.h:304
RCC_CRSInitTypeDef::Source
uint32_t Source
Specifies the SYNC signal source.
Definition stm32h7xx_hal_rcc_ex.h:298
RCC_CRSInitTypeDef::ErrorLimitValue
uint32_t ErrorLimitValue
Specifies the value to be used to evaluate the captured frequency error value.
Definition stm32h7xx_hal_rcc_ex.h:308
RCC_CRSSynchroInfoTypeDef
RCC_CRS Synchronization structure definition.
Definition stm32h7xx_hal_rcc_ex.h:320
RCC_CRSSynchroInfoTypeDef::HSI48CalibrationValue
uint32_t HSI48CalibrationValue
Specifies value loaded in HSI48 oscillator smooth trimming.
Definition stm32h7xx_hal_rcc_ex.h:324
RCC_CRSSynchroInfoTypeDef::ReloadValue
uint32_t ReloadValue
Specifies the value loaded in the Counter reload value.
Definition stm32h7xx_hal_rcc_ex.h:321
RCC_CRSSynchroInfoTypeDef::FreqErrorDirection
uint32_t FreqErrorDirection
Specifies the value loaded in the .FEDIR, the counting direction of the frequency error counter latch...
Definition stm32h7xx_hal_rcc_ex.h:331
RCC_CRSSynchroInfoTypeDef::FreqErrorCapture
uint32_t FreqErrorCapture
Specifies the value loaded in the .FECAP, the frequency error counter value latched in the time of th...
Definition stm32h7xx_hal_rcc_ex.h:327
RCC_PLL2InitTypeDef
PLL2 Clock structure definition.
Definition stm32h7xx_hal_rcc_ex.h:46
RCC_PLL2InitTypeDef::PLL2R
uint32_t PLL2R
PLL2R: Division factor for peripheral clocks.
Definition stm32h7xx_hal_rcc_ex.h:63
RCC_PLL2InitTypeDef::PLL2M
uint32_t PLL2M
PLL2M: Division factor for PLL2 VCO input clock.
Definition stm32h7xx_hal_rcc_ex.h:48
RCC_PLL2InitTypeDef::PLL2RGE
uint32_t PLL2RGE
PLL2RGE: PLL2 clock Input range This parameter must be a value of RCC PLL2 VCI Range.
Definition stm32h7xx_hal_rcc_ex.h:65
RCC_PLL2InitTypeDef::PLL2N
uint32_t PLL2N
PLL2N: Multiplication factor for PLL2 VCO output clock.
Definition stm32h7xx_hal_rcc_ex.h:51
RCC_PLL2InitTypeDef::PLL2FRACN
uint32_t PLL2FRACN
PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for PLL2 VCO It should be a value b...
Definition stm32h7xx_hal_rcc_ex.h:70
RCC_PLL2InitTypeDef::PLL2VCOSEL
uint32_t PLL2VCOSEL
PLL2VCOSEL: PLL2 clock Output range This parameter must be a value of RCC PLL2 VCO Range.
Definition stm32h7xx_hal_rcc_ex.h:67
RCC_PLL2InitTypeDef::PLL2P
uint32_t PLL2P
PLL2P: Division factor for system clock.
Definition stm32h7xx_hal_rcc_ex.h:56
RCC_PLL2InitTypeDef::PLL2Q
uint32_t PLL2Q
PLL2Q: Division factor for peripheral clocks.
Definition stm32h7xx_hal_rcc_ex.h:60
RCC_PLL3InitTypeDef
PLL3 Clock structure definition.
Definition stm32h7xx_hal_rcc_ex.h:78
RCC_PLL3InitTypeDef::PLL3Q
uint32_t PLL3Q
PLL3Q: Division factor for peripheral clocks.
Definition stm32h7xx_hal_rcc_ex.h:92
RCC_PLL3InitTypeDef::PLL3FRACN
uint32_t PLL3FRACN
PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for PLL3 VCO It should be a value b...
Definition stm32h7xx_hal_rcc_ex.h:102
RCC_PLL3InitTypeDef::PLL3N
uint32_t PLL3N
PLL3N: Multiplication factor for PLL3 VCO output clock.
Definition stm32h7xx_hal_rcc_ex.h:83
RCC_PLL3InitTypeDef::PLL3VCOSEL
uint32_t PLL3VCOSEL
PLL3VCOSEL: PLL3 clock Output range This parameter must be a value of RCC PLL3 VCO Range.
Definition stm32h7xx_hal_rcc_ex.h:99
RCC_PLL3InitTypeDef::PLL3P
uint32_t PLL3P
PLL3P: Division factor for system clock.
Definition stm32h7xx_hal_rcc_ex.h:88
RCC_PLL3InitTypeDef::PLL3R
uint32_t PLL3R
PLL3R: Division factor for peripheral clocks.
Definition stm32h7xx_hal_rcc_ex.h:95
RCC_PLL3InitTypeDef::PLL3RGE
uint32_t PLL3RGE
PLL3RGE: PLL3 clock Input range This parameter must be a value of RCC PLL3 VCI Range.
Definition stm32h7xx_hal_rcc_ex.h:97
RCC_PLL3InitTypeDef::PLL3M
uint32_t PLL3M
PLL3M: Division factor for PLL3 VCO input clock.
Definition stm32h7xx_hal_rcc_ex.h:80
RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition.
Definition stm32h7xx_hal_rcc_ex.h:141
RCC_PeriphCLKInitTypeDef::Spi123ClockSelection
uint32_t Spi123ClockSelection
Specifies SPI1/2/3 clock source This parameter can be a value of SPI1/2/3 Clock Source.
Definition stm32h7xx_hal_rcc_ex.h:194
RCC_PeriphCLKInitTypeDef::Spi6ClockSelection
uint32_t Spi6ClockSelection
Specifies SPI6 clock source This parameter can be a value of SPI6 Clock Source.
Definition stm32h7xx_hal_rcc_ex.h:267
RCC_PeriphCLKInitTypeDef::I2c123ClockSelection
uint32_t I2c123ClockSelection
Specifies I2C1/2/3 clock source This parameter can be a value of RCCEx I2C1/2/3/5 Clock Source.
Definition stm32h7xx_hal_rcc_ex.h:232
RCC_PeriphCLKInitTypeDef::Usart16ClockSelection
uint32_t Usart16ClockSelection
Specifies USART1/6 clock source This parameter can be a value of RCCEx USART1/6 Clock Source.
Definition stm32h7xx_hal_rcc_ex.h:222
RCC_PeriphCLKInitTypeDef::TIMPresSelection
uint32_t TIMPresSelection
Specifies TIM Clock Prescalers Selection.
Definition stm32h7xx_hal_rcc_ex.h:278
RCC_PeriphCLKInitTypeDef::Lptim1ClockSelection
uint32_t Lptim1ClockSelection
Specifies LPTIM1 clock source This parameter can be a value of RCCEx LPTIM1 Clock Source.
Definition stm32h7xx_hal_rcc_ex.h:242
RCC_PeriphCLKInitTypeDef::CkperClockSelection
uint32_t CkperClockSelection
Specifies CKPER clock source This parameter can be a value of RCCEx CLKP Clock Source.
Definition stm32h7xx_hal_rcc_ex.h:173
RCC_PeriphCLKInitTypeDef::CecClockSelection
uint32_t CecClockSelection
Specifies CEC clock source This parameter can be a value of RCCEx CEC Clock Source.
Definition stm32h7xx_hal_rcc_ex.h:239
RCC_PeriphCLKInitTypeDef::Swpmi1ClockSelection
uint32_t Swpmi1ClockSelection
Specifies SWPMI1 Clock clock source This parameter can be a value of RCCEx SWPMI1 Clock Source.
Definition stm32h7xx_hal_rcc_ex.h:216
RCC_PeriphCLKInitTypeDef::PeriphClockSelection
uint64_t PeriphClockSelection
The Extended Clock to be configured.
Definition stm32h7xx_hal_rcc_ex.h:142
RCC_PeriphCLKInitTypeDef::I2c4ClockSelection
uint32_t I2c4ClockSelection
Specifies I2C4 clock source This parameter can be a value of RCCEx I2C4 Clock Source.
Definition stm32h7xx_hal_rcc_ex.h:248
RCC_PeriphCLKInitTypeDef::Lptim2ClockSelection
uint32_t Lptim2ClockSelection
Specifies LPTIM2 clock source This parameter can be a value of RCCEx LPTIM2 Clock Source.
Definition stm32h7xx_hal_rcc_ex.h:251
RCC_PeriphCLKInitTypeDef::SpdifrxClockSelection
uint32_t SpdifrxClockSelection
Specifies SPDIFRX Clock clock source This parameter can be a value of RCCEx SPDIFRX Clock Source.
Definition stm32h7xx_hal_rcc_ex.h:200
RCC_PeriphCLKInitTypeDef::SdmmcClockSelection
uint32_t SdmmcClockSelection
Specifies SDMMC clock source This parameter can be a value of RCCEx SDMMC Clock Source.
Definition stm32h7xx_hal_rcc_ex.h:170
RCC_PeriphCLKInitTypeDef::PLL2
RCC_PLL2InitTypeDef PLL2
PLL2structure parameters.
Definition stm32h7xx_hal_rcc_ex.h:145
RCC_PeriphCLKInitTypeDef::Dfsdm1ClockSelection
uint32_t Dfsdm1ClockSelection
Specifies DFSDM1 Clock clock source This parameter can be a value of RCCEx DFSDM1 Clock Source.
Definition stm32h7xx_hal_rcc_ex.h:203
RCC_PeriphCLKInitTypeDef::PLL3
RCC_PLL3InitTypeDef PLL3
PLL3 structure parameters.
Definition stm32h7xx_hal_rcc_ex.h:148
RCC_PeriphCLKInitTypeDef::Lptim345ClockSelection
uint32_t Lptim345ClockSelection
Specifies LPTIM3/4/5 clock source This parameter can be a value of RCCEx LPTIM3/4/5 Clock Source.
Definition stm32h7xx_hal_rcc_ex.h:254
RCC_PeriphCLKInitTypeDef::AdcClockSelection
uint32_t AdcClockSelection
Specifies ADC interface clock source This parameter can be a value of RCCEx ADC Clock Source.
Definition stm32h7xx_hal_rcc_ex.h:257
RCC_PeriphCLKInitTypeDef::Usart234578ClockSelection
uint32_t Usart234578ClockSelection
Specifies USART2/3/4/5/7/8 clock source This parameter can be a value of RCCEx USART2/3/4/5/7/8 Clock...
Definition stm32h7xx_hal_rcc_ex.h:219
RCC_PeriphCLKInitTypeDef::FmcClockSelection
uint32_t FmcClockSelection
Specifies FMC clock source This parameter can be a value of RCCEx FMC Clock Source.
Definition stm32h7xx_hal_rcc_ex.h:151
RCC_PeriphCLKInitTypeDef::RTCClockSelection
uint32_t RTCClockSelection
Specifies RTC Clock clock source This parameter can be a value of RCC RTC Clock Source.
Definition stm32h7xx_hal_rcc_ex.h:270
RCC_PeriphCLKInitTypeDef::Sai1ClockSelection
uint32_t Sai1ClockSelection
Specifies SAI1 clock source This parameter can be a value of SAI1 Clock Source.
Definition stm32h7xx_hal_rcc_ex.h:176
RCC_PeriphCLKInitTypeDef::UsbClockSelection
uint32_t UsbClockSelection
Specifies USB clock source This parameter can be a value of RCCEx USB Clock Source.
Definition stm32h7xx_hal_rcc_ex.h:236
RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection
uint32_t Lpuart1ClockSelection
Specifies LPUART1 clock source This parameter can be a value of RCCEx LPUART1 Clock Source.
Definition stm32h7xx_hal_rcc_ex.h:245
RCC_PeriphCLKInitTypeDef::Spi45ClockSelection
uint32_t Spi45ClockSelection
Specifies SPI4/5 clock source This parameter can be a value of SPI4/5 Clock Source.
Definition stm32h7xx_hal_rcc_ex.h:197
RCC_PeriphCLKInitTypeDef::RngClockSelection
uint32_t RngClockSelection
Specifies RNG clock source This parameter can be a value of RCCEx RNG Clock Source.
Definition stm32h7xx_hal_rcc_ex.h:225