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Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...
#include <core_armv81mml.h>
Public Attributes | |
| union { | |
| __OM uint8_t ITM_Type::u8 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More... | |
| __OM uint16_t ITM_Type::u16 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More... | |
| __OM uint32_t ITM_Type::u32 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More... | |
| } | PORT [32U] |
| Offset: 0x000 ( /W) ITM Stimulus Port Registers. | |
| uint32_t | RESERVED0 [864U] |
| __IOM uint32_t | TER |
| Offset: 0xE00 (R/W) ITM Trace Enable Register. | |
| uint32_t | RESERVED1 [15U] |
| __IOM uint32_t | TPR |
| Offset: 0xE40 (R/W) ITM Trace Privilege Register. | |
| uint32_t | RESERVED2 [15U] |
| __IOM uint32_t | TCR |
| Offset: 0xE80 (R/W) ITM Trace Control Register. | |
| uint32_t | RESERVED3 [32U] |
| uint32_t | RESERVED4 [43U] |
| __OM uint32_t | LAR |
| Offset: 0xFB0 ( /W) ITM Lock Access Register. | |
| __IM uint32_t | LSR |
| Offset: 0xFB4 (R/ ) ITM Lock Status Register. | |
| uint32_t | RESERVED5 [1U] |
| __IM uint32_t | DEVARCH |
| Offset: 0xFBC (R/ ) ITM Device Architecture Register. | |
| uint32_t | RESERVED6 [3U] |
| __IM uint32_t | DEVTYPE |
| Offset: 0xFCC (R/ ) ITM Device Type Register. | |
| __IM uint32_t | PID4 |
| Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4. | |
| __IM uint32_t | PID5 |
| Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5. | |
| __IM uint32_t | PID6 |
| Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6. | |
| __IM uint32_t | PID7 |
| Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7. | |
| __IM uint32_t | PID0 |
| Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0. | |
| __IM uint32_t | PID1 |
| Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1. | |
| __IM uint32_t | PID2 |
| Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2. | |
| __IM uint32_t | PID3 |
| Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3. | |
| __IM uint32_t | CID0 |
| Offset: 0xFF0 (R/ ) ITM Component Identification Register #0. | |
| __IM uint32_t | CID1 |
| Offset: 0xFF4 (R/ ) ITM Component Identification Register #1. | |
| __IM uint32_t | CID2 |
| Offset: 0xFF8 (R/ ) ITM Component Identification Register #2. | |
| __IM uint32_t | CID3 |
| Offset: 0xFFC (R/ ) ITM Component Identification Register #3. | |
| union { | |
| __OM uint8_t ITM_Type::u8 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More... | |
| __OM uint16_t ITM_Type::u16 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More... | |
| __OM uint32_t ITM_Type::u32 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More... | |
| } | PORT [32U] |
| Offset: 0x000 ( /W) ITM Stimulus Port Registers. | |
| union { | |
| __OM uint8_t ITM_Type::u8 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More... | |
| __OM uint16_t ITM_Type::u16 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More... | |
| __OM uint32_t ITM_Type::u32 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More... | |
| } | PORT [32U] |
| Offset: 0x000 ( /W) ITM Stimulus Port Registers. | |
| union { | |
| __OM uint8_t ITM_Type::u8 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More... | |
| __OM uint16_t ITM_Type::u16 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More... | |
| __OM uint32_t ITM_Type::u32 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More... | |
| } | PORT [32U] |
| Offset: 0x000 ( /W) ITM Stimulus Port Registers. | |
| union { | |
| __OM uint8_t ITM_Type::u8 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More... | |
| __OM uint16_t ITM_Type::u16 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More... | |
| __OM uint32_t ITM_Type::u32 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More... | |
| } | PORT [32U] |
| Offset: 0x000 ( /W) ITM Stimulus Port Registers. | |
| union { | |
| __OM uint8_t ITM_Type::u8 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More... | |
| __OM uint16_t ITM_Type::u16 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More... | |
| __OM uint32_t ITM_Type::u32 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More... | |
| } | PORT [32U] |
| Offset: 0x000 ( /W) ITM Stimulus Port Registers. | |
| union { | |
| __OM uint8_t ITM_Type::u8 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More... | |
| __OM uint16_t ITM_Type::u16 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More... | |
| __OM uint32_t ITM_Type::u32 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More... | |
| } | PORT [32U] |
| Offset: 0x000 ( /W) ITM Stimulus Port Registers. | |
| union { | |
| __OM uint8_t ITM_Type::u8 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More... | |
| __OM uint16_t ITM_Type::u16 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More... | |
| __OM uint32_t ITM_Type::u32 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More... | |
| } | PORT [32U] |
| Offset: 0x000 ( /W) ITM Stimulus Port Registers. | |
| union { | |
| __OM uint8_t ITM_Type::u8 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More... | |
| __OM uint16_t ITM_Type::u16 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More... | |
| __OM uint32_t ITM_Type::u32 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More... | |
| } | PORT [32U] |
| Offset: 0x000 ( /W) ITM Stimulus Port Registers. | |
| union { | |
| __OM uint8_t ITM_Type::u8 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More... | |
| __OM uint16_t ITM_Type::u16 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More... | |
| __OM uint32_t ITM_Type::u32 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More... | |
| } | PORT [32U] |
| Offset: 0x000 ( /W) ITM Stimulus Port Registers. | |
| union { | |
| __OM uint8_t ITM_Type::u8 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 8-bit. More... | |
| __OM uint16_t ITM_Type::u16 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 16-bit. More... | |
| __OM uint32_t ITM_Type::u32 | |
| Offset: 0x000 ( /W) ITM Stimulus Port 32-bit. More... | |
| } | PORT [32U] |
| Offset: 0x000 ( /W) ITM Stimulus Port Registers. | |
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition at line 1078 of file core_armv81mml.h.