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STAR
Cal STAR — firmware, DAQ server, and engine design
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Type definitions for the Error Banking Registers (ERRBNK). More...
Topics | |
| Processor Configuration Information Registers (IMPLEMENTATION DEFINED) | |
| Type definitions for the Processor Configuration Information Registerss (PRCCFGINF). | |
Classes | |
| struct | ErrBnk_Type |
| Structure type to access the Error Banking Registers (ERRBNK). More... | |
| #define | ERRBNK_IEBR0_SWDEF_Pos 30U |
| ERRBNK IEBR0: SWDEF Position. | |
| #define | ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) |
| ERRBNK IEBR0: SWDEF Mask. | |
| #define | ERRBNK_IEBR0_BANK_Pos 16U |
| ERRBNK IEBR0: BANK Position. | |
| #define | ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) |
| ERRBNK IEBR0: BANK Mask. | |
| #define | ERRBNK_IEBR0_LOCATION_Pos 2U |
| ERRBNK IEBR0: LOCATION Position. | |
| #define | ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) |
| ERRBNK IEBR0: LOCATION Mask. | |
| #define | ERRBNK_IEBR0_LOCKED_Pos 1U |
| ERRBNK IEBR0: LOCKED Position. | |
| #define | ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) |
| ERRBNK IEBR0: LOCKED Mask. | |
| #define | ERRBNK_IEBR0_VALID_Pos 0U |
| ERRBNK IEBR0: VALID Position. | |
| #define | ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) |
| ERRBNK IEBR0: VALID Mask. | |
| #define | ERRBNK_IEBR1_SWDEF_Pos 30U |
| ERRBNK IEBR1: SWDEF Position. | |
| #define | ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) |
| ERRBNK IEBR1: SWDEF Mask. | |
| #define | ERRBNK_IEBR1_BANK_Pos 16U |
| ERRBNK IEBR1: BANK Position. | |
| #define | ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) |
| ERRBNK IEBR1: BANK Mask. | |
| #define | ERRBNK_IEBR1_LOCATION_Pos 2U |
| ERRBNK IEBR1: LOCATION Position. | |
| #define | ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) |
| ERRBNK IEBR1: LOCATION Mask. | |
| #define | ERRBNK_IEBR1_LOCKED_Pos 1U |
| ERRBNK IEBR1: LOCKED Position. | |
| #define | ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) |
| ERRBNK IEBR1: LOCKED Mask. | |
| #define | ERRBNK_IEBR1_VALID_Pos 0U |
| ERRBNK IEBR1: VALID Position. | |
| #define | ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) |
| ERRBNK IEBR1: VALID Mask. | |
| #define | ERRBNK_DEBR0_SWDEF_Pos 30U |
| ERRBNK DEBR0: SWDEF Position. | |
| #define | ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) |
| ERRBNK DEBR0: SWDEF Mask. | |
| #define | ERRBNK_DEBR0_TYPE_Pos 17U |
| ERRBNK DEBR0: TYPE Position. | |
| #define | ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) |
| ERRBNK DEBR0: TYPE Mask. | |
| #define | ERRBNK_DEBR0_BANK_Pos 16U |
| ERRBNK DEBR0: BANK Position. | |
| #define | ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) |
| ERRBNK DEBR0: BANK Mask. | |
| #define | ERRBNK_DEBR0_LOCATION_Pos 2U |
| ERRBNK DEBR0: LOCATION Position. | |
| #define | ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) |
| ERRBNK DEBR0: LOCATION Mask. | |
| #define | ERRBNK_DEBR0_LOCKED_Pos 1U |
| ERRBNK DEBR0: LOCKED Position. | |
| #define | ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) |
| ERRBNK DEBR0: LOCKED Mask. | |
| #define | ERRBNK_DEBR0_VALID_Pos 0U |
| ERRBNK DEBR0: VALID Position. | |
| #define | ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) |
| ERRBNK DEBR0: VALID Mask. | |
| #define | ERRBNK_DEBR1_SWDEF_Pos 30U |
| ERRBNK DEBR1: SWDEF Position. | |
| #define | ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) |
| ERRBNK DEBR1: SWDEF Mask. | |
| #define | ERRBNK_DEBR1_TYPE_Pos 17U |
| ERRBNK DEBR1: TYPE Position. | |
| #define | ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) |
| ERRBNK DEBR1: TYPE Mask. | |
| #define | ERRBNK_DEBR1_BANK_Pos 16U |
| ERRBNK DEBR1: BANK Position. | |
| #define | ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) |
| ERRBNK DEBR1: BANK Mask. | |
| #define | ERRBNK_DEBR1_LOCATION_Pos 2U |
| ERRBNK DEBR1: LOCATION Position. | |
| #define | ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) |
| ERRBNK DEBR1: LOCATION Mask. | |
| #define | ERRBNK_DEBR1_LOCKED_Pos 1U |
| ERRBNK DEBR1: LOCKED Position. | |
| #define | ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) |
| ERRBNK DEBR1: LOCKED Mask. | |
| #define | ERRBNK_DEBR1_VALID_Pos 0U |
| ERRBNK DEBR1: VALID Position. | |
| #define | ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) |
| ERRBNK DEBR1: VALID Mask. | |
| #define | ERRBNK_TEBR0_SWDEF_Pos 30U |
| ERRBNK TEBR0: SWDEF Position. | |
| #define | ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) |
| ERRBNK TEBR0: SWDEF Mask. | |
| #define | ERRBNK_TEBR0_POISON_Pos 28U |
| ERRBNK TEBR0: POISON Position. | |
| #define | ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) |
| ERRBNK TEBR0: POISON Mask. | |
| #define | ERRBNK_TEBR0_TYPE_Pos 27U |
| ERRBNK TEBR0: TYPE Position. | |
| #define | ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) |
| ERRBNK TEBR0: TYPE Mask. | |
| #define | ERRBNK_TEBR0_BANK_Pos 24U |
| ERRBNK TEBR0: BANK Position. | |
| #define | ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) |
| ERRBNK TEBR0: BANK Mask. | |
| #define | ERRBNK_TEBR0_LOCATION_Pos 2U |
| ERRBNK TEBR0: LOCATION Position. | |
| #define | ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) |
| ERRBNK TEBR0: LOCATION Mask. | |
| #define | ERRBNK_TEBR0_LOCKED_Pos 1U |
| ERRBNK TEBR0: LOCKED Position. | |
| #define | ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) |
| ERRBNK TEBR0: LOCKED Mask. | |
| #define | ERRBNK_TEBR0_VALID_Pos 0U |
| ERRBNK TEBR0: VALID Position. | |
| #define | ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) |
| ERRBNK TEBR0: VALID Mask. | |
| #define | ERRBNK_TEBR1_SWDEF_Pos 30U |
| ERRBNK TEBR1: SWDEF Position. | |
| #define | ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) |
| ERRBNK TEBR1: SWDEF Mask. | |
| #define | ERRBNK_TEBR1_POISON_Pos 28U |
| ERRBNK TEBR1: POISON Position. | |
| #define | ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) |
| ERRBNK TEBR1: POISON Mask. | |
| #define | ERRBNK_TEBR1_TYPE_Pos 27U |
| ERRBNK TEBR1: TYPE Position. | |
| #define | ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) |
| ERRBNK TEBR1: TYPE Mask. | |
| #define | ERRBNK_TEBR1_BANK_Pos 24U |
| ERRBNK TEBR1: BANK Position. | |
| #define | ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) |
| ERRBNK TEBR1: BANK Mask. | |
| #define | ERRBNK_TEBR1_LOCATION_Pos 2U |
| ERRBNK TEBR1: LOCATION Position. | |
| #define | ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) |
| ERRBNK TEBR1: LOCATION Mask. | |
| #define | ERRBNK_TEBR1_LOCKED_Pos 1U |
| ERRBNK TEBR1: LOCKED Position. | |
| #define | ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) |
| ERRBNK TEBR1: LOCKED Mask. | |
| #define | ERRBNK_TEBR1_VALID_Pos 0U |
| ERRBNK TEBR1: VALID Position. | |
| #define | ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) |
| ERRBNK TEBR1: VALID Mask. | |
| #define | ERRBNK_IEBR0_SWDEF_Pos 30U |
| ERRBNK IEBR0: SWDEF Position. | |
| #define | ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) |
| ERRBNK IEBR0: SWDEF Mask. | |
| #define | ERRBNK_IEBR0_BANK_Pos 16U |
| ERRBNK IEBR0: BANK Position. | |
| #define | ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) |
| ERRBNK IEBR0: BANK Mask. | |
| #define | ERRBNK_IEBR0_LOCATION_Pos 2U |
| ERRBNK IEBR0: LOCATION Position. | |
| #define | ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) |
| ERRBNK IEBR0: LOCATION Mask. | |
| #define | ERRBNK_IEBR0_LOCKED_Pos 1U |
| ERRBNK IEBR0: LOCKED Position. | |
| #define | ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) |
| ERRBNK IEBR0: LOCKED Mask. | |
| #define | ERRBNK_IEBR0_VALID_Pos 0U |
| ERRBNK IEBR0: VALID Position. | |
| #define | ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) |
| ERRBNK IEBR0: VALID Mask. | |
| #define | ERRBNK_IEBR1_SWDEF_Pos 30U |
| ERRBNK IEBR1: SWDEF Position. | |
| #define | ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) |
| ERRBNK IEBR1: SWDEF Mask. | |
| #define | ERRBNK_IEBR1_BANK_Pos 16U |
| ERRBNK IEBR1: BANK Position. | |
| #define | ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) |
| ERRBNK IEBR1: BANK Mask. | |
| #define | ERRBNK_IEBR1_LOCATION_Pos 2U |
| ERRBNK IEBR1: LOCATION Position. | |
| #define | ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) |
| ERRBNK IEBR1: LOCATION Mask. | |
| #define | ERRBNK_IEBR1_LOCKED_Pos 1U |
| ERRBNK IEBR1: LOCKED Position. | |
| #define | ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) |
| ERRBNK IEBR1: LOCKED Mask. | |
| #define | ERRBNK_IEBR1_VALID_Pos 0U |
| ERRBNK IEBR1: VALID Position. | |
| #define | ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) |
| ERRBNK IEBR1: VALID Mask. | |
| #define | ERRBNK_DEBR0_SWDEF_Pos 30U |
| ERRBNK DEBR0: SWDEF Position. | |
| #define | ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) |
| ERRBNK DEBR0: SWDEF Mask. | |
| #define | ERRBNK_DEBR0_TYPE_Pos 17U |
| ERRBNK DEBR0: TYPE Position. | |
| #define | ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) |
| ERRBNK DEBR0: TYPE Mask. | |
| #define | ERRBNK_DEBR0_BANK_Pos 16U |
| ERRBNK DEBR0: BANK Position. | |
| #define | ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) |
| ERRBNK DEBR0: BANK Mask. | |
| #define | ERRBNK_DEBR0_LOCATION_Pos 2U |
| ERRBNK DEBR0: LOCATION Position. | |
| #define | ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) |
| ERRBNK DEBR0: LOCATION Mask. | |
| #define | ERRBNK_DEBR0_LOCKED_Pos 1U |
| ERRBNK DEBR0: LOCKED Position. | |
| #define | ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) |
| ERRBNK DEBR0: LOCKED Mask. | |
| #define | ERRBNK_DEBR0_VALID_Pos 0U |
| ERRBNK DEBR0: VALID Position. | |
| #define | ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) |
| ERRBNK DEBR0: VALID Mask. | |
| #define | ERRBNK_DEBR1_SWDEF_Pos 30U |
| ERRBNK DEBR1: SWDEF Position. | |
| #define | ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) |
| ERRBNK DEBR1: SWDEF Mask. | |
| #define | ERRBNK_DEBR1_TYPE_Pos 17U |
| ERRBNK DEBR1: TYPE Position. | |
| #define | ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) |
| ERRBNK DEBR1: TYPE Mask. | |
| #define | ERRBNK_DEBR1_BANK_Pos 16U |
| ERRBNK DEBR1: BANK Position. | |
| #define | ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) |
| ERRBNK DEBR1: BANK Mask. | |
| #define | ERRBNK_DEBR1_LOCATION_Pos 2U |
| ERRBNK DEBR1: LOCATION Position. | |
| #define | ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) |
| ERRBNK DEBR1: LOCATION Mask. | |
| #define | ERRBNK_DEBR1_LOCKED_Pos 1U |
| ERRBNK DEBR1: LOCKED Position. | |
| #define | ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) |
| ERRBNK DEBR1: LOCKED Mask. | |
| #define | ERRBNK_DEBR1_VALID_Pos 0U |
| ERRBNK DEBR1: VALID Position. | |
| #define | ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) |
| ERRBNK DEBR1: VALID Mask. | |
| #define | ERRBNK_TEBR0_SWDEF_Pos 30U |
| ERRBNK TEBR0: SWDEF Position. | |
| #define | ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) |
| ERRBNK TEBR0: SWDEF Mask. | |
| #define | ERRBNK_TEBR0_POISON_Pos 28U |
| ERRBNK TEBR0: POISON Position. | |
| #define | ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) |
| ERRBNK TEBR0: POISON Mask. | |
| #define | ERRBNK_TEBR0_TYPE_Pos 27U |
| ERRBNK TEBR0: TYPE Position. | |
| #define | ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) |
| ERRBNK TEBR0: TYPE Mask. | |
| #define | ERRBNK_TEBR0_BANK_Pos 24U |
| ERRBNK TEBR0: BANK Position. | |
| #define | ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) |
| ERRBNK TEBR0: BANK Mask. | |
| #define | ERRBNK_TEBR0_LOCATION_Pos 2U |
| ERRBNK TEBR0: LOCATION Position. | |
| #define | ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) |
| ERRBNK TEBR0: LOCATION Mask. | |
| #define | ERRBNK_TEBR0_LOCKED_Pos 1U |
| ERRBNK TEBR0: LOCKED Position. | |
| #define | ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) |
| ERRBNK TEBR0: LOCKED Mask. | |
| #define | ERRBNK_TEBR0_VALID_Pos 0U |
| ERRBNK TEBR0: VALID Position. | |
| #define | ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) |
| ERRBNK TEBR0: VALID Mask. | |
| #define | ERRBNK_TEBR1_SWDEF_Pos 30U |
| ERRBNK TEBR1: SWDEF Position. | |
| #define | ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) |
| ERRBNK TEBR1: SWDEF Mask. | |
| #define | ERRBNK_TEBR1_POISON_Pos 28U |
| ERRBNK TEBR1: POISON Position. | |
| #define | ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) |
| ERRBNK TEBR1: POISON Mask. | |
| #define | ERRBNK_TEBR1_TYPE_Pos 27U |
| ERRBNK TEBR1: TYPE Position. | |
| #define | ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) |
| ERRBNK TEBR1: TYPE Mask. | |
| #define | ERRBNK_TEBR1_BANK_Pos 24U |
| ERRBNK TEBR1: BANK Position. | |
| #define | ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) |
| ERRBNK TEBR1: BANK Mask. | |
| #define | ERRBNK_TEBR1_LOCATION_Pos 2U |
| ERRBNK TEBR1: LOCATION Position. | |
| #define | ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) |
| ERRBNK TEBR1: LOCATION Mask. | |
| #define | ERRBNK_TEBR1_LOCKED_Pos 1U |
| ERRBNK TEBR1: LOCKED Position. | |
| #define | ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) |
| ERRBNK TEBR1: LOCKED Mask. | |
| #define | ERRBNK_TEBR1_VALID_Pos 0U |
| ERRBNK TEBR1: VALID Position. | |
| #define | ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) |
| ERRBNK TEBR1: VALID Mask. | |
Type definitions for the Error Banking Registers (ERRBNK).
| #define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) |
ERRBNK DEBR0: BANK Mask.
Definition at line 1668 of file core_cm55.h.
| #define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) |
ERRBNK DEBR0: BANK Mask.
Definition at line 1655 of file core_cm85.h.
| #define ERRBNK_DEBR0_BANK_Pos 16U |
ERRBNK DEBR0: BANK Position.
Definition at line 1667 of file core_cm55.h.
| #define ERRBNK_DEBR0_BANK_Pos 16U |
ERRBNK DEBR0: BANK Position.
Definition at line 1654 of file core_cm85.h.
| #define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) |
ERRBNK DEBR0: LOCATION Mask.
Definition at line 1671 of file core_cm55.h.
| #define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) |
ERRBNK DEBR0: LOCATION Mask.
Definition at line 1658 of file core_cm85.h.
| #define ERRBNK_DEBR0_LOCATION_Pos 2U |
ERRBNK DEBR0: LOCATION Position.
Definition at line 1670 of file core_cm55.h.
| #define ERRBNK_DEBR0_LOCATION_Pos 2U |
ERRBNK DEBR0: LOCATION Position.
Definition at line 1657 of file core_cm85.h.
| #define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) |
ERRBNK DEBR0: LOCKED Mask.
Definition at line 1674 of file core_cm55.h.
| #define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) |
ERRBNK DEBR0: LOCKED Mask.
Definition at line 1661 of file core_cm85.h.
| #define ERRBNK_DEBR0_LOCKED_Pos 1U |
ERRBNK DEBR0: LOCKED Position.
Definition at line 1673 of file core_cm55.h.
| #define ERRBNK_DEBR0_LOCKED_Pos 1U |
ERRBNK DEBR0: LOCKED Position.
Definition at line 1660 of file core_cm85.h.
| #define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) |
ERRBNK DEBR0: SWDEF Mask.
Definition at line 1662 of file core_cm55.h.
| #define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) |
ERRBNK DEBR0: SWDEF Mask.
Definition at line 1649 of file core_cm85.h.
| #define ERRBNK_DEBR0_SWDEF_Pos 30U |
ERRBNK DEBR0: SWDEF Position.
Definition at line 1661 of file core_cm55.h.
| #define ERRBNK_DEBR0_SWDEF_Pos 30U |
ERRBNK DEBR0: SWDEF Position.
Definition at line 1648 of file core_cm85.h.
| #define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) |
ERRBNK DEBR0: TYPE Mask.
Definition at line 1665 of file core_cm55.h.
| #define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) |
ERRBNK DEBR0: TYPE Mask.
Definition at line 1652 of file core_cm85.h.
| #define ERRBNK_DEBR0_TYPE_Pos 17U |
ERRBNK DEBR0: TYPE Position.
Definition at line 1664 of file core_cm55.h.
| #define ERRBNK_DEBR0_TYPE_Pos 17U |
ERRBNK DEBR0: TYPE Position.
Definition at line 1651 of file core_cm85.h.
| #define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) |
ERRBNK DEBR0: VALID Mask.
Definition at line 1677 of file core_cm55.h.
| #define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) |
ERRBNK DEBR0: VALID Mask.
Definition at line 1664 of file core_cm85.h.
| #define ERRBNK_DEBR0_VALID_Pos 0U |
ERRBNK DEBR0: VALID Position.
Definition at line 1676 of file core_cm55.h.
| #define ERRBNK_DEBR0_VALID_Pos 0U |
ERRBNK DEBR0: VALID Position.
Definition at line 1663 of file core_cm85.h.
| #define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) |
ERRBNK DEBR1: BANK Mask.
Definition at line 1687 of file core_cm55.h.
| #define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) |
ERRBNK DEBR1: BANK Mask.
Definition at line 1674 of file core_cm85.h.
| #define ERRBNK_DEBR1_BANK_Pos 16U |
ERRBNK DEBR1: BANK Position.
Definition at line 1686 of file core_cm55.h.
| #define ERRBNK_DEBR1_BANK_Pos 16U |
ERRBNK DEBR1: BANK Position.
Definition at line 1673 of file core_cm85.h.
| #define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) |
ERRBNK DEBR1: LOCATION Mask.
Definition at line 1690 of file core_cm55.h.
| #define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) |
ERRBNK DEBR1: LOCATION Mask.
Definition at line 1677 of file core_cm85.h.
| #define ERRBNK_DEBR1_LOCATION_Pos 2U |
ERRBNK DEBR1: LOCATION Position.
Definition at line 1689 of file core_cm55.h.
| #define ERRBNK_DEBR1_LOCATION_Pos 2U |
ERRBNK DEBR1: LOCATION Position.
Definition at line 1676 of file core_cm85.h.
| #define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) |
ERRBNK DEBR1: LOCKED Mask.
Definition at line 1693 of file core_cm55.h.
| #define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) |
ERRBNK DEBR1: LOCKED Mask.
Definition at line 1680 of file core_cm85.h.
| #define ERRBNK_DEBR1_LOCKED_Pos 1U |
ERRBNK DEBR1: LOCKED Position.
Definition at line 1692 of file core_cm55.h.
| #define ERRBNK_DEBR1_LOCKED_Pos 1U |
ERRBNK DEBR1: LOCKED Position.
Definition at line 1679 of file core_cm85.h.
| #define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) |
ERRBNK DEBR1: SWDEF Mask.
Definition at line 1681 of file core_cm55.h.
| #define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) |
ERRBNK DEBR1: SWDEF Mask.
Definition at line 1668 of file core_cm85.h.
| #define ERRBNK_DEBR1_SWDEF_Pos 30U |
ERRBNK DEBR1: SWDEF Position.
Definition at line 1680 of file core_cm55.h.
| #define ERRBNK_DEBR1_SWDEF_Pos 30U |
ERRBNK DEBR1: SWDEF Position.
Definition at line 1667 of file core_cm85.h.
| #define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) |
ERRBNK DEBR1: TYPE Mask.
Definition at line 1684 of file core_cm55.h.
| #define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) |
ERRBNK DEBR1: TYPE Mask.
Definition at line 1671 of file core_cm85.h.
| #define ERRBNK_DEBR1_TYPE_Pos 17U |
ERRBNK DEBR1: TYPE Position.
Definition at line 1683 of file core_cm55.h.
| #define ERRBNK_DEBR1_TYPE_Pos 17U |
ERRBNK DEBR1: TYPE Position.
Definition at line 1670 of file core_cm85.h.
| #define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) |
ERRBNK DEBR1: VALID Mask.
Definition at line 1696 of file core_cm55.h.
| #define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) |
ERRBNK DEBR1: VALID Mask.
Definition at line 1683 of file core_cm85.h.
| #define ERRBNK_DEBR1_VALID_Pos 0U |
ERRBNK DEBR1: VALID Position.
Definition at line 1695 of file core_cm55.h.
| #define ERRBNK_DEBR1_VALID_Pos 0U |
ERRBNK DEBR1: VALID Position.
Definition at line 1682 of file core_cm85.h.
| #define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) |
ERRBNK IEBR0: BANK Mask.
Definition at line 1633 of file core_cm55.h.
| #define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) |
ERRBNK IEBR0: BANK Mask.
Definition at line 1620 of file core_cm85.h.
| #define ERRBNK_IEBR0_BANK_Pos 16U |
ERRBNK IEBR0: BANK Position.
Definition at line 1632 of file core_cm55.h.
| #define ERRBNK_IEBR0_BANK_Pos 16U |
ERRBNK IEBR0: BANK Position.
Definition at line 1619 of file core_cm85.h.
| #define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) |
ERRBNK IEBR0: LOCATION Mask.
Definition at line 1636 of file core_cm55.h.
| #define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) |
ERRBNK IEBR0: LOCATION Mask.
Definition at line 1623 of file core_cm85.h.
| #define ERRBNK_IEBR0_LOCATION_Pos 2U |
ERRBNK IEBR0: LOCATION Position.
Definition at line 1635 of file core_cm55.h.
| #define ERRBNK_IEBR0_LOCATION_Pos 2U |
ERRBNK IEBR0: LOCATION Position.
Definition at line 1622 of file core_cm85.h.
| #define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) |
ERRBNK IEBR0: LOCKED Mask.
Definition at line 1639 of file core_cm55.h.
| #define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) |
ERRBNK IEBR0: LOCKED Mask.
Definition at line 1626 of file core_cm85.h.
| #define ERRBNK_IEBR0_LOCKED_Pos 1U |
ERRBNK IEBR0: LOCKED Position.
Definition at line 1638 of file core_cm55.h.
| #define ERRBNK_IEBR0_LOCKED_Pos 1U |
ERRBNK IEBR0: LOCKED Position.
Definition at line 1625 of file core_cm85.h.
| #define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) |
ERRBNK IEBR0: SWDEF Mask.
Definition at line 1630 of file core_cm55.h.
| #define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) |
ERRBNK IEBR0: SWDEF Mask.
Definition at line 1617 of file core_cm85.h.
| #define ERRBNK_IEBR0_SWDEF_Pos 30U |
ERRBNK IEBR0: SWDEF Position.
Definition at line 1629 of file core_cm55.h.
| #define ERRBNK_IEBR0_SWDEF_Pos 30U |
ERRBNK IEBR0: SWDEF Position.
Definition at line 1616 of file core_cm85.h.
| #define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) |
ERRBNK IEBR0: VALID Mask.
Definition at line 1642 of file core_cm55.h.
| #define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) |
ERRBNK IEBR0: VALID Mask.
Definition at line 1629 of file core_cm85.h.
| #define ERRBNK_IEBR0_VALID_Pos 0U |
ERRBNK IEBR0: VALID Position.
Definition at line 1641 of file core_cm55.h.
| #define ERRBNK_IEBR0_VALID_Pos 0U |
ERRBNK IEBR0: VALID Position.
Definition at line 1628 of file core_cm85.h.
| #define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) |
ERRBNK IEBR1: BANK Mask.
Definition at line 1649 of file core_cm55.h.
| #define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) |
ERRBNK IEBR1: BANK Mask.
Definition at line 1636 of file core_cm85.h.
| #define ERRBNK_IEBR1_BANK_Pos 16U |
ERRBNK IEBR1: BANK Position.
Definition at line 1648 of file core_cm55.h.
| #define ERRBNK_IEBR1_BANK_Pos 16U |
ERRBNK IEBR1: BANK Position.
Definition at line 1635 of file core_cm85.h.
| #define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) |
ERRBNK IEBR1: LOCATION Mask.
Definition at line 1652 of file core_cm55.h.
| #define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) |
ERRBNK IEBR1: LOCATION Mask.
Definition at line 1639 of file core_cm85.h.
| #define ERRBNK_IEBR1_LOCATION_Pos 2U |
ERRBNK IEBR1: LOCATION Position.
Definition at line 1651 of file core_cm55.h.
| #define ERRBNK_IEBR1_LOCATION_Pos 2U |
ERRBNK IEBR1: LOCATION Position.
Definition at line 1638 of file core_cm85.h.
| #define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) |
ERRBNK IEBR1: LOCKED Mask.
Definition at line 1655 of file core_cm55.h.
| #define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) |
ERRBNK IEBR1: LOCKED Mask.
Definition at line 1642 of file core_cm85.h.
| #define ERRBNK_IEBR1_LOCKED_Pos 1U |
ERRBNK IEBR1: LOCKED Position.
Definition at line 1654 of file core_cm55.h.
| #define ERRBNK_IEBR1_LOCKED_Pos 1U |
ERRBNK IEBR1: LOCKED Position.
Definition at line 1641 of file core_cm85.h.
| #define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) |
ERRBNK IEBR1: SWDEF Mask.
Definition at line 1646 of file core_cm55.h.
| #define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) |
ERRBNK IEBR1: SWDEF Mask.
Definition at line 1633 of file core_cm85.h.
| #define ERRBNK_IEBR1_SWDEF_Pos 30U |
ERRBNK IEBR1: SWDEF Position.
Definition at line 1645 of file core_cm55.h.
| #define ERRBNK_IEBR1_SWDEF_Pos 30U |
ERRBNK IEBR1: SWDEF Position.
Definition at line 1632 of file core_cm85.h.
| #define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) |
ERRBNK IEBR1: VALID Mask.
Definition at line 1658 of file core_cm55.h.
| #define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) |
ERRBNK IEBR1: VALID Mask.
Definition at line 1645 of file core_cm85.h.
| #define ERRBNK_IEBR1_VALID_Pos 0U |
ERRBNK IEBR1: VALID Position.
Definition at line 1657 of file core_cm55.h.
| #define ERRBNK_IEBR1_VALID_Pos 0U |
ERRBNK IEBR1: VALID Position.
Definition at line 1644 of file core_cm85.h.
| #define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) |
ERRBNK TEBR0: BANK Mask.
Definition at line 1709 of file core_cm55.h.
| #define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) |
ERRBNK TEBR0: BANK Mask.
Definition at line 1696 of file core_cm85.h.
| #define ERRBNK_TEBR0_BANK_Pos 24U |
ERRBNK TEBR0: BANK Position.
Definition at line 1708 of file core_cm55.h.
| #define ERRBNK_TEBR0_BANK_Pos 24U |
ERRBNK TEBR0: BANK Position.
Definition at line 1695 of file core_cm85.h.
| #define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) |
ERRBNK TEBR0: LOCATION Mask.
Definition at line 1712 of file core_cm55.h.
| #define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) |
ERRBNK TEBR0: LOCATION Mask.
Definition at line 1699 of file core_cm85.h.
| #define ERRBNK_TEBR0_LOCATION_Pos 2U |
ERRBNK TEBR0: LOCATION Position.
Definition at line 1711 of file core_cm55.h.
| #define ERRBNK_TEBR0_LOCATION_Pos 2U |
ERRBNK TEBR0: LOCATION Position.
Definition at line 1698 of file core_cm85.h.
| #define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) |
ERRBNK TEBR0: LOCKED Mask.
Definition at line 1715 of file core_cm55.h.
| #define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) |
ERRBNK TEBR0: LOCKED Mask.
Definition at line 1702 of file core_cm85.h.
| #define ERRBNK_TEBR0_LOCKED_Pos 1U |
ERRBNK TEBR0: LOCKED Position.
Definition at line 1714 of file core_cm55.h.
| #define ERRBNK_TEBR0_LOCKED_Pos 1U |
ERRBNK TEBR0: LOCKED Position.
Definition at line 1701 of file core_cm85.h.
| #define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) |
ERRBNK TEBR0: POISON Mask.
Definition at line 1703 of file core_cm55.h.
| #define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) |
ERRBNK TEBR0: POISON Mask.
Definition at line 1690 of file core_cm85.h.
| #define ERRBNK_TEBR0_POISON_Pos 28U |
ERRBNK TEBR0: POISON Position.
Definition at line 1702 of file core_cm55.h.
| #define ERRBNK_TEBR0_POISON_Pos 28U |
ERRBNK TEBR0: POISON Position.
Definition at line 1689 of file core_cm85.h.
| #define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) |
ERRBNK TEBR0: SWDEF Mask.
Definition at line 1700 of file core_cm55.h.
| #define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) |
ERRBNK TEBR0: SWDEF Mask.
Definition at line 1687 of file core_cm85.h.
| #define ERRBNK_TEBR0_SWDEF_Pos 30U |
ERRBNK TEBR0: SWDEF Position.
Definition at line 1699 of file core_cm55.h.
| #define ERRBNK_TEBR0_SWDEF_Pos 30U |
ERRBNK TEBR0: SWDEF Position.
Definition at line 1686 of file core_cm85.h.
| #define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) |
ERRBNK TEBR0: TYPE Mask.
Definition at line 1706 of file core_cm55.h.
| #define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) |
ERRBNK TEBR0: TYPE Mask.
Definition at line 1693 of file core_cm85.h.
| #define ERRBNK_TEBR0_TYPE_Pos 27U |
ERRBNK TEBR0: TYPE Position.
Definition at line 1705 of file core_cm55.h.
| #define ERRBNK_TEBR0_TYPE_Pos 27U |
ERRBNK TEBR0: TYPE Position.
Definition at line 1692 of file core_cm85.h.
| #define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) |
ERRBNK TEBR0: VALID Mask.
Definition at line 1718 of file core_cm55.h.
| #define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) |
ERRBNK TEBR0: VALID Mask.
Definition at line 1705 of file core_cm85.h.
| #define ERRBNK_TEBR0_VALID_Pos 0U |
ERRBNK TEBR0: VALID Position.
Definition at line 1717 of file core_cm55.h.
| #define ERRBNK_TEBR0_VALID_Pos 0U |
ERRBNK TEBR0: VALID Position.
Definition at line 1704 of file core_cm85.h.
| #define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) |
ERRBNK TEBR1: BANK Mask.
Definition at line 1731 of file core_cm55.h.
| #define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) |
ERRBNK TEBR1: BANK Mask.
Definition at line 1718 of file core_cm85.h.
| #define ERRBNK_TEBR1_BANK_Pos 24U |
ERRBNK TEBR1: BANK Position.
Definition at line 1730 of file core_cm55.h.
| #define ERRBNK_TEBR1_BANK_Pos 24U |
ERRBNK TEBR1: BANK Position.
Definition at line 1717 of file core_cm85.h.
| #define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) |
ERRBNK TEBR1: LOCATION Mask.
Definition at line 1734 of file core_cm55.h.
| #define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) |
ERRBNK TEBR1: LOCATION Mask.
Definition at line 1721 of file core_cm85.h.
| #define ERRBNK_TEBR1_LOCATION_Pos 2U |
ERRBNK TEBR1: LOCATION Position.
Definition at line 1733 of file core_cm55.h.
| #define ERRBNK_TEBR1_LOCATION_Pos 2U |
ERRBNK TEBR1: LOCATION Position.
Definition at line 1720 of file core_cm85.h.
| #define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) |
ERRBNK TEBR1: LOCKED Mask.
Definition at line 1737 of file core_cm55.h.
| #define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) |
ERRBNK TEBR1: LOCKED Mask.
Definition at line 1724 of file core_cm85.h.
| #define ERRBNK_TEBR1_LOCKED_Pos 1U |
ERRBNK TEBR1: LOCKED Position.
Definition at line 1736 of file core_cm55.h.
| #define ERRBNK_TEBR1_LOCKED_Pos 1U |
ERRBNK TEBR1: LOCKED Position.
Definition at line 1723 of file core_cm85.h.
| #define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) |
ERRBNK TEBR1: POISON Mask.
Definition at line 1725 of file core_cm55.h.
| #define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) |
ERRBNK TEBR1: POISON Mask.
Definition at line 1712 of file core_cm85.h.
| #define ERRBNK_TEBR1_POISON_Pos 28U |
ERRBNK TEBR1: POISON Position.
Definition at line 1724 of file core_cm55.h.
| #define ERRBNK_TEBR1_POISON_Pos 28U |
ERRBNK TEBR1: POISON Position.
Definition at line 1711 of file core_cm85.h.
| #define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) |
ERRBNK TEBR1: SWDEF Mask.
Definition at line 1722 of file core_cm55.h.
| #define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) |
ERRBNK TEBR1: SWDEF Mask.
Definition at line 1709 of file core_cm85.h.
| #define ERRBNK_TEBR1_SWDEF_Pos 30U |
ERRBNK TEBR1: SWDEF Position.
Definition at line 1721 of file core_cm55.h.
| #define ERRBNK_TEBR1_SWDEF_Pos 30U |
ERRBNK TEBR1: SWDEF Position.
Definition at line 1708 of file core_cm85.h.
| #define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) |
ERRBNK TEBR1: TYPE Mask.
Definition at line 1728 of file core_cm55.h.
| #define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) |
ERRBNK TEBR1: TYPE Mask.
Definition at line 1715 of file core_cm85.h.
| #define ERRBNK_TEBR1_TYPE_Pos 27U |
ERRBNK TEBR1: TYPE Position.
Definition at line 1727 of file core_cm55.h.
| #define ERRBNK_TEBR1_TYPE_Pos 27U |
ERRBNK TEBR1: TYPE Position.
Definition at line 1714 of file core_cm85.h.
| #define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) |
ERRBNK TEBR1: VALID Mask.
Definition at line 1740 of file core_cm55.h.
| #define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) |
ERRBNK TEBR1: VALID Mask.
Definition at line 1727 of file core_cm85.h.
| #define ERRBNK_TEBR1_VALID_Pos 0U |
ERRBNK TEBR1: VALID Position.
Definition at line 1739 of file core_cm55.h.
| #define ERRBNK_TEBR1_VALID_Pos 0U |
ERRBNK TEBR1: VALID Position.
Definition at line 1726 of file core_cm85.h.