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Structure type to access the Error Banking Registers (ERRBNK). More...

#include <core_cm55.h>

Public Attributes

__IOM uint32_t IEBR0
 Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0.
__IOM uint32_t IEBR1
 Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1.
uint32_t RESERVED0 [2U]
__IOM uint32_t DEBR0
 Offset: 0x010 (R/W) Data Cache Error Bank Register 0.
__IOM uint32_t DEBR1
 Offset: 0x014 (R/W) Data Cache Error Bank Register 1.
uint32_t RESERVED1 [2U]
__IOM uint32_t TEBR0
 Offset: 0x020 (R/W) TCM Error Bank Register 0.
uint32_t RESERVED2 [1U]
__IOM uint32_t TEBR1
 Offset: 0x028 (R/W) TCM Error Bank Register 1.

Detailed Description

Structure type to access the Error Banking Registers (ERRBNK).

Definition at line 1615 of file core_cm55.h.


The documentation for this struct was generated from the following files:
  • firmware/Flight_Computer/Drivers/CMSIS/Include/core_cm55.h
  • firmware/Flight_Computer/Drivers/CMSIS/Include/core_cm85.h