CMSIS Cortex-M85 Core Peripheral Access Layer Header File. More...

#include <stdint.h>
#include "cmsis_version.h"
#include "cmsis_compiler.h"
#include "mpu_armv8.h"
#include "cachel1_armv7.h"

Include dependency graph for core_cm85.h:

Classes
union	APSR_Type
	Union type to access the Application Program Status Register (APSR). More...
union	IPSR_Type
	Union type to access the Interrupt Program Status Register (IPSR). More...
union	xPSR_Type
	Union type to access the Special-Purpose Program Status Registers (xPSR). More...
union	CONTROL_Type
	Union type to access the Control Registers (CONTROL). More...
struct	NVIC_Type
	Structure type to access the Nested Vectored Interrupt Controller (NVIC). More...
struct	SCB_Type
	Structure type to access the System Control Block (SCB). More...
struct	ICB_Type
	Structure type to access the Implementation Control Block (ICB). More...
struct	SysTick_Type
	Structure type to access the System Timer (SysTick). More...
struct	ITM_Type
	Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...
struct	DWT_Type
	Structure type to access the Data Watchpoint and Trace Register (DWT). More...
struct	MemSysCtl_Type
	Structure type to access the Memory System Control Registers (MEMSYSCTL). More...
struct	PwrModCtl_Type
	Structure type to access the Power Mode Control Registers (PWRMODCTL). More...
struct	EWIC_Type
	Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). More...
struct	ErrBnk_Type
	Structure type to access the Error Banking Registers (ERRBNK). More...
struct	PrcCfgInf_Type
	Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). More...
struct	TPI_Type
	Structure type to access the Trace Port Interface Register (TPI). More...
struct	MPU_Type
	Structure type to access the Memory Protection Unit (MPU). More...
struct	FPU_Type
	Structure type to access the Floating Point Unit (FPU). More...
struct	CoreDebug_Type
	Structure type to access the Core Debug Register (CoreDebug). More...
struct	DCB_Type
	Structure type to access the Debug Control Block Registers (DCB). More...
struct	DIB_Type
	Structure type to access the Debug Identification Block Registers (DIB). More...

Macros
#define	__CORE_CM85_H_GENERIC

#define	APSR_N_Pos 31U
	APSR: N Position.
#define	APSR_N_Msk (1UL << APSR_N_Pos)
	APSR: N Mask.
#define	APSR_Z_Pos 30U
	APSR: Z Position.
#define	APSR_Z_Msk (1UL << APSR_Z_Pos)
	APSR: Z Mask.
#define	APSR_C_Pos 29U
	APSR: C Position.
#define	APSR_C_Msk (1UL << APSR_C_Pos)
	APSR: C Mask.
#define	APSR_V_Pos 28U
	APSR: V Position.
#define	APSR_V_Msk (1UL << APSR_V_Pos)
	APSR: V Mask.
#define	APSR_Q_Pos 27U
	APSR: Q Position.
#define	APSR_Q_Msk (1UL << APSR_Q_Pos)
	APSR: Q Mask.
#define	APSR_GE_Pos 16U
	APSR: GE Position.
#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)
	APSR: GE Mask.
#define	IPSR_ISR_Pos 0U
	IPSR: ISR Position.
#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)
	IPSR: ISR Mask.
#define	xPSR_N_Pos 31U
	xPSR: N Position
#define	xPSR_N_Msk (1UL << xPSR_N_Pos)
	xPSR: N Mask
#define	xPSR_Z_Pos 30U
	xPSR: Z Position
#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)
	xPSR: Z Mask
#define	xPSR_C_Pos 29U
	xPSR: C Position
#define	xPSR_C_Msk (1UL << xPSR_C_Pos)
	xPSR: C Mask
#define	xPSR_V_Pos 28U
	xPSR: V Position
#define	xPSR_V_Msk (1UL << xPSR_V_Pos)
	xPSR: V Mask
#define	xPSR_Q_Pos 27U
	xPSR: Q Position
#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)
	xPSR: Q Mask
#define	xPSR_IT_Pos 25U
	xPSR: IT Position
#define	xPSR_IT_Msk (3UL << xPSR_IT_Pos)
	xPSR: IT Mask
#define	xPSR_T_Pos 24U
	xPSR: T Position
#define	xPSR_T_Msk (1UL << xPSR_T_Pos)
	xPSR: T Mask
#define	xPSR_GE_Pos 16U
	xPSR: GE Position
#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
	xPSR: GE Mask
#define	xPSR_ISR_Pos 0U
	xPSR: ISR Position
#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)
	xPSR: ISR Mask
#define	CONTROL_SFPA_Pos 3U
	CONTROL: SFPA Position.
#define	CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)
	CONTROL: SFPA Mask.
#define	CONTROL_FPCA_Pos 2U
	CONTROL: FPCA Position.
#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
	CONTROL: FPCA Mask.
#define	CONTROL_SPSEL_Pos 1U
	CONTROL: SPSEL Position.
#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
	CONTROL: SPSEL Mask.
#define	CONTROL_nPRIV_Pos 0U
	CONTROL: nPRIV Position.
#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)
	CONTROL: nPRIV Mask.
#define	NVIC_STIR_INTID_Pos 0U
	STIR: INTLINESNUM Position.
#define	NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/)
	STIR: INTLINESNUM Mask.
#define	SCB_CPUID_IMPLEMENTER_Pos 24U
	SCB CPUID: IMPLEMENTER Position.
#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
	SCB CPUID: IMPLEMENTER Mask.
#define	SCB_CPUID_VARIANT_Pos 20U
	SCB CPUID: VARIANT Position.
#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
	SCB CPUID: VARIANT Mask.
#define	SCB_CPUID_ARCHITECTURE_Pos 16U
	SCB CPUID: ARCHITECTURE Position.
#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
	SCB CPUID: ARCHITECTURE Mask.
#define	SCB_CPUID_PARTNO_Pos 4U
	SCB CPUID: PARTNO Position.
#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
	SCB CPUID: PARTNO Mask.
#define	SCB_CPUID_REVISION_Pos 0U
	SCB CPUID: REVISION Position.
#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)
	SCB CPUID: REVISION Mask.
#define	SCB_ICSR_PENDNMISET_Pos 31U
	SCB ICSR: PENDNMISET Position.
#define	SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)
	SCB ICSR: PENDNMISET Mask.
#define	SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos
	SCB ICSR: NMIPENDSET Position, backward compatibility.
#define	SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk
	SCB ICSR: NMIPENDSET Mask, backward compatibility.
#define	SCB_ICSR_PENDNMICLR_Pos 30U
	SCB ICSR: PENDNMICLR Position.
#define	SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)
	SCB ICSR: PENDNMICLR Mask.
#define	SCB_ICSR_PENDSVSET_Pos 28U
	SCB ICSR: PENDSVSET Position.
#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
	SCB ICSR: PENDSVSET Mask.
#define	SCB_ICSR_PENDSVCLR_Pos 27U
	SCB ICSR: PENDSVCLR Position.
#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
	SCB ICSR: PENDSVCLR Mask.
#define	SCB_ICSR_PENDSTSET_Pos 26U
	SCB ICSR: PENDSTSET Position.
#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
	SCB ICSR: PENDSTSET Mask.
#define	SCB_ICSR_PENDSTCLR_Pos 25U
	SCB ICSR: PENDSTCLR Position.
#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
	SCB ICSR: PENDSTCLR Mask.
#define	SCB_ICSR_STTNS_Pos 24U
	SCB ICSR: STTNS Position (Security Extension).
#define	SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)
	SCB ICSR: STTNS Mask (Security Extension).
#define	SCB_ICSR_ISRPREEMPT_Pos 23U
	SCB ICSR: ISRPREEMPT Position.
#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
	SCB ICSR: ISRPREEMPT Mask.
#define	SCB_ICSR_ISRPENDING_Pos 22U
	SCB ICSR: ISRPENDING Position.
#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
	SCB ICSR: ISRPENDING Mask.
#define	SCB_ICSR_VECTPENDING_Pos 12U
	SCB ICSR: VECTPENDING Position.
#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
	SCB ICSR: VECTPENDING Mask.
#define	SCB_ICSR_RETTOBASE_Pos 11U
	SCB ICSR: RETTOBASE Position.
#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
	SCB ICSR: RETTOBASE Mask.
#define	SCB_ICSR_VECTACTIVE_Pos 0U
	SCB ICSR: VECTACTIVE Position.
#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)
	SCB ICSR: VECTACTIVE Mask.
#define	SCB_VTOR_TBLOFF_Pos 7U
	SCB VTOR: TBLOFF Position.
#define	SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
	SCB VTOR: TBLOFF Mask.
#define	SCB_AIRCR_VECTKEY_Pos 16U
	SCB AIRCR: VECTKEY Position.
#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
	SCB AIRCR: VECTKEY Mask.
#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U
	SCB AIRCR: VECTKEYSTAT Position.
#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
	SCB AIRCR: VECTKEYSTAT Mask.
#define	SCB_AIRCR_ENDIANESS_Pos 15U
	SCB AIRCR: ENDIANESS Position.
#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
	SCB AIRCR: ENDIANESS Mask.
#define	SCB_AIRCR_PRIS_Pos 14U
	SCB AIRCR: PRIS Position.
#define	SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)
	SCB AIRCR: PRIS Mask.
#define	SCB_AIRCR_BFHFNMINS_Pos 13U
	SCB AIRCR: BFHFNMINS Position.
#define	SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)
	SCB AIRCR: BFHFNMINS Mask.
#define	SCB_AIRCR_PRIGROUP_Pos 8U
	SCB AIRCR: PRIGROUP Position.
#define	SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
	SCB AIRCR: PRIGROUP Mask.
#define	SCB_AIRCR_SYSRESETREQS_Pos 3U
	SCB AIRCR: SYSRESETREQS Position.
#define	SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
	SCB AIRCR: SYSRESETREQS Mask.
#define	SCB_AIRCR_SYSRESETREQ_Pos 2U
	SCB AIRCR: SYSRESETREQ Position.
#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
	SCB AIRCR: SYSRESETREQ Mask.
#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U
	SCB AIRCR: VECTCLRACTIVE Position.
#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
	SCB AIRCR: VECTCLRACTIVE Mask.
#define	SCB_SCR_SEVONPEND_Pos 4U
	SCB SCR: SEVONPEND Position.
#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
	SCB SCR: SEVONPEND Mask.
#define	SCB_SCR_SLEEPDEEPS_Pos 3U
	SCB SCR: SLEEPDEEPS Position.
#define	SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)
	SCB SCR: SLEEPDEEPS Mask.
#define	SCB_SCR_SLEEPDEEP_Pos 2U
	SCB SCR: SLEEPDEEP Position.
#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
	SCB SCR: SLEEPDEEP Mask.
#define	SCB_SCR_SLEEPONEXIT_Pos 1U
	SCB SCR: SLEEPONEXIT Position.
#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
	SCB SCR: SLEEPONEXIT Mask.
#define	SCB_CCR_BP_Pos 18U
	SCB CCR: BP Position.
#define	SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
	SCB CCR: BP Mask.
#define	SCB_CCR_IC_Pos 17U
	SCB CCR: IC Position.
#define	SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
	SCB CCR: IC Mask.
#define	SCB_CCR_DC_Pos 16U
	SCB CCR: DC Position.
#define	SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
	SCB CCR: DC Mask.
#define	SCB_CCR_STKOFHFNMIGN_Pos 10U
	SCB CCR: STKOFHFNMIGN Position.
#define	SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
	SCB CCR: STKOFHFNMIGN Mask.
#define	SCB_CCR_BFHFNMIGN_Pos 8U
	SCB CCR: BFHFNMIGN Position.
#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
	SCB CCR: BFHFNMIGN Mask.
#define	SCB_CCR_DIV_0_TRP_Pos 4U
	SCB CCR: DIV_0_TRP Position.
#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
	SCB CCR: DIV_0_TRP Mask.
#define	SCB_CCR_UNALIGN_TRP_Pos 3U
	SCB CCR: UNALIGN_TRP Position.
#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
	SCB CCR: UNALIGN_TRP Mask.
#define	SCB_CCR_USERSETMPEND_Pos 1U
	SCB CCR: USERSETMPEND Position.
#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
	SCB CCR: USERSETMPEND Mask.
#define	SCB_SHCSR_HARDFAULTPENDED_Pos 21U
	SCB SHCSR: HARDFAULTPENDED Position.
#define	SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
	SCB SHCSR: HARDFAULTPENDED Mask.
#define	SCB_SHCSR_SECUREFAULTPENDED_Pos 20U
	SCB SHCSR: SECUREFAULTPENDED Position.
#define	SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
	SCB SHCSR: SECUREFAULTPENDED Mask.
#define	SCB_SHCSR_SECUREFAULTENA_Pos 19U
	SCB SHCSR: SECUREFAULTENA Position.
#define	SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
	SCB SHCSR: SECUREFAULTENA Mask.
#define	SCB_SHCSR_USGFAULTENA_Pos 18U
	SCB SHCSR: USGFAULTENA Position.
#define	SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
	SCB SHCSR: USGFAULTENA Mask.
#define	SCB_SHCSR_BUSFAULTENA_Pos 17U
	SCB SHCSR: BUSFAULTENA Position.
#define	SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
	SCB SHCSR: BUSFAULTENA Mask.
#define	SCB_SHCSR_MEMFAULTENA_Pos 16U
	SCB SHCSR: MEMFAULTENA Position.
#define	SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
	SCB SHCSR: MEMFAULTENA Mask.
#define	SCB_SHCSR_SVCALLPENDED_Pos 15U
	SCB SHCSR: SVCALLPENDED Position.
#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
	SCB SHCSR: SVCALLPENDED Mask.
#define	SCB_SHCSR_BUSFAULTPENDED_Pos 14U
	SCB SHCSR: BUSFAULTPENDED Position.
#define	SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
	SCB SHCSR: BUSFAULTPENDED Mask.
#define	SCB_SHCSR_MEMFAULTPENDED_Pos 13U
	SCB SHCSR: MEMFAULTPENDED Position.
#define	SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
	SCB SHCSR: MEMFAULTPENDED Mask.
#define	SCB_SHCSR_USGFAULTPENDED_Pos 12U
	SCB SHCSR: USGFAULTPENDED Position.
#define	SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
	SCB SHCSR: USGFAULTPENDED Mask.
#define	SCB_SHCSR_SYSTICKACT_Pos 11U
	SCB SHCSR: SYSTICKACT Position.
#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
	SCB SHCSR: SYSTICKACT Mask.
#define	SCB_SHCSR_PENDSVACT_Pos 10U
	SCB SHCSR: PENDSVACT Position.
#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
	SCB SHCSR: PENDSVACT Mask.
#define	SCB_SHCSR_MONITORACT_Pos 8U
	SCB SHCSR: MONITORACT Position.
#define	SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
	SCB SHCSR: MONITORACT Mask.
#define	SCB_SHCSR_SVCALLACT_Pos 7U
	SCB SHCSR: SVCALLACT Position.
#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
	SCB SHCSR: SVCALLACT Mask.
#define	SCB_SHCSR_NMIACT_Pos 5U
	SCB SHCSR: NMIACT Position.
#define	SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)
	SCB SHCSR: NMIACT Mask.
#define	SCB_SHCSR_SECUREFAULTACT_Pos 4U
	SCB SHCSR: SECUREFAULTACT Position.
#define	SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
	SCB SHCSR: SECUREFAULTACT Mask.
#define	SCB_SHCSR_USGFAULTACT_Pos 3U
	SCB SHCSR: USGFAULTACT Position.
#define	SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
	SCB SHCSR: USGFAULTACT Mask.
#define	SCB_SHCSR_HARDFAULTACT_Pos 2U
	SCB SHCSR: HARDFAULTACT Position.
#define	SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
	SCB SHCSR: HARDFAULTACT Mask.
#define	SCB_SHCSR_BUSFAULTACT_Pos 1U
	SCB SHCSR: BUSFAULTACT Position.
#define	SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
	SCB SHCSR: BUSFAULTACT Mask.
#define	SCB_SHCSR_MEMFAULTACT_Pos 0U
	SCB SHCSR: MEMFAULTACT Position.
#define	SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/)
	SCB SHCSR: MEMFAULTACT Mask.
#define	SCB_CFSR_USGFAULTSR_Pos 16U
	SCB CFSR: Usage Fault Status Register Position.
#define	SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
	SCB CFSR: Usage Fault Status Register Mask.
#define	SCB_CFSR_BUSFAULTSR_Pos 8U
	SCB CFSR: Bus Fault Status Register Position.
#define	SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
	SCB CFSR: Bus Fault Status Register Mask.
#define	SCB_CFSR_MEMFAULTSR_Pos 0U
	SCB CFSR: Memory Manage Fault Status Register Position.
#define	SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/)
	SCB CFSR: Memory Manage Fault Status Register Mask.
#define	SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U)
	SCB CFSR (MMFSR): MMARVALID Position.
#define	SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
	SCB CFSR (MMFSR): MMARVALID Mask.
#define	SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U)
	SCB CFSR (MMFSR): MLSPERR Position.
#define	SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)
	SCB CFSR (MMFSR): MLSPERR Mask.
#define	SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U)
	SCB CFSR (MMFSR): MSTKERR Position.
#define	SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
	SCB CFSR (MMFSR): MSTKERR Mask.
#define	SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U)
	SCB CFSR (MMFSR): MUNSTKERR Position.
#define	SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
	SCB CFSR (MMFSR): MUNSTKERR Mask.
#define	SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U)
	SCB CFSR (MMFSR): DACCVIOL Position.
#define	SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
	SCB CFSR (MMFSR): DACCVIOL Mask.
#define	SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U)
	SCB CFSR (MMFSR): IACCVIOL Position.
#define	SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/)
	SCB CFSR (MMFSR): IACCVIOL Mask.
#define	SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
	SCB CFSR (BFSR): BFARVALID Position.
#define	SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
	SCB CFSR (BFSR): BFARVALID Mask.
#define	SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)
	SCB CFSR (BFSR): LSPERR Position.
#define	SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)
	SCB CFSR (BFSR): LSPERR Mask.
#define	SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
	SCB CFSR (BFSR): STKERR Position.
#define	SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
	SCB CFSR (BFSR): STKERR Mask.
#define	SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
	SCB CFSR (BFSR): UNSTKERR Position.
#define	SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
	SCB CFSR (BFSR): UNSTKERR Mask.
#define	SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
	SCB CFSR (BFSR): IMPRECISERR Position.
#define	SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
	SCB CFSR (BFSR): IMPRECISERR Mask.
#define	SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
	SCB CFSR (BFSR): PRECISERR Position.
#define	SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
	SCB CFSR (BFSR): PRECISERR Mask.
#define	SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
	SCB CFSR (BFSR): IBUSERR Position.
#define	SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
	SCB CFSR (BFSR): IBUSERR Mask.
#define	SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
	SCB CFSR (UFSR): DIVBYZERO Position.
#define	SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
	SCB CFSR (UFSR): DIVBYZERO Mask.
#define	SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
	SCB CFSR (UFSR): UNALIGNED Position.
#define	SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
	SCB CFSR (UFSR): UNALIGNED Mask.
#define	SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)
	SCB CFSR (UFSR): STKOF Position.
#define	SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)
	SCB CFSR (UFSR): STKOF Mask.
#define	SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
	SCB CFSR (UFSR): NOCP Position.
#define	SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
	SCB CFSR (UFSR): NOCP Mask.
#define	SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
	SCB CFSR (UFSR): INVPC Position.
#define	SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
	SCB CFSR (UFSR): INVPC Mask.
#define	SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
	SCB CFSR (UFSR): INVSTATE Position.
#define	SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
	SCB CFSR (UFSR): INVSTATE Mask.
#define	SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
	SCB CFSR (UFSR): UNDEFINSTR Position.
#define	SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
	SCB CFSR (UFSR): UNDEFINSTR Mask.
#define	SCB_HFSR_DEBUGEVT_Pos 31U
	SCB HFSR: DEBUGEVT Position.
#define	SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
	SCB HFSR: DEBUGEVT Mask.
#define	SCB_HFSR_FORCED_Pos 30U
	SCB HFSR: FORCED Position.
#define	SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
	SCB HFSR: FORCED Mask.
#define	SCB_HFSR_VECTTBL_Pos 1U
	SCB HFSR: VECTTBL Position.
#define	SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
	SCB HFSR: VECTTBL Mask.
#define	SCB_DFSR_EXTERNAL_Pos 4U
	SCB DFSR: EXTERNAL Position.
#define	SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
	SCB DFSR: EXTERNAL Mask.
#define	SCB_DFSR_VCATCH_Pos 3U
	SCB DFSR: VCATCH Position.
#define	SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
	SCB DFSR: VCATCH Mask.
#define	SCB_DFSR_DWTTRAP_Pos 2U
	SCB DFSR: DWTTRAP Position.
#define	SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
	SCB DFSR: DWTTRAP Mask.
#define	SCB_DFSR_BKPT_Pos 1U
	SCB DFSR: BKPT Position.
#define	SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
	SCB DFSR: BKPT Mask.
#define	SCB_DFSR_HALTED_Pos 0U
	SCB DFSR: HALTED Position.
#define	SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/)
	SCB DFSR: HALTED Mask.
#define	SCB_NSACR_CP11_Pos 11U
	SCB NSACR: CP11 Position.
#define	SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)
	SCB NSACR: CP11 Mask.
#define	SCB_NSACR_CP10_Pos 10U
	SCB NSACR: CP10 Position.
#define	SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)
	SCB NSACR: CP10 Mask.
#define	SCB_CLIDR_LOUU_Pos 27U
	SCB CLIDR: LoUU Position.
#define	SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)
	SCB CLIDR: LoUU Mask.
#define	SCB_CLIDR_LOC_Pos 24U
	SCB CLIDR: LoC Position.
#define	SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)
	SCB CLIDR: LoC Mask.
#define	SCB_CTR_FORMAT_Pos 29U
	SCB CTR: Format Position.
#define	SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)
	SCB CTR: Format Mask.
#define	SCB_CTR_CWG_Pos 24U
	SCB CTR: CWG Position.
#define	SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)
	SCB CTR: CWG Mask.
#define	SCB_CTR_ERG_Pos 20U
	SCB CTR: ERG Position.
#define	SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)
	SCB CTR: ERG Mask.
#define	SCB_CTR_DMINLINE_Pos 16U
	SCB CTR: DminLine Position.
#define	SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)
	SCB CTR: DminLine Mask.
#define	SCB_CTR_IMINLINE_Pos 0U
	SCB CTR: ImInLine Position.
#define	SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/)
	SCB CTR: ImInLine Mask.
#define	SCB_CCSIDR_WT_Pos 31U
	SCB CCSIDR: WT Position.
#define	SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)
	SCB CCSIDR: WT Mask.
#define	SCB_CCSIDR_WB_Pos 30U
	SCB CCSIDR: WB Position.
#define	SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)
	SCB CCSIDR: WB Mask.
#define	SCB_CCSIDR_RA_Pos 29U
	SCB CCSIDR: RA Position.
#define	SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)
	SCB CCSIDR: RA Mask.
#define	SCB_CCSIDR_WA_Pos 28U
	SCB CCSIDR: WA Position.
#define	SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)
	SCB CCSIDR: WA Mask.
#define	SCB_CCSIDR_NUMSETS_Pos 13U
	SCB CCSIDR: NumSets Position.
#define	SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
	SCB CCSIDR: NumSets Mask.
#define	SCB_CCSIDR_ASSOCIATIVITY_Pos 3U
	SCB CCSIDR: Associativity Position.
#define	SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
	SCB CCSIDR: Associativity Mask.
#define	SCB_CCSIDR_LINESIZE_Pos 0U
	SCB CCSIDR: LineSize Position.
#define	SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/)
	SCB CCSIDR: LineSize Mask.
#define	SCB_CSSELR_LEVEL_Pos 1U
	SCB CSSELR: Level Position.
#define	SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)
	SCB CSSELR: Level Mask.
#define	SCB_CSSELR_IND_Pos 0U
	SCB CSSELR: InD Position.
#define	SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/)
	SCB CSSELR: InD Mask.
#define	SCB_STIR_INTID_Pos 0U
	SCB STIR: INTID Position.
#define	SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/)
	SCB STIR: INTID Mask.
#define	SCB_DCISW_WAY_Pos 30U
	SCB DCISW: Way Position.
#define	SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)
	SCB DCISW: Way Mask.
#define	SCB_DCISW_SET_Pos 5U
	SCB DCISW: Set Position.
#define	SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)
	SCB DCISW: Set Mask.
#define	SCB_DCCSW_WAY_Pos 30U
	SCB DCCSW: Way Position.
#define	SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)
	SCB DCCSW: Way Mask.
#define	SCB_DCCSW_SET_Pos 5U
	SCB DCCSW: Set Position.
#define	SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)
	SCB DCCSW: Set Mask.
#define	SCB_DCCISW_WAY_Pos 30U
	SCB DCCISW: Way Position.
#define	SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)
	SCB DCCISW: Way Mask.
#define	SCB_DCCISW_SET_Pos 5U
	SCB DCCISW: Set Position.
#define	SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)
	SCB DCCISW: Set Mask.
#define	SysTick_CTRL_COUNTFLAG_Pos 16U
	SysTick CTRL: COUNTFLAG Position.
#define	SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
	SysTick CTRL: COUNTFLAG Mask.
#define	SysTick_CTRL_CLKSOURCE_Pos 2U
	SysTick CTRL: CLKSOURCE Position.
#define	SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
	SysTick CTRL: CLKSOURCE Mask.
#define	SysTick_CTRL_TICKINT_Pos 1U
	SysTick CTRL: TICKINT Position.
#define	SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
	SysTick CTRL: TICKINT Mask.
#define	SysTick_CTRL_ENABLE_Pos 0U
	SysTick CTRL: ENABLE Position.
#define	SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/)
	SysTick CTRL: ENABLE Mask.
#define	SysTick_LOAD_RELOAD_Pos 0U
	SysTick LOAD: RELOAD Position.
#define	SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/)
	SysTick LOAD: RELOAD Mask.
#define	SysTick_VAL_CURRENT_Pos 0U
	SysTick VAL: CURRENT Position.
#define	SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/)
	SysTick VAL: CURRENT Mask.
#define	SysTick_CALIB_NOREF_Pos 31U
	SysTick CALIB: NOREF Position.
#define	SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
	SysTick CALIB: NOREF Mask.
#define	SysTick_CALIB_SKEW_Pos 30U
	SysTick CALIB: SKEW Position.
#define	SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
	SysTick CALIB: SKEW Mask.
#define	SysTick_CALIB_TENMS_Pos 0U
	SysTick CALIB: TENMS Position.
#define	SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/)
	SysTick CALIB: TENMS Mask.
#define	ITM_STIM_DISABLED_Pos 1U
	ITM STIM: DISABLED Position.
#define	ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)
	ITM STIM: DISABLED Mask.
#define	ITM_STIM_FIFOREADY_Pos 0U
	ITM STIM: FIFOREADY Position.
#define	ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/)
	ITM STIM: FIFOREADY Mask.
#define	ITM_TPR_PRIVMASK_Pos 0U
	ITM TPR: PRIVMASK Position.
#define	ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/)
	ITM TPR: PRIVMASK Mask.
#define	ITM_TCR_BUSY_Pos 23U
	ITM TCR: BUSY Position.
#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
	ITM TCR: BUSY Mask.
#define	ITM_TCR_TRACEBUSID_Pos 16U
	ITM TCR: ATBID Position.
#define	ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
	ITM TCR: ATBID Mask.
#define	ITM_TCR_GTSFREQ_Pos 10U
	ITM TCR: Global timestamp frequency Position.
#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
	ITM TCR: Global timestamp frequency Mask.
#define	ITM_TCR_TSPRESCALE_Pos 8U
	ITM TCR: TSPRESCALE Position.
#define	ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)
	ITM TCR: TSPRESCALE Mask.
#define	ITM_TCR_STALLENA_Pos 5U
	ITM TCR: STALLENA Position.
#define	ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)
	ITM TCR: STALLENA Mask.
#define	ITM_TCR_SWOENA_Pos 4U
	ITM TCR: SWOENA Position.
#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
	ITM TCR: SWOENA Mask.
#define	ITM_TCR_DWTENA_Pos 3U
	ITM TCR: DWTENA Position.
#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
	ITM TCR: DWTENA Mask.
#define	ITM_TCR_SYNCENA_Pos 2U
	ITM TCR: SYNCENA Position.
#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
	ITM TCR: SYNCENA Mask.
#define	ITM_TCR_TSENA_Pos 1U
	ITM TCR: TSENA Position.
#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
	ITM TCR: TSENA Mask.
#define	ITM_TCR_ITMENA_Pos 0U
	ITM TCR: ITM Enable bit Position.
#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)
	ITM TCR: ITM Enable bit Mask.
#define	ITM_LSR_ByteAcc_Pos 2U
	ITM LSR: ByteAcc Position.
#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
	ITM LSR: ByteAcc Mask.
#define	ITM_LSR_Access_Pos 1U
	ITM LSR: Access Position.
#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
	ITM LSR: Access Mask.
#define	ITM_LSR_Present_Pos 0U
	ITM LSR: Present Position.
#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)
	ITM LSR: Present Mask.
#define	DWT_CTRL_NUMCOMP_Pos 28U
	DWT CTRL: NUMCOMP Position.
#define	DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
	DWT CTRL: NUMCOMP Mask.
#define	DWT_CTRL_NOTRCPKT_Pos 27U
	DWT CTRL: NOTRCPKT Position.
#define	DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
	DWT CTRL: NOTRCPKT Mask.
#define	DWT_CTRL_NOEXTTRIG_Pos 26U
	DWT CTRL: NOEXTTRIG Position.
#define	DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
	DWT CTRL: NOEXTTRIG Mask.
#define	DWT_CTRL_NOCYCCNT_Pos 25U
	DWT CTRL: NOCYCCNT Position.
#define	DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
	DWT CTRL: NOCYCCNT Mask.
#define	DWT_CTRL_NOPRFCNT_Pos 24U
	DWT CTRL: NOPRFCNT Position.
#define	DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
	DWT CTRL: NOPRFCNT Mask.
#define	DWT_CTRL_CYCDISS_Pos 23U
	DWT CTRL: CYCDISS Position.
#define	DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos)
	DWT CTRL: CYCDISS Mask.
#define	DWT_CTRL_CYCEVTENA_Pos 22U
	DWT CTRL: CYCEVTENA Position.
#define	DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
	DWT CTRL: CYCEVTENA Mask.
#define	DWT_CTRL_FOLDEVTENA_Pos 21U
	DWT CTRL: FOLDEVTENA Position.
#define	DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
	DWT CTRL: FOLDEVTENA Mask.
#define	DWT_CTRL_LSUEVTENA_Pos 20U
	DWT CTRL: LSUEVTENA Position.
#define	DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
	DWT CTRL: LSUEVTENA Mask.
#define	DWT_CTRL_SLEEPEVTENA_Pos 19U
	DWT CTRL: SLEEPEVTENA Position.
#define	DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
	DWT CTRL: SLEEPEVTENA Mask.
#define	DWT_CTRL_EXCEVTENA_Pos 18U
	DWT CTRL: EXCEVTENA Position.
#define	DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
	DWT CTRL: EXCEVTENA Mask.
#define	DWT_CTRL_CPIEVTENA_Pos 17U
	DWT CTRL: CPIEVTENA Position.
#define	DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
	DWT CTRL: CPIEVTENA Mask.
#define	DWT_CTRL_EXCTRCENA_Pos 16U
	DWT CTRL: EXCTRCENA Position.
#define	DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
	DWT CTRL: EXCTRCENA Mask.
#define	DWT_CTRL_PCSAMPLENA_Pos 12U
	DWT CTRL: PCSAMPLENA Position.
#define	DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
	DWT CTRL: PCSAMPLENA Mask.
#define	DWT_CTRL_SYNCTAP_Pos 10U
	DWT CTRL: SYNCTAP Position.
#define	DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
	DWT CTRL: SYNCTAP Mask.
#define	DWT_CTRL_CYCTAP_Pos 9U
	DWT CTRL: CYCTAP Position.
#define	DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
	DWT CTRL: CYCTAP Mask.
#define	DWT_CTRL_POSTINIT_Pos 5U
	DWT CTRL: POSTINIT Position.
#define	DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
	DWT CTRL: POSTINIT Mask.
#define	DWT_CTRL_POSTPRESET_Pos 1U
	DWT CTRL: POSTPRESET Position.
#define	DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
	DWT CTRL: POSTPRESET Mask.
#define	DWT_CTRL_CYCCNTENA_Pos 0U
	DWT CTRL: CYCCNTENA Position.
#define	DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/)
	DWT CTRL: CYCCNTENA Mask.
#define	DWT_CPICNT_CPICNT_Pos 0U
	DWT CPICNT: CPICNT Position.
#define	DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/)
	DWT CPICNT: CPICNT Mask.
#define	DWT_EXCCNT_EXCCNT_Pos 0U
	DWT EXCCNT: EXCCNT Position.
#define	DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/)
	DWT EXCCNT: EXCCNT Mask.
#define	DWT_SLEEPCNT_SLEEPCNT_Pos 0U
	DWT SLEEPCNT: SLEEPCNT Position.
#define	DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/)
	DWT SLEEPCNT: SLEEPCNT Mask.
#define	DWT_LSUCNT_LSUCNT_Pos 0U
	DWT LSUCNT: LSUCNT Position.
#define	DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/)
	DWT LSUCNT: LSUCNT Mask.
#define	DWT_FOLDCNT_FOLDCNT_Pos 0U
	DWT FOLDCNT: FOLDCNT Position.
#define	DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/)
	DWT FOLDCNT: FOLDCNT Mask.
#define	DWT_FUNCTION_ID_Pos 27U
	DWT FUNCTION: ID Position.
#define	DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)
	DWT FUNCTION: ID Mask.
#define	DWT_FUNCTION_MATCHED_Pos 24U
	DWT FUNCTION: MATCHED Position.
#define	DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
	DWT FUNCTION: MATCHED Mask.
#define	DWT_FUNCTION_DATAVSIZE_Pos 10U
	DWT FUNCTION: DATAVSIZE Position.
#define	DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
	DWT FUNCTION: DATAVSIZE Mask.
#define	DWT_FUNCTION_ACTION_Pos 4U
	DWT FUNCTION: ACTION Position.
#define	DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos)
	DWT FUNCTION: ACTION Mask.
#define	DWT_FUNCTION_MATCH_Pos 0U
	DWT FUNCTION: MATCH Position.
#define	DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/)
	DWT FUNCTION: MATCH Mask.
#define	TPI_SPPR_TXMODE_Pos 0U
	TPI SPPR: TXMODE Position.
#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)
	TPI SPPR: TXMODE Mask.
#define	TPI_FFSR_FtNonStop_Pos 3U
	TPI FFSR: FtNonStop Position.
#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
	TPI FFSR: FtNonStop Mask.
#define	TPI_FFSR_TCPresent_Pos 2U
	TPI FFSR: TCPresent Position.
#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
	TPI FFSR: TCPresent Mask.
#define	TPI_FFSR_FtStopped_Pos 1U
	TPI FFSR: FtStopped Position.
#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
	TPI FFSR: FtStopped Mask.
#define	TPI_FFSR_FlInProg_Pos 0U
	TPI FFSR: FlInProg Position.
#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)
	TPI FFSR: FlInProg Mask.
#define	TPI_FFCR_TrigIn_Pos 8U
	TPI FFCR: TrigIn Position.
#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
	TPI FFCR: TrigIn Mask.
#define	TPI_FFCR_FOnMan_Pos 6U
	TPI FFCR: FOnMan Position.
#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
	TPI FFCR: FOnMan Mask.
#define	TPI_DEVID_NRZVALID_Pos 11U
	TPI DEVID: NRZVALID Position.
#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
	TPI DEVID: NRZVALID Mask.
#define	TPI_DEVID_MANCVALID_Pos 10U
	TPI DEVID: MANCVALID Position.
#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
	TPI DEVID: MANCVALID Mask.
#define	TPI_DEVID_PTINVALID_Pos 9U
	TPI DEVID: PTINVALID Position.
#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
	TPI DEVID: PTINVALID Mask.
#define	TPI_DEVID_FIFOSZ_Pos 6U
	TPI DEVID: FIFO depth Position.
#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
	TPI DEVID: FIFO depth Mask.
#define	TPI_DEVTYPE_SubType_Pos 4U
	TPI DEVTYPE: SubType Position.
#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)
	TPI DEVTYPE: SubType Mask.
#define	TPI_DEVTYPE_MajorType_Pos 0U
	TPI DEVTYPE: MajorType Position.
#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
	TPI DEVTYPE: MajorType Mask.
#define	MPU_TYPE_RALIASES 4U
#define	MPU_TYPE_IREGION_Pos 16U
	MPU TYPE: IREGION Position.
#define	MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
	MPU TYPE: IREGION Mask.
#define	MPU_TYPE_DREGION_Pos 8U
	MPU TYPE: DREGION Position.
#define	MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
	MPU TYPE: DREGION Mask.
#define	MPU_TYPE_SEPARATE_Pos 0U
	MPU TYPE: SEPARATE Position.
#define	MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/)
	MPU TYPE: SEPARATE Mask.
#define	MPU_CTRL_PRIVDEFENA_Pos 2U
	MPU CTRL: PRIVDEFENA Position.
#define	MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
	MPU CTRL: PRIVDEFENA Mask.
#define	MPU_CTRL_HFNMIENA_Pos 1U
	MPU CTRL: HFNMIENA Position.
#define	MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
	MPU CTRL: HFNMIENA Mask.
#define	MPU_CTRL_ENABLE_Pos 0U
	MPU CTRL: ENABLE Position.
#define	MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/)
	MPU CTRL: ENABLE Mask.
#define	MPU_RNR_REGION_Pos 0U
	MPU RNR: REGION Position.
#define	MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/)
	MPU RNR: REGION Mask.
#define	MPU_RBAR_BASE_Pos 5U
	MPU RBAR: BASE Position.
#define	MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
	MPU RBAR: BASE Mask.
#define	MPU_RBAR_SH_Pos 3U
	MPU RBAR: SH Position.
#define	MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
	MPU RBAR: SH Mask.
#define	MPU_RBAR_AP_Pos 1U
	MPU RBAR: AP Position.
#define	MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
	MPU RBAR: AP Mask.
#define	MPU_RBAR_XN_Pos 0U
	MPU RBAR: XN Position.
#define	MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/)
	MPU RBAR: XN Mask.
#define	MPU_RLAR_LIMIT_Pos 5U
	MPU RLAR: LIMIT Position.
#define	MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
	MPU RLAR: LIMIT Mask.
#define	MPU_RLAR_AttrIndx_Pos 1U
	MPU RLAR: AttrIndx Position.
#define	MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos)
	MPU RLAR: AttrIndx Mask.
#define	MPU_RLAR_EN_Pos 0U
	MPU RLAR: Region enable bit Position.
#define	MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/)
	MPU RLAR: Region enable bit Disable Mask.
#define	MPU_MAIR0_Attr3_Pos 24U
	MPU MAIR0: Attr3 Position.
#define	MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
	MPU MAIR0: Attr3 Mask.
#define	MPU_MAIR0_Attr2_Pos 16U
	MPU MAIR0: Attr2 Position.
#define	MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
	MPU MAIR0: Attr2 Mask.
#define	MPU_MAIR0_Attr1_Pos 8U
	MPU MAIR0: Attr1 Position.
#define	MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
	MPU MAIR0: Attr1 Mask.
#define	MPU_MAIR0_Attr0_Pos 0U
	MPU MAIR0: Attr0 Position.
#define	MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/)
	MPU MAIR0: Attr0 Mask.
#define	MPU_MAIR1_Attr7_Pos 24U
	MPU MAIR1: Attr7 Position.
#define	MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
	MPU MAIR1: Attr7 Mask.
#define	MPU_MAIR1_Attr6_Pos 16U
	MPU MAIR1: Attr6 Position.
#define	MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
	MPU MAIR1: Attr6 Mask.
#define	MPU_MAIR1_Attr5_Pos 8U
	MPU MAIR1: Attr5 Position.
#define	MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
	MPU MAIR1: Attr5 Mask.
#define	MPU_MAIR1_Attr4_Pos 0U
	MPU MAIR1: Attr4 Position.
#define	MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/)
	MPU MAIR1: Attr4 Mask.
#define	FPU_FPCCR_ASPEN_Pos 31U
	FPCCR: ASPEN bit Position.
#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
	FPCCR: ASPEN bit Mask.
#define	FPU_FPCCR_LSPEN_Pos 30U
	FPCCR: LSPEN Position.
#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
	FPCCR: LSPEN bit Mask.
#define	FPU_FPCCR_LSPENS_Pos 29U
	FPCCR: LSPENS Position.
#define	FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)
	FPCCR: LSPENS bit Mask.
#define	FPU_FPCCR_CLRONRET_Pos 28U
	FPCCR: CLRONRET Position.
#define	FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)
	FPCCR: CLRONRET bit Mask.
#define	FPU_FPCCR_CLRONRETS_Pos 27U
	FPCCR: CLRONRETS Position.
#define	FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)
	FPCCR: CLRONRETS bit Mask.
#define	FPU_FPCCR_TS_Pos 26U
	FPCCR: TS Position.
#define	FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)
	FPCCR: TS bit Mask.
#define	FPU_FPCCR_UFRDY_Pos 10U
	FPCCR: UFRDY Position.
#define	FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)
	FPCCR: UFRDY bit Mask.
#define	FPU_FPCCR_SPLIMVIOL_Pos 9U
	FPCCR: SPLIMVIOL Position.
#define	FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
	FPCCR: SPLIMVIOL bit Mask.
#define	FPU_FPCCR_MONRDY_Pos 8U
	FPCCR: MONRDY Position.
#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
	FPCCR: MONRDY bit Mask.
#define	FPU_FPCCR_SFRDY_Pos 7U
	FPCCR: SFRDY Position.
#define	FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)
	FPCCR: SFRDY bit Mask.
#define	FPU_FPCCR_BFRDY_Pos 6U
	FPCCR: BFRDY Position.
#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
	FPCCR: BFRDY bit Mask.
#define	FPU_FPCCR_MMRDY_Pos 5U
	FPCCR: MMRDY Position.
#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
	FPCCR: MMRDY bit Mask.
#define	FPU_FPCCR_HFRDY_Pos 4U
	FPCCR: HFRDY Position.
#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
	FPCCR: HFRDY bit Mask.
#define	FPU_FPCCR_THREAD_Pos 3U
	FPCCR: processor mode bit Position.
#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
	FPCCR: processor mode active bit Mask.
#define	FPU_FPCCR_S_Pos 2U
	FPCCR: Security status of the FP context bit Position.
#define	FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)
	FPCCR: Security status of the FP context bit Mask.
#define	FPU_FPCCR_USER_Pos 1U
	FPCCR: privilege level bit Position.
#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
	FPCCR: privilege level bit Mask.
#define	FPU_FPCCR_LSPACT_Pos 0U
	FPCCR: Lazy state preservation active bit Position.
#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)
	FPCCR: Lazy state preservation active bit Mask.
#define	FPU_FPCAR_ADDRESS_Pos 3U
	FPCAR: ADDRESS bit Position.
#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
	FPCAR: ADDRESS bit Mask.
#define	FPU_FPDSCR_AHP_Pos 26U
	FPDSCR: AHP bit Position.
#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
	FPDSCR: AHP bit Mask.
#define	FPU_FPDSCR_DN_Pos 25U
	FPDSCR: DN bit Position.
#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
	FPDSCR: DN bit Mask.
#define	FPU_FPDSCR_FZ_Pos 24U
	FPDSCR: FZ bit Position.
#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
	FPDSCR: FZ bit Mask.
#define	FPU_FPDSCR_RMode_Pos 22U
	FPDSCR: RMode bit Position.
#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
	FPDSCR: RMode bit Mask.
#define	FPU_MVFR2_FPMisc_Pos 4U
	MVFR2: FPMisc bits Position.
#define	FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos)
	MVFR2: FPMisc bits Mask.
#define	DCB_DHCSR_DBGKEY_Pos 16U
	DCB DHCSR: Debug key Position.
#define	DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
	DCB DHCSR: Debug key Mask.
#define	DCB_DHCSR_S_RESTART_ST_Pos 26U
	DCB DHCSR: Restart sticky status Position.
#define	DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
	DCB DHCSR: Restart sticky status Mask.
#define	DCB_DHCSR_S_RESET_ST_Pos 25U
	DCB DHCSR: Reset sticky status Position.
#define	DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
	DCB DHCSR: Reset sticky status Mask.
#define	DCB_DHCSR_S_RETIRE_ST_Pos 24U
	DCB DHCSR: Retire sticky status Position.
#define	DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
	DCB DHCSR: Retire sticky status Mask.
#define	DCB_DHCSR_S_SDE_Pos 20U
	DCB DHCSR: Secure debug enabled Position.
#define	DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)
	DCB DHCSR: Secure debug enabled Mask.
#define	DCB_DHCSR_S_LOCKUP_Pos 19U
	DCB DHCSR: Lockup status Position.
#define	DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
	DCB DHCSR: Lockup status Mask.
#define	DCB_DHCSR_S_SLEEP_Pos 18U
	DCB DHCSR: Sleeping status Position.
#define	DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
	DCB DHCSR: Sleeping status Mask.
#define	DCB_DHCSR_S_HALT_Pos 17U
	DCB DHCSR: Halted status Position.
#define	DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)
	DCB DHCSR: Halted status Mask.
#define	DCB_DHCSR_S_REGRDY_Pos 16U
	DCB DHCSR: Register ready status Position.
#define	DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
	DCB DHCSR: Register ready status Mask.
#define	DCB_DHCSR_C_SNAPSTALL_Pos 5U
	DCB DHCSR: Snap stall control Position.
#define	DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
	DCB DHCSR: Snap stall control Mask.
#define	DCB_DHCSR_C_MASKINTS_Pos 3U
	DCB DHCSR: Mask interrupts control Position.
#define	DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
	DCB DHCSR: Mask interrupts control Mask.
#define	DCB_DHCSR_C_STEP_Pos 2U
	DCB DHCSR: Step control Position.
#define	DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)
	DCB DHCSR: Step control Mask.
#define	DCB_DHCSR_C_HALT_Pos 1U
	DCB DHCSR: Halt control Position.
#define	DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)
	DCB DHCSR: Halt control Mask.
#define	DCB_DHCSR_C_DEBUGEN_Pos 0U
	DCB DHCSR: Debug enable control Position.
#define	DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /<< DCB_DHCSR_C_DEBUGEN_Pos/)
	DCB DHCSR: Debug enable control Mask.
#define	DCB_DCRSR_REGWnR_Pos 16U
	DCB DCRSR: Register write/not-read Position.
#define	DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)
	DCB DCRSR: Register write/not-read Mask.
#define	DCB_DCRSR_REGSEL_Pos 0U
	DCB DCRSR: Register selector Position.
#define	DCB_DCRSR_REGSEL_Msk (0x7FUL /<< DCB_DCRSR_REGSEL_Pos/)
	DCB DCRSR: Register selector Mask.
#define	DCB_DCRDR_DBGTMP_Pos 0U
	DCB DCRDR: Data temporary buffer Position.
#define	DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /<< DCB_DCRDR_DBGTMP_Pos/)
	DCB DCRDR: Data temporary buffer Mask.
#define	DCB_DEMCR_TRCENA_Pos 24U
	DCB DEMCR: Trace enable Position.
#define	DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)
	DCB DEMCR: Trace enable Mask.
#define	DCB_DEMCR_MONPRKEY_Pos 23U
	DCB DEMCR: Monitor pend req key Position.
#define	DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
	DCB DEMCR: Monitor pend req key Mask.
#define	DCB_DEMCR_UMON_EN_Pos 21U
	DCB DEMCR: Unprivileged monitor enable Position.
#define	DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos)
	DCB DEMCR: Unprivileged monitor enable Mask.
#define	DCB_DEMCR_SDME_Pos 20U
	DCB DEMCR: Secure DebugMonitor enable Position.
#define	DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos)
	DCB DEMCR: Secure DebugMonitor enable Mask.
#define	DCB_DEMCR_MON_REQ_Pos 19U
	DCB DEMCR: Monitor request Position.
#define	DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos)
	DCB DEMCR: Monitor request Mask.
#define	DCB_DEMCR_MON_STEP_Pos 18U
	DCB DEMCR: Monitor step Position.
#define	DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos)
	DCB DEMCR: Monitor step Mask.
#define	DCB_DEMCR_MON_PEND_Pos 17U
	DCB DEMCR: Monitor pend Position.
#define	DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos)
	DCB DEMCR: Monitor pend Mask.
#define	DCB_DEMCR_MON_EN_Pos 16U
	DCB DEMCR: Monitor enable Position.
#define	DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos)
	DCB DEMCR: Monitor enable Mask.
#define	DCB_DEMCR_VC_SFERR_Pos 11U
	DCB DEMCR: Vector Catch SecureFault Position.
#define	DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
	DCB DEMCR: Vector Catch SecureFault Mask.
#define	DCB_DEMCR_VC_HARDERR_Pos 10U
	DCB DEMCR: Vector Catch HardFault errors Position.
#define	DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
	DCB DEMCR: Vector Catch HardFault errors Mask.
#define	DCB_DEMCR_VC_INTERR_Pos 9U
	DCB DEMCR: Vector Catch interrupt errors Position.
#define	DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
	DCB DEMCR: Vector Catch interrupt errors Mask.
#define	DCB_DEMCR_VC_BUSERR_Pos 8U
	DCB DEMCR: Vector Catch BusFault errors Position.
#define	DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
	DCB DEMCR: Vector Catch BusFault errors Mask.
#define	DCB_DEMCR_VC_STATERR_Pos 7U
	DCB DEMCR: Vector Catch state errors Position.
#define	DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
	DCB DEMCR: Vector Catch state errors Mask.
#define	DCB_DEMCR_VC_CHKERR_Pos 6U
	DCB DEMCR: Vector Catch check errors Position.
#define	DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
	DCB DEMCR: Vector Catch check errors Mask.
#define	DCB_DEMCR_VC_NOCPERR_Pos 5U
	DCB DEMCR: Vector Catch NOCP errors Position.
#define	DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
	DCB DEMCR: Vector Catch NOCP errors Mask.
#define	DCB_DEMCR_VC_MMERR_Pos 4U
	DCB DEMCR: Vector Catch MemManage errors Position.
#define	DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
	DCB DEMCR: Vector Catch MemManage errors Mask.
#define	DCB_DEMCR_VC_CORERESET_Pos 0U
	DCB DEMCR: Vector Catch Core reset Position.
#define	DCB_DEMCR_VC_CORERESET_Msk (0x1UL /<< DCB_DEMCR_VC_CORERESET_Pos/)
	DCB DEMCR: Vector Catch Core reset Mask.
#define	DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U
	DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position.
#define	DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
	DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask.
#define	DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U
	DCB DAUTHCTRL: Secure non-invasive debug enable select Position.
#define	DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
	DCB DAUTHCTRL: Secure non-invasive debug enable select Mask.
#define	DCB_DAUTHCTRL_INTSPIDEN_Pos 1U
	DCB DAUTHCTRL: Internal Secure invasive debug enable Position.
#define	DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
	DCB DAUTHCTRL: Internal Secure invasive debug enable Mask.
#define	DCB_DAUTHCTRL_SPIDENSEL_Pos 0U
	DCB DAUTHCTRL: Secure invasive debug enable select Position.
#define	DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /<< DCB_DAUTHCTRL_SPIDENSEL_Pos/)
	DCB DAUTHCTRL: Secure invasive debug enable select Mask.
#define	DCB_DSCSR_CDSKEY_Pos 17U
	DCB DSCSR: CDS write-enable key Position.
#define	DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)
	DCB DSCSR: CDS write-enable key Mask.
#define	DCB_DSCSR_CDS_Pos 16U
	DCB DSCSR: Current domain Secure Position.
#define	DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)
	DCB DSCSR: Current domain Secure Mask.
#define	DCB_DSCSR_SBRSEL_Pos 1U
	DCB DSCSR: Secure banked register select Position.
#define	DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)
	DCB DSCSR: Secure banked register select Mask.
#define	DCB_DSCSR_SBRSELEN_Pos 0U
	DCB DSCSR: Secure banked register select enable Position.
#define	DCB_DSCSR_SBRSELEN_Msk (0x1UL /<< DCB_DSCSR_SBRSELEN_Pos/)
	DCB DSCSR: Secure banked register select enable Mask.
#define	DIB_DLAR_KEY_Pos 0U
	DIB DLAR: KEY Position.
#define	DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /<< DIB_DLAR_KEY_Pos /)
	DIB DLAR: KEY Mask.
#define	DIB_DLSR_nTT_Pos 2U
	DIB DLSR: Not thirty-two bit Position.
#define	DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos )
	DIB DLSR: Not thirty-two bit Mask.
#define	DIB_DLSR_SLK_Pos 1U
	DIB DLSR: Software Lock status Position.
#define	DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos )
	DIB DLSR: Software Lock status Mask.
#define	DIB_DLSR_SLI_Pos 0U
	DIB DLSR: Software Lock implemented Position.
#define	DIB_DLSR_SLI_Msk (0x1UL /<< DIB_DLSR_SLI_Pos/)
	DIB DLSR: Software Lock implemented Mask.
#define	DIB_DAUTHSTATUS_SNID_Pos 6U
	DIB DAUTHSTATUS: Secure Non-invasive Debug Position.
#define	DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos )
	DIB DAUTHSTATUS: Secure Non-invasive Debug Mask.
#define	DIB_DAUTHSTATUS_SID_Pos 4U
	DIB DAUTHSTATUS: Secure Invasive Debug Position.
#define	DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos )
	DIB DAUTHSTATUS: Secure Invasive Debug Mask.
#define	DIB_DAUTHSTATUS_NSNID_Pos 2U
	DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position.
#define	DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos )
	DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask.
#define	DIB_DAUTHSTATUS_NSID_Pos 0U
	DIB DAUTHSTATUS: Non-secure Invasive Debug Position.
#define	DIB_DAUTHSTATUS_NSID_Msk (0x3UL /<< DIB_DAUTHSTATUS_NSID_Pos/)
	DIB DAUTHSTATUS: Non-secure Invasive Debug Mask.
#define	DIB_DDEVARCH_ARCHITECT_Pos 21U
	DIB DDEVARCH: Architect Position.
#define	DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos )
	DIB DDEVARCH: Architect Mask.
#define	DIB_DDEVARCH_PRESENT_Pos 20U
	DIB DDEVARCH: DEVARCH Present Position.
#define	DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos )
	DIB DDEVARCH: DEVARCH Present Mask.
#define	DIB_DDEVARCH_REVISION_Pos 16U
	DIB DDEVARCH: Revision Position.
#define	DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos )
	DIB DDEVARCH: Revision Mask.
#define	DIB_DDEVARCH_ARCHVER_Pos 12U
	DIB DDEVARCH: Architecture Version Position.
#define	DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos )
	DIB DDEVARCH: Architecture Version Mask.
#define	DIB_DDEVARCH_ARCHPART_Pos 0U
	DIB DDEVARCH: Architecture Part Position.
#define	DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /<< DIB_DDEVARCH_ARCHPART_Pos/)
	DIB DDEVARCH: Architecture Part Mask.
#define	DIB_DDEVTYPE_SUB_Pos 4U
	DIB DDEVTYPE: Sub-type Position.
#define	DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos )
	DIB DDEVTYPE: Sub-type Mask.
#define	DIB_DDEVTYPE_MAJOR_Pos 0U
	DIB DDEVTYPE: Major type Position.
#define	DIB_DDEVTYPE_MAJOR_Msk (0xFUL /<< DIB_DDEVTYPE_MAJOR_Pos/)
	DIB DDEVTYPE: Major type Mask.
#define	_VAL2FLD(field, value)
	Mask and shift a bit field value for use in a register bit range.
#define	_FLD2VAL(field, value)
	Mask and shift a register value to extract a bit filed value.
#define	SCS_BASE (0xE000E000UL)
	System Control Space Base Address.
#define	ITM_BASE (0xE0000000UL)
	ITM Base Address.
#define	DWT_BASE (0xE0001000UL)
	DWT Base Address.
#define	TPI_BASE (0xE0040000UL)
	TPI Base Address.
#define	DCB_BASE (0xE000EDF0UL)
	DCB Base Address.
#define	DIB_BASE (0xE000EFB0UL)
	DIB Base Address.
#define	SysTick_BASE (SCS_BASE + 0x0010UL)
	SysTick Base Address.
#define	NVIC_BASE (SCS_BASE + 0x0100UL)
	NVIC Base Address.
#define	SCB_BASE (SCS_BASE + 0x0D00UL)
	System Control Block Base Address.
#define	SCB ((SCB_Type *) SCB_BASE )
	SCB configuration struct.
#define	SysTick ((SysTick_Type *) SysTick_BASE )
	SysTick configuration struct.
#define	NVIC ((NVIC_Type *) NVIC_BASE )
	NVIC configuration struct.
#define	ITM ((ITM_Type *) ITM_BASE )
	ITM configuration struct.
#define	DWT ((DWT_Type *) DWT_BASE )
	DWT configuration struct.
#define	TPI ((TPI_Type *) TPI_BASE )
	TPI configuration struct.
#define	DCB ((DCB_Type *) DCB_BASE )
	DCB configuration struct.
#define	DIB ((DIB_Type *) DIB_BASE )
	DIB configuration struct.
#define	MPU_BASE (SCS_BASE + 0x0D90UL)
	Memory Protection Unit.
#define	MPU ((MPU_Type *) MPU_BASE )
	Memory Protection Unit.
#define	FPU_BASE (SCS_BASE + 0x0F30UL)
	Floating Point Unit.
#define	FPU ((FPU_Type *) FPU_BASE )
	Floating Point Unit.
#define	NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define	NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define	NVIC_EnableIRQ __NVIC_EnableIRQ
#define	NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define	NVIC_DisableIRQ __NVIC_DisableIRQ
#define	NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define	NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define	NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define	NVIC_GetActive __NVIC_GetActive
#define	NVIC_SetPriority __NVIC_SetPriority
#define	NVIC_GetPriority __NVIC_GetPriority
#define	NVIC_SystemReset __NVIC_SystemReset
#define	NVIC_SetVector __NVIC_SetVector
#define	NVIC_GetVector __NVIC_GetVector
#define	NVIC_USER_IRQ_OFFSET 16
#define	FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
#define	EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
#define	EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
#define	EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
#define	EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
#define	EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
#define	EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
#define	EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
#define	EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
	Value identifying ITM_RxBuffer is ready for next character.

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U
	CoreDebug DHCSR: DBGKEY Position.
#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
	CoreDebug DHCSR: DBGKEY Mask.
#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U
	CoreDebug DHCSR: S_RESET_ST Position.
#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
	CoreDebug DHCSR: S_RESET_ST Mask.
#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
	CoreDebug DHCSR: S_RETIRE_ST Position.
#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
	CoreDebug DHCSR: S_RETIRE_ST Mask.
#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U
	CoreDebug DHCSR: S_LOCKUP Position.
#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
	CoreDebug DHCSR: S_LOCKUP Mask.
#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U
	CoreDebug DHCSR: S_SLEEP Position.
#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
	CoreDebug DHCSR: S_SLEEP Mask.
#define	CoreDebug_DHCSR_S_HALT_Pos 17U
	CoreDebug DHCSR: S_HALT Position.
#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
	CoreDebug DHCSR: S_HALT Mask.
#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U
	CoreDebug DHCSR: S_REGRDY Position.
#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
	CoreDebug DHCSR: S_REGRDY Mask.
#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
	CoreDebug DHCSR: C_SNAPSTALL Position.
#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
	CoreDebug DHCSR: C_SNAPSTALL Mask.
#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U
	CoreDebug DHCSR: C_MASKINTS Position.
#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
	CoreDebug DHCSR: C_MASKINTS Mask.
#define	CoreDebug_DHCSR_C_STEP_Pos 2U
	CoreDebug DHCSR: C_STEP Position.
#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
	CoreDebug DHCSR: C_STEP Mask.
#define	CoreDebug_DHCSR_C_HALT_Pos 1U
	CoreDebug DHCSR: C_HALT Position.
#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
	CoreDebug DHCSR: C_HALT Mask.
#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
	CoreDebug DHCSR: C_DEBUGEN Position.
#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)
	CoreDebug DHCSR: C_DEBUGEN Mask.
#define	CoreDebug_DCRSR_REGWnR_Pos 16U
	CoreDebug DCRSR: REGWnR Position.
#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
	CoreDebug DCRSR: REGWnR Mask.
#define	CoreDebug_DCRSR_REGSEL_Pos 0U
	CoreDebug DCRSR: REGSEL Position.
#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)
	CoreDebug DCRSR: REGSEL Mask.
#define	CoreDebug_DEMCR_TRCENA_Pos 24U
	CoreDebug DEMCR: TRCENA Position.
#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
	CoreDebug DEMCR: TRCENA Mask.
#define	CoreDebug_DEMCR_MON_REQ_Pos 19U
	CoreDebug DEMCR: MON_REQ Position.
#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
	CoreDebug DEMCR: MON_REQ Mask.
#define	CoreDebug_DEMCR_MON_STEP_Pos 18U
	CoreDebug DEMCR: MON_STEP Position.
#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
	CoreDebug DEMCR: MON_STEP Mask.
#define	CoreDebug_DEMCR_MON_PEND_Pos 17U
	CoreDebug DEMCR: MON_PEND Position.
#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
	CoreDebug DEMCR: MON_PEND Mask.
#define	CoreDebug_DEMCR_MON_EN_Pos 16U
	CoreDebug DEMCR: MON_EN Position.
#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
	CoreDebug DEMCR: MON_EN Mask.
#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U
	CoreDebug DEMCR: VC_HARDERR Position.
#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
	CoreDebug DEMCR: VC_HARDERR Mask.
#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U
	CoreDebug DEMCR: VC_INTERR Position.
#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
	CoreDebug DEMCR: VC_INTERR Mask.
#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U
	CoreDebug DEMCR: VC_BUSERR Position.
#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
	CoreDebug DEMCR: VC_BUSERR Mask.
#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U
	CoreDebug DEMCR: VC_STATERR Position.
#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
	CoreDebug DEMCR: VC_STATERR Mask.
#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U
	CoreDebug DEMCR: VC_CHKERR Position.
#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
	CoreDebug DEMCR: VC_CHKERR Mask.
#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
	CoreDebug DEMCR: VC_NOCPERR Position.
#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
	CoreDebug DEMCR: VC_NOCPERR Mask.
#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U
	CoreDebug DEMCR: VC_MMERR Position.
#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
	CoreDebug DEMCR: VC_MMERR Mask.
#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U
	CoreDebug DEMCR: VC_CORERESET Position.
#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)
	CoreDebug DEMCR: VC_CORERESET Mask.
#define	CoreDebug_BASE (0xE000EDF0UL)
	Core Debug Base Address.
#define	CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )
	Core Debug configuration struct.

Functions

__STATIC_INLINE void	__NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
	Set Priority Grouping.
__STATIC_INLINE uint32_t	__NVIC_GetPriorityGrouping (void)
	Get Priority Grouping.
__STATIC_INLINE void	__NVIC_EnableIRQ (IRQn_Type IRQn)
	Enable Interrupt.
__STATIC_INLINE uint32_t	__NVIC_GetEnableIRQ (IRQn_Type IRQn)
	Get Interrupt Enable status.
__STATIC_INLINE void	__NVIC_DisableIRQ (IRQn_Type IRQn)
	Disable Interrupt.
__STATIC_INLINE uint32_t	__NVIC_GetPendingIRQ (IRQn_Type IRQn)
	Get Pending Interrupt.
__STATIC_INLINE void	__NVIC_SetPendingIRQ (IRQn_Type IRQn)
	Set Pending Interrupt.
__STATIC_INLINE void	__NVIC_ClearPendingIRQ (IRQn_Type IRQn)
	Clear Pending Interrupt.
__STATIC_INLINE uint32_t	__NVIC_GetActive (IRQn_Type IRQn)
	Get Active Interrupt.
__STATIC_INLINE void	__NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)
	Set Interrupt Priority.
__STATIC_INLINE uint32_t	__NVIC_GetPriority (IRQn_Type IRQn)
	Get Interrupt Priority.
__STATIC_INLINE uint32_t	NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
	Encode Priority.
__STATIC_INLINE void	NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t const pPreemptPriority, uint32_t const pSubPriority)
	Decode Priority.
__STATIC_INLINE void	__NVIC_SetVector (IRQn_Type IRQn, uint32_t vector)
	Set Interrupt Vector.
__STATIC_INLINE uint32_t	__NVIC_GetVector (IRQn_Type IRQn)
	Get Interrupt Vector.
__NO_RETURN __STATIC_INLINE void	__NVIC_SystemReset (void)
	System Reset.
__STATIC_INLINE uint32_t	SCB_GetFPUType (void)
	get FPU type
__STATIC_INLINE uint32_t	SCB_GetMVEType (void)
	get MVE type
__STATIC_INLINE void	DCB_SetAuthCtrl (uint32_t value)
	Set Debug Authentication Control Register.
__STATIC_INLINE uint32_t	DCB_GetAuthCtrl (void)
	Get Debug Authentication Control Register.
__STATIC_INLINE uint32_t	DIB_GetAuthStatus (void)
	Get Debug Authentication Status Register.
__STATIC_INLINE uint32_t	SysTick_Config (uint32_t ticks)
	System Tick Configuration.
__STATIC_INLINE uint32_t	ITM_SendChar (uint32_t ch)
	ITM Send Character.
__STATIC_INLINE int32_t	ITM_ReceiveChar (void)
	ITM Receive Character.
__STATIC_INLINE int32_t	ITM_CheckChar (void)
	ITM Check Character.
#define	__CORTEX_M (85U)
	Cortex-M Core.
#define	__CORE_CM85_H_DEPENDANT
#define	__I volatile const
	Defines 'read only' permissions.
#define	__O volatile
	Defines 'write only' permissions.
#define	__IO volatile
	Defines 'read / write' permissions.
#define	__IM volatile const /! Defines 'read only' structure member permissions /
#define	__OM volatile /! Defines 'write only' structure member permissions /
#define	__IOM volatile /! Defines 'read / write' structure member permissions /
#define	xPSR_B_Pos 21U
	xPSR: B Position
#define	xPSR_B_Msk (1UL << xPSR_B_Pos)
	xPSR: B Mask
#define	CONTROL_UPAC_EN_Pos 7U
	CONTROL: UPAC_EN Position.
#define	CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos)
	CONTROL: UPAC_EN Mask.
#define	CONTROL_PAC_EN_Pos 6U
	CONTROL: PAC_EN Position.
#define	CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos)
	CONTROL: PAC_EN Mask.
#define	CONTROL_UBTI_EN_Pos 5U
	CONTROL: UBTI_EN Position.
#define	CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos)
	CONTROL: UBTI_EN Mask.
#define	CONTROL_BTI_EN_Pos 4U
	CONTROL: BTI_EN Position.
#define	CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos)
	CONTROL: BTI_EN Mask.
#define	SCB_AIRCR_IESB_Pos 5U
	SCB AIRCR: Implicit ESB Enable Position.
#define	SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos)
	SCB AIRCR: Implicit ESB Enable Mask.
#define	SCB_AIRCR_DIT_Pos 4U
	SCB AIRCR: Data Independent Timing Position.
#define	SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos)
	SCB AIRCR: Data Independent Timing Mask.
#define	SCB_CCR_TRD_Pos 20U
	SCB CCR: TRD Position.
#define	SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos)
	SCB CCR: TRD Mask.
#define	SCB_CCR_LOB_Pos 19U
	SCB CCR: LOB Position.
#define	SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos)
	SCB CCR: LOB Mask.
#define	SCB_DFSR_PMU_Pos 5U
	SCB DFSR: PMU Position.
#define	SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos)
	SCB DFSR: PMU Mask.
#define	SCB_NSACR_CP7_Pos 7U
	SCB NSACR: CP7 Position.
#define	SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos)
	SCB NSACR: CP7 Mask.
#define	SCB_NSACR_CP6_Pos 6U
	SCB NSACR: CP6 Position.
#define	SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos)
	SCB NSACR: CP6 Mask.
#define	SCB_NSACR_CP5_Pos 5U
	SCB NSACR: CP5 Position.
#define	SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos)
	SCB NSACR: CP5 Mask.
#define	SCB_NSACR_CP4_Pos 4U
	SCB NSACR: CP4 Position.
#define	SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos)
	SCB NSACR: CP4 Mask.
#define	SCB_NSACR_CP3_Pos 3U
	SCB NSACR: CP3 Position.
#define	SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos)
	SCB NSACR: CP3 Mask.
#define	SCB_NSACR_CP2_Pos 2U
	SCB NSACR: CP2 Position.
#define	SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos)
	SCB NSACR: CP2 Mask.
#define	SCB_NSACR_CP1_Pos 1U
	SCB NSACR: CP1 Position.
#define	SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos)
	SCB NSACR: CP1 Mask.
#define	SCB_NSACR_CP0_Pos 0U
	SCB NSACR: CP0 Position.
#define	SCB_NSACR_CP0_Msk (1UL /<< SCB_NSACR_CP0_Pos/)
	SCB NSACR: CP0 Mask.
#define	SCB_ID_DFR_UDE_Pos 28U
	SCB ID_DFR: UDE Position.
#define	SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos)
	SCB ID_DFR: UDE Mask.
#define	SCB_ID_DFR_MProfDbg_Pos 20U
	SCB ID_DFR: MProfDbg Position.
#define	SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos)
	SCB ID_DFR: MProfDbg Mask.
#define	SCB_RFSR_V_Pos 31U
	SCB RFSR: V Position.
#define	SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos)
	SCB RFSR: V Mask.
#define	SCB_RFSR_IS_Pos 16U
	SCB RFSR: IS Position.
#define	SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos)
	SCB RFSR: IS Mask.
#define	SCB_RFSR_UET_Pos 0U
	SCB RFSR: UET Position.
#define	SCB_RFSR_UET_Msk (3UL /<< SCB_RFSR_UET_Pos/)
	SCB RFSR: UET Mask.
#define	ICB_ACTLR_DISCRITAXIRUW_Pos 27U
	ACTLR: DISCRITAXIRUW Position.
#define	ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos)
	ACTLR: DISCRITAXIRUW Mask.
#define	ICB_ACTLR_DISCRITAXIRUR_Pos 15U
	ACTLR: DISCRITAXIRUR Position.
#define	ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos)
	ACTLR: DISCRITAXIRUR Mask.
#define	ICB_ACTLR_EVENTBUSEN_Pos 14U
	ACTLR: EVENTBUSEN Position.
#define	ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos)
	ACTLR: EVENTBUSEN Mask.
#define	ICB_ACTLR_EVENTBUSEN_S_Pos 13U
	ACTLR: EVENTBUSEN_S Position.
#define	ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos)
	ACTLR: EVENTBUSEN_S Mask.
#define	ICB_ACTLR_DISITMATBFLUSH_Pos 12U
	ACTLR: DISITMATBFLUSH Position.
#define	ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos)
	ACTLR: DISITMATBFLUSH Mask.
#define	ICB_ACTLR_DISNWAMODE_Pos 11U
	ACTLR: DISNWAMODE Position.
#define	ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos)
	ACTLR: DISNWAMODE Mask.
#define	ICB_ACTLR_FPEXCODIS_Pos 10U
	ACTLR: FPEXCODIS Position.
#define	ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos)
	ACTLR: FPEXCODIS Mask.
#define	ICB_ICTR_INTLINESNUM_Pos 0U
	ICTR: INTLINESNUM Position.
#define	ICB_ICTR_INTLINESNUM_Msk (0xFUL /<< ICB_ICTR_INTLINESNUM_Pos/)
	ICTR: INTLINESNUM Mask.
#define	MEMSYSCTL_MSCR_CPWRDN_Pos 17U
	MEMSYSCTL MSCR: CPWRDN Position.
#define	MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos)
	MEMSYSCTL MSCR: CPWRDN Mask.
#define	MEMSYSCTL_MSCR_DCCLEAN_Pos 16U
	MEMSYSCTL MSCR: DCCLEAN Position.
#define	MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos)
	MEMSYSCTL MSCR: DCCLEAN Mask.
#define	MEMSYSCTL_MSCR_ICACTIVE_Pos 13U
	MEMSYSCTL MSCR: ICACTIVE Position.
#define	MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos)
	MEMSYSCTL MSCR: ICACTIVE Mask.
#define	MEMSYSCTL_MSCR_DCACTIVE_Pos 12U
	MEMSYSCTL MSCR: DCACTIVE Position.
#define	MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos)
	MEMSYSCTL MSCR: DCACTIVE Mask.
#define	MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U
	MEMSYSCTL MSCR: EVECCFAULT Position.
#define	MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos)
	MEMSYSCTL MSCR: EVECCFAULT Mask.
#define	MEMSYSCTL_MSCR_FORCEWT_Pos 2U
	MEMSYSCTL MSCR: FORCEWT Position.
#define	MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos)
	MEMSYSCTL MSCR: FORCEWT Mask.
#define	MEMSYSCTL_MSCR_ECCEN_Pos 1U
	MEMSYSCTL MSCR: ECCEN Position.
#define	MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos)
	MEMSYSCTL MSCR: ECCEN Mask.
#define	MEMSYSCTL_PFCR_DIS_NLP_Pos 7U
	MEMSYSCTL PFCR: DIS_NLP Position.
#define	MEMSYSCTL_PFCR_DIS_NLP_Msk (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos)
	MEMSYSCTL PFCR: DIS_NLP Mask.
#define	MEMSYSCTL_PFCR_ENABLE_Pos 0U
	MEMSYSCTL PFCR: ENABLE Position.
#define	MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /<< MEMSYSCTL_PFCR_ENABLE_Pos/)
	MEMSYSCTL PFCR: ENABLE Mask.
#define	MEMSYSCTL_ITCMCR_SZ_Pos 3U
	MEMSYSCTL ITCMCR: SZ Position.
#define	MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos)
	MEMSYSCTL ITCMCR: SZ Mask.
#define	MEMSYSCTL_ITCMCR_EN_Pos 0U
	MEMSYSCTL ITCMCR: EN Position.
#define	MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /<< MEMSYSCTL_ITCMCR_EN_Pos/)
	MEMSYSCTL ITCMCR: EN Mask.
#define	MEMSYSCTL_DTCMCR_SZ_Pos 3U
	MEMSYSCTL DTCMCR: SZ Position.
#define	MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos)
	MEMSYSCTL DTCMCR: SZ Mask.
#define	MEMSYSCTL_DTCMCR_EN_Pos 0U
	MEMSYSCTL DTCMCR: EN Position.
#define	MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /<< MEMSYSCTL_DTCMCR_EN_Pos/)
	MEMSYSCTL DTCMCR: EN Mask.
#define	MEMSYSCTL_PAHBCR_SZ_Pos 1U
	MEMSYSCTL PAHBCR: SZ Position.
#define	MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos)
	MEMSYSCTL PAHBCR: SZ Mask.
#define	MEMSYSCTL_PAHBCR_EN_Pos 0U
	MEMSYSCTL PAHBCR: EN Position.
#define	MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /<< MEMSYSCTL_PAHBCR_EN_Pos/)
	MEMSYSCTL PAHBCR: EN Mask.
#define	MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U
	MEMSYSCTL ITGU_CTRL: DEREN Position.
#define	MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos)
	MEMSYSCTL ITGU_CTRL: DEREN Mask.
#define	MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U
	MEMSYSCTL ITGU_CTRL: DBFEN Position.
#define	MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos/)
	MEMSYSCTL ITGU_CTRL: DBFEN Mask.
#define	MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U
	MEMSYSCTL ITGU_CFG: PRESENT Position.
#define	MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos)
	MEMSYSCTL ITGU_CFG: PRESENT Mask.
#define	MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U
	MEMSYSCTL ITGU_CFG: NUMBLKS Position.
#define	MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos)
	MEMSYSCTL ITGU_CFG: NUMBLKS Mask.
#define	MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U
	MEMSYSCTL ITGU_CFG: BLKSZ Position.
#define	MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos/)
	MEMSYSCTL ITGU_CFG: BLKSZ Mask.
#define	MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U
	MEMSYSCTL DTGU_CTRL: DEREN Position.
#define	MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos)
	MEMSYSCTL DTGU_CTRL: DEREN Mask.
#define	MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U
	MEMSYSCTL DTGU_CTRL: DBFEN Position.
#define	MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos/)
	MEMSYSCTL DTGU_CTRL: DBFEN Mask.
#define	MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U
	MEMSYSCTL DTGU_CFG: PRESENT Position.
#define	MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos)
	MEMSYSCTL DTGU_CFG: PRESENT Mask.
#define	MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U
	MEMSYSCTL DTGU_CFG: NUMBLKS Position.
#define	MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos)
	MEMSYSCTL DTGU_CFG: NUMBLKS Mask.
#define	MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U
	MEMSYSCTL DTGU_CFG: BLKSZ Position.
#define	MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos/)
	MEMSYSCTL DTGU_CFG: BLKSZ Mask.
#define	PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U
	PWRMODCTL CPDLPSTATE: RLPSTATE Position.
#define	PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos)
	PWRMODCTL CPDLPSTATE: RLPSTATE Mask.
#define	PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U
	PWRMODCTL CPDLPSTATE: ELPSTATE Position.
#define	PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos)
	PWRMODCTL CPDLPSTATE: ELPSTATE Mask.
#define	PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U
	PWRMODCTL CPDLPSTATE: CLPSTATE Position.
#define	PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos/)
	PWRMODCTL CPDLPSTATE: CLPSTATE Mask.
#define	PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U
	PWRMODCTL DPDLPSTATE: DLPSTATE Position.
#define	PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos/)
	PWRMODCTL DPDLPSTATE: DLPSTATE Mask.
#define	EWIC_EVENTSPR_EDBGREQ_Pos 2U
	EWIC EVENTSPR: EDBGREQ Position.
#define	EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos)
	EWIC EVENTSPR: EDBGREQ Mask.
#define	EWIC_EVENTSPR_NMI_Pos 1U
	EWIC EVENTSPR: NMI Position.
#define	EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos)
	EWIC EVENTSPR: NMI Mask.
#define	EWIC_EVENTSPR_EVENT_Pos 0U
	EWIC EVENTSPR: EVENT Position.
#define	EWIC_EVENTSPR_EVENT_Msk (0x1UL /<< EWIC_EVENTSPR_EVENT_Pos/)
	EWIC EVENTSPR: EVENT Mask.
#define	EWIC_EVENTMASKA_EDBGREQ_Pos 2U
	EWIC EVENTMASKA: EDBGREQ Position.
#define	EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos)
	EWIC EVENTMASKA: EDBGREQ Mask.
#define	EWIC_EVENTMASKA_NMI_Pos 1U
	EWIC EVENTMASKA: NMI Position.
#define	EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos)
	EWIC EVENTMASKA: NMI Mask.
#define	EWIC_EVENTMASKA_EVENT_Pos 0U
	EWIC EVENTMASKA: EVENT Position.
#define	EWIC_EVENTMASKA_EVENT_Msk (0x1UL /<< EWIC_EVENTMASKA_EVENT_Pos/)
	EWIC EVENTMASKA: EVENT Mask.
#define	EWIC_EVENTMASK_IRQ_Pos 0U
	EWIC EVENTMASKA: IRQ Position.
#define	EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /<< EWIC_EVENTMASKA_IRQ_Pos/)
	EWIC EVENTMASKA: IRQ Mask.
#define	ERRBNK_IEBR0_SWDEF_Pos 30U
	ERRBNK IEBR0: SWDEF Position.
#define	ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos)
	ERRBNK IEBR0: SWDEF Mask.
#define	ERRBNK_IEBR0_BANK_Pos 16U
	ERRBNK IEBR0: BANK Position.
#define	ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos)
	ERRBNK IEBR0: BANK Mask.
#define	ERRBNK_IEBR0_LOCATION_Pos 2U
	ERRBNK IEBR0: LOCATION Position.
#define	ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos)
	ERRBNK IEBR0: LOCATION Mask.
#define	ERRBNK_IEBR0_LOCKED_Pos 1U
	ERRBNK IEBR0: LOCKED Position.
#define	ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos)
	ERRBNK IEBR0: LOCKED Mask.
#define	ERRBNK_IEBR0_VALID_Pos 0U
	ERRBNK IEBR0: VALID Position.
#define	ERRBNK_IEBR0_VALID_Msk (0x1UL << /ERRBNK_IEBR0_VALID_Pos/)
	ERRBNK IEBR0: VALID Mask.
#define	ERRBNK_IEBR1_SWDEF_Pos 30U
	ERRBNK IEBR1: SWDEF Position.
#define	ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos)
	ERRBNK IEBR1: SWDEF Mask.
#define	ERRBNK_IEBR1_BANK_Pos 16U
	ERRBNK IEBR1: BANK Position.
#define	ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos)
	ERRBNK IEBR1: BANK Mask.
#define	ERRBNK_IEBR1_LOCATION_Pos 2U
	ERRBNK IEBR1: LOCATION Position.
#define	ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos)
	ERRBNK IEBR1: LOCATION Mask.
#define	ERRBNK_IEBR1_LOCKED_Pos 1U
	ERRBNK IEBR1: LOCKED Position.
#define	ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos)
	ERRBNK IEBR1: LOCKED Mask.
#define	ERRBNK_IEBR1_VALID_Pos 0U
	ERRBNK IEBR1: VALID Position.
#define	ERRBNK_IEBR1_VALID_Msk (0x1UL << /ERRBNK_IEBR1_VALID_Pos/)
	ERRBNK IEBR1: VALID Mask.
#define	ERRBNK_DEBR0_SWDEF_Pos 30U
	ERRBNK DEBR0: SWDEF Position.
#define	ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos)
	ERRBNK DEBR0: SWDEF Mask.
#define	ERRBNK_DEBR0_TYPE_Pos 17U
	ERRBNK DEBR0: TYPE Position.
#define	ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos)
	ERRBNK DEBR0: TYPE Mask.
#define	ERRBNK_DEBR0_BANK_Pos 16U
	ERRBNK DEBR0: BANK Position.
#define	ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos)
	ERRBNK DEBR0: BANK Mask.
#define	ERRBNK_DEBR0_LOCATION_Pos 2U
	ERRBNK DEBR0: LOCATION Position.
#define	ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos)
	ERRBNK DEBR0: LOCATION Mask.
#define	ERRBNK_DEBR0_LOCKED_Pos 1U
	ERRBNK DEBR0: LOCKED Position.
#define	ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos)
	ERRBNK DEBR0: LOCKED Mask.
#define	ERRBNK_DEBR0_VALID_Pos 0U
	ERRBNK DEBR0: VALID Position.
#define	ERRBNK_DEBR0_VALID_Msk (0x1UL << /ERRBNK_DEBR0_VALID_Pos/)
	ERRBNK DEBR0: VALID Mask.
#define	ERRBNK_DEBR1_SWDEF_Pos 30U
	ERRBNK DEBR1: SWDEF Position.
#define	ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos)
	ERRBNK DEBR1: SWDEF Mask.
#define	ERRBNK_DEBR1_TYPE_Pos 17U
	ERRBNK DEBR1: TYPE Position.
#define	ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos)
	ERRBNK DEBR1: TYPE Mask.
#define	ERRBNK_DEBR1_BANK_Pos 16U
	ERRBNK DEBR1: BANK Position.
#define	ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos)
	ERRBNK DEBR1: BANK Mask.
#define	ERRBNK_DEBR1_LOCATION_Pos 2U
	ERRBNK DEBR1: LOCATION Position.
#define	ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos)
	ERRBNK DEBR1: LOCATION Mask.
#define	ERRBNK_DEBR1_LOCKED_Pos 1U
	ERRBNK DEBR1: LOCKED Position.
#define	ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos)
	ERRBNK DEBR1: LOCKED Mask.
#define	ERRBNK_DEBR1_VALID_Pos 0U
	ERRBNK DEBR1: VALID Position.
#define	ERRBNK_DEBR1_VALID_Msk (0x1UL << /ERRBNK_DEBR1_VALID_Pos/)
	ERRBNK DEBR1: VALID Mask.
#define	ERRBNK_TEBR0_SWDEF_Pos 30U
	ERRBNK TEBR0: SWDEF Position.
#define	ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos)
	ERRBNK TEBR0: SWDEF Mask.
#define	ERRBNK_TEBR0_POISON_Pos 28U
	ERRBNK TEBR0: POISON Position.
#define	ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos)
	ERRBNK TEBR0: POISON Mask.
#define	ERRBNK_TEBR0_TYPE_Pos 27U
	ERRBNK TEBR0: TYPE Position.
#define	ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos)
	ERRBNK TEBR0: TYPE Mask.
#define	ERRBNK_TEBR0_BANK_Pos 24U
	ERRBNK TEBR0: BANK Position.
#define	ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos)
	ERRBNK TEBR0: BANK Mask.
#define	ERRBNK_TEBR0_LOCATION_Pos 2U
	ERRBNK TEBR0: LOCATION Position.
#define	ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos)
	ERRBNK TEBR0: LOCATION Mask.
#define	ERRBNK_TEBR0_LOCKED_Pos 1U
	ERRBNK TEBR0: LOCKED Position.
#define	ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos)
	ERRBNK TEBR0: LOCKED Mask.
#define	ERRBNK_TEBR0_VALID_Pos 0U
	ERRBNK TEBR0: VALID Position.
#define	ERRBNK_TEBR0_VALID_Msk (0x1UL << /ERRBNK_TEBR0_VALID_Pos/)
	ERRBNK TEBR0: VALID Mask.
#define	ERRBNK_TEBR1_SWDEF_Pos 30U
	ERRBNK TEBR1: SWDEF Position.
#define	ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos)
	ERRBNK TEBR1: SWDEF Mask.
#define	ERRBNK_TEBR1_POISON_Pos 28U
	ERRBNK TEBR1: POISON Position.
#define	ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos)
	ERRBNK TEBR1: POISON Mask.
#define	ERRBNK_TEBR1_TYPE_Pos 27U
	ERRBNK TEBR1: TYPE Position.
#define	ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos)
	ERRBNK TEBR1: TYPE Mask.
#define	ERRBNK_TEBR1_BANK_Pos 24U
	ERRBNK TEBR1: BANK Position.
#define	ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos)
	ERRBNK TEBR1: BANK Mask.
#define	ERRBNK_TEBR1_LOCATION_Pos 2U
	ERRBNK TEBR1: LOCATION Position.
#define	ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos)
	ERRBNK TEBR1: LOCATION Mask.
#define	ERRBNK_TEBR1_LOCKED_Pos 1U
	ERRBNK TEBR1: LOCKED Position.
#define	ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos)
	ERRBNK TEBR1: LOCKED Mask.
#define	ERRBNK_TEBR1_VALID_Pos 0U
	ERRBNK TEBR1: VALID Position.
#define	ERRBNK_TEBR1_VALID_Msk (0x1UL << /ERRBNK_TEBR1_VALID_Pos/)
	ERRBNK TEBR1: VALID Mask.
#define	TPI_ACPR_SWOSCALER_Pos 0U
	TPI ACPR: SWOSCALER Position.
#define	TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/)
	TPI ACPR: SWOSCALER Mask.
#define	TPI_FFCR_EnFmt_Pos 0U
	TPI FFCR: EnFmt Position.
#define	TPI_FFCR_EnFmt_Msk (0x3UL << /TPI_FFCR_EnFmt_Pos/)
	TPI FFCR: EnFmt Mask.
#define	TPI_PSCR_PSCount_Pos 0U
	TPI PSCR: PSCount Position.
#define	TPI_PSCR_PSCount_Msk (0x1FUL /<< TPI_PSCR_PSCount_Pos/)
	TPI PSCR: TPSCount Mask.
#define	TPI_LSR_nTT_Pos 1U
	TPI LSR: Not thirty-two bit.
#define	TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)
	TPI LSR: Not thirty-two bit.
#define	TPI_LSR_SLK_Pos 1U
	TPI LSR: Software Lock status Position.
#define	TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)
	TPI LSR: Software Lock status Mask.
#define	TPI_LSR_SLI_Pos 0U
	TPI LSR: Software Lock implemented Position.
#define	TPI_LSR_SLI_Msk (0x1UL /<< TPI_LSR_SLI_Pos/)
	TPI LSR: Software Lock implemented Mask.
#define	MPU_RLAR_PXN_Pos 4U
	MPU RLAR: PXN Position.
#define	MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos)
	MPU RLAR: PXN Mask.
#define	FPU_FPDSCR_FZ16_Pos 19U
	FPDSCR: FZ16 bit Position.
#define	FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos)
	FPDSCR: FZ16 bit Mask.
#define	FPU_FPDSCR_LTPSIZE_Pos 16U
	FPDSCR: LTPSIZE bit Position.
#define	FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos)
	FPDSCR: LTPSIZE bit Mask.
#define	FPU_MVFR0_FPRound_Pos 28U
	MVFR0: FPRound bits Position.
#define	FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos)
	MVFR0: FPRound bits Mask.
#define	FPU_MVFR0_FPSqrt_Pos 20U
	MVFR0: FPSqrt bits Position.
#define	FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos)
	MVFR0: FPSqrt bits Mask.
#define	FPU_MVFR0_FPDivide_Pos 16U
	MVFR0: FPDivide bits Position.
#define	FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos)
	MVFR0: Divide bits Mask.
#define	FPU_MVFR0_FPDP_Pos 8U
	MVFR0: FPDP bits Position.
#define	FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos)
	MVFR0: FPDP bits Mask.
#define	FPU_MVFR0_FPSP_Pos 4U
	MVFR0: FPSP bits Position.
#define	FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos)
	MVFR0: FPSP bits Mask.
#define	FPU_MVFR0_SIMDReg_Pos 0U
	MVFR0: SIMDReg bits Position.
#define	FPU_MVFR0_SIMDReg_Msk (0xFUL /<< FPU_MVFR0_SIMDReg_Pos/)
	MVFR0: SIMDReg bits Mask.
#define	FPU_MVFR1_FMAC_Pos 28U
	MVFR1: FMAC bits Position.
#define	FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos)
	MVFR1: FMAC bits Mask.
#define	FPU_MVFR1_FPHP_Pos 24U
	MVFR1: FPHP bits Position.
#define	FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos)
	MVFR1: FPHP bits Mask.
#define	FPU_MVFR1_FP16_Pos 20U
	MVFR1: FP16 bits Position.
#define	FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos)
	MVFR1: FP16 bits Mask.
#define	FPU_MVFR1_MVE_Pos 8U
	MVFR1: MVE bits Position.
#define	FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos)
	MVFR1: MVE bits Mask.
#define	FPU_MVFR1_FPDNaN_Pos 4U
	MVFR1: FPDNaN bits Position.
#define	FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos)
	MVFR1: FPDNaN bits Mask.
#define	FPU_MVFR1_FPFtZ_Pos 0U
	MVFR1: FPFtZ bits Position.
#define	FPU_MVFR1_FPFtZ_Msk (0xFUL /<< FPU_MVFR1_FPFtZ_Pos/)
	MVFR1: FPFtZ bits Mask.
#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U
#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
#define	CoreDebug_DHCSR_S_FPD_Pos 23U
#define	CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos)
#define	CoreDebug_DHCSR_S_SUIDE_Pos 22U
#define	CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos)
#define	CoreDebug_DHCSR_S_NSUIDE_Pos 21U
#define	CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos)
#define	CoreDebug_DHCSR_S_SDE_Pos 20U
#define	CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos)
#define	CoreDebug_DHCSR_C_PMOV_Pos 6U
#define	CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos)
#define	CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U
#define	CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos)
#define	CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U
#define	CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos)
#define	CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U
#define	CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos)
#define	CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U
#define	CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos)
#define	CoreDebug_DAUTHCTRL_UIDEN_Pos 10U
#define	CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos)
#define	CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U
#define	CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos)
#define	CoreDebug_DAUTHCTRL_FSDMA_Pos 8U
#define	CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos)
#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U
#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U
#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U
#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U
#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)
#define	CoreDebug_DSCSR_CDS_Pos 16U
#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)
#define	CoreDebug_DSCSR_SBRSEL_Pos 1U
#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U
#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)
#define	DCB_DHCSR_S_FPD_Pos 23U
	DCB DHCSR: Floating-point registers Debuggable Position.
#define	DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos)
	DCB DHCSR: Floating-point registers Debuggable Mask.
#define	DCB_DHCSR_S_SUIDE_Pos 22U
	DCB DHCSR: Secure unprivileged halting debug enabled Position.
#define	DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos)
	DCB DHCSR: Secure unprivileged halting debug enabled Mask.
#define	DCB_DHCSR_S_NSUIDE_Pos 21U
	DCB DHCSR: Non-secure unprivileged halting debug enabled Position.
#define	DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)
	DCB DHCSR: Non-secure unprivileged halting debug enabled Mask.
#define	DCB_DHCSR_C_PMOV_Pos 6U
	DCB DHCSR: Halt on PMU overflow control Position.
#define	DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos)
	DCB DHCSR: Halt on PMU overflow control Mask.
#define	DCB_DSCEMCR_CLR_MON_REQ_Pos 19U
	DCB DSCEMCR: Clear monitor request Position.
#define	DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)
	DCB DSCEMCR: Clear monitor request Mask.
#define	DCB_DSCEMCR_CLR_MON_PEND_Pos 17U
	DCB DSCEMCR: Clear monitor pend Position.
#define	DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)
	DCB DSCEMCR: Clear monitor pend Mask.
#define	DCB_DSCEMCR_SET_MON_REQ_Pos 3U
	DCB DSCEMCR: Set monitor request Position.
#define	DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)
	DCB DSCEMCR: Set monitor request Mask.
#define	DCB_DSCEMCR_SET_MON_PEND_Pos 1U
	DCB DSCEMCR: Set monitor pend Position.
#define	DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)
	DCB DSCEMCR: Set monitor pend Mask.
#define	DCB_DAUTHCTRL_UIDEN_Pos 10U
	DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position.
#define	DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)
	DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask.
#define	DCB_DAUTHCTRL_UIDAPEN_Pos 9U
	DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position.
#define	DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)
	DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask.
#define	DCB_DAUTHCTRL_FSDMA_Pos 8U
	DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position.
#define	DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)
	DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask.
#define	DIB_DAUTHSTATUS_SUNID_Pos 22U
	DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position.
#define	DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos )
	DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask.
#define	DIB_DAUTHSTATUS_SUID_Pos 20U
	DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position.
#define	DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos )
	DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask.
#define	DIB_DAUTHSTATUS_NSUNID_Pos 18U
	DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position.
#define	DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos )
	DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask.
#define	DIB_DAUTHSTATUS_NSUID_Pos 16U
	DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position.
#define	DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos )
	DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask.
#define	MEMSYSCTL_BASE (0xE001E000UL)
	Memory System Control Base Address.
#define	ERRBNK_BASE (0xE001E100UL)
	Error Banking Base Address.
#define	PWRMODCTL_BASE (0xE001E300UL)
	Power Mode Control Base Address.
#define	EWIC_BASE (0xE001E400UL)
	External Wakeup Interrupt Controller Base Address.
#define	PRCCFGINF_BASE (0xE001E700UL)
	Processor Configuration Information Base Address.
#define	ICB ((ICB_Type *) SCS_BASE )
	System control Register not in SCB.
#define	MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE )
	Memory System Control configuration struct.
#define	ERRBNK ((ErrBnk_Type *) ERRBNK_BASE )
	Error Banking configuration struct.
#define	PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE )
	Power Mode Control configuration struct.
#define	EWIC ((EWIC_Type *) EWIC_BASE )
	EWIC configuration struct.
#define	PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE )
	Processor Configuration Information configuration struct.
volatile int32_t	ITM_RxBuffer
	External variable to receive characters.

Detailed Description

CMSIS Cortex-M85 Core Peripheral Access Layer Header File.

Version: V1.0.4

Date: 21. April 2022

Definition in file core_cm85.h.

Macro Definition Documentation

◆ __CORE_CM85_H_DEPENDANT

#define __CORE_CM85_H_DEPENDANT

Definition at line 192 of file core_cm85.h.

◆ __CORE_CM85_H_GENERIC

#define __CORE_CM85_H_GENERIC

Definition at line 34 of file core_cm85.h.

◆ __CORTEX_M

#define __CORTEX_M (85U)

Cortex-M Core.

Definition at line 69 of file core_cm85.h.

◆ __I

#define __I volatile const

Defines 'read only' permissions.

Definition at line 283 of file core_cm85.h.

◆ __IM

#define __IM volatile const /*! Defines 'read only' structure member permissions */

Definition at line 289 of file core_cm85.h.

◆ __IO

#define __IO volatile

Defines 'read / write' permissions.

Definition at line 286 of file core_cm85.h.

◆ __IOM

#define __IOM volatile /*! Defines 'read / write' structure member permissions */

Definition at line 291 of file core_cm85.h.

◆ __O

#define __O volatile

Defines 'write only' permissions.

Definition at line 285 of file core_cm85.h.

◆ __OM

#define __OM volatile /*! Defines 'write only' structure member permissions */

Definition at line 290 of file core_cm85.h.

Classes

Macros

Functions