core_armv8mbl.h File Reference

CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File. More...

#include <stdint.h>
#include "cmsis_version.h"
#include "cmsis_compiler.h"
#include "mpu_armv8.h"

Include dependency graph for core_armv8mbl.h:

Go to the source code of this file.

Classes
union	APSR_Type
	Union type to access the Application Program Status Register (APSR). More...
union	IPSR_Type
	Union type to access the Interrupt Program Status Register (IPSR). More...
union	xPSR_Type
	Union type to access the Special-Purpose Program Status Registers (xPSR). More...
union	CONTROL_Type
	Union type to access the Control Registers (CONTROL). More...
struct	NVIC_Type
	Structure type to access the Nested Vectored Interrupt Controller (NVIC). More...
struct	SCB_Type
	Structure type to access the System Control Block (SCB). More...
struct	SysTick_Type
	Structure type to access the System Timer (SysTick). More...
struct	DWT_Type
	Structure type to access the Data Watchpoint and Trace Register (DWT). More...
struct	TPI_Type
	Structure type to access the Trace Port Interface Register (TPI). More...
struct	MPU_Type
	Structure type to access the Memory Protection Unit (MPU). More...
struct	CoreDebug_Type
	Structure type to access the Core Debug Register (CoreDebug). More...
struct	DCB_Type
	Structure type to access the Debug Control Block Registers (DCB). More...
struct	DIB_Type
	Structure type to access the Debug Identification Block Registers (DIB). More...

Macros
#define	__CORE_ARMV8MBL_H_GENERIC
#define	__ARMv8MBL_CMSIS_VERSION_MAIN   (__CM_CMSIS_VERSION_MAIN)
#define	__ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)
#define	__ARMv8MBL_CMSIS_VERSION
#define	__CORTEX_M   (2U)
	Cortex-M Core.
#define	__FPU_USED   0U
	__FPU_USED indicates whether an FPU is used or not.
#define	__CORE_ARMV8MBL_H_DEPENDANT
#define	__I   volatile const
	Defines 'read only' permissions.
#define	__O   volatile
	Defines 'write only' permissions.
#define	__IO   volatile
	Defines 'read / write' permissions.
#define	__IM   volatile const /*! Defines 'read only' structure member permissions */
#define	__OM   volatile /*! Defines 'write only' structure member permissions */
#define	__IOM   volatile /*! Defines 'read / write' structure member permissions */
#define	APSR_N_Pos   31U
	APSR: N Position.
#define	APSR_N_Msk   (1UL << APSR_N_Pos)
	APSR: N Mask.
#define	APSR_Z_Pos   30U
	APSR: Z Position.
#define	APSR_Z_Msk   (1UL << APSR_Z_Pos)
	APSR: Z Mask.
#define	APSR_C_Pos   29U
	APSR: C Position.
#define	APSR_C_Msk   (1UL << APSR_C_Pos)
	APSR: C Mask.
#define	APSR_V_Pos   28U
	APSR: V Position.
#define	APSR_V_Msk   (1UL << APSR_V_Pos)
	APSR: V Mask.
#define	IPSR_ISR_Pos   0U
	IPSR: ISR Position.
#define	IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)
	IPSR: ISR Mask.
#define	xPSR_N_Pos   31U
	xPSR: N Position
#define	xPSR_N_Msk   (1UL << xPSR_N_Pos)
	xPSR: N Mask
#define	xPSR_Z_Pos   30U
	xPSR: Z Position
#define	xPSR_Z_Msk   (1UL << xPSR_Z_Pos)
	xPSR: Z Mask
#define	xPSR_C_Pos   29U
	xPSR: C Position
#define	xPSR_C_Msk   (1UL << xPSR_C_Pos)
	xPSR: C Mask
#define	xPSR_V_Pos   28U
	xPSR: V Position
#define	xPSR_V_Msk   (1UL << xPSR_V_Pos)
	xPSR: V Mask
#define	xPSR_T_Pos   24U
	xPSR: T Position
#define	xPSR_T_Msk   (1UL << xPSR_T_Pos)
	xPSR: T Mask
#define	xPSR_ISR_Pos   0U
	xPSR: ISR Position
#define	xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)
	xPSR: ISR Mask
#define	CONTROL_SPSEL_Pos   1U
	CONTROL: SPSEL Position.
#define	CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)
	CONTROL: SPSEL Mask.
#define	CONTROL_nPRIV_Pos   0U
	CONTROL: nPRIV Position.
#define	CONTROL_nPRIV_Msk   (1UL /*<< CONTROL_nPRIV_Pos*/)
	CONTROL: nPRIV Mask.
#define	SCB_CPUID_IMPLEMENTER_Pos   24U
	SCB CPUID: IMPLEMENTER Position.
#define	SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
	SCB CPUID: IMPLEMENTER Mask.
#define	SCB_CPUID_VARIANT_Pos   20U
	SCB CPUID: VARIANT Position.
#define	SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
	SCB CPUID: VARIANT Mask.
#define	SCB_CPUID_ARCHITECTURE_Pos   16U
	SCB CPUID: ARCHITECTURE Position.
#define	SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
	SCB CPUID: ARCHITECTURE Mask.
#define	SCB_CPUID_PARTNO_Pos   4U
	SCB CPUID: PARTNO Position.
#define	SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
	SCB CPUID: PARTNO Mask.
#define	SCB_CPUID_REVISION_Pos   0U
	SCB CPUID: REVISION Position.
#define	SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
	SCB CPUID: REVISION Mask.
#define	SCB_ICSR_PENDNMISET_Pos   31U
	SCB ICSR: PENDNMISET Position.
#define	SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
	SCB ICSR: PENDNMISET Mask.
#define	SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
	SCB ICSR: NMIPENDSET Position, backward compatibility.
#define	SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
	SCB ICSR: NMIPENDSET Mask, backward compatibility.
#define	SCB_ICSR_PENDNMICLR_Pos   30U
	SCB ICSR: PENDNMICLR Position.
#define	SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
	SCB ICSR: PENDNMICLR Mask.
#define	SCB_ICSR_PENDSVSET_Pos   28U
	SCB ICSR: PENDSVSET Position.
#define	SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
	SCB ICSR: PENDSVSET Mask.
#define	SCB_ICSR_PENDSVCLR_Pos   27U
	SCB ICSR: PENDSVCLR Position.
#define	SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
	SCB ICSR: PENDSVCLR Mask.
#define	SCB_ICSR_PENDSTSET_Pos   26U
	SCB ICSR: PENDSTSET Position.
#define	SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
	SCB ICSR: PENDSTSET Mask.
#define	SCB_ICSR_PENDSTCLR_Pos   25U
	SCB ICSR: PENDSTCLR Position.
#define	SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
	SCB ICSR: PENDSTCLR Mask.
#define	SCB_ICSR_STTNS_Pos   24U
	SCB ICSR: STTNS Position (Security Extension).
#define	SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
	SCB ICSR: STTNS Mask (Security Extension).
#define	SCB_ICSR_ISRPREEMPT_Pos   23U
	SCB ICSR: ISRPREEMPT Position.
#define	SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
	SCB ICSR: ISRPREEMPT Mask.
#define	SCB_ICSR_ISRPENDING_Pos   22U
	SCB ICSR: ISRPENDING Position.
#define	SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
	SCB ICSR: ISRPENDING Mask.
#define	SCB_ICSR_VECTPENDING_Pos   12U
	SCB ICSR: VECTPENDING Position.
#define	SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
	SCB ICSR: VECTPENDING Mask.
#define	SCB_ICSR_RETTOBASE_Pos   11U
	SCB ICSR: RETTOBASE Position.
#define	SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
	SCB ICSR: RETTOBASE Mask.
#define	SCB_ICSR_VECTACTIVE_Pos   0U
	SCB ICSR: VECTACTIVE Position.
#define	SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
	SCB ICSR: VECTACTIVE Mask.
#define	SCB_AIRCR_VECTKEY_Pos   16U
	SCB AIRCR: VECTKEY Position.
#define	SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
	SCB AIRCR: VECTKEY Mask.
#define	SCB_AIRCR_VECTKEYSTAT_Pos   16U
	SCB AIRCR: VECTKEYSTAT Position.
#define	SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
	SCB AIRCR: VECTKEYSTAT Mask.
#define	SCB_AIRCR_ENDIANESS_Pos   15U
	SCB AIRCR: ENDIANESS Position.
#define	SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
	SCB AIRCR: ENDIANESS Mask.
#define	SCB_AIRCR_PRIS_Pos   14U
	SCB AIRCR: PRIS Position.
#define	SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
	SCB AIRCR: PRIS Mask.
#define	SCB_AIRCR_BFHFNMINS_Pos   13U
	SCB AIRCR: BFHFNMINS Position.
#define	SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
	SCB AIRCR: BFHFNMINS Mask.
#define	SCB_AIRCR_SYSRESETREQS_Pos   3U
	SCB AIRCR: SYSRESETREQS Position.
#define	SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
	SCB AIRCR: SYSRESETREQS Mask.
#define	SCB_AIRCR_SYSRESETREQ_Pos   2U
	SCB AIRCR: SYSRESETREQ Position.
#define	SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
	SCB AIRCR: SYSRESETREQ Mask.
#define	SCB_AIRCR_VECTCLRACTIVE_Pos   1U
	SCB AIRCR: VECTCLRACTIVE Position.
#define	SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
	SCB AIRCR: VECTCLRACTIVE Mask.
#define	SCB_SCR_SEVONPEND_Pos   4U
	SCB SCR: SEVONPEND Position.
#define	SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
	SCB SCR: SEVONPEND Mask.
#define	SCB_SCR_SLEEPDEEPS_Pos   3U
	SCB SCR: SLEEPDEEPS Position.
#define	SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
	SCB SCR: SLEEPDEEPS Mask.
#define	SCB_SCR_SLEEPDEEP_Pos   2U
	SCB SCR: SLEEPDEEP Position.
#define	SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
	SCB SCR: SLEEPDEEP Mask.
#define	SCB_SCR_SLEEPONEXIT_Pos   1U
	SCB SCR: SLEEPONEXIT Position.
#define	SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
	SCB SCR: SLEEPONEXIT Mask.
#define	SCB_CCR_BP_Pos   18U
	SCB CCR: BP Position.
#define	SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
	SCB CCR: BP Mask.
#define	SCB_CCR_IC_Pos   17U
	SCB CCR: IC Position.
#define	SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
	SCB CCR: IC Mask.
#define	SCB_CCR_DC_Pos   16U
	SCB CCR: DC Position.
#define	SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
	SCB CCR: DC Mask.
#define	SCB_CCR_STKOFHFNMIGN_Pos   10U
	SCB CCR: STKOFHFNMIGN Position.
#define	SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
	SCB CCR: STKOFHFNMIGN Mask.
#define	SCB_CCR_BFHFNMIGN_Pos   8U
	SCB CCR: BFHFNMIGN Position.
#define	SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
	SCB CCR: BFHFNMIGN Mask.
#define	SCB_CCR_DIV_0_TRP_Pos   4U
	SCB CCR: DIV_0_TRP Position.
#define	SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
	SCB CCR: DIV_0_TRP Mask.
#define	SCB_CCR_UNALIGN_TRP_Pos   3U
	SCB CCR: UNALIGN_TRP Position.
#define	SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
	SCB CCR: UNALIGN_TRP Mask.
#define	SCB_CCR_USERSETMPEND_Pos   1U
	SCB CCR: USERSETMPEND Position.
#define	SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
	SCB CCR: USERSETMPEND Mask.
#define	SCB_SHCSR_HARDFAULTPENDED_Pos   21U
	SCB SHCSR: HARDFAULTPENDED Position.
#define	SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
	SCB SHCSR: HARDFAULTPENDED Mask.
#define	SCB_SHCSR_SVCALLPENDED_Pos   15U
	SCB SHCSR: SVCALLPENDED Position.
#define	SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
	SCB SHCSR: SVCALLPENDED Mask.
#define	SCB_SHCSR_SYSTICKACT_Pos   11U
	SCB SHCSR: SYSTICKACT Position.
#define	SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
	SCB SHCSR: SYSTICKACT Mask.
#define	SCB_SHCSR_PENDSVACT_Pos   10U
	SCB SHCSR: PENDSVACT Position.
#define	SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
	SCB SHCSR: PENDSVACT Mask.
#define	SCB_SHCSR_SVCALLACT_Pos   7U
	SCB SHCSR: SVCALLACT Position.
#define	SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
	SCB SHCSR: SVCALLACT Mask.
#define	SCB_SHCSR_NMIACT_Pos   5U
	SCB SHCSR: NMIACT Position.
#define	SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
	SCB SHCSR: NMIACT Mask.
#define	SCB_SHCSR_HARDFAULTACT_Pos   2U
	SCB SHCSR: HARDFAULTACT Position.
#define	SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
	SCB SHCSR: HARDFAULTACT Mask.
#define	SysTick_CTRL_COUNTFLAG_Pos   16U
	SysTick CTRL: COUNTFLAG Position.
#define	SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)
	SysTick CTRL: COUNTFLAG Mask.
#define	SysTick_CTRL_CLKSOURCE_Pos   2U
	SysTick CTRL: CLKSOURCE Position.
#define	SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)
	SysTick CTRL: CLKSOURCE Mask.
#define	SysTick_CTRL_TICKINT_Pos   1U
	SysTick CTRL: TICKINT Position.
#define	SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)
	SysTick CTRL: TICKINT Mask.
#define	SysTick_CTRL_ENABLE_Pos   0U
	SysTick CTRL: ENABLE Position.
#define	SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
	SysTick CTRL: ENABLE Mask.
#define	SysTick_LOAD_RELOAD_Pos   0U
	SysTick LOAD: RELOAD Position.
#define	SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
	SysTick LOAD: RELOAD Mask.
#define	SysTick_VAL_CURRENT_Pos   0U
	SysTick VAL: CURRENT Position.
#define	SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
	SysTick VAL: CURRENT Mask.
#define	SysTick_CALIB_NOREF_Pos   31U
	SysTick CALIB: NOREF Position.
#define	SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)
	SysTick CALIB: NOREF Mask.
#define	SysTick_CALIB_SKEW_Pos   30U
	SysTick CALIB: SKEW Position.
#define	SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)
	SysTick CALIB: SKEW Mask.
#define	SysTick_CALIB_TENMS_Pos   0U
	SysTick CALIB: TENMS Position.
#define	SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
	SysTick CALIB: TENMS Mask.
#define	DWT_CTRL_NUMCOMP_Pos   28U
	DWT CTRL: NUMCOMP Position.
#define	DWT_CTRL_NUMCOMP_Msk   (0xFUL << DWT_CTRL_NUMCOMP_Pos)
	DWT CTRL: NUMCOMP Mask.
#define	DWT_CTRL_NOTRCPKT_Pos   27U
	DWT CTRL: NOTRCPKT Position.
#define	DWT_CTRL_NOTRCPKT_Msk   (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
	DWT CTRL: NOTRCPKT Mask.
#define	DWT_CTRL_NOEXTTRIG_Pos   26U
	DWT CTRL: NOEXTTRIG Position.
#define	DWT_CTRL_NOEXTTRIG_Msk   (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
	DWT CTRL: NOEXTTRIG Mask.
#define	DWT_CTRL_NOCYCCNT_Pos   25U
	DWT CTRL: NOCYCCNT Position.
#define	DWT_CTRL_NOCYCCNT_Msk   (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
	DWT CTRL: NOCYCCNT Mask.
#define	DWT_CTRL_NOPRFCNT_Pos   24U
	DWT CTRL: NOPRFCNT Position.
#define	DWT_CTRL_NOPRFCNT_Msk   (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
	DWT CTRL: NOPRFCNT Mask.
#define	DWT_FUNCTION_ID_Pos   27U
	DWT FUNCTION: ID Position.
#define	DWT_FUNCTION_ID_Msk   (0x1FUL << DWT_FUNCTION_ID_Pos)
	DWT FUNCTION: ID Mask.
#define	DWT_FUNCTION_MATCHED_Pos   24U
	DWT FUNCTION: MATCHED Position.
#define	DWT_FUNCTION_MATCHED_Msk   (0x1UL << DWT_FUNCTION_MATCHED_Pos)
	DWT FUNCTION: MATCHED Mask.
#define	DWT_FUNCTION_DATAVSIZE_Pos   10U
	DWT FUNCTION: DATAVSIZE Position.
#define	DWT_FUNCTION_DATAVSIZE_Msk   (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
	DWT FUNCTION: DATAVSIZE Mask.
#define	DWT_FUNCTION_ACTION_Pos   4U
	DWT FUNCTION: ACTION Position.
#define	DWT_FUNCTION_ACTION_Msk   (0x3UL << DWT_FUNCTION_ACTION_Pos)
	DWT FUNCTION: ACTION Mask.
#define	DWT_FUNCTION_MATCH_Pos   0U
	DWT FUNCTION: MATCH Position.
#define	DWT_FUNCTION_MATCH_Msk   (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)
	DWT FUNCTION: MATCH Mask.
#define	TPI_SPPR_TXMODE_Pos   0U
	TPI SPPR: TXMODE Position.
#define	TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
	TPI SPPR: TXMODE Mask.
#define	TPI_FFSR_FtNonStop_Pos   3U
	TPI FFSR: FtNonStop Position.
#define	TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
	TPI FFSR: FtNonStop Mask.
#define	TPI_FFSR_TCPresent_Pos   2U
	TPI FFSR: TCPresent Position.
#define	TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
	TPI FFSR: TCPresent Mask.
#define	TPI_FFSR_FtStopped_Pos   1U
	TPI FFSR: FtStopped Position.
#define	TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
	TPI FFSR: FtStopped Mask.
#define	TPI_FFSR_FlInProg_Pos   0U
	TPI FFSR: FlInProg Position.
#define	TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
	TPI FFSR: FlInProg Mask.
#define	TPI_FFCR_TrigIn_Pos   8U
	TPI FFCR: TrigIn Position.
#define	TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
	TPI FFCR: TrigIn Mask.
#define	TPI_FFCR_FOnMan_Pos   6U
	TPI FFCR: FOnMan Position.
#define	TPI_FFCR_FOnMan_Msk   (0x1UL << TPI_FFCR_FOnMan_Pos)
	TPI FFCR: FOnMan Mask.
#define	TPI_FFCR_EnFCont_Pos   1U
	TPI FFCR: EnFCont Position.
#define	TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
	TPI FFCR: EnFCont Mask.
#define	TPI_DEVID_NRZVALID_Pos   11U
	TPI DEVID: NRZVALID Position.
#define	TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
	TPI DEVID: NRZVALID Mask.
#define	TPI_DEVID_MANCVALID_Pos   10U
	TPI DEVID: MANCVALID Position.
#define	TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
	TPI DEVID: MANCVALID Mask.
#define	TPI_DEVID_PTINVALID_Pos   9U
	TPI DEVID: PTINVALID Position.
#define	TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
	TPI DEVID: PTINVALID Mask.
#define	TPI_DEVID_FIFOSZ_Pos   6U
	TPI DEVID: FIFO depth Position.
#define	TPI_DEVID_FIFOSZ_Msk   (0x7UL << TPI_DEVID_FIFOSZ_Pos)
	TPI DEVID: FIFO depth Mask.
#define	TPI_DEVTYPE_SubType_Pos   4U
	TPI DEVTYPE: SubType Position.
#define	TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
	TPI DEVTYPE: SubType Mask.
#define	TPI_DEVTYPE_MajorType_Pos   0U
	TPI DEVTYPE: MajorType Position.
#define	TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
	TPI DEVTYPE: MajorType Mask.
#define	MPU_TYPE_RALIASES   1U
#define	MPU_TYPE_IREGION_Pos   16U
	MPU TYPE: IREGION Position.
#define	MPU_TYPE_IREGION_Msk   (0xFFUL << MPU_TYPE_IREGION_Pos)
	MPU TYPE: IREGION Mask.
#define	MPU_TYPE_DREGION_Pos   8U
	MPU TYPE: DREGION Position.
#define	MPU_TYPE_DREGION_Msk   (0xFFUL << MPU_TYPE_DREGION_Pos)
	MPU TYPE: DREGION Mask.
#define	MPU_TYPE_SEPARATE_Pos   0U
	MPU TYPE: SEPARATE Position.
#define	MPU_TYPE_SEPARATE_Msk   (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
	MPU TYPE: SEPARATE Mask.
#define	MPU_CTRL_PRIVDEFENA_Pos   2U
	MPU CTRL: PRIVDEFENA Position.
#define	MPU_CTRL_PRIVDEFENA_Msk   (1UL << MPU_CTRL_PRIVDEFENA_Pos)
	MPU CTRL: PRIVDEFENA Mask.
#define	MPU_CTRL_HFNMIENA_Pos   1U
	MPU CTRL: HFNMIENA Position.
#define	MPU_CTRL_HFNMIENA_Msk   (1UL << MPU_CTRL_HFNMIENA_Pos)
	MPU CTRL: HFNMIENA Mask.
#define	MPU_CTRL_ENABLE_Pos   0U
	MPU CTRL: ENABLE Position.
#define	MPU_CTRL_ENABLE_Msk   (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
	MPU CTRL: ENABLE Mask.
#define	MPU_RNR_REGION_Pos   0U
	MPU RNR: REGION Position.
#define	MPU_RNR_REGION_Msk   (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
	MPU RNR: REGION Mask.
#define	MPU_RBAR_BASE_Pos   5U
	MPU RBAR: BASE Position.
#define	MPU_RBAR_BASE_Msk   (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
	MPU RBAR: BASE Mask.
#define	MPU_RBAR_SH_Pos   3U
	MPU RBAR: SH Position.
#define	MPU_RBAR_SH_Msk   (0x3UL << MPU_RBAR_SH_Pos)
	MPU RBAR: SH Mask.
#define	MPU_RBAR_AP_Pos   1U
	MPU RBAR: AP Position.
#define	MPU_RBAR_AP_Msk   (0x3UL << MPU_RBAR_AP_Pos)
	MPU RBAR: AP Mask.
#define	MPU_RBAR_XN_Pos   0U
	MPU RBAR: XN Position.
#define	MPU_RBAR_XN_Msk   (01UL /*<< MPU_RBAR_XN_Pos*/)
	MPU RBAR: XN Mask.
#define	MPU_RLAR_LIMIT_Pos   5U
	MPU RLAR: LIMIT Position.
#define	MPU_RLAR_LIMIT_Msk   (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
	MPU RLAR: LIMIT Mask.
#define	MPU_RLAR_AttrIndx_Pos   1U
	MPU RLAR: AttrIndx Position.
#define	MPU_RLAR_AttrIndx_Msk   (0x7UL << MPU_RLAR_AttrIndx_Pos)
	MPU RLAR: AttrIndx Mask.
#define	MPU_RLAR_EN_Pos   0U
	MPU RLAR: EN Position.
#define	MPU_RLAR_EN_Msk   (1UL /*<< MPU_RLAR_EN_Pos*/)
	MPU RLAR: EN Mask.
#define	MPU_MAIR0_Attr3_Pos   24U
	MPU MAIR0: Attr3 Position.
#define	MPU_MAIR0_Attr3_Msk   (0xFFUL << MPU_MAIR0_Attr3_Pos)
	MPU MAIR0: Attr3 Mask.
#define	MPU_MAIR0_Attr2_Pos   16U
	MPU MAIR0: Attr2 Position.
#define	MPU_MAIR0_Attr2_Msk   (0xFFUL << MPU_MAIR0_Attr2_Pos)
	MPU MAIR0: Attr2 Mask.
#define	MPU_MAIR0_Attr1_Pos   8U
	MPU MAIR0: Attr1 Position.
#define	MPU_MAIR0_Attr1_Msk   (0xFFUL << MPU_MAIR0_Attr1_Pos)
	MPU MAIR0: Attr1 Mask.
#define	MPU_MAIR0_Attr0_Pos   0U
	MPU MAIR0: Attr0 Position.
#define	MPU_MAIR0_Attr0_Msk   (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)
	MPU MAIR0: Attr0 Mask.
#define	MPU_MAIR1_Attr7_Pos   24U
	MPU MAIR1: Attr7 Position.
#define	MPU_MAIR1_Attr7_Msk   (0xFFUL << MPU_MAIR1_Attr7_Pos)
	MPU MAIR1: Attr7 Mask.
#define	MPU_MAIR1_Attr6_Pos   16U
	MPU MAIR1: Attr6 Position.
#define	MPU_MAIR1_Attr6_Msk   (0xFFUL << MPU_MAIR1_Attr6_Pos)
	MPU MAIR1: Attr6 Mask.
#define	MPU_MAIR1_Attr5_Pos   8U
	MPU MAIR1: Attr5 Position.
#define	MPU_MAIR1_Attr5_Msk   (0xFFUL << MPU_MAIR1_Attr5_Pos)
	MPU MAIR1: Attr5 Mask.
#define	MPU_MAIR1_Attr4_Pos   0U
	MPU MAIR1: Attr4 Position.
#define	MPU_MAIR1_Attr4_Msk   (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)
	MPU MAIR1: Attr4 Mask.
#define	DCB_DHCSR_DBGKEY_Pos   16U
	DCB DHCSR: Debug key Position.
#define	DCB_DHCSR_DBGKEY_Msk   (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
	DCB DHCSR: Debug key Mask.
#define	DCB_DHCSR_S_RESTART_ST_Pos   26U
	DCB DHCSR: Restart sticky status Position.
#define	DCB_DHCSR_S_RESTART_ST_Msk   (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
	DCB DHCSR: Restart sticky status Mask.
#define	DCB_DHCSR_S_RESET_ST_Pos   25U
	DCB DHCSR: Reset sticky status Position.
#define	DCB_DHCSR_S_RESET_ST_Msk   (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
	DCB DHCSR: Reset sticky status Mask.
#define	DCB_DHCSR_S_RETIRE_ST_Pos   24U
	DCB DHCSR: Retire sticky status Position.
#define	DCB_DHCSR_S_RETIRE_ST_Msk   (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
	DCB DHCSR: Retire sticky status Mask.
#define	DCB_DHCSR_S_SDE_Pos   20U
	DCB DHCSR: Secure debug enabled Position.
#define	DCB_DHCSR_S_SDE_Msk   (0x1UL << DCB_DHCSR_S_SDE_Pos)
	DCB DHCSR: Secure debug enabled Mask.
#define	DCB_DHCSR_S_LOCKUP_Pos   19U
	DCB DHCSR: Lockup status Position.
#define	DCB_DHCSR_S_LOCKUP_Msk   (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
	DCB DHCSR: Lockup status Mask.
#define	DCB_DHCSR_S_SLEEP_Pos   18U
	DCB DHCSR: Sleeping status Position.
#define	DCB_DHCSR_S_SLEEP_Msk   (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
	DCB DHCSR: Sleeping status Mask.
#define	DCB_DHCSR_S_HALT_Pos   17U
	DCB DHCSR: Halted status Position.
#define	DCB_DHCSR_S_HALT_Msk   (0x1UL << DCB_DHCSR_S_HALT_Pos)
	DCB DHCSR: Halted status Mask.
#define	DCB_DHCSR_S_REGRDY_Pos   16U
	DCB DHCSR: Register ready status Position.
#define	DCB_DHCSR_S_REGRDY_Msk   (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
	DCB DHCSR: Register ready status Mask.
#define	DCB_DHCSR_C_MASKINTS_Pos   3U
	DCB DHCSR: Mask interrupts control Position.
#define	DCB_DHCSR_C_MASKINTS_Msk   (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
	DCB DHCSR: Mask interrupts control Mask.
#define	DCB_DHCSR_C_STEP_Pos   2U
	DCB DHCSR: Step control Position.
#define	DCB_DHCSR_C_STEP_Msk   (0x1UL << DCB_DHCSR_C_STEP_Pos)
	DCB DHCSR: Step control Mask.
#define	DCB_DHCSR_C_HALT_Pos   1U
	DCB DHCSR: Halt control Position.
#define	DCB_DHCSR_C_HALT_Msk   (0x1UL << DCB_DHCSR_C_HALT_Pos)
	DCB DHCSR: Halt control Mask.
#define	DCB_DHCSR_C_DEBUGEN_Pos   0U
	DCB DHCSR: Debug enable control Position.
#define	DCB_DHCSR_C_DEBUGEN_Msk   (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)
	DCB DHCSR: Debug enable control Mask.
#define	DCB_DCRSR_REGWnR_Pos   16U
	DCB DCRSR: Register write/not-read Position.
#define	DCB_DCRSR_REGWnR_Msk   (0x1UL << DCB_DCRSR_REGWnR_Pos)
	DCB DCRSR: Register write/not-read Mask.
#define	DCB_DCRSR_REGSEL_Pos   0U
	DCB DCRSR: Register selector Position.
#define	DCB_DCRSR_REGSEL_Msk   (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)
	DCB DCRSR: Register selector Mask.
#define	DCB_DCRDR_DBGTMP_Pos   0U
	DCB DCRDR: Data temporary buffer Position.
#define	DCB_DCRDR_DBGTMP_Msk   (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)
	DCB DCRDR: Data temporary buffer Mask.
#define	DCB_DEMCR_TRCENA_Pos   24U
	DCB DEMCR: Trace enable Position.
#define	DCB_DEMCR_TRCENA_Msk   (0x1UL << DCB_DEMCR_TRCENA_Pos)
	DCB DEMCR: Trace enable Mask.
#define	DCB_DEMCR_VC_HARDERR_Pos   10U
	DCB DEMCR: Vector Catch HardFault errors Position.
#define	DCB_DEMCR_VC_HARDERR_Msk   (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
	DCB DEMCR: Vector Catch HardFault errors Mask.
#define	DCB_DEMCR_VC_CORERESET_Pos   0U
	DCB DEMCR: Vector Catch Core reset Position.
#define	DCB_DEMCR_VC_CORERESET_Msk   (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)
	DCB DEMCR: Vector Catch Core reset Mask.
#define	DCB_DAUTHCTRL_INTSPNIDEN_Pos   3U
	DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position.
#define	DCB_DAUTHCTRL_INTSPNIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
	DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask.
#define	DCB_DAUTHCTRL_SPNIDENSEL_Pos   2U
	DCB DAUTHCTRL: Secure non-invasive debug enable select Position.
#define	DCB_DAUTHCTRL_SPNIDENSEL_Msk   (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
	DCB DAUTHCTRL: Secure non-invasive debug enable select Mask.
#define	DCB_DAUTHCTRL_INTSPIDEN_Pos   1U
	DCB DAUTHCTRL: Internal Secure invasive debug enable Position.
#define	DCB_DAUTHCTRL_INTSPIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
	DCB DAUTHCTRL: Internal Secure invasive debug enable Mask.
#define	DCB_DAUTHCTRL_SPIDENSEL_Pos   0U
	DCB DAUTHCTRL: Secure invasive debug enable select Position.
#define	DCB_DAUTHCTRL_SPIDENSEL_Msk   (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)
	DCB DAUTHCTRL: Secure invasive debug enable select Mask.
#define	DCB_DSCSR_CDSKEY_Pos   17U
	DCB DSCSR: CDS write-enable key Position.
#define	DCB_DSCSR_CDSKEY_Msk   (0x1UL << DCB_DSCSR_CDSKEY_Pos)
	DCB DSCSR: CDS write-enable key Mask.
#define	DCB_DSCSR_CDS_Pos   16U
	DCB DSCSR: Current domain Secure Position.
#define	DCB_DSCSR_CDS_Msk   (0x1UL << DCB_DSCSR_CDS_Pos)
	DCB DSCSR: Current domain Secure Mask.
#define	DCB_DSCSR_SBRSEL_Pos   1U
	DCB DSCSR: Secure banked register select Position.
#define	DCB_DSCSR_SBRSEL_Msk   (0x1UL << DCB_DSCSR_SBRSEL_Pos)
	DCB DSCSR: Secure banked register select Mask.
#define	DCB_DSCSR_SBRSELEN_Pos   0U
	DCB DSCSR: Secure banked register select enable Position.
#define	DCB_DSCSR_SBRSELEN_Msk   (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)
	DCB DSCSR: Secure banked register select enable Mask.
#define	DIB_DLAR_KEY_Pos   0U
	DIB DLAR: KEY Position.
#define	DIB_DLAR_KEY_Msk   (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */)
	DIB DLAR: KEY Mask.
#define	DIB_DLSR_nTT_Pos   2U
	DIB DLSR: Not thirty-two bit Position.
#define	DIB_DLSR_nTT_Msk   (0x1UL << DIB_DLSR_nTT_Pos )
	DIB DLSR: Not thirty-two bit Mask.
#define	DIB_DLSR_SLK_Pos   1U
	DIB DLSR: Software Lock status Position.
#define	DIB_DLSR_SLK_Msk   (0x1UL << DIB_DLSR_SLK_Pos )
	DIB DLSR: Software Lock status Mask.
#define	DIB_DLSR_SLI_Pos   0U
	DIB DLSR: Software Lock implemented Position.
#define	DIB_DLSR_SLI_Msk   (0x1UL /*<< DIB_DLSR_SLI_Pos*/)
	DIB DLSR: Software Lock implemented Mask.
#define	DIB_DAUTHSTATUS_SNID_Pos   6U
	DIB DAUTHSTATUS: Secure Non-invasive Debug Position.
#define	DIB_DAUTHSTATUS_SNID_Msk   (0x3UL << DIB_DAUTHSTATUS_SNID_Pos )
	DIB DAUTHSTATUS: Secure Non-invasive Debug Mask.
#define	DIB_DAUTHSTATUS_SID_Pos   4U
	DIB DAUTHSTATUS: Secure Invasive Debug Position.
#define	DIB_DAUTHSTATUS_SID_Msk   (0x3UL << DIB_DAUTHSTATUS_SID_Pos )
	DIB DAUTHSTATUS: Secure Invasive Debug Mask.
#define	DIB_DAUTHSTATUS_NSNID_Pos   2U
	DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position.
#define	DIB_DAUTHSTATUS_NSNID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos )
	DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask.
#define	DIB_DAUTHSTATUS_NSID_Pos   0U
	DIB DAUTHSTATUS: Non-secure Invasive Debug Position.
#define	DIB_DAUTHSTATUS_NSID_Msk   (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/)
	DIB DAUTHSTATUS: Non-secure Invasive Debug Mask.
#define	DIB_DDEVARCH_ARCHITECT_Pos   21U
	DIB DDEVARCH: Architect Position.
#define	DIB_DDEVARCH_ARCHITECT_Msk   (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos )
	DIB DDEVARCH: Architect Mask.
#define	DIB_DDEVARCH_PRESENT_Pos   20U
	DIB DDEVARCH: DEVARCH Present Position.
#define	DIB_DDEVARCH_PRESENT_Msk   (0x1FUL << DIB_DDEVARCH_PRESENT_Pos )
	DIB DDEVARCH: DEVARCH Present Mask.
#define	DIB_DDEVARCH_REVISION_Pos   16U
	DIB DDEVARCH: Revision Position.
#define	DIB_DDEVARCH_REVISION_Msk   (0xFUL << DIB_DDEVARCH_REVISION_Pos )
	DIB DDEVARCH: Revision Mask.
#define	DIB_DDEVARCH_ARCHVER_Pos   12U
	DIB DDEVARCH: Architecture Version Position.
#define	DIB_DDEVARCH_ARCHVER_Msk   (0xFUL << DIB_DDEVARCH_ARCHVER_Pos )
	DIB DDEVARCH: Architecture Version Mask.
#define	DIB_DDEVARCH_ARCHPART_Pos   0U
	DIB DDEVARCH: Architecture Part Position.
#define	DIB_DDEVARCH_ARCHPART_Msk   (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/)
	DIB DDEVARCH: Architecture Part Mask.
#define	DIB_DDEVTYPE_SUB_Pos   4U
	DIB DDEVTYPE: Sub-type Position.
#define	DIB_DDEVTYPE_SUB_Msk   (0xFUL << DIB_DDEVTYPE_SUB_Pos )
	DIB DDEVTYPE: Sub-type Mask.
#define	DIB_DDEVTYPE_MAJOR_Pos   0U
	DIB DDEVTYPE: Major type Position.
#define	DIB_DDEVTYPE_MAJOR_Msk   (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/)
	DIB DDEVTYPE: Major type Mask.
#define	_VAL2FLD(field, value)
	Mask and shift a bit field value for use in a register bit range.
#define	_FLD2VAL(field, value)
	Mask and shift a register value to extract a bit filed value.
#define	SCS_BASE   (0xE000E000UL)
	System Control Space Base Address.
#define	DWT_BASE   (0xE0001000UL)
	DWT Base Address.
#define	TPI_BASE   (0xE0040000UL)
	TPI Base Address.
#define	DCB_BASE   (0xE000EDF0UL)
	DCB Base Address.
#define	DIB_BASE   (0xE000EFB0UL)
	DIB Base Address.
#define	SysTick_BASE   (SCS_BASE + 0x0010UL)
	SysTick Base Address.
#define	NVIC_BASE   (SCS_BASE + 0x0100UL)
	NVIC Base Address.
#define	SCB_BASE   (SCS_BASE + 0x0D00UL)
	System Control Block Base Address.
#define	SCB   ((SCB_Type *) SCB_BASE )
	SCB configuration struct.
#define	SysTick   ((SysTick_Type *) SysTick_BASE )
	SysTick configuration struct.
#define	NVIC   ((NVIC_Type *) NVIC_BASE )
	NVIC configuration struct.
#define	DWT   ((DWT_Type *) DWT_BASE )
	DWT configuration struct.
#define	TPI   ((TPI_Type *) TPI_BASE )
	TPI configuration struct.
#define	DCB   ((DCB_Type *) DCB_BASE )
	DCB configuration struct.
#define	DIB   ((DIB_Type *) DIB_BASE )
	DIB configuration struct.
#define	MPU_BASE   (SCS_BASE + 0x0D90UL)
	Memory Protection Unit.
#define	MPU   ((MPU_Type *) MPU_BASE )
	Memory Protection Unit.
#define	NVIC_SetPriorityGrouping   __NVIC_SetPriorityGrouping
#define	NVIC_GetPriorityGrouping   __NVIC_GetPriorityGrouping
#define	NVIC_EnableIRQ   __NVIC_EnableIRQ
#define	NVIC_GetEnableIRQ   __NVIC_GetEnableIRQ
#define	NVIC_DisableIRQ   __NVIC_DisableIRQ
#define	NVIC_GetPendingIRQ   __NVIC_GetPendingIRQ
#define	NVIC_SetPendingIRQ   __NVIC_SetPendingIRQ
#define	NVIC_ClearPendingIRQ   __NVIC_ClearPendingIRQ
#define	NVIC_GetActive   __NVIC_GetActive
#define	NVIC_SetPriority   __NVIC_SetPriority
#define	NVIC_GetPriority   __NVIC_GetPriority
#define	NVIC_SystemReset   __NVIC_SystemReset
#define	NVIC_SetVector   __NVIC_SetVector
#define	NVIC_GetVector   __NVIC_GetVector
#define	NVIC_USER_IRQ_OFFSET   16
#define	FNC_RETURN   (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
#define	EXC_RETURN_PREFIX   (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
#define	EXC_RETURN_S   (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
#define	EXC_RETURN_DCRS   (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
#define	EXC_RETURN_FTYPE   (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
#define	EXC_RETURN_MODE   (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
#define	EXC_RETURN_SPSEL   (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
#define	EXC_RETURN_ES   (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
#define	EXC_INTEGRITY_SIGNATURE   (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
#define	TPI_ACPR_SWOSCALER_Pos   0U
	TPI ACPR: SWOSCALER Position.
#define	TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
	TPI ACPR: SWOSCALER Mask.
#define	TPI_PSCR_PSCount_Pos   0U
	TPI PSCR: PSCount Position.
#define	TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
	TPI PSCR: TPSCount Mask.
#define	TPI_LSR_nTT_Pos   1U
	TPI LSR: Not thirty-two bit.
#define	TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)
	TPI LSR: Not thirty-two bit.
#define	TPI_LSR_SLK_Pos   1U
	TPI LSR: Software Lock status Position.
#define	TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)
	TPI LSR: Software Lock status Mask.
#define	TPI_LSR_SLI_Pos   0U
	TPI LSR: Software Lock implemented Position.
#define	TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)
	TPI LSR: Software Lock implemented Mask.
#define	CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
#define	CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
#define	CoreDebug_DSCSR_CDS_Pos   16U
#define	CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
#define	CoreDebug_DSCSR_SBRSEL_Pos   1U
#define	CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
#define	CoreDebug_DSCSR_SBRSELEN_Pos   0U
#define	CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
#define	CoreDebug_DHCSR_DBGKEY_Pos   16U
	CoreDebug DHCSR: DBGKEY Position.
#define	CoreDebug_DHCSR_DBGKEY_Msk   (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
	CoreDebug DHCSR: DBGKEY Mask.
#define	CoreDebug_DHCSR_S_RESET_ST_Pos   25U
	CoreDebug DHCSR: S_RESET_ST Position.
#define	CoreDebug_DHCSR_S_RESET_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
	CoreDebug DHCSR: S_RESET_ST Mask.
#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos   24U
	CoreDebug DHCSR: S_RETIRE_ST Position.
#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk   (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
	CoreDebug DHCSR: S_RETIRE_ST Mask.
#define	CoreDebug_DHCSR_S_LOCKUP_Pos   19U
	CoreDebug DHCSR: S_LOCKUP Position.
#define	CoreDebug_DHCSR_S_LOCKUP_Msk   (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
	CoreDebug DHCSR: S_LOCKUP Mask.
#define	CoreDebug_DHCSR_S_SLEEP_Pos   18U
	CoreDebug DHCSR: S_SLEEP Position.
#define	CoreDebug_DHCSR_S_SLEEP_Msk   (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
	CoreDebug DHCSR: S_SLEEP Mask.
#define	CoreDebug_DHCSR_S_HALT_Pos   17U
	CoreDebug DHCSR: S_HALT Position.
#define	CoreDebug_DHCSR_S_HALT_Msk   (1UL << CoreDebug_DHCSR_S_HALT_Pos)
	CoreDebug DHCSR: S_HALT Mask.
#define	CoreDebug_DHCSR_S_REGRDY_Pos   16U
	CoreDebug DHCSR: S_REGRDY Position.
#define	CoreDebug_DHCSR_S_REGRDY_Msk   (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
	CoreDebug DHCSR: S_REGRDY Mask.
#define	CoreDebug_DHCSR_C_MASKINTS_Pos   3U
	CoreDebug DHCSR: C_MASKINTS Position.
#define	CoreDebug_DHCSR_C_MASKINTS_Msk   (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
	CoreDebug DHCSR: C_MASKINTS Mask.
#define	CoreDebug_DHCSR_C_STEP_Pos   2U
	CoreDebug DHCSR: C_STEP Position.
#define	CoreDebug_DHCSR_C_STEP_Msk   (1UL << CoreDebug_DHCSR_C_STEP_Pos)
	CoreDebug DHCSR: C_STEP Mask.
#define	CoreDebug_DHCSR_C_HALT_Pos   1U
	CoreDebug DHCSR: C_HALT Position.
#define	CoreDebug_DHCSR_C_HALT_Msk   (1UL << CoreDebug_DHCSR_C_HALT_Pos)
	CoreDebug DHCSR: C_HALT Mask.
#define	CoreDebug_DHCSR_C_DEBUGEN_Pos   0U
	CoreDebug DHCSR: C_DEBUGEN Position.
#define	CoreDebug_DHCSR_C_DEBUGEN_Msk   (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
	CoreDebug DHCSR: C_DEBUGEN Mask.
#define	CoreDebug_DCRSR_REGWnR_Pos   16U
	CoreDebug DCRSR: REGWnR Position.
#define	CoreDebug_DCRSR_REGWnR_Msk   (1UL << CoreDebug_DCRSR_REGWnR_Pos)
	CoreDebug DCRSR: REGWnR Mask.
#define	CoreDebug_DCRSR_REGSEL_Pos   0U
	CoreDebug DCRSR: REGSEL Position.
#define	CoreDebug_DCRSR_REGSEL_Msk   (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
	CoreDebug DCRSR: REGSEL Mask.
#define	CoreDebug_DEMCR_VC_HARDERR_Pos   10U
	CoreDebug DEMCR: VC_HARDERR Position.
#define	CoreDebug_DEMCR_VC_HARDERR_Msk   (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
	CoreDebug DEMCR: VC_HARDERR Mask.
#define	CoreDebug_DEMCR_VC_CORERESET_Pos   0U
	CoreDebug DEMCR: VC_CORERESET Position.
#define	CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
	CoreDebug DEMCR: VC_CORERESET Mask.
#define	CoreDebug_BASE   (0xE000EDF0UL)
	Core Debug Base Address.
#define	CoreDebug   ((CoreDebug_Type *) CoreDebug_BASE )
	Core Debug configuration struct.
#define	CoreDebug_DEMCR_DWTENA_Pos   24U
#define	CoreDebug_DEMCR_DWTENA_Msk   (1UL << CoreDebug_DEMCR_DWTENA_Pos)
#define	__NVIC_SetPriorityGrouping(X)
#define	__NVIC_GetPriorityGrouping()
	Get Priority Grouping.
#define	_BIT_SHIFT(IRQn)
#define	_SHP_IDX(IRQn)
#define	_IP_IDX(IRQn)

Functions
__STATIC_INLINE void	__NVIC_EnableIRQ (IRQn_Type IRQn)
	Enable Interrupt.
__STATIC_INLINE uint32_t	__NVIC_GetEnableIRQ (IRQn_Type IRQn)
	Get Interrupt Enable status.
__STATIC_INLINE void	__NVIC_DisableIRQ (IRQn_Type IRQn)
	Disable Interrupt.
__STATIC_INLINE uint32_t	__NVIC_GetPendingIRQ (IRQn_Type IRQn)
	Get Pending Interrupt.
__STATIC_INLINE void	__NVIC_SetPendingIRQ (IRQn_Type IRQn)
	Set Pending Interrupt.
__STATIC_INLINE void	__NVIC_ClearPendingIRQ (IRQn_Type IRQn)
	Clear Pending Interrupt.
__STATIC_INLINE uint32_t	__NVIC_GetActive (IRQn_Type IRQn)
	Get Active Interrupt.
__STATIC_INLINE void	__NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)
	Set Interrupt Priority.
__STATIC_INLINE uint32_t	__NVIC_GetPriority (IRQn_Type IRQn)
	Get Interrupt Priority.
__STATIC_INLINE uint32_t	NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
	Encode Priority.
__STATIC_INLINE void	NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
	Decode Priority.
__STATIC_INLINE void	__NVIC_SetVector (IRQn_Type IRQn, uint32_t vector)
	Set Interrupt Vector.
__STATIC_INLINE uint32_t	__NVIC_GetVector (IRQn_Type IRQn)
	Get Interrupt Vector.
__NO_RETURN __STATIC_INLINE void	__NVIC_SystemReset (void)
	System Reset.
__STATIC_INLINE uint32_t	SCB_GetFPUType (void)
	get FPU type
__STATIC_INLINE void	DCB_SetAuthCtrl (uint32_t value)
	Set Debug Authentication Control Register.
__STATIC_INLINE uint32_t	DCB_GetAuthCtrl (void)
	Get Debug Authentication Control Register.
__STATIC_INLINE uint32_t	DIB_GetAuthStatus (void)
	Get Debug Authentication Status Register.
__STATIC_INLINE uint32_t	SysTick_Config (uint32_t ticks)
	System Tick Configuration.

Detailed Description

CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File.

Version

V5.1.0

Date

27. March 2020

Definition in file core_armv8mbl.h.

Macro Definition Documentation

__ARMv8MBL_CMSIS_VERSION

#define __ARMv8MBL_CMSIS_VERSION

Value:

                                         ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
                                         __ARMv8MBL_CMSIS_VERSION_SUB           )

Deprecated

CMSIS HAL version number

Definition at line 70 of file core_armv8mbl.h.

__ARMv8MBL_CMSIS_VERSION_MAIN

#define __ARMv8MBL_CMSIS_VERSION_MAIN   (__CM_CMSIS_VERSION_MAIN)

Deprecated

[31:16] CMSIS HAL main version

Definition at line 68 of file core_armv8mbl.h.

__ARMv8MBL_CMSIS_VERSION_SUB

#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)

Deprecated

[15:0] CMSIS HAL sub version

Definition at line 69 of file core_armv8mbl.h.

__CORE_ARMV8MBL_H_DEPENDANT

#define __CORE_ARMV8MBL_H_DEPENDANT

Definition at line 129 of file core_armv8mbl.h.

__CORE_ARMV8MBL_H_GENERIC

#define __CORE_ARMV8MBL_H_GENERIC

Definition at line 34 of file core_armv8mbl.h.

__CORTEX_M

#define __CORTEX_M   (2U)

Cortex-M Core.

Definition at line 73 of file core_armv8mbl.h.

__FPU_USED

#define __FPU_USED   0U

__FPU_USED indicates whether an FPU is used or not.

This core does not support an FPU at all

Definition at line 78 of file core_armv8mbl.h.

__I

#define __I   volatile const

Defines 'read only' permissions.

Definition at line 195 of file core_armv8mbl.h.

__IM

#define __IM   volatile const /*! Defines 'read only' structure member permissions */

Definition at line 201 of file core_armv8mbl.h.

__IO

#define __IO   volatile

Defines 'read / write' permissions.

Definition at line 198 of file core_armv8mbl.h.

__IOM

#define __IOM   volatile /*! Defines 'read / write' structure member permissions */

Definition at line 203 of file core_armv8mbl.h.

__O

#define __O   volatile

Defines 'write only' permissions.

Definition at line 197 of file core_armv8mbl.h.

__OM

#define __OM   volatile /*! Defines 'write only' structure member permissions */

Definition at line 202 of file core_armv8mbl.h.