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DWT_Type Struct Reference
Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » Implementation Control Block register (ICB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT)

Structure type to access the Data Watchpoint and Trace Register (DWT). More...

#include <core_armv81mml.h>

Public Attributes

__IOM uint32_t CTRL
 Offset: 0x000 (R/W) Control Register.
__IOM uint32_t CYCCNT
 Offset: 0x004 (R/W) Cycle Count Register.
__IOM uint32_t CPICNT
 Offset: 0x008 (R/W) CPI Count Register.
__IOM uint32_t EXCCNT
 Offset: 0x00C (R/W) Exception Overhead Count Register.
__IOM uint32_t SLEEPCNT
 Offset: 0x010 (R/W) Sleep Count Register.
__IOM uint32_t LSUCNT
 Offset: 0x014 (R/W) LSU Count Register.
__IOM uint32_t FOLDCNT
 Offset: 0x018 (R/W) Folded-instruction Count Register.
__IM uint32_t PCSR
 Offset: 0x01C (R/ ) Program Counter Sample Register.
__IOM uint32_t COMP0
 Offset: 0x020 (R/W) Comparator Register 0.
uint32_t RESERVED1 [1U]
__IOM uint32_t FUNCTION0
 Offset: 0x028 (R/W) Function Register 0.
uint32_t RESERVED2 [1U]
__IOM uint32_t COMP1
 Offset: 0x030 (R/W) Comparator Register 1.
uint32_t RESERVED3 [1U]
__IOM uint32_t FUNCTION1
 Offset: 0x038 (R/W) Function Register 1.
uint32_t RESERVED4 [1U]
__IOM uint32_t COMP2
 Offset: 0x040 (R/W) Comparator Register 2.
uint32_t RESERVED5 [1U]
__IOM uint32_t FUNCTION2
 Offset: 0x048 (R/W) Function Register 2.
uint32_t RESERVED6 [1U]
__IOM uint32_t COMP3
 Offset: 0x050 (R/W) Comparator Register 3.
uint32_t RESERVED7 [1U]
__IOM uint32_t FUNCTION3
 Offset: 0x058 (R/W) Function Register 3.
uint32_t RESERVED8 [1U]
__IOM uint32_t COMP4
 Offset: 0x060 (R/W) Comparator Register 4.
uint32_t RESERVED9 [1U]
__IOM uint32_t FUNCTION4
 Offset: 0x068 (R/W) Function Register 4.
uint32_t RESERVED10 [1U]
__IOM uint32_t COMP5
 Offset: 0x070 (R/W) Comparator Register 5.
uint32_t RESERVED11 [1U]
__IOM uint32_t FUNCTION5
 Offset: 0x078 (R/W) Function Register 5.
uint32_t RESERVED12 [1U]
__IOM uint32_t COMP6
 Offset: 0x080 (R/W) Comparator Register 6.
uint32_t RESERVED13 [1U]
__IOM uint32_t FUNCTION6
 Offset: 0x088 (R/W) Function Register 6.
uint32_t RESERVED14 [1U]
__IOM uint32_t COMP7
 Offset: 0x090 (R/W) Comparator Register 7.
uint32_t RESERVED15 [1U]
__IOM uint32_t FUNCTION7
 Offset: 0x098 (R/W) Function Register 7.
uint32_t RESERVED16 [1U]
__IOM uint32_t COMP8
 Offset: 0x0A0 (R/W) Comparator Register 8.
uint32_t RESERVED17 [1U]
__IOM uint32_t FUNCTION8
 Offset: 0x0A8 (R/W) Function Register 8.
uint32_t RESERVED18 [1U]
__IOM uint32_t COMP9
 Offset: 0x0B0 (R/W) Comparator Register 9.
uint32_t RESERVED19 [1U]
__IOM uint32_t FUNCTION9
 Offset: 0x0B8 (R/W) Function Register 9.
uint32_t RESERVED20 [1U]
__IOM uint32_t COMP10
 Offset: 0x0C0 (R/W) Comparator Register 10.
uint32_t RESERVED21 [1U]
__IOM uint32_t FUNCTION10
 Offset: 0x0C8 (R/W) Function Register 10.
uint32_t RESERVED22 [1U]
__IOM uint32_t COMP11
 Offset: 0x0D0 (R/W) Comparator Register 11.
uint32_t RESERVED23 [1U]
__IOM uint32_t FUNCTION11
 Offset: 0x0D8 (R/W) Function Register 11.
uint32_t RESERVED24 [1U]
__IOM uint32_t COMP12
 Offset: 0x0E0 (R/W) Comparator Register 12.
uint32_t RESERVED25 [1U]
__IOM uint32_t FUNCTION12
 Offset: 0x0E8 (R/W) Function Register 12.
uint32_t RESERVED26 [1U]
__IOM uint32_t COMP13
 Offset: 0x0F0 (R/W) Comparator Register 13.
uint32_t RESERVED27 [1U]
__IOM uint32_t FUNCTION13
 Offset: 0x0F8 (R/W) Function Register 13.
uint32_t RESERVED28 [1U]
__IOM uint32_t COMP14
 Offset: 0x100 (R/W) Comparator Register 14.
uint32_t RESERVED29 [1U]
__IOM uint32_t FUNCTION14
 Offset: 0x108 (R/W) Function Register 14.
uint32_t RESERVED30 [1U]
__IOM uint32_t COMP15
 Offset: 0x110 (R/W) Comparator Register 15.
uint32_t RESERVED31 [1U]
__IOM uint32_t FUNCTION15
 Offset: 0x118 (R/W) Function Register 15.
uint32_t RESERVED32 [934U]
__IM uint32_t LSR
 Offset: 0xFB4 (R ) Lock Status Register.
uint32_t RESERVED33 [1U]
__IM uint32_t DEVARCH
 Offset: 0xFBC (R/ ) Device Architecture Register.
uint32_t RESERVED0 [6U]
__IOM uint32_t MASK0
 Offset: 0x024 (R/W) Mask Register 0.
__IOM uint32_t MASK1
 Offset: 0x034 (R/W) Mask Register 1.
__IOM uint32_t MASK2
 Offset: 0x044 (R/W) Mask Register 2.
__IOM uint32_t MASK3
 Offset: 0x054 (R/W) Mask Register 3.
__OM uint32_t LAR
 Offset: 0xFB0 ( W) Lock Access Register.

Detailed Description

Structure type to access the Data Watchpoint and Trace Register (DWT).

Definition at line 1179 of file core_armv81mml.h.

The documentation for this struct was generated from the following files: