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TPI_Type Struct Reference
Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » Implementation Control Block register (ICB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » Implementation Control Block register (ICB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Memory System Control Registers (IMPLEMENTATION DEFINED) » Power Mode Control Registers » External Wakeup Interrupt Controller Registers » Error Banking Registers (IMPLEMENTATION DEFINED) » Processor Configuration Information Registers (IMPLEMENTATION DEFINED) » Software Test Library Observation Registers » Trace Port Interface (TPI)

Structure type to access the Trace Port Interface Register (TPI). More...

#include <core_armv81mml.h>

Public Attributes

__IM uint32_t SSPSR
 Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register.
__IOM uint32_t CSPSR
 Offset: 0x004 (R/W) Current Parallel Port Sizes Register.
uint32_t RESERVED0 [2U]
__IOM uint32_t ACPR
 Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register.
uint32_t RESERVED1 [55U]
__IOM uint32_t SPPR
 Offset: 0x0F0 (R/W) Selected Pin Protocol Register.
uint32_t RESERVED2 [131U]
__IM uint32_t FFSR
 Offset: 0x300 (R/ ) Formatter and Flush Status Register.
__IOM uint32_t FFCR
 Offset: 0x304 (R/W) Formatter and Flush Control Register.
__IOM uint32_t PSCR
 Offset: 0x308 (R/W) Periodic Synchronization Control Register.
uint32_t RESERVED3 [809U]
__OM uint32_t LAR
 Offset: 0xFB0 ( /W) Software Lock Access Register.
__IM uint32_t LSR
 Offset: 0xFB4 (R/ ) Software Lock Status Register.
uint32_t RESERVED4 [4U]
__IM uint32_t TYPE
 Offset: 0xFC8 (R/ ) Device Identifier Register.
__IM uint32_t DEVTYPE
 Offset: 0xFCC (R/ ) Device Type Register.
__IM uint32_t TRIGGER
 Offset: 0xEE8 (R/ ) TRIGGER Register.
__IM uint32_t ITFTTD0
 Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register.
__IOM uint32_t ITATBCTR2
 Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2.
__IM uint32_t ITATBCTR0
 Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0.
__IM uint32_t ITFTTD1
 Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register.
__IOM uint32_t ITCTRL
 Offset: 0xF00 (R/W) Integration Mode Control.
uint32_t RESERVED5 [39U]
__IOM uint32_t CLAIMSET
 Offset: 0xFA0 (R/W) Claim tag set.
__IOM uint32_t CLAIMCLR
 Offset: 0xFA4 (R/W) Claim tag clear.
uint32_t RESERVED7 [8U]
__IM uint32_t DEVID
 Offset: 0xFC8 (R/ ) Device Configuration Register.
__IM uint32_t FSCR
 Offset: 0x308 (R/ ) Formatter Synchronization Counter Register.
__IM uint32_t FIFO0
 Offset: 0xEEC (R/ ) Integration ETM Data.
__IM uint32_t ITATBCTR2
 Offset: 0xEF0 (R/ ) ITATBCTR2.
__IM uint32_t FIFO1
 Offset: 0xEFC (R/ ) Integration ITM Data.

Detailed Description

Structure type to access the Trace Port Interface Register (TPI).

Definition at line 1365 of file core_armv81mml.h.

The documentation for this struct was generated from the following files: