STAR
Cal STAR — firmware, DAQ server, and engine design
Loading...
Searching...
No Matches
DCB_Type Struct Reference
Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » Implementation Control Block register (ICB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » Implementation Control Block register (ICB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Memory System Control Registers (IMPLEMENTATION DEFINED) » Power Mode Control Registers » External Wakeup Interrupt Controller Registers » Error Banking Registers (IMPLEMENTATION DEFINED) » Processor Configuration Information Registers (IMPLEMENTATION DEFINED) » Software Test Library Observation Registers » Trace Port Interface (TPI) » Memory Protection Unit (MPU) » Floating Point Unit (FPU) » Core Debug Registers (CoreDebug) » Debug Control Block

Structure type to access the Debug Control Block Registers (DCB). More...

#include <core_armv81mml.h>

Public Attributes

__IOM uint32_t DHCSR
 Offset: 0x000 (R/W) Debug Halting Control and Status Register.
__OM uint32_t DCRSR
 Offset: 0x004 ( /W) Debug Core Register Selector Register.
__IOM uint32_t DCRDR
 Offset: 0x008 (R/W) Debug Core Register Data Register.
__IOM uint32_t DEMCR
 Offset: 0x00C (R/W) Debug Exception and Monitor Control Register.
__OM uint32_t DSCEMCR
 Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register.
__IOM uint32_t DAUTHCTRL
 Offset: 0x014 (R/W) Debug Authentication Control Register.
__IOM uint32_t DSCSR
 Offset: 0x018 (R/W) Debug Security Control and Status Register.
uint32_t RESERVED0 [1U]

Detailed Description

Structure type to access the Debug Control Block Registers (DCB).

Definition at line 2794 of file core_armv81mml.h.

The documentation for this struct was generated from the following files: