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STL_Type Struct Reference
Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » Implementation Control Block register (ICB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Memory System Control Registers (IMPLEMENTATION DEFINED) » Power Mode Control Registers » External Wakeup Interrupt Controller Registers » Error Banking Registers (IMPLEMENTATION DEFINED) » Processor Configuration Information Registers (IMPLEMENTATION DEFINED) » Software Test Library Observation Registers

Structure type to access the Software Test Library Observation Registerss (STL). More...

#include <core_cm55.h>

Public Attributes

__IM uint32_t STLNVICPENDOR
 Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register.
__IM uint32_t STLNVICACTVOR
 Offset: 0x004 (R/ ) NVIC Active Priority Tree Register.
uint32_t RESERVED0 [2U]
__OM uint32_t STLIDMPUSR
 Offset: 0x010 ( /W) MPU Sanple Register.
__IM uint32_t STLIMPUOR
 Offset: 0x014 (R/ ) MPU Region Hit Register.
__IM uint32_t STLD0MPUOR
 Offset: 0x018 (R/ ) MPU Memory Attributes Register 0.
__IM uint32_t STLD1MPUOR
 Offset: 0x01C (R/ ) MPU Memory Attributes Register 1.

Detailed Description

Structure type to access the Software Test Library Observation Registerss (STL).

Definition at line 1778 of file core_cm55.h.

The documentation for this struct was generated from the following file:
  • firmware/Flight_Computer/Drivers/CMSIS/Include/core_cm55.h