Type definitions for the Debug Control Block Registers. More...

Collaboration diagram for Debug Control Block:

Topics
	Debug Identification Block
	Type definitions for the Debug Identification Block Registers.

Classes
struct	DCB_Type
	Structure type to access the Debug Control Block Registers (DCB). More...
#define	DCB_DHCSR_DBGKEY_Pos 16U
	DCB DHCSR: Debug key Position.
#define	DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
	DCB DHCSR: Debug key Mask.
#define	DCB_DHCSR_S_RESTART_ST_Pos 26U
	DCB DHCSR: Restart sticky status Position.
#define	DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
	DCB DHCSR: Restart sticky status Mask.
#define	DCB_DHCSR_S_RESET_ST_Pos 25U
	DCB DHCSR: Reset sticky status Position.
#define	DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
	DCB DHCSR: Reset sticky status Mask.
#define	DCB_DHCSR_S_RETIRE_ST_Pos 24U
	DCB DHCSR: Retire sticky status Position.
#define	DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
	DCB DHCSR: Retire sticky status Mask.
#define	DCB_DHCSR_S_SDE_Pos 20U
	DCB DHCSR: Secure debug enabled Position.
#define	DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)
	DCB DHCSR: Secure debug enabled Mask.
#define	DCB_DHCSR_S_LOCKUP_Pos 19U
	DCB DHCSR: Lockup status Position.
#define	DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
	DCB DHCSR: Lockup status Mask.
#define	DCB_DHCSR_S_SLEEP_Pos 18U
	DCB DHCSR: Sleeping status Position.
#define	DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
	DCB DHCSR: Sleeping status Mask.
#define	DCB_DHCSR_S_HALT_Pos 17U
	DCB DHCSR: Halted status Position.
#define	DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)
	DCB DHCSR: Halted status Mask.
#define	DCB_DHCSR_S_REGRDY_Pos 16U
	DCB DHCSR: Register ready status Position.
#define	DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
	DCB DHCSR: Register ready status Mask.
#define	DCB_DHCSR_C_SNAPSTALL_Pos 5U
	DCB DHCSR: Snap stall control Position.
#define	DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
	DCB DHCSR: Snap stall control Mask.
#define	DCB_DHCSR_C_MASKINTS_Pos 3U
	DCB DHCSR: Mask interrupts control Position.
#define	DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
	DCB DHCSR: Mask interrupts control Mask.
#define	DCB_DHCSR_C_STEP_Pos 2U
	DCB DHCSR: Step control Position.
#define	DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)
	DCB DHCSR: Step control Mask.
#define	DCB_DHCSR_C_HALT_Pos 1U
	DCB DHCSR: Halt control Position.
#define	DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)
	DCB DHCSR: Halt control Mask.
#define	DCB_DHCSR_C_DEBUGEN_Pos 0U
	DCB DHCSR: Debug enable control Position.
#define	DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /<< DCB_DHCSR_C_DEBUGEN_Pos/)
	DCB DHCSR: Debug enable control Mask.
#define	DCB_DCRSR_REGWnR_Pos 16U
	DCB DCRSR: Register write/not-read Position.
#define	DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)
	DCB DCRSR: Register write/not-read Mask.
#define	DCB_DCRSR_REGSEL_Pos 0U
	DCB DCRSR: Register selector Position.
#define	DCB_DCRSR_REGSEL_Msk (0x7FUL /<< DCB_DCRSR_REGSEL_Pos/)
	DCB DCRSR: Register selector Mask.
#define	DCB_DCRDR_DBGTMP_Pos 0U
	DCB DCRDR: Data temporary buffer Position.
#define	DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /<< DCB_DCRDR_DBGTMP_Pos/)
	DCB DCRDR: Data temporary buffer Mask.
#define	DCB_DEMCR_TRCENA_Pos 24U
	DCB DEMCR: Trace enable Position.
#define	DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)
	DCB DEMCR: Trace enable Mask.
#define	DCB_DEMCR_MONPRKEY_Pos 23U
	DCB DEMCR: Monitor pend req key Position.
#define	DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
	DCB DEMCR: Monitor pend req key Mask.
#define	DCB_DEMCR_UMON_EN_Pos 21U
	DCB DEMCR: Unprivileged monitor enable Position.
#define	DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos)
	DCB DEMCR: Unprivileged monitor enable Mask.
#define	DCB_DEMCR_SDME_Pos 20U
	DCB DEMCR: Secure DebugMonitor enable Position.
#define	DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos)
	DCB DEMCR: Secure DebugMonitor enable Mask.
#define	DCB_DEMCR_MON_REQ_Pos 19U
	DCB DEMCR: Monitor request Position.
#define	DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos)
	DCB DEMCR: Monitor request Mask.
#define	DCB_DEMCR_MON_STEP_Pos 18U
	DCB DEMCR: Monitor step Position.
#define	DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos)
	DCB DEMCR: Monitor step Mask.
#define	DCB_DEMCR_MON_PEND_Pos 17U
	DCB DEMCR: Monitor pend Position.
#define	DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos)
	DCB DEMCR: Monitor pend Mask.
#define	DCB_DEMCR_MON_EN_Pos 16U
	DCB DEMCR: Monitor enable Position.
#define	DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos)
	DCB DEMCR: Monitor enable Mask.
#define	DCB_DEMCR_VC_SFERR_Pos 11U
	DCB DEMCR: Vector Catch SecureFault Position.
#define	DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
	DCB DEMCR: Vector Catch SecureFault Mask.
#define	DCB_DEMCR_VC_HARDERR_Pos 10U
	DCB DEMCR: Vector Catch HardFault errors Position.
#define	DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
	DCB DEMCR: Vector Catch HardFault errors Mask.
#define	DCB_DEMCR_VC_INTERR_Pos 9U
	DCB DEMCR: Vector Catch interrupt errors Position.
#define	DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
	DCB DEMCR: Vector Catch interrupt errors Mask.
#define	DCB_DEMCR_VC_BUSERR_Pos 8U
	DCB DEMCR: Vector Catch BusFault errors Position.
#define	DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
	DCB DEMCR: Vector Catch BusFault errors Mask.
#define	DCB_DEMCR_VC_STATERR_Pos 7U
	DCB DEMCR: Vector Catch state errors Position.
#define	DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
	DCB DEMCR: Vector Catch state errors Mask.
#define	DCB_DEMCR_VC_CHKERR_Pos 6U
	DCB DEMCR: Vector Catch check errors Position.
#define	DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
	DCB DEMCR: Vector Catch check errors Mask.
#define	DCB_DEMCR_VC_NOCPERR_Pos 5U
	DCB DEMCR: Vector Catch NOCP errors Position.
#define	DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
	DCB DEMCR: Vector Catch NOCP errors Mask.
#define	DCB_DEMCR_VC_MMERR_Pos 4U
	DCB DEMCR: Vector Catch MemManage errors Position.
#define	DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
	DCB DEMCR: Vector Catch MemManage errors Mask.
#define	DCB_DEMCR_VC_CORERESET_Pos 0U
	DCB DEMCR: Vector Catch Core reset Position.
#define	DCB_DEMCR_VC_CORERESET_Msk (0x1UL /<< DCB_DEMCR_VC_CORERESET_Pos/)
	DCB DEMCR: Vector Catch Core reset Mask.
#define	DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U
	DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position.
#define	DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
	DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask.
#define	DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U
	DCB DAUTHCTRL: Secure non-invasive debug enable select Position.
#define	DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
	DCB DAUTHCTRL: Secure non-invasive debug enable select Mask.
#define	DCB_DAUTHCTRL_INTSPIDEN_Pos 1U
	DCB DAUTHCTRL: Internal Secure invasive debug enable Position.
#define	DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
	DCB DAUTHCTRL: Internal Secure invasive debug enable Mask.
#define	DCB_DAUTHCTRL_SPIDENSEL_Pos 0U
	DCB DAUTHCTRL: Secure invasive debug enable select Position.
#define	DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /<< DCB_DAUTHCTRL_SPIDENSEL_Pos/)
	DCB DAUTHCTRL: Secure invasive debug enable select Mask.
#define	DCB_DSCSR_CDSKEY_Pos 17U
	DCB DSCSR: CDS write-enable key Position.
#define	DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)
	DCB DSCSR: CDS write-enable key Mask.
#define	DCB_DSCSR_CDS_Pos 16U
	DCB DSCSR: Current domain Secure Position.
#define	DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)
	DCB DSCSR: Current domain Secure Mask.
#define	DCB_DSCSR_SBRSEL_Pos 1U
	DCB DSCSR: Secure banked register select Position.
#define	DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)
	DCB DSCSR: Secure banked register select Mask.
#define	DCB_DSCSR_SBRSELEN_Pos 0U
	DCB DSCSR: Secure banked register select enable Position.
#define	DCB_DSCSR_SBRSELEN_Msk (0x1UL /<< DCB_DSCSR_SBRSELEN_Pos/)
	DCB DSCSR: Secure banked register select enable Mask.
#define	DCB_DHCSR_DBGKEY_Pos 16U
	DCB DHCSR: Debug key Position.
#define	DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
	DCB DHCSR: Debug key Mask.
#define	DCB_DHCSR_S_RESTART_ST_Pos 26U
	DCB DHCSR: Restart sticky status Position.
#define	DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
	DCB DHCSR: Restart sticky status Mask.
#define	DCB_DHCSR_S_RESET_ST_Pos 25U
	DCB DHCSR: Reset sticky status Position.
#define	DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
	DCB DHCSR: Reset sticky status Mask.
#define	DCB_DHCSR_S_RETIRE_ST_Pos 24U
	DCB DHCSR: Retire sticky status Position.
#define	DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
	DCB DHCSR: Retire sticky status Mask.
#define	DCB_DHCSR_S_SDE_Pos 20U
	DCB DHCSR: Secure debug enabled Position.
#define	DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)
	DCB DHCSR: Secure debug enabled Mask.
#define	DCB_DHCSR_S_LOCKUP_Pos 19U
	DCB DHCSR: Lockup status Position.
#define	DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
	DCB DHCSR: Lockup status Mask.
#define	DCB_DHCSR_S_SLEEP_Pos 18U
	DCB DHCSR: Sleeping status Position.
#define	DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
	DCB DHCSR: Sleeping status Mask.
#define	DCB_DHCSR_S_HALT_Pos 17U
	DCB DHCSR: Halted status Position.
#define	DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)
	DCB DHCSR: Halted status Mask.
#define	DCB_DHCSR_S_REGRDY_Pos 16U
	DCB DHCSR: Register ready status Position.
#define	DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
	DCB DHCSR: Register ready status Mask.
#define	DCB_DHCSR_C_MASKINTS_Pos 3U
	DCB DHCSR: Mask interrupts control Position.
#define	DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
	DCB DHCSR: Mask interrupts control Mask.
#define	DCB_DHCSR_C_STEP_Pos 2U
	DCB DHCSR: Step control Position.
#define	DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)
	DCB DHCSR: Step control Mask.
#define	DCB_DHCSR_C_HALT_Pos 1U
	DCB DHCSR: Halt control Position.
#define	DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)
	DCB DHCSR: Halt control Mask.
#define	DCB_DHCSR_C_DEBUGEN_Pos 0U
	DCB DHCSR: Debug enable control Position.
#define	DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /<< DCB_DHCSR_C_DEBUGEN_Pos/)
	DCB DHCSR: Debug enable control Mask.
#define	DCB_DCRSR_REGWnR_Pos 16U
	DCB DCRSR: Register write/not-read Position.
#define	DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)
	DCB DCRSR: Register write/not-read Mask.
#define	DCB_DCRSR_REGSEL_Pos 0U
	DCB DCRSR: Register selector Position.
#define	DCB_DCRSR_REGSEL_Msk (0x7FUL /<< DCB_DCRSR_REGSEL_Pos/)
	DCB DCRSR: Register selector Mask.
#define	DCB_DCRDR_DBGTMP_Pos 0U
	DCB DCRDR: Data temporary buffer Position.
#define	DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /<< DCB_DCRDR_DBGTMP_Pos/)
	DCB DCRDR: Data temporary buffer Mask.
#define	DCB_DEMCR_TRCENA_Pos 24U
	DCB DEMCR: Trace enable Position.
#define	DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)
	DCB DEMCR: Trace enable Mask.
#define	DCB_DEMCR_VC_HARDERR_Pos 10U
	DCB DEMCR: Vector Catch HardFault errors Position.
#define	DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
	DCB DEMCR: Vector Catch HardFault errors Mask.
#define	DCB_DEMCR_VC_CORERESET_Pos 0U
	DCB DEMCR: Vector Catch Core reset Position.
#define	DCB_DEMCR_VC_CORERESET_Msk (0x1UL /<< DCB_DEMCR_VC_CORERESET_Pos/)
	DCB DEMCR: Vector Catch Core reset Mask.
#define	DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U
	DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position.
#define	DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
	DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask.
#define	DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U
	DCB DAUTHCTRL: Secure non-invasive debug enable select Position.
#define	DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
	DCB DAUTHCTRL: Secure non-invasive debug enable select Mask.
#define	DCB_DAUTHCTRL_INTSPIDEN_Pos 1U
	DCB DAUTHCTRL: Internal Secure invasive debug enable Position.
#define	DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
	DCB DAUTHCTRL: Internal Secure invasive debug enable Mask.
#define	DCB_DAUTHCTRL_SPIDENSEL_Pos 0U
	DCB DAUTHCTRL: Secure invasive debug enable select Position.
#define	DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /<< DCB_DAUTHCTRL_SPIDENSEL_Pos/)
	DCB DAUTHCTRL: Secure invasive debug enable select Mask.
#define	DCB_DSCSR_CDSKEY_Pos 17U
	DCB DSCSR: CDS write-enable key Position.
#define	DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)
	DCB DSCSR: CDS write-enable key Mask.
#define	DCB_DSCSR_CDS_Pos 16U
	DCB DSCSR: Current domain Secure Position.
#define	DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)
	DCB DSCSR: Current domain Secure Mask.
#define	DCB_DSCSR_SBRSEL_Pos 1U
	DCB DSCSR: Secure banked register select Position.
#define	DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)
	DCB DSCSR: Secure banked register select Mask.
#define	DCB_DSCSR_SBRSELEN_Pos 0U
	DCB DSCSR: Secure banked register select enable Position.
#define	DCB_DSCSR_SBRSELEN_Msk (0x1UL /<< DCB_DSCSR_SBRSELEN_Pos/)
	DCB DSCSR: Secure banked register select enable Mask.
#define	DCB_DHCSR_DBGKEY_Pos 16U
	DCB DHCSR: Debug key Position.
#define	DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
	DCB DHCSR: Debug key Mask.
#define	DCB_DHCSR_S_RESTART_ST_Pos 26U
	DCB DHCSR: Restart sticky status Position.
#define	DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
	DCB DHCSR: Restart sticky status Mask.
#define	DCB_DHCSR_S_RESET_ST_Pos 25U
	DCB DHCSR: Reset sticky status Position.
#define	DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
	DCB DHCSR: Reset sticky status Mask.
#define	DCB_DHCSR_S_RETIRE_ST_Pos 24U
	DCB DHCSR: Retire sticky status Position.
#define	DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
	DCB DHCSR: Retire sticky status Mask.
#define	DCB_DHCSR_S_SDE_Pos 20U
	DCB DHCSR: Secure debug enabled Position.
#define	DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)
	DCB DHCSR: Secure debug enabled Mask.
#define	DCB_DHCSR_S_LOCKUP_Pos 19U
	DCB DHCSR: Lockup status Position.
#define	DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
	DCB DHCSR: Lockup status Mask.
#define	DCB_DHCSR_S_SLEEP_Pos 18U
	DCB DHCSR: Sleeping status Position.
#define	DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
	DCB DHCSR: Sleeping status Mask.
#define	DCB_DHCSR_S_HALT_Pos 17U
	DCB DHCSR: Halted status Position.
#define	DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)
	DCB DHCSR: Halted status Mask.
#define	DCB_DHCSR_S_REGRDY_Pos 16U
	DCB DHCSR: Register ready status Position.
#define	DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
	DCB DHCSR: Register ready status Mask.
#define	DCB_DHCSR_C_SNAPSTALL_Pos 5U
	DCB DHCSR: Snap stall control Position.
#define	DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
	DCB DHCSR: Snap stall control Mask.
#define	DCB_DHCSR_C_MASKINTS_Pos 3U
	DCB DHCSR: Mask interrupts control Position.
#define	DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
	DCB DHCSR: Mask interrupts control Mask.
#define	DCB_DHCSR_C_STEP_Pos 2U
	DCB DHCSR: Step control Position.
#define	DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)
	DCB DHCSR: Step control Mask.
#define	DCB_DHCSR_C_HALT_Pos 1U
	DCB DHCSR: Halt control Position.
#define	DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)
	DCB DHCSR: Halt control Mask.
#define	DCB_DHCSR_C_DEBUGEN_Pos 0U
	DCB DHCSR: Debug enable control Position.
#define	DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /<< DCB_DHCSR_C_DEBUGEN_Pos/)
	DCB DHCSR: Debug enable control Mask.
#define	DCB_DCRSR_REGWnR_Pos 16U
	DCB DCRSR: Register write/not-read Position.
#define	DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)
	DCB DCRSR: Register write/not-read Mask.
#define	DCB_DCRSR_REGSEL_Pos 0U
	DCB DCRSR: Register selector Position.
#define	DCB_DCRSR_REGSEL_Msk (0x7FUL /<< DCB_DCRSR_REGSEL_Pos/)
	DCB DCRSR: Register selector Mask.
#define	DCB_DCRDR_DBGTMP_Pos 0U
	DCB DCRDR: Data temporary buffer Position.
#define	DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /<< DCB_DCRDR_DBGTMP_Pos/)
	DCB DCRDR: Data temporary buffer Mask.
#define	DCB_DEMCR_TRCENA_Pos 24U
	DCB DEMCR: Trace enable Position.
#define	DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)
	DCB DEMCR: Trace enable Mask.
#define	DCB_DEMCR_MONPRKEY_Pos 23U
	DCB DEMCR: Monitor pend req key Position.
#define	DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
	DCB DEMCR: Monitor pend req key Mask.
#define	DCB_DEMCR_UMON_EN_Pos 21U
	DCB DEMCR: Unprivileged monitor enable Position.
#define	DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos)
	DCB DEMCR: Unprivileged monitor enable Mask.
#define	DCB_DEMCR_SDME_Pos 20U
	DCB DEMCR: Secure DebugMonitor enable Position.
#define	DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos)
	DCB DEMCR: Secure DebugMonitor enable Mask.
#define	DCB_DEMCR_MON_REQ_Pos 19U
	DCB DEMCR: Monitor request Position.
#define	DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos)
	DCB DEMCR: Monitor request Mask.
#define	DCB_DEMCR_MON_STEP_Pos 18U
	DCB DEMCR: Monitor step Position.
#define	DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos)
	DCB DEMCR: Monitor step Mask.
#define	DCB_DEMCR_MON_PEND_Pos 17U
	DCB DEMCR: Monitor pend Position.
#define	DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos)
	DCB DEMCR: Monitor pend Mask.
#define	DCB_DEMCR_MON_EN_Pos 16U
	DCB DEMCR: Monitor enable Position.
#define	DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos)
	DCB DEMCR: Monitor enable Mask.
#define	DCB_DEMCR_VC_SFERR_Pos 11U
	DCB DEMCR: Vector Catch SecureFault Position.
#define	DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
	DCB DEMCR: Vector Catch SecureFault Mask.
#define	DCB_DEMCR_VC_HARDERR_Pos 10U
	DCB DEMCR: Vector Catch HardFault errors Position.
#define	DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
	DCB DEMCR: Vector Catch HardFault errors Mask.
#define	DCB_DEMCR_VC_INTERR_Pos 9U
	DCB DEMCR: Vector Catch interrupt errors Position.
#define	DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
	DCB DEMCR: Vector Catch interrupt errors Mask.
#define	DCB_DEMCR_VC_BUSERR_Pos 8U
	DCB DEMCR: Vector Catch BusFault errors Position.
#define	DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
	DCB DEMCR: Vector Catch BusFault errors Mask.
#define	DCB_DEMCR_VC_STATERR_Pos 7U
	DCB DEMCR: Vector Catch state errors Position.
#define	DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
	DCB DEMCR: Vector Catch state errors Mask.
#define	DCB_DEMCR_VC_CHKERR_Pos 6U
	DCB DEMCR: Vector Catch check errors Position.
#define	DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
	DCB DEMCR: Vector Catch check errors Mask.
#define	DCB_DEMCR_VC_NOCPERR_Pos 5U
	DCB DEMCR: Vector Catch NOCP errors Position.
#define	DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
	DCB DEMCR: Vector Catch NOCP errors Mask.
#define	DCB_DEMCR_VC_MMERR_Pos 4U
	DCB DEMCR: Vector Catch MemManage errors Position.
#define	DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
	DCB DEMCR: Vector Catch MemManage errors Mask.
#define	DCB_DEMCR_VC_CORERESET_Pos 0U
	DCB DEMCR: Vector Catch Core reset Position.
#define	DCB_DEMCR_VC_CORERESET_Msk (0x1UL /<< DCB_DEMCR_VC_CORERESET_Pos/)
	DCB DEMCR: Vector Catch Core reset Mask.
#define	DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U
	DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position.
#define	DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
	DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask.
#define	DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U
	DCB DAUTHCTRL: Secure non-invasive debug enable select Position.
#define	DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
	DCB DAUTHCTRL: Secure non-invasive debug enable select Mask.
#define	DCB_DAUTHCTRL_INTSPIDEN_Pos 1U
	DCB DAUTHCTRL: Internal Secure invasive debug enable Position.
#define	DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
	DCB DAUTHCTRL: Internal Secure invasive debug enable Mask.
#define	DCB_DAUTHCTRL_SPIDENSEL_Pos 0U
	DCB DAUTHCTRL: Secure invasive debug enable select Position.
#define	DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /<< DCB_DAUTHCTRL_SPIDENSEL_Pos/)
	DCB DAUTHCTRL: Secure invasive debug enable select Mask.
#define	DCB_DSCSR_CDSKEY_Pos 17U
	DCB DSCSR: CDS write-enable key Position.
#define	DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)
	DCB DSCSR: CDS write-enable key Mask.
#define	DCB_DSCSR_CDS_Pos 16U
	DCB DSCSR: Current domain Secure Position.
#define	DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)
	DCB DSCSR: Current domain Secure Mask.
#define	DCB_DSCSR_SBRSEL_Pos 1U
	DCB DSCSR: Secure banked register select Position.
#define	DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)
	DCB DSCSR: Secure banked register select Mask.
#define	DCB_DSCSR_SBRSELEN_Pos 0U
	DCB DSCSR: Secure banked register select enable Position.
#define	DCB_DSCSR_SBRSELEN_Msk (0x1UL /<< DCB_DSCSR_SBRSELEN_Pos/)
	DCB DSCSR: Secure banked register select enable Mask.
#define	DCB_DHCSR_DBGKEY_Pos 16U
	DCB DHCSR: Debug key Position.
#define	DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
	DCB DHCSR: Debug key Mask.
#define	DCB_DHCSR_S_RESTART_ST_Pos 26U
	DCB DHCSR: Restart sticky status Position.
#define	DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
	DCB DHCSR: Restart sticky status Mask.
#define	DCB_DHCSR_S_RESET_ST_Pos 25U
	DCB DHCSR: Reset sticky status Position.
#define	DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
	DCB DHCSR: Reset sticky status Mask.
#define	DCB_DHCSR_S_RETIRE_ST_Pos 24U
	DCB DHCSR: Retire sticky status Position.
#define	DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
	DCB DHCSR: Retire sticky status Mask.
#define	DCB_DHCSR_S_SDE_Pos 20U
	DCB DHCSR: Secure debug enabled Position.
#define	DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)
	DCB DHCSR: Secure debug enabled Mask.
#define	DCB_DHCSR_S_LOCKUP_Pos 19U
	DCB DHCSR: Lockup status Position.
#define	DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
	DCB DHCSR: Lockup status Mask.
#define	DCB_DHCSR_S_SLEEP_Pos 18U
	DCB DHCSR: Sleeping status Position.
#define	DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
	DCB DHCSR: Sleeping status Mask.
#define	DCB_DHCSR_S_HALT_Pos 17U
	DCB DHCSR: Halted status Position.
#define	DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)
	DCB DHCSR: Halted status Mask.
#define	DCB_DHCSR_S_REGRDY_Pos 16U
	DCB DHCSR: Register ready status Position.
#define	DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
	DCB DHCSR: Register ready status Mask.
#define	DCB_DHCSR_C_MASKINTS_Pos 3U
	DCB DHCSR: Mask interrupts control Position.
#define	DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
	DCB DHCSR: Mask interrupts control Mask.
#define	DCB_DHCSR_C_STEP_Pos 2U
	DCB DHCSR: Step control Position.
#define	DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)
	DCB DHCSR: Step control Mask.
#define	DCB_DHCSR_C_HALT_Pos 1U
	DCB DHCSR: Halt control Position.
#define	DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)
	DCB DHCSR: Halt control Mask.
#define	DCB_DHCSR_C_DEBUGEN_Pos 0U
	DCB DHCSR: Debug enable control Position.
#define	DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /<< DCB_DHCSR_C_DEBUGEN_Pos/)
	DCB DHCSR: Debug enable control Mask.
#define	DCB_DCRSR_REGWnR_Pos 16U
	DCB DCRSR: Register write/not-read Position.
#define	DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)
	DCB DCRSR: Register write/not-read Mask.
#define	DCB_DCRSR_REGSEL_Pos 0U
	DCB DCRSR: Register selector Position.
#define	DCB_DCRSR_REGSEL_Msk (0x7FUL /<< DCB_DCRSR_REGSEL_Pos/)
	DCB DCRSR: Register selector Mask.
#define	DCB_DCRDR_DBGTMP_Pos 0U
	DCB DCRDR: Data temporary buffer Position.
#define	DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /<< DCB_DCRDR_DBGTMP_Pos/)
	DCB DCRDR: Data temporary buffer Mask.
#define	DCB_DEMCR_TRCENA_Pos 24U
	DCB DEMCR: Trace enable Position.
#define	DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)
	DCB DEMCR: Trace enable Mask.
#define	DCB_DEMCR_VC_HARDERR_Pos 10U
	DCB DEMCR: Vector Catch HardFault errors Position.
#define	DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
	DCB DEMCR: Vector Catch HardFault errors Mask.
#define	DCB_DEMCR_VC_CORERESET_Pos 0U
	DCB DEMCR: Vector Catch Core reset Position.
#define	DCB_DEMCR_VC_CORERESET_Msk (0x1UL /<< DCB_DEMCR_VC_CORERESET_Pos/)
	DCB DEMCR: Vector Catch Core reset Mask.
#define	DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U
	DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position.
#define	DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
	DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask.
#define	DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U
	DCB DAUTHCTRL: Secure non-invasive debug enable select Position.
#define	DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
	DCB DAUTHCTRL: Secure non-invasive debug enable select Mask.
#define	DCB_DAUTHCTRL_INTSPIDEN_Pos 1U
	DCB DAUTHCTRL: Internal Secure invasive debug enable Position.
#define	DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
	DCB DAUTHCTRL: Internal Secure invasive debug enable Mask.
#define	DCB_DAUTHCTRL_SPIDENSEL_Pos 0U
	DCB DAUTHCTRL: Secure invasive debug enable select Position.
#define	DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /<< DCB_DAUTHCTRL_SPIDENSEL_Pos/)
	DCB DAUTHCTRL: Secure invasive debug enable select Mask.
#define	DCB_DSCSR_CDSKEY_Pos 17U
	DCB DSCSR: CDS write-enable key Position.
#define	DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)
	DCB DSCSR: CDS write-enable key Mask.
#define	DCB_DSCSR_CDS_Pos 16U
	DCB DSCSR: Current domain Secure Position.
#define	DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)
	DCB DSCSR: Current domain Secure Mask.
#define	DCB_DSCSR_SBRSEL_Pos 1U
	DCB DSCSR: Secure banked register select Position.
#define	DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)
	DCB DSCSR: Secure banked register select Mask.
#define	DCB_DSCSR_SBRSELEN_Pos 0U
	DCB DSCSR: Secure banked register select enable Position.
#define	DCB_DSCSR_SBRSELEN_Msk (0x1UL /<< DCB_DSCSR_SBRSELEN_Pos/)
	DCB DSCSR: Secure banked register select enable Mask.
#define	DCB_DHCSR_DBGKEY_Pos 16U
	DCB DHCSR: Debug key Position.
#define	DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
	DCB DHCSR: Debug key Mask.
#define	DCB_DHCSR_S_RESTART_ST_Pos 26U
	DCB DHCSR: Restart sticky status Position.
#define	DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
	DCB DHCSR: Restart sticky status Mask.
#define	DCB_DHCSR_S_RESET_ST_Pos 25U
	DCB DHCSR: Reset sticky status Position.
#define	DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
	DCB DHCSR: Reset sticky status Mask.
#define	DCB_DHCSR_S_RETIRE_ST_Pos 24U
	DCB DHCSR: Retire sticky status Position.
#define	DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
	DCB DHCSR: Retire sticky status Mask.
#define	DCB_DHCSR_S_SDE_Pos 20U
	DCB DHCSR: Secure debug enabled Position.
#define	DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)
	DCB DHCSR: Secure debug enabled Mask.
#define	DCB_DHCSR_S_LOCKUP_Pos 19U
	DCB DHCSR: Lockup status Position.
#define	DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
	DCB DHCSR: Lockup status Mask.
#define	DCB_DHCSR_S_SLEEP_Pos 18U
	DCB DHCSR: Sleeping status Position.
#define	DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
	DCB DHCSR: Sleeping status Mask.
#define	DCB_DHCSR_S_HALT_Pos 17U
	DCB DHCSR: Halted status Position.
#define	DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)
	DCB DHCSR: Halted status Mask.
#define	DCB_DHCSR_S_REGRDY_Pos 16U
	DCB DHCSR: Register ready status Position.
#define	DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
	DCB DHCSR: Register ready status Mask.
#define	DCB_DHCSR_C_SNAPSTALL_Pos 5U
	DCB DHCSR: Snap stall control Position.
#define	DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
	DCB DHCSR: Snap stall control Mask.
#define	DCB_DHCSR_C_MASKINTS_Pos 3U
	DCB DHCSR: Mask interrupts control Position.
#define	DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
	DCB DHCSR: Mask interrupts control Mask.
#define	DCB_DHCSR_C_STEP_Pos 2U
	DCB DHCSR: Step control Position.
#define	DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)
	DCB DHCSR: Step control Mask.
#define	DCB_DHCSR_C_HALT_Pos 1U
	DCB DHCSR: Halt control Position.
#define	DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)
	DCB DHCSR: Halt control Mask.
#define	DCB_DHCSR_C_DEBUGEN_Pos 0U
	DCB DHCSR: Debug enable control Position.
#define	DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /<< DCB_DHCSR_C_DEBUGEN_Pos/)
	DCB DHCSR: Debug enable control Mask.
#define	DCB_DCRSR_REGWnR_Pos 16U
	DCB DCRSR: Register write/not-read Position.
#define	DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)
	DCB DCRSR: Register write/not-read Mask.
#define	DCB_DCRSR_REGSEL_Pos 0U
	DCB DCRSR: Register selector Position.
#define	DCB_DCRSR_REGSEL_Msk (0x7FUL /<< DCB_DCRSR_REGSEL_Pos/)
	DCB DCRSR: Register selector Mask.
#define	DCB_DCRDR_DBGTMP_Pos 0U
	DCB DCRDR: Data temporary buffer Position.
#define	DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /<< DCB_DCRDR_DBGTMP_Pos/)
	DCB DCRDR: Data temporary buffer Mask.
#define	DCB_DEMCR_TRCENA_Pos 24U
	DCB DEMCR: Trace enable Position.
#define	DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)
	DCB DEMCR: Trace enable Mask.
#define	DCB_DEMCR_MONPRKEY_Pos 23U
	DCB DEMCR: Monitor pend req key Position.
#define	DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
	DCB DEMCR: Monitor pend req key Mask.
#define	DCB_DEMCR_UMON_EN_Pos 21U
	DCB DEMCR: Unprivileged monitor enable Position.
#define	DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos)
	DCB DEMCR: Unprivileged monitor enable Mask.
#define	DCB_DEMCR_SDME_Pos 20U
	DCB DEMCR: Secure DebugMonitor enable Position.
#define	DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos)
	DCB DEMCR: Secure DebugMonitor enable Mask.
#define	DCB_DEMCR_MON_REQ_Pos 19U
	DCB DEMCR: Monitor request Position.
#define	DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos)
	DCB DEMCR: Monitor request Mask.
#define	DCB_DEMCR_MON_STEP_Pos 18U
	DCB DEMCR: Monitor step Position.
#define	DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos)
	DCB DEMCR: Monitor step Mask.
#define	DCB_DEMCR_MON_PEND_Pos 17U
	DCB DEMCR: Monitor pend Position.
#define	DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos)
	DCB DEMCR: Monitor pend Mask.
#define	DCB_DEMCR_MON_EN_Pos 16U
	DCB DEMCR: Monitor enable Position.
#define	DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos)
	DCB DEMCR: Monitor enable Mask.
#define	DCB_DEMCR_VC_SFERR_Pos 11U
	DCB DEMCR: Vector Catch SecureFault Position.
#define	DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
	DCB DEMCR: Vector Catch SecureFault Mask.
#define	DCB_DEMCR_VC_HARDERR_Pos 10U
	DCB DEMCR: Vector Catch HardFault errors Position.
#define	DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
	DCB DEMCR: Vector Catch HardFault errors Mask.
#define	DCB_DEMCR_VC_INTERR_Pos 9U
	DCB DEMCR: Vector Catch interrupt errors Position.
#define	DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
	DCB DEMCR: Vector Catch interrupt errors Mask.
#define	DCB_DEMCR_VC_BUSERR_Pos 8U
	DCB DEMCR: Vector Catch BusFault errors Position.
#define	DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
	DCB DEMCR: Vector Catch BusFault errors Mask.
#define	DCB_DEMCR_VC_STATERR_Pos 7U
	DCB DEMCR: Vector Catch state errors Position.
#define	DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
	DCB DEMCR: Vector Catch state errors Mask.
#define	DCB_DEMCR_VC_CHKERR_Pos 6U
	DCB DEMCR: Vector Catch check errors Position.
#define	DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
	DCB DEMCR: Vector Catch check errors Mask.
#define	DCB_DEMCR_VC_NOCPERR_Pos 5U
	DCB DEMCR: Vector Catch NOCP errors Position.
#define	DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
	DCB DEMCR: Vector Catch NOCP errors Mask.
#define	DCB_DEMCR_VC_MMERR_Pos 4U
	DCB DEMCR: Vector Catch MemManage errors Position.
#define	DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
	DCB DEMCR: Vector Catch MemManage errors Mask.
#define	DCB_DEMCR_VC_CORERESET_Pos 0U
	DCB DEMCR: Vector Catch Core reset Position.
#define	DCB_DEMCR_VC_CORERESET_Msk (0x1UL /<< DCB_DEMCR_VC_CORERESET_Pos/)
	DCB DEMCR: Vector Catch Core reset Mask.
#define	DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U
	DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position.
#define	DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
	DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask.
#define	DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U
	DCB DAUTHCTRL: Secure non-invasive debug enable select Position.
#define	DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
	DCB DAUTHCTRL: Secure non-invasive debug enable select Mask.
#define	DCB_DAUTHCTRL_INTSPIDEN_Pos 1U
	DCB DAUTHCTRL: Internal Secure invasive debug enable Position.
#define	DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
	DCB DAUTHCTRL: Internal Secure invasive debug enable Mask.
#define	DCB_DAUTHCTRL_SPIDENSEL_Pos 0U
	DCB DAUTHCTRL: Secure invasive debug enable select Position.
#define	DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /<< DCB_DAUTHCTRL_SPIDENSEL_Pos/)
	DCB DAUTHCTRL: Secure invasive debug enable select Mask.
#define	DCB_DSCSR_CDSKEY_Pos 17U
	DCB DSCSR: CDS write-enable key Position.
#define	DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)
	DCB DSCSR: CDS write-enable key Mask.
#define	DCB_DSCSR_CDS_Pos 16U
	DCB DSCSR: Current domain Secure Position.
#define	DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)
	DCB DSCSR: Current domain Secure Mask.
#define	DCB_DSCSR_SBRSEL_Pos 1U
	DCB DSCSR: Secure banked register select Position.
#define	DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)
	DCB DSCSR: Secure banked register select Mask.
#define	DCB_DSCSR_SBRSELEN_Pos 0U
	DCB DSCSR: Secure banked register select enable Position.
#define	DCB_DSCSR_SBRSELEN_Msk (0x1UL /<< DCB_DSCSR_SBRSELEN_Pos/)
	DCB DSCSR: Secure banked register select enable Mask.
#define	DCB_DHCSR_DBGKEY_Pos 16U
	DCB DHCSR: Debug key Position.
#define	DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
	DCB DHCSR: Debug key Mask.
#define	DCB_DHCSR_S_RESTART_ST_Pos 26U
	DCB DHCSR: Restart sticky status Position.
#define	DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
	DCB DHCSR: Restart sticky status Mask.
#define	DCB_DHCSR_S_RESET_ST_Pos 25U
	DCB DHCSR: Reset sticky status Position.
#define	DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
	DCB DHCSR: Reset sticky status Mask.
#define	DCB_DHCSR_S_RETIRE_ST_Pos 24U
	DCB DHCSR: Retire sticky status Position.
#define	DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
	DCB DHCSR: Retire sticky status Mask.
#define	DCB_DHCSR_S_SDE_Pos 20U
	DCB DHCSR: Secure debug enabled Position.
#define	DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)
	DCB DHCSR: Secure debug enabled Mask.
#define	DCB_DHCSR_S_LOCKUP_Pos 19U
	DCB DHCSR: Lockup status Position.
#define	DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
	DCB DHCSR: Lockup status Mask.
#define	DCB_DHCSR_S_SLEEP_Pos 18U
	DCB DHCSR: Sleeping status Position.
#define	DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
	DCB DHCSR: Sleeping status Mask.
#define	DCB_DHCSR_S_HALT_Pos 17U
	DCB DHCSR: Halted status Position.
#define	DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)
	DCB DHCSR: Halted status Mask.
#define	DCB_DHCSR_S_REGRDY_Pos 16U
	DCB DHCSR: Register ready status Position.
#define	DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
	DCB DHCSR: Register ready status Mask.
#define	DCB_DHCSR_C_SNAPSTALL_Pos 5U
	DCB DHCSR: Snap stall control Position.
#define	DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
	DCB DHCSR: Snap stall control Mask.
#define	DCB_DHCSR_C_MASKINTS_Pos 3U
	DCB DHCSR: Mask interrupts control Position.
#define	DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
	DCB DHCSR: Mask interrupts control Mask.
#define	DCB_DHCSR_C_STEP_Pos 2U
	DCB DHCSR: Step control Position.
#define	DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)
	DCB DHCSR: Step control Mask.
#define	DCB_DHCSR_C_HALT_Pos 1U
	DCB DHCSR: Halt control Position.
#define	DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)
	DCB DHCSR: Halt control Mask.
#define	DCB_DHCSR_C_DEBUGEN_Pos 0U
	DCB DHCSR: Debug enable control Position.
#define	DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /<< DCB_DHCSR_C_DEBUGEN_Pos/)
	DCB DHCSR: Debug enable control Mask.
#define	DCB_DCRSR_REGWnR_Pos 16U
	DCB DCRSR: Register write/not-read Position.
#define	DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)
	DCB DCRSR: Register write/not-read Mask.
#define	DCB_DCRSR_REGSEL_Pos 0U
	DCB DCRSR: Register selector Position.
#define	DCB_DCRSR_REGSEL_Msk (0x7FUL /<< DCB_DCRSR_REGSEL_Pos/)
	DCB DCRSR: Register selector Mask.
#define	DCB_DCRDR_DBGTMP_Pos 0U
	DCB DCRDR: Data temporary buffer Position.
#define	DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /<< DCB_DCRDR_DBGTMP_Pos/)
	DCB DCRDR: Data temporary buffer Mask.
#define	DCB_DEMCR_TRCENA_Pos 24U
	DCB DEMCR: Trace enable Position.
#define	DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)
	DCB DEMCR: Trace enable Mask.
#define	DCB_DEMCR_MONPRKEY_Pos 23U
	DCB DEMCR: Monitor pend req key Position.
#define	DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
	DCB DEMCR: Monitor pend req key Mask.
#define	DCB_DEMCR_UMON_EN_Pos 21U
	DCB DEMCR: Unprivileged monitor enable Position.
#define	DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos)
	DCB DEMCR: Unprivileged monitor enable Mask.
#define	DCB_DEMCR_SDME_Pos 20U
	DCB DEMCR: Secure DebugMonitor enable Position.
#define	DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos)
	DCB DEMCR: Secure DebugMonitor enable Mask.
#define	DCB_DEMCR_MON_REQ_Pos 19U
	DCB DEMCR: Monitor request Position.
#define	DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos)
	DCB DEMCR: Monitor request Mask.
#define	DCB_DEMCR_MON_STEP_Pos 18U
	DCB DEMCR: Monitor step Position.
#define	DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos)
	DCB DEMCR: Monitor step Mask.
#define	DCB_DEMCR_MON_PEND_Pos 17U
	DCB DEMCR: Monitor pend Position.
#define	DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos)
	DCB DEMCR: Monitor pend Mask.
#define	DCB_DEMCR_MON_EN_Pos 16U
	DCB DEMCR: Monitor enable Position.
#define	DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos)
	DCB DEMCR: Monitor enable Mask.
#define	DCB_DEMCR_VC_SFERR_Pos 11U
	DCB DEMCR: Vector Catch SecureFault Position.
#define	DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
	DCB DEMCR: Vector Catch SecureFault Mask.
#define	DCB_DEMCR_VC_HARDERR_Pos 10U
	DCB DEMCR: Vector Catch HardFault errors Position.
#define	DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
	DCB DEMCR: Vector Catch HardFault errors Mask.
#define	DCB_DEMCR_VC_INTERR_Pos 9U
	DCB DEMCR: Vector Catch interrupt errors Position.
#define	DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
	DCB DEMCR: Vector Catch interrupt errors Mask.
#define	DCB_DEMCR_VC_BUSERR_Pos 8U
	DCB DEMCR: Vector Catch BusFault errors Position.
#define	DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
	DCB DEMCR: Vector Catch BusFault errors Mask.
#define	DCB_DEMCR_VC_STATERR_Pos 7U
	DCB DEMCR: Vector Catch state errors Position.
#define	DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
	DCB DEMCR: Vector Catch state errors Mask.
#define	DCB_DEMCR_VC_CHKERR_Pos 6U
	DCB DEMCR: Vector Catch check errors Position.
#define	DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
	DCB DEMCR: Vector Catch check errors Mask.
#define	DCB_DEMCR_VC_NOCPERR_Pos 5U
	DCB DEMCR: Vector Catch NOCP errors Position.
#define	DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
	DCB DEMCR: Vector Catch NOCP errors Mask.
#define	DCB_DEMCR_VC_MMERR_Pos 4U
	DCB DEMCR: Vector Catch MemManage errors Position.
#define	DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
	DCB DEMCR: Vector Catch MemManage errors Mask.
#define	DCB_DEMCR_VC_CORERESET_Pos 0U
	DCB DEMCR: Vector Catch Core reset Position.
#define	DCB_DEMCR_VC_CORERESET_Msk (0x1UL /<< DCB_DEMCR_VC_CORERESET_Pos/)
	DCB DEMCR: Vector Catch Core reset Mask.
#define	DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U
	DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position.
#define	DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
	DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask.
#define	DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U
	DCB DAUTHCTRL: Secure non-invasive debug enable select Position.
#define	DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
	DCB DAUTHCTRL: Secure non-invasive debug enable select Mask.
#define	DCB_DAUTHCTRL_INTSPIDEN_Pos 1U
	DCB DAUTHCTRL: Internal Secure invasive debug enable Position.
#define	DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
	DCB DAUTHCTRL: Internal Secure invasive debug enable Mask.
#define	DCB_DAUTHCTRL_SPIDENSEL_Pos 0U
	DCB DAUTHCTRL: Secure invasive debug enable select Position.
#define	DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /<< DCB_DAUTHCTRL_SPIDENSEL_Pos/)
	DCB DAUTHCTRL: Secure invasive debug enable select Mask.
#define	DCB_DSCSR_CDSKEY_Pos 17U
	DCB DSCSR: CDS write-enable key Position.
#define	DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)
	DCB DSCSR: CDS write-enable key Mask.
#define	DCB_DSCSR_CDS_Pos 16U
	DCB DSCSR: Current domain Secure Position.
#define	DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)
	DCB DSCSR: Current domain Secure Mask.
#define	DCB_DSCSR_SBRSEL_Pos 1U
	DCB DSCSR: Secure banked register select Position.
#define	DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)
	DCB DSCSR: Secure banked register select Mask.
#define	DCB_DSCSR_SBRSELEN_Pos 0U
	DCB DSCSR: Secure banked register select enable Position.
#define	DCB_DSCSR_SBRSELEN_Msk (0x1UL /<< DCB_DSCSR_SBRSELEN_Pos/)
	DCB DSCSR: Secure banked register select enable Mask.
#define	DCB_DHCSR_DBGKEY_Pos 16U
	DCB DHCSR: Debug key Position.
#define	DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
	DCB DHCSR: Debug key Mask.
#define	DCB_DHCSR_S_RESTART_ST_Pos 26U
	DCB DHCSR: Restart sticky status Position.
#define	DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
	DCB DHCSR: Restart sticky status Mask.
#define	DCB_DHCSR_S_RESET_ST_Pos 25U
	DCB DHCSR: Reset sticky status Position.
#define	DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
	DCB DHCSR: Reset sticky status Mask.
#define	DCB_DHCSR_S_RETIRE_ST_Pos 24U
	DCB DHCSR: Retire sticky status Position.
#define	DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
	DCB DHCSR: Retire sticky status Mask.
#define	DCB_DHCSR_S_SDE_Pos 20U
	DCB DHCSR: Secure debug enabled Position.
#define	DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)
	DCB DHCSR: Secure debug enabled Mask.
#define	DCB_DHCSR_S_LOCKUP_Pos 19U
	DCB DHCSR: Lockup status Position.
#define	DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
	DCB DHCSR: Lockup status Mask.
#define	DCB_DHCSR_S_SLEEP_Pos 18U
	DCB DHCSR: Sleeping status Position.
#define	DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
	DCB DHCSR: Sleeping status Mask.
#define	DCB_DHCSR_S_HALT_Pos 17U
	DCB DHCSR: Halted status Position.
#define	DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)
	DCB DHCSR: Halted status Mask.
#define	DCB_DHCSR_S_REGRDY_Pos 16U
	DCB DHCSR: Register ready status Position.
#define	DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
	DCB DHCSR: Register ready status Mask.
#define	DCB_DHCSR_C_SNAPSTALL_Pos 5U
	DCB DHCSR: Snap stall control Position.
#define	DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
	DCB DHCSR: Snap stall control Mask.
#define	DCB_DHCSR_C_MASKINTS_Pos 3U
	DCB DHCSR: Mask interrupts control Position.
#define	DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
	DCB DHCSR: Mask interrupts control Mask.
#define	DCB_DHCSR_C_STEP_Pos 2U
	DCB DHCSR: Step control Position.
#define	DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)
	DCB DHCSR: Step control Mask.
#define	DCB_DHCSR_C_HALT_Pos 1U
	DCB DHCSR: Halt control Position.
#define	DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)
	DCB DHCSR: Halt control Mask.
#define	DCB_DHCSR_C_DEBUGEN_Pos 0U
	DCB DHCSR: Debug enable control Position.
#define	DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /<< DCB_DHCSR_C_DEBUGEN_Pos/)
	DCB DHCSR: Debug enable control Mask.
#define	DCB_DCRSR_REGWnR_Pos 16U
	DCB DCRSR: Register write/not-read Position.
#define	DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)
	DCB DCRSR: Register write/not-read Mask.
#define	DCB_DCRSR_REGSEL_Pos 0U
	DCB DCRSR: Register selector Position.
#define	DCB_DCRSR_REGSEL_Msk (0x7FUL /<< DCB_DCRSR_REGSEL_Pos/)
	DCB DCRSR: Register selector Mask.
#define	DCB_DCRDR_DBGTMP_Pos 0U
	DCB DCRDR: Data temporary buffer Position.
#define	DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /<< DCB_DCRDR_DBGTMP_Pos/)
	DCB DCRDR: Data temporary buffer Mask.
#define	DCB_DEMCR_TRCENA_Pos 24U
	DCB DEMCR: Trace enable Position.
#define	DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)
	DCB DEMCR: Trace enable Mask.
#define	DCB_DEMCR_MONPRKEY_Pos 23U
	DCB DEMCR: Monitor pend req key Position.
#define	DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
	DCB DEMCR: Monitor pend req key Mask.
#define	DCB_DEMCR_UMON_EN_Pos 21U
	DCB DEMCR: Unprivileged monitor enable Position.
#define	DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos)
	DCB DEMCR: Unprivileged monitor enable Mask.
#define	DCB_DEMCR_SDME_Pos 20U
	DCB DEMCR: Secure DebugMonitor enable Position.
#define	DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos)
	DCB DEMCR: Secure DebugMonitor enable Mask.
#define	DCB_DEMCR_MON_REQ_Pos 19U
	DCB DEMCR: Monitor request Position.
#define	DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos)
	DCB DEMCR: Monitor request Mask.
#define	DCB_DEMCR_MON_STEP_Pos 18U
	DCB DEMCR: Monitor step Position.
#define	DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos)
	DCB DEMCR: Monitor step Mask.
#define	DCB_DEMCR_MON_PEND_Pos 17U
	DCB DEMCR: Monitor pend Position.
#define	DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos)
	DCB DEMCR: Monitor pend Mask.
#define	DCB_DEMCR_MON_EN_Pos 16U
	DCB DEMCR: Monitor enable Position.
#define	DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos)
	DCB DEMCR: Monitor enable Mask.
#define	DCB_DEMCR_VC_SFERR_Pos 11U
	DCB DEMCR: Vector Catch SecureFault Position.
#define	DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
	DCB DEMCR: Vector Catch SecureFault Mask.
#define	DCB_DEMCR_VC_HARDERR_Pos 10U
	DCB DEMCR: Vector Catch HardFault errors Position.
#define	DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
	DCB DEMCR: Vector Catch HardFault errors Mask.
#define	DCB_DEMCR_VC_INTERR_Pos 9U
	DCB DEMCR: Vector Catch interrupt errors Position.
#define	DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
	DCB DEMCR: Vector Catch interrupt errors Mask.
#define	DCB_DEMCR_VC_BUSERR_Pos 8U
	DCB DEMCR: Vector Catch BusFault errors Position.
#define	DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
	DCB DEMCR: Vector Catch BusFault errors Mask.
#define	DCB_DEMCR_VC_STATERR_Pos 7U
	DCB DEMCR: Vector Catch state errors Position.
#define	DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
	DCB DEMCR: Vector Catch state errors Mask.
#define	DCB_DEMCR_VC_CHKERR_Pos 6U
	DCB DEMCR: Vector Catch check errors Position.
#define	DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
	DCB DEMCR: Vector Catch check errors Mask.
#define	DCB_DEMCR_VC_NOCPERR_Pos 5U
	DCB DEMCR: Vector Catch NOCP errors Position.
#define	DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
	DCB DEMCR: Vector Catch NOCP errors Mask.
#define	DCB_DEMCR_VC_MMERR_Pos 4U
	DCB DEMCR: Vector Catch MemManage errors Position.
#define	DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
	DCB DEMCR: Vector Catch MemManage errors Mask.
#define	DCB_DEMCR_VC_CORERESET_Pos 0U
	DCB DEMCR: Vector Catch Core reset Position.
#define	DCB_DEMCR_VC_CORERESET_Msk (0x1UL /<< DCB_DEMCR_VC_CORERESET_Pos/)
	DCB DEMCR: Vector Catch Core reset Mask.
#define	DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U
	DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position.
#define	DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
	DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask.
#define	DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U
	DCB DAUTHCTRL: Secure non-invasive debug enable select Position.
#define	DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
	DCB DAUTHCTRL: Secure non-invasive debug enable select Mask.
#define	DCB_DAUTHCTRL_INTSPIDEN_Pos 1U
	DCB DAUTHCTRL: Internal Secure invasive debug enable Position.
#define	DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
	DCB DAUTHCTRL: Internal Secure invasive debug enable Mask.
#define	DCB_DAUTHCTRL_SPIDENSEL_Pos 0U
	DCB DAUTHCTRL: Secure invasive debug enable select Position.
#define	DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /<< DCB_DAUTHCTRL_SPIDENSEL_Pos/)
	DCB DAUTHCTRL: Secure invasive debug enable select Mask.
#define	DCB_DSCSR_CDSKEY_Pos 17U
	DCB DSCSR: CDS write-enable key Position.
#define	DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)
	DCB DSCSR: CDS write-enable key Mask.
#define	DCB_DSCSR_CDS_Pos 16U
	DCB DSCSR: Current domain Secure Position.
#define	DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)
	DCB DSCSR: Current domain Secure Mask.
#define	DCB_DSCSR_SBRSEL_Pos 1U
	DCB DSCSR: Secure banked register select Position.
#define	DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)
	DCB DSCSR: Secure banked register select Mask.
#define	DCB_DSCSR_SBRSELEN_Pos 0U
	DCB DSCSR: Secure banked register select enable Position.
#define	DCB_DSCSR_SBRSELEN_Msk (0x1UL /<< DCB_DSCSR_SBRSELEN_Pos/)
	DCB DSCSR: Secure banked register select enable Mask.
#define	DCB_DHCSR_DBGKEY_Pos 16U
	DCB DHCSR: Debug key Position.
#define	DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
	DCB DHCSR: Debug key Mask.
#define	DCB_DHCSR_S_RESTART_ST_Pos 26U
	DCB DHCSR: Restart sticky status Position.
#define	DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
	DCB DHCSR: Restart sticky status Mask.
#define	DCB_DHCSR_S_RESET_ST_Pos 25U
	DCB DHCSR: Reset sticky status Position.
#define	DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
	DCB DHCSR: Reset sticky status Mask.
#define	DCB_DHCSR_S_RETIRE_ST_Pos 24U
	DCB DHCSR: Retire sticky status Position.
#define	DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
	DCB DHCSR: Retire sticky status Mask.
#define	DCB_DHCSR_S_SDE_Pos 20U
	DCB DHCSR: Secure debug enabled Position.
#define	DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)
	DCB DHCSR: Secure debug enabled Mask.
#define	DCB_DHCSR_S_LOCKUP_Pos 19U
	DCB DHCSR: Lockup status Position.
#define	DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
	DCB DHCSR: Lockup status Mask.
#define	DCB_DHCSR_S_SLEEP_Pos 18U
	DCB DHCSR: Sleeping status Position.
#define	DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
	DCB DHCSR: Sleeping status Mask.
#define	DCB_DHCSR_S_HALT_Pos 17U
	DCB DHCSR: Halted status Position.
#define	DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)
	DCB DHCSR: Halted status Mask.
#define	DCB_DHCSR_S_REGRDY_Pos 16U
	DCB DHCSR: Register ready status Position.
#define	DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
	DCB DHCSR: Register ready status Mask.
#define	DCB_DHCSR_C_SNAPSTALL_Pos 5U
	DCB DHCSR: Snap stall control Position.
#define	DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
	DCB DHCSR: Snap stall control Mask.
#define	DCB_DHCSR_C_MASKINTS_Pos 3U
	DCB DHCSR: Mask interrupts control Position.
#define	DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
	DCB DHCSR: Mask interrupts control Mask.
#define	DCB_DHCSR_C_STEP_Pos 2U
	DCB DHCSR: Step control Position.
#define	DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)
	DCB DHCSR: Step control Mask.
#define	DCB_DHCSR_C_HALT_Pos 1U
	DCB DHCSR: Halt control Position.
#define	DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)
	DCB DHCSR: Halt control Mask.
#define	DCB_DHCSR_C_DEBUGEN_Pos 0U
	DCB DHCSR: Debug enable control Position.
#define	DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /<< DCB_DHCSR_C_DEBUGEN_Pos/)
	DCB DHCSR: Debug enable control Mask.
#define	DCB_DCRSR_REGWnR_Pos 16U
	DCB DCRSR: Register write/not-read Position.
#define	DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)
	DCB DCRSR: Register write/not-read Mask.
#define	DCB_DCRSR_REGSEL_Pos 0U
	DCB DCRSR: Register selector Position.
#define	DCB_DCRSR_REGSEL_Msk (0x7FUL /<< DCB_DCRSR_REGSEL_Pos/)
	DCB DCRSR: Register selector Mask.
#define	DCB_DCRDR_DBGTMP_Pos 0U
	DCB DCRDR: Data temporary buffer Position.
#define	DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /<< DCB_DCRDR_DBGTMP_Pos/)
	DCB DCRDR: Data temporary buffer Mask.
#define	DCB_DEMCR_TRCENA_Pos 24U
	DCB DEMCR: Trace enable Position.
#define	DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)
	DCB DEMCR: Trace enable Mask.
#define	DCB_DEMCR_MONPRKEY_Pos 23U
	DCB DEMCR: Monitor pend req key Position.
#define	DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
	DCB DEMCR: Monitor pend req key Mask.
#define	DCB_DEMCR_UMON_EN_Pos 21U
	DCB DEMCR: Unprivileged monitor enable Position.
#define	DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos)
	DCB DEMCR: Unprivileged monitor enable Mask.
#define	DCB_DEMCR_SDME_Pos 20U
	DCB DEMCR: Secure DebugMonitor enable Position.
#define	DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos)
	DCB DEMCR: Secure DebugMonitor enable Mask.
#define	DCB_DEMCR_MON_REQ_Pos 19U
	DCB DEMCR: Monitor request Position.
#define	DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos)
	DCB DEMCR: Monitor request Mask.
#define	DCB_DEMCR_MON_STEP_Pos 18U
	DCB DEMCR: Monitor step Position.
#define	DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos)
	DCB DEMCR: Monitor step Mask.
#define	DCB_DEMCR_MON_PEND_Pos 17U
	DCB DEMCR: Monitor pend Position.
#define	DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos)
	DCB DEMCR: Monitor pend Mask.
#define	DCB_DEMCR_MON_EN_Pos 16U
	DCB DEMCR: Monitor enable Position.
#define	DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos)
	DCB DEMCR: Monitor enable Mask.
#define	DCB_DEMCR_VC_SFERR_Pos 11U
	DCB DEMCR: Vector Catch SecureFault Position.
#define	DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
	DCB DEMCR: Vector Catch SecureFault Mask.
#define	DCB_DEMCR_VC_HARDERR_Pos 10U
	DCB DEMCR: Vector Catch HardFault errors Position.
#define	DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
	DCB DEMCR: Vector Catch HardFault errors Mask.
#define	DCB_DEMCR_VC_INTERR_Pos 9U
	DCB DEMCR: Vector Catch interrupt errors Position.
#define	DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
	DCB DEMCR: Vector Catch interrupt errors Mask.
#define	DCB_DEMCR_VC_BUSERR_Pos 8U
	DCB DEMCR: Vector Catch BusFault errors Position.
#define	DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
	DCB DEMCR: Vector Catch BusFault errors Mask.
#define	DCB_DEMCR_VC_STATERR_Pos 7U
	DCB DEMCR: Vector Catch state errors Position.
#define	DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
	DCB DEMCR: Vector Catch state errors Mask.
#define	DCB_DEMCR_VC_CHKERR_Pos 6U
	DCB DEMCR: Vector Catch check errors Position.
#define	DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
	DCB DEMCR: Vector Catch check errors Mask.
#define	DCB_DEMCR_VC_NOCPERR_Pos 5U
	DCB DEMCR: Vector Catch NOCP errors Position.
#define	DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
	DCB DEMCR: Vector Catch NOCP errors Mask.
#define	DCB_DEMCR_VC_MMERR_Pos 4U
	DCB DEMCR: Vector Catch MemManage errors Position.
#define	DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
	DCB DEMCR: Vector Catch MemManage errors Mask.
#define	DCB_DEMCR_VC_CORERESET_Pos 0U
	DCB DEMCR: Vector Catch Core reset Position.
#define	DCB_DEMCR_VC_CORERESET_Msk (0x1UL /<< DCB_DEMCR_VC_CORERESET_Pos/)
	DCB DEMCR: Vector Catch Core reset Mask.
#define	DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U
	DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position.
#define	DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
	DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask.
#define	DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U
	DCB DAUTHCTRL: Secure non-invasive debug enable select Position.
#define	DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
	DCB DAUTHCTRL: Secure non-invasive debug enable select Mask.
#define	DCB_DAUTHCTRL_INTSPIDEN_Pos 1U
	DCB DAUTHCTRL: Internal Secure invasive debug enable Position.
#define	DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
	DCB DAUTHCTRL: Internal Secure invasive debug enable Mask.
#define	DCB_DAUTHCTRL_SPIDENSEL_Pos 0U
	DCB DAUTHCTRL: Secure invasive debug enable select Position.
#define	DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /<< DCB_DAUTHCTRL_SPIDENSEL_Pos/)
	DCB DAUTHCTRL: Secure invasive debug enable select Mask.
#define	DCB_DSCSR_CDSKEY_Pos 17U
	DCB DSCSR: CDS write-enable key Position.
#define	DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)
	DCB DSCSR: CDS write-enable key Mask.
#define	DCB_DSCSR_CDS_Pos 16U
	DCB DSCSR: Current domain Secure Position.
#define	DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)
	DCB DSCSR: Current domain Secure Mask.
#define	DCB_DSCSR_SBRSEL_Pos 1U
	DCB DSCSR: Secure banked register select Position.
#define	DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)
	DCB DSCSR: Secure banked register select Mask.
#define	DCB_DSCSR_SBRSELEN_Pos 0U
	DCB DSCSR: Secure banked register select enable Position.
#define	DCB_DSCSR_SBRSELEN_Msk (0x1UL /<< DCB_DSCSR_SBRSELEN_Pos/)
	DCB DSCSR: Secure banked register select enable Mask.
#define	DCB_DHCSR_DBGKEY_Pos 16U
	DCB DHCSR: Debug key Position.
#define	DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)
	DCB DHCSR: Debug key Mask.
#define	DCB_DHCSR_S_RESTART_ST_Pos 26U
	DCB DHCSR: Restart sticky status Position.
#define	DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)
	DCB DHCSR: Restart sticky status Mask.
#define	DCB_DHCSR_S_RESET_ST_Pos 25U
	DCB DHCSR: Reset sticky status Position.
#define	DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)
	DCB DHCSR: Reset sticky status Mask.
#define	DCB_DHCSR_S_RETIRE_ST_Pos 24U
	DCB DHCSR: Retire sticky status Position.
#define	DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)
	DCB DHCSR: Retire sticky status Mask.
#define	DCB_DHCSR_S_SDE_Pos 20U
	DCB DHCSR: Secure debug enabled Position.
#define	DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos)
	DCB DHCSR: Secure debug enabled Mask.
#define	DCB_DHCSR_S_LOCKUP_Pos 19U
	DCB DHCSR: Lockup status Position.
#define	DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)
	DCB DHCSR: Lockup status Mask.
#define	DCB_DHCSR_S_SLEEP_Pos 18U
	DCB DHCSR: Sleeping status Position.
#define	DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos)
	DCB DHCSR: Sleeping status Mask.
#define	DCB_DHCSR_S_HALT_Pos 17U
	DCB DHCSR: Halted status Position.
#define	DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos)
	DCB DHCSR: Halted status Mask.
#define	DCB_DHCSR_S_REGRDY_Pos 16U
	DCB DHCSR: Register ready status Position.
#define	DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos)
	DCB DHCSR: Register ready status Mask.
#define	DCB_DHCSR_C_SNAPSTALL_Pos 5U
	DCB DHCSR: Snap stall control Position.
#define	DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)
	DCB DHCSR: Snap stall control Mask.
#define	DCB_DHCSR_C_MASKINTS_Pos 3U
	DCB DHCSR: Mask interrupts control Position.
#define	DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)
	DCB DHCSR: Mask interrupts control Mask.
#define	DCB_DHCSR_C_STEP_Pos 2U
	DCB DHCSR: Step control Position.
#define	DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos)
	DCB DHCSR: Step control Mask.
#define	DCB_DHCSR_C_HALT_Pos 1U
	DCB DHCSR: Halt control Position.
#define	DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos)
	DCB DHCSR: Halt control Mask.
#define	DCB_DHCSR_C_DEBUGEN_Pos 0U
	DCB DHCSR: Debug enable control Position.
#define	DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /<< DCB_DHCSR_C_DEBUGEN_Pos/)
	DCB DHCSR: Debug enable control Mask.
#define	DCB_DCRSR_REGWnR_Pos 16U
	DCB DCRSR: Register write/not-read Position.
#define	DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos)
	DCB DCRSR: Register write/not-read Mask.
#define	DCB_DCRSR_REGSEL_Pos 0U
	DCB DCRSR: Register selector Position.
#define	DCB_DCRSR_REGSEL_Msk (0x7FUL /<< DCB_DCRSR_REGSEL_Pos/)
	DCB DCRSR: Register selector Mask.
#define	DCB_DCRDR_DBGTMP_Pos 0U
	DCB DCRDR: Data temporary buffer Position.
#define	DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /<< DCB_DCRDR_DBGTMP_Pos/)
	DCB DCRDR: Data temporary buffer Mask.
#define	DCB_DEMCR_TRCENA_Pos 24U
	DCB DEMCR: Trace enable Position.
#define	DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos)
	DCB DEMCR: Trace enable Mask.
#define	DCB_DEMCR_MONPRKEY_Pos 23U
	DCB DEMCR: Monitor pend req key Position.
#define	DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos)
	DCB DEMCR: Monitor pend req key Mask.
#define	DCB_DEMCR_UMON_EN_Pos 21U
	DCB DEMCR: Unprivileged monitor enable Position.
#define	DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos)
	DCB DEMCR: Unprivileged monitor enable Mask.
#define	DCB_DEMCR_SDME_Pos 20U
	DCB DEMCR: Secure DebugMonitor enable Position.
#define	DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos)
	DCB DEMCR: Secure DebugMonitor enable Mask.
#define	DCB_DEMCR_MON_REQ_Pos 19U
	DCB DEMCR: Monitor request Position.
#define	DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos)
	DCB DEMCR: Monitor request Mask.
#define	DCB_DEMCR_MON_STEP_Pos 18U
	DCB DEMCR: Monitor step Position.
#define	DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos)
	DCB DEMCR: Monitor step Mask.
#define	DCB_DEMCR_MON_PEND_Pos 17U
	DCB DEMCR: Monitor pend Position.
#define	DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos)
	DCB DEMCR: Monitor pend Mask.
#define	DCB_DEMCR_MON_EN_Pos 16U
	DCB DEMCR: Monitor enable Position.
#define	DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos)
	DCB DEMCR: Monitor enable Mask.
#define	DCB_DEMCR_VC_SFERR_Pos 11U
	DCB DEMCR: Vector Catch SecureFault Position.
#define	DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos)
	DCB DEMCR: Vector Catch SecureFault Mask.
#define	DCB_DEMCR_VC_HARDERR_Pos 10U
	DCB DEMCR: Vector Catch HardFault errors Position.
#define	DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)
	DCB DEMCR: Vector Catch HardFault errors Mask.
#define	DCB_DEMCR_VC_INTERR_Pos 9U
	DCB DEMCR: Vector Catch interrupt errors Position.
#define	DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos)
	DCB DEMCR: Vector Catch interrupt errors Mask.
#define	DCB_DEMCR_VC_BUSERR_Pos 8U
	DCB DEMCR: Vector Catch BusFault errors Position.
#define	DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)
	DCB DEMCR: Vector Catch BusFault errors Mask.
#define	DCB_DEMCR_VC_STATERR_Pos 7U
	DCB DEMCR: Vector Catch state errors Position.
#define	DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos)
	DCB DEMCR: Vector Catch state errors Mask.
#define	DCB_DEMCR_VC_CHKERR_Pos 6U
	DCB DEMCR: Vector Catch check errors Position.
#define	DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)
	DCB DEMCR: Vector Catch check errors Mask.
#define	DCB_DEMCR_VC_NOCPERR_Pos 5U
	DCB DEMCR: Vector Catch NOCP errors Position.
#define	DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)
	DCB DEMCR: Vector Catch NOCP errors Mask.
#define	DCB_DEMCR_VC_MMERR_Pos 4U
	DCB DEMCR: Vector Catch MemManage errors Position.
#define	DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos)
	DCB DEMCR: Vector Catch MemManage errors Mask.
#define	DCB_DEMCR_VC_CORERESET_Pos 0U
	DCB DEMCR: Vector Catch Core reset Position.
#define	DCB_DEMCR_VC_CORERESET_Msk (0x1UL /<< DCB_DEMCR_VC_CORERESET_Pos/)
	DCB DEMCR: Vector Catch Core reset Mask.
#define	DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U
	DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position.
#define	DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)
	DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask.
#define	DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U
	DCB DAUTHCTRL: Secure non-invasive debug enable select Position.
#define	DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)
	DCB DAUTHCTRL: Secure non-invasive debug enable select Mask.
#define	DCB_DAUTHCTRL_INTSPIDEN_Pos 1U
	DCB DAUTHCTRL: Internal Secure invasive debug enable Position.
#define	DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)
	DCB DAUTHCTRL: Internal Secure invasive debug enable Mask.
#define	DCB_DAUTHCTRL_SPIDENSEL_Pos 0U
	DCB DAUTHCTRL: Secure invasive debug enable select Position.
#define	DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /<< DCB_DAUTHCTRL_SPIDENSEL_Pos/)
	DCB DAUTHCTRL: Secure invasive debug enable select Mask.
#define	DCB_DSCSR_CDSKEY_Pos 17U
	DCB DSCSR: CDS write-enable key Position.
#define	DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos)
	DCB DSCSR: CDS write-enable key Mask.
#define	DCB_DSCSR_CDS_Pos 16U
	DCB DSCSR: Current domain Secure Position.
#define	DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos)
	DCB DSCSR: Current domain Secure Mask.
#define	DCB_DSCSR_SBRSEL_Pos 1U
	DCB DSCSR: Secure banked register select Position.
#define	DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos)
	DCB DSCSR: Secure banked register select Mask.
#define	DCB_DSCSR_SBRSELEN_Pos 0U
	DCB DSCSR: Secure banked register select enable Position.
#define	DCB_DSCSR_SBRSELEN_Msk (0x1UL /<< DCB_DSCSR_SBRSELEN_Pos/)
	DCB DSCSR: Secure banked register select enable Mask.
#define	DCB_DHCSR_S_FPD_Pos 23U
	DCB DHCSR: Floating-point registers Debuggable Position.
#define	DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos)
	DCB DHCSR: Floating-point registers Debuggable Mask.
#define	DCB_DHCSR_S_SUIDE_Pos 22U
	DCB DHCSR: Secure unprivileged halting debug enabled Position.
#define	DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos)
	DCB DHCSR: Secure unprivileged halting debug enabled Mask.
#define	DCB_DHCSR_S_NSUIDE_Pos 21U
	DCB DHCSR: Non-secure unprivileged halting debug enabled Position.
#define	DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)
	DCB DHCSR: Non-secure unprivileged halting debug enabled Mask.
#define	DCB_DHCSR_C_PMOV_Pos 6U
	DCB DHCSR: Halt on PMU overflow control Position.
#define	DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos)
	DCB DHCSR: Halt on PMU overflow control Mask.
#define	DCB_DSCEMCR_CLR_MON_REQ_Pos 19U
	DCB DSCEMCR: Clear monitor request Position.
#define	DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)
	DCB DSCEMCR: Clear monitor request Mask.
#define	DCB_DSCEMCR_CLR_MON_PEND_Pos 17U
	DCB DSCEMCR: Clear monitor pend Position.
#define	DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)
	DCB DSCEMCR: Clear monitor pend Mask.
#define	DCB_DSCEMCR_SET_MON_REQ_Pos 3U
	DCB DSCEMCR: Set monitor request Position.
#define	DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)
	DCB DSCEMCR: Set monitor request Mask.
#define	DCB_DSCEMCR_SET_MON_PEND_Pos 1U
	DCB DSCEMCR: Set monitor pend Position.
#define	DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)
	DCB DSCEMCR: Set monitor pend Mask.
#define	DCB_DAUTHCTRL_UIDEN_Pos 10U
	DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position.
#define	DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)
	DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask.
#define	DCB_DAUTHCTRL_UIDAPEN_Pos 9U
	DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position.
#define	DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)
	DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask.
#define	DCB_DAUTHCTRL_FSDMA_Pos 8U
	DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position.
#define	DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)
	DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask.
#define	DCB_DHCSR_S_FPD_Pos 23U
	DCB DHCSR: Floating-point registers Debuggable Position.
#define	DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos)
	DCB DHCSR: Floating-point registers Debuggable Mask.
#define	DCB_DHCSR_S_SUIDE_Pos 22U
	DCB DHCSR: Secure unprivileged halting debug enabled Position.
#define	DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos)
	DCB DHCSR: Secure unprivileged halting debug enabled Mask.
#define	DCB_DHCSR_S_NSUIDE_Pos 21U
	DCB DHCSR: Non-secure unprivileged halting debug enabled Position.
#define	DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)
	DCB DHCSR: Non-secure unprivileged halting debug enabled Mask.
#define	DCB_DHCSR_C_PMOV_Pos 6U
	DCB DHCSR: Halt on PMU overflow control Position.
#define	DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos)
	DCB DHCSR: Halt on PMU overflow control Mask.
#define	DCB_DSCEMCR_CLR_MON_REQ_Pos 19U
	DCB DSCEMCR: Clear monitor request Position.
#define	DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)
	DCB DSCEMCR: Clear monitor request Mask.
#define	DCB_DSCEMCR_CLR_MON_PEND_Pos 17U
	DCB DSCEMCR: Clear monitor pend Position.
#define	DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)
	DCB DSCEMCR: Clear monitor pend Mask.
#define	DCB_DSCEMCR_SET_MON_REQ_Pos 3U
	DCB DSCEMCR: Set monitor request Position.
#define	DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)
	DCB DSCEMCR: Set monitor request Mask.
#define	DCB_DSCEMCR_SET_MON_PEND_Pos 1U
	DCB DSCEMCR: Set monitor pend Position.
#define	DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)
	DCB DSCEMCR: Set monitor pend Mask.
#define	DCB_DAUTHCTRL_UIDEN_Pos 10U
	DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position.
#define	DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)
	DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask.
#define	DCB_DAUTHCTRL_UIDAPEN_Pos 9U
	DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position.
#define	DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)
	DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask.
#define	DCB_DAUTHCTRL_FSDMA_Pos 8U
	DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position.
#define	DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)
	DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask.
#define	DCB_DHCSR_S_FPD_Pos 23U
	DCB DHCSR: Floating-point registers Debuggable Position.
#define	DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos)
	DCB DHCSR: Floating-point registers Debuggable Mask.
#define	DCB_DHCSR_S_SUIDE_Pos 22U
	DCB DHCSR: Secure unprivileged halting debug enabled Position.
#define	DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos)
	DCB DHCSR: Secure unprivileged halting debug enabled Mask.
#define	DCB_DHCSR_S_NSUIDE_Pos 21U
	DCB DHCSR: Non-secure unprivileged halting debug enabled Position.
#define	DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)
	DCB DHCSR: Non-secure unprivileged halting debug enabled Mask.
#define	DCB_DHCSR_C_PMOV_Pos 6U
	DCB DHCSR: Halt on PMU overflow control Position.
#define	DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos)
	DCB DHCSR: Halt on PMU overflow control Mask.
#define	DCB_DSCEMCR_CLR_MON_REQ_Pos 19U
	DCB DSCEMCR: Clear monitor request Position.
#define	DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)
	DCB DSCEMCR: Clear monitor request Mask.
#define	DCB_DSCEMCR_CLR_MON_PEND_Pos 17U
	DCB DSCEMCR: Clear monitor pend Position.
#define	DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)
	DCB DSCEMCR: Clear monitor pend Mask.
#define	DCB_DSCEMCR_SET_MON_REQ_Pos 3U
	DCB DSCEMCR: Set monitor request Position.
#define	DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)
	DCB DSCEMCR: Set monitor request Mask.
#define	DCB_DSCEMCR_SET_MON_PEND_Pos 1U
	DCB DSCEMCR: Set monitor pend Position.
#define	DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)
	DCB DSCEMCR: Set monitor pend Mask.
#define	DCB_DAUTHCTRL_UIDEN_Pos 10U
	DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position.
#define	DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)
	DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask.
#define	DCB_DAUTHCTRL_UIDAPEN_Pos 9U
	DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position.
#define	DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)
	DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask.
#define	DCB_DAUTHCTRL_FSDMA_Pos 8U
	DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position.
#define	DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)
	DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask.

Detailed Description

Type definitions for the Debug Control Block Registers.

Macro Definition Documentation

◆ DCB_DAUTHCTRL_FSDMA_Msk [1/3]

#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask.

Definition at line 2944 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_FSDMA_Msk [2/3]

#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask.

Definition at line 3440 of file core_cm55.h.

◆ DCB_DAUTHCTRL_FSDMA_Msk [3/3]

#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask.

Definition at line 3345 of file core_cm85.h.

◆ DCB_DAUTHCTRL_FSDMA_Pos [1/3]

#define DCB_DAUTHCTRL_FSDMA_Pos 8U

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position.

Definition at line 2943 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_FSDMA_Pos [2/3]

#define DCB_DAUTHCTRL_FSDMA_Pos 8U

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position.

Definition at line 3439 of file core_cm55.h.

◆ DCB_DAUTHCTRL_FSDMA_Pos [3/3]

#define DCB_DAUTHCTRL_FSDMA_Pos 8U

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position.

Definition at line 3344 of file core_cm85.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Msk [1/9]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask.

Definition at line 2953 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Msk [2/9]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask.

Definition at line 1172 of file core_armv8mbl.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Msk [3/9]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask.

Definition at line 1995 of file core_armv8mml.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Msk [4/9]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask.

Definition at line 1247 of file core_cm23.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Msk [5/9]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask.

Definition at line 2070 of file core_cm33.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Msk [6/9]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask.

Definition at line 2070 of file core_cm35p.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Msk [7/9]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask.

Definition at line 3449 of file core_cm55.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Msk [8/9]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask.

Definition at line 3354 of file core_cm85.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Msk [9/9]

#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)

DCB DAUTHCTRL: Internal Secure invasive debug enable Mask.

Definition at line 1997 of file core_starmc1.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Pos [1/9]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position.

Definition at line 2952 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Pos [2/9]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position.

Definition at line 1171 of file core_armv8mbl.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Pos [3/9]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position.

Definition at line 1994 of file core_armv8mml.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Pos [4/9]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position.

Definition at line 1246 of file core_cm23.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Pos [5/9]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position.

Definition at line 2069 of file core_cm33.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Pos [6/9]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position.

Definition at line 2069 of file core_cm35p.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Pos [7/9]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position.

Definition at line 3448 of file core_cm55.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Pos [8/9]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position.

Definition at line 3353 of file core_cm85.h.

◆ DCB_DAUTHCTRL_INTSPIDEN_Pos [9/9]

#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U

DCB DAUTHCTRL: Internal Secure invasive debug enable Position.

Definition at line 1996 of file core_starmc1.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Msk [1/9]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask.

Definition at line 2947 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Msk [2/9]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask.

Definition at line 1166 of file core_armv8mbl.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Msk [3/9]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask.

Definition at line 1989 of file core_armv8mml.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Msk [4/9]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask.

Definition at line 1241 of file core_cm23.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Msk [5/9]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask.

Definition at line 2064 of file core_cm33.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Msk [6/9]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask.

Definition at line 2064 of file core_cm35p.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Msk [7/9]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask.

Definition at line 3443 of file core_cm55.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Msk [8/9]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask.

Definition at line 3348 of file core_cm85.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Msk [9/9]

#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask.

Definition at line 1991 of file core_starmc1.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Pos [1/9]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position.

Definition at line 2946 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Pos [2/9]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position.

Definition at line 1165 of file core_armv8mbl.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Pos [3/9]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position.

Definition at line 1988 of file core_armv8mml.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Pos [4/9]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position.

Definition at line 1240 of file core_cm23.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Pos [5/9]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position.

Definition at line 2063 of file core_cm33.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Pos [6/9]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position.

Definition at line 2063 of file core_cm35p.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Pos [7/9]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position.

Definition at line 3442 of file core_cm55.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Pos [8/9]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position.

Definition at line 3347 of file core_cm85.h.

◆ DCB_DAUTHCTRL_INTSPNIDEN_Pos [9/9]

#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U

DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position.

Definition at line 1990 of file core_starmc1.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Msk [1/9]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask.

Definition at line 2956 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Msk [2/9]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask.

Definition at line 1175 of file core_armv8mbl.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Msk [3/9]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask.

Definition at line 1998 of file core_armv8mml.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Msk [4/9]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask.

Definition at line 1250 of file core_cm23.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Msk [5/9]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask.

Definition at line 2073 of file core_cm33.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Msk [6/9]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask.

Definition at line 2073 of file core_cm35p.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Msk [7/9]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask.

Definition at line 3452 of file core_cm55.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Msk [8/9]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask.

Definition at line 3357 of file core_cm85.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Msk [9/9]

#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)

DCB DAUTHCTRL: Secure invasive debug enable select Mask.

Definition at line 2000 of file core_starmc1.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Pos [1/9]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U

DCB DAUTHCTRL: Secure invasive debug enable select Position.

Definition at line 2955 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Pos [2/9]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U

DCB DAUTHCTRL: Secure invasive debug enable select Position.

Definition at line 1174 of file core_armv8mbl.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Pos [3/9]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U

DCB DAUTHCTRL: Secure invasive debug enable select Position.

Definition at line 1997 of file core_armv8mml.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Pos [4/9]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U

DCB DAUTHCTRL: Secure invasive debug enable select Position.

Definition at line 1249 of file core_cm23.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Pos [5/9]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U

DCB DAUTHCTRL: Secure invasive debug enable select Position.

Definition at line 2072 of file core_cm33.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Pos [6/9]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U

DCB DAUTHCTRL: Secure invasive debug enable select Position.

Definition at line 2072 of file core_cm35p.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Pos [7/9]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U

DCB DAUTHCTRL: Secure invasive debug enable select Position.

Definition at line 3451 of file core_cm55.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Pos [8/9]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U

DCB DAUTHCTRL: Secure invasive debug enable select Position.

Definition at line 3356 of file core_cm85.h.

◆ DCB_DAUTHCTRL_SPIDENSEL_Pos [9/9]

#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U

DCB DAUTHCTRL: Secure invasive debug enable select Position.

Definition at line 1999 of file core_starmc1.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Msk [1/9]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask.

Definition at line 2950 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Msk [2/9]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask.

Definition at line 1169 of file core_armv8mbl.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Msk [3/9]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask.

Definition at line 1992 of file core_armv8mml.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Msk [4/9]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask.

Definition at line 1244 of file core_cm23.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Msk [5/9]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask.

Definition at line 2067 of file core_cm33.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Msk [6/9]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask.

Definition at line 2067 of file core_cm35p.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Msk [7/9]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask.

Definition at line 3446 of file core_cm55.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Msk [8/9]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask.

Definition at line 3351 of file core_cm85.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Msk [9/9]

#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)

DCB DAUTHCTRL: Secure non-invasive debug enable select Mask.

Definition at line 1994 of file core_starmc1.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Pos [1/9]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position.

Definition at line 2949 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Pos [2/9]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position.

Definition at line 1168 of file core_armv8mbl.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Pos [3/9]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position.

Definition at line 1991 of file core_armv8mml.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Pos [4/9]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position.

Definition at line 1243 of file core_cm23.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Pos [5/9]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position.

Definition at line 2066 of file core_cm33.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Pos [6/9]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position.

Definition at line 2066 of file core_cm35p.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Pos [7/9]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position.

Definition at line 3445 of file core_cm55.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Pos [8/9]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position.

Definition at line 3350 of file core_cm85.h.

◆ DCB_DAUTHCTRL_SPNIDENSEL_Pos [9/9]

#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U

DCB DAUTHCTRL: Secure non-invasive debug enable select Position.

Definition at line 1993 of file core_starmc1.h.

◆ DCB_DAUTHCTRL_UIDAPEN_Msk [1/3]

#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask.

Definition at line 2941 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_UIDAPEN_Msk [2/3]

#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask.

Definition at line 3437 of file core_cm55.h.

◆ DCB_DAUTHCTRL_UIDAPEN_Msk [3/3]

#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask.

Definition at line 3342 of file core_cm85.h.

◆ DCB_DAUTHCTRL_UIDAPEN_Pos [1/3]

#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position.

Definition at line 2940 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_UIDAPEN_Pos [2/3]

#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position.

Definition at line 3436 of file core_cm55.h.

◆ DCB_DAUTHCTRL_UIDAPEN_Pos [3/3]

#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position.

Definition at line 3341 of file core_cm85.h.

◆ DCB_DAUTHCTRL_UIDEN_Msk [1/3]

#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask.

Definition at line 2938 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_UIDEN_Msk [2/3]

#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask.

Definition at line 3434 of file core_cm55.h.

◆ DCB_DAUTHCTRL_UIDEN_Msk [3/3]

#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask.

Definition at line 3339 of file core_cm85.h.

◆ DCB_DAUTHCTRL_UIDEN_Pos [1/3]

#define DCB_DAUTHCTRL_UIDEN_Pos 10U

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position.

Definition at line 2937 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_UIDEN_Pos [2/3]

#define DCB_DAUTHCTRL_UIDEN_Pos 10U

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position.

Definition at line 3433 of file core_cm55.h.

◆ DCB_DAUTHCTRL_UIDEN_Pos [3/3]

#define DCB_DAUTHCTRL_UIDEN_Pos 10U

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position.

Definition at line 3338 of file core_cm85.h.