Type definitions for the Memory Protection Unit (MPU). More...

Collaboration diagram for Memory Protection Unit (MPU):

Topics
	Floating Point Unit (FPU)
	Type definitions for the Floating Point Unit (FPU).

Classes
struct	MPU_Type
	Structure type to access the Memory Protection Unit (MPU). More...
#define	MPU_TYPE_RALIASES 4U
#define	MPU_TYPE_IREGION_Pos 16U
	MPU TYPE: IREGION Position.
#define	MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
	MPU TYPE: IREGION Mask.
#define	MPU_TYPE_DREGION_Pos 8U
	MPU TYPE: DREGION Position.
#define	MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
	MPU TYPE: DREGION Mask.
#define	MPU_TYPE_SEPARATE_Pos 0U
	MPU TYPE: SEPARATE Position.
#define	MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/)
	MPU TYPE: SEPARATE Mask.
#define	MPU_CTRL_PRIVDEFENA_Pos 2U
	MPU CTRL: PRIVDEFENA Position.
#define	MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
	MPU CTRL: PRIVDEFENA Mask.
#define	MPU_CTRL_HFNMIENA_Pos 1U
	MPU CTRL: HFNMIENA Position.
#define	MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
	MPU CTRL: HFNMIENA Mask.
#define	MPU_CTRL_ENABLE_Pos 0U
	MPU CTRL: ENABLE Position.
#define	MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/)
	MPU CTRL: ENABLE Mask.
#define	MPU_RNR_REGION_Pos 0U
	MPU RNR: REGION Position.
#define	MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/)
	MPU RNR: REGION Mask.
#define	MPU_RBAR_BASE_Pos 5U
	MPU RBAR: BASE Position.
#define	MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
	MPU RBAR: BASE Mask.
#define	MPU_RBAR_SH_Pos 3U
	MPU RBAR: SH Position.
#define	MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
	MPU RBAR: SH Mask.
#define	MPU_RBAR_AP_Pos 1U
	MPU RBAR: AP Position.
#define	MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
	MPU RBAR: AP Mask.
#define	MPU_RBAR_XN_Pos 0U
	MPU RBAR: XN Position.
#define	MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/)
	MPU RBAR: XN Mask.
#define	MPU_RLAR_LIMIT_Pos 5U
	MPU RLAR: LIMIT Position.
#define	MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
	MPU RLAR: LIMIT Mask.
#define	MPU_RLAR_AttrIndx_Pos 1U
	MPU RLAR: AttrIndx Position.
#define	MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos)
	MPU RLAR: AttrIndx Mask.
#define	MPU_RLAR_EN_Pos 0U
	MPU RLAR: Region enable bit Position.
#define	MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/)
	MPU RLAR: Region enable bit Disable Mask.
#define	MPU_MAIR0_Attr3_Pos 24U
	MPU MAIR0: Attr3 Position.
#define	MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
	MPU MAIR0: Attr3 Mask.
#define	MPU_MAIR0_Attr2_Pos 16U
	MPU MAIR0: Attr2 Position.
#define	MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
	MPU MAIR0: Attr2 Mask.
#define	MPU_MAIR0_Attr1_Pos 8U
	MPU MAIR0: Attr1 Position.
#define	MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
	MPU MAIR0: Attr1 Mask.
#define	MPU_MAIR0_Attr0_Pos 0U
	MPU MAIR0: Attr0 Position.
#define	MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/)
	MPU MAIR0: Attr0 Mask.
#define	MPU_MAIR1_Attr7_Pos 24U
	MPU MAIR1: Attr7 Position.
#define	MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
	MPU MAIR1: Attr7 Mask.
#define	MPU_MAIR1_Attr6_Pos 16U
	MPU MAIR1: Attr6 Position.
#define	MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
	MPU MAIR1: Attr6 Mask.
#define	MPU_MAIR1_Attr5_Pos 8U
	MPU MAIR1: Attr5 Position.
#define	MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
	MPU MAIR1: Attr5 Mask.
#define	MPU_MAIR1_Attr4_Pos 0U
	MPU MAIR1: Attr4 Position.
#define	MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/)
	MPU MAIR1: Attr4 Mask.
#define	MPU_TYPE_RALIASES 1U
#define	MPU_TYPE_IREGION_Pos 16U
	MPU TYPE: IREGION Position.
#define	MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
	MPU TYPE: IREGION Mask.
#define	MPU_TYPE_DREGION_Pos 8U
	MPU TYPE: DREGION Position.
#define	MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
	MPU TYPE: DREGION Mask.
#define	MPU_TYPE_SEPARATE_Pos 0U
	MPU TYPE: SEPARATE Position.
#define	MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/)
	MPU TYPE: SEPARATE Mask.
#define	MPU_CTRL_PRIVDEFENA_Pos 2U
	MPU CTRL: PRIVDEFENA Position.
#define	MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
	MPU CTRL: PRIVDEFENA Mask.
#define	MPU_CTRL_HFNMIENA_Pos 1U
	MPU CTRL: HFNMIENA Position.
#define	MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
	MPU CTRL: HFNMIENA Mask.
#define	MPU_CTRL_ENABLE_Pos 0U
	MPU CTRL: ENABLE Position.
#define	MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/)
	MPU CTRL: ENABLE Mask.
#define	MPU_RNR_REGION_Pos 0U
	MPU RNR: REGION Position.
#define	MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/)
	MPU RNR: REGION Mask.
#define	MPU_RBAR_BASE_Pos 5U
	MPU RBAR: BASE Position.
#define	MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
	MPU RBAR: BASE Mask.
#define	MPU_RBAR_SH_Pos 3U
	MPU RBAR: SH Position.
#define	MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
	MPU RBAR: SH Mask.
#define	MPU_RBAR_AP_Pos 1U
	MPU RBAR: AP Position.
#define	MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
	MPU RBAR: AP Mask.
#define	MPU_RBAR_XN_Pos 0U
	MPU RBAR: XN Position.
#define	MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/)
	MPU RBAR: XN Mask.
#define	MPU_RLAR_LIMIT_Pos 5U
	MPU RLAR: LIMIT Position.
#define	MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
	MPU RLAR: LIMIT Mask.
#define	MPU_RLAR_AttrIndx_Pos 1U
	MPU RLAR: AttrIndx Position.
#define	MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
	MPU RLAR: AttrIndx Mask.
#define	MPU_RLAR_EN_Pos 0U
	MPU RLAR: EN Position.
#define	MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/)
	MPU RLAR: EN Mask.
#define	MPU_MAIR0_Attr3_Pos 24U
	MPU MAIR0: Attr3 Position.
#define	MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
	MPU MAIR0: Attr3 Mask.
#define	MPU_MAIR0_Attr2_Pos 16U
	MPU MAIR0: Attr2 Position.
#define	MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
	MPU MAIR0: Attr2 Mask.
#define	MPU_MAIR0_Attr1_Pos 8U
	MPU MAIR0: Attr1 Position.
#define	MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
	MPU MAIR0: Attr1 Mask.
#define	MPU_MAIR0_Attr0_Pos 0U
	MPU MAIR0: Attr0 Position.
#define	MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/)
	MPU MAIR0: Attr0 Mask.
#define	MPU_MAIR1_Attr7_Pos 24U
	MPU MAIR1: Attr7 Position.
#define	MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
	MPU MAIR1: Attr7 Mask.
#define	MPU_MAIR1_Attr6_Pos 16U
	MPU MAIR1: Attr6 Position.
#define	MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
	MPU MAIR1: Attr6 Mask.
#define	MPU_MAIR1_Attr5_Pos 8U
	MPU MAIR1: Attr5 Position.
#define	MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
	MPU MAIR1: Attr5 Mask.
#define	MPU_MAIR1_Attr4_Pos 0U
	MPU MAIR1: Attr4 Position.
#define	MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/)
	MPU MAIR1: Attr4 Mask.
#define	MPU_TYPE_RALIASES 4U
#define	MPU_TYPE_IREGION_Pos 16U
	MPU TYPE: IREGION Position.
#define	MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
	MPU TYPE: IREGION Mask.
#define	MPU_TYPE_DREGION_Pos 8U
	MPU TYPE: DREGION Position.
#define	MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
	MPU TYPE: DREGION Mask.
#define	MPU_TYPE_SEPARATE_Pos 0U
	MPU TYPE: SEPARATE Position.
#define	MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/)
	MPU TYPE: SEPARATE Mask.
#define	MPU_CTRL_PRIVDEFENA_Pos 2U
	MPU CTRL: PRIVDEFENA Position.
#define	MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
	MPU CTRL: PRIVDEFENA Mask.
#define	MPU_CTRL_HFNMIENA_Pos 1U
	MPU CTRL: HFNMIENA Position.
#define	MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
	MPU CTRL: HFNMIENA Mask.
#define	MPU_CTRL_ENABLE_Pos 0U
	MPU CTRL: ENABLE Position.
#define	MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/)
	MPU CTRL: ENABLE Mask.
#define	MPU_RNR_REGION_Pos 0U
	MPU RNR: REGION Position.
#define	MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/)
	MPU RNR: REGION Mask.
#define	MPU_RBAR_BASE_Pos 5U
	MPU RBAR: BASE Position.
#define	MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
	MPU RBAR: BASE Mask.
#define	MPU_RBAR_SH_Pos 3U
	MPU RBAR: SH Position.
#define	MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
	MPU RBAR: SH Mask.
#define	MPU_RBAR_AP_Pos 1U
	MPU RBAR: AP Position.
#define	MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
	MPU RBAR: AP Mask.
#define	MPU_RBAR_XN_Pos 0U
	MPU RBAR: XN Position.
#define	MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/)
	MPU RBAR: XN Mask.
#define	MPU_RLAR_LIMIT_Pos 5U
	MPU RLAR: LIMIT Position.
#define	MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
	MPU RLAR: LIMIT Mask.
#define	MPU_RLAR_AttrIndx_Pos 1U
	MPU RLAR: AttrIndx Position.
#define	MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
	MPU RLAR: AttrIndx Mask.
#define	MPU_RLAR_EN_Pos 0U
	MPU RLAR: Region enable bit Position.
#define	MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/)
	MPU RLAR: Region enable bit Disable Mask.
#define	MPU_MAIR0_Attr3_Pos 24U
	MPU MAIR0: Attr3 Position.
#define	MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
	MPU MAIR0: Attr3 Mask.
#define	MPU_MAIR0_Attr2_Pos 16U
	MPU MAIR0: Attr2 Position.
#define	MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
	MPU MAIR0: Attr2 Mask.
#define	MPU_MAIR0_Attr1_Pos 8U
	MPU MAIR0: Attr1 Position.
#define	MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
	MPU MAIR0: Attr1 Mask.
#define	MPU_MAIR0_Attr0_Pos 0U
	MPU MAIR0: Attr0 Position.
#define	MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/)
	MPU MAIR0: Attr0 Mask.
#define	MPU_MAIR1_Attr7_Pos 24U
	MPU MAIR1: Attr7 Position.
#define	MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
	MPU MAIR1: Attr7 Mask.
#define	MPU_MAIR1_Attr6_Pos 16U
	MPU MAIR1: Attr6 Position.
#define	MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
	MPU MAIR1: Attr6 Mask.
#define	MPU_MAIR1_Attr5_Pos 8U
	MPU MAIR1: Attr5 Position.
#define	MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
	MPU MAIR1: Attr5 Mask.
#define	MPU_MAIR1_Attr4_Pos 0U
	MPU MAIR1: Attr4 Position.
#define	MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/)
	MPU MAIR1: Attr4 Mask.
#define	MPU_TYPE_RALIASES 1U
#define	MPU_TYPE_IREGION_Pos 16U
	MPU TYPE: IREGION Position.
#define	MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
	MPU TYPE: IREGION Mask.
#define	MPU_TYPE_DREGION_Pos 8U
	MPU TYPE: DREGION Position.
#define	MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
	MPU TYPE: DREGION Mask.
#define	MPU_TYPE_SEPARATE_Pos 0U
	MPU TYPE: SEPARATE Position.
#define	MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/)
	MPU TYPE: SEPARATE Mask.
#define	MPU_CTRL_PRIVDEFENA_Pos 2U
	MPU CTRL: PRIVDEFENA Position.
#define	MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
	MPU CTRL: PRIVDEFENA Mask.
#define	MPU_CTRL_HFNMIENA_Pos 1U
	MPU CTRL: HFNMIENA Position.
#define	MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
	MPU CTRL: HFNMIENA Mask.
#define	MPU_CTRL_ENABLE_Pos 0U
	MPU CTRL: ENABLE Position.
#define	MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/)
	MPU CTRL: ENABLE Mask.
#define	MPU_RNR_REGION_Pos 0U
	MPU RNR: REGION Position.
#define	MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/)
	MPU RNR: REGION Mask.
#define	MPU_TYPE_RALIASES 1U
#define	MPU_TYPE_IREGION_Pos 16U
	MPU TYPE: IREGION Position.
#define	MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
	MPU TYPE: IREGION Mask.
#define	MPU_TYPE_DREGION_Pos 8U
	MPU TYPE: DREGION Position.
#define	MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
	MPU TYPE: DREGION Mask.
#define	MPU_TYPE_SEPARATE_Pos 0U
	MPU TYPE: SEPARATE Position.
#define	MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/)
	MPU TYPE: SEPARATE Mask.
#define	MPU_CTRL_PRIVDEFENA_Pos 2U
	MPU CTRL: PRIVDEFENA Position.
#define	MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
	MPU CTRL: PRIVDEFENA Mask.
#define	MPU_CTRL_HFNMIENA_Pos 1U
	MPU CTRL: HFNMIENA Position.
#define	MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
	MPU CTRL: HFNMIENA Mask.
#define	MPU_CTRL_ENABLE_Pos 0U
	MPU CTRL: ENABLE Position.
#define	MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/)
	MPU CTRL: ENABLE Mask.
#define	MPU_RNR_REGION_Pos 0U
	MPU RNR: REGION Position.
#define	MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/)
	MPU RNR: REGION Mask.
#define	MPU_RBAR_BASE_Pos 5U
	MPU RBAR: BASE Position.
#define	MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
	MPU RBAR: BASE Mask.
#define	MPU_RBAR_SH_Pos 3U
	MPU RBAR: SH Position.
#define	MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
	MPU RBAR: SH Mask.
#define	MPU_RBAR_AP_Pos 1U
	MPU RBAR: AP Position.
#define	MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
	MPU RBAR: AP Mask.
#define	MPU_RBAR_XN_Pos 0U
	MPU RBAR: XN Position.
#define	MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/)
	MPU RBAR: XN Mask.
#define	MPU_RLAR_LIMIT_Pos 5U
	MPU RLAR: LIMIT Position.
#define	MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
	MPU RLAR: LIMIT Mask.
#define	MPU_RLAR_AttrIndx_Pos 1U
	MPU RLAR: AttrIndx Position.
#define	MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
	MPU RLAR: AttrIndx Mask.
#define	MPU_RLAR_EN_Pos 0U
	MPU RLAR: EN Position.
#define	MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/)
	MPU RLAR: EN Mask.
#define	MPU_MAIR0_Attr3_Pos 24U
	MPU MAIR0: Attr3 Position.
#define	MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
	MPU MAIR0: Attr3 Mask.
#define	MPU_MAIR0_Attr2_Pos 16U
	MPU MAIR0: Attr2 Position.
#define	MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
	MPU MAIR0: Attr2 Mask.
#define	MPU_MAIR0_Attr1_Pos 8U
	MPU MAIR0: Attr1 Position.
#define	MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
	MPU MAIR0: Attr1 Mask.
#define	MPU_MAIR0_Attr0_Pos 0U
	MPU MAIR0: Attr0 Position.
#define	MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/)
	MPU MAIR0: Attr0 Mask.
#define	MPU_MAIR1_Attr7_Pos 24U
	MPU MAIR1: Attr7 Position.
#define	MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
	MPU MAIR1: Attr7 Mask.
#define	MPU_MAIR1_Attr6_Pos 16U
	MPU MAIR1: Attr6 Position.
#define	MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
	MPU MAIR1: Attr6 Mask.
#define	MPU_MAIR1_Attr5_Pos 8U
	MPU MAIR1: Attr5 Position.
#define	MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
	MPU MAIR1: Attr5 Mask.
#define	MPU_MAIR1_Attr4_Pos 0U
	MPU MAIR1: Attr4 Position.
#define	MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/)
	MPU MAIR1: Attr4 Mask.
#define	MPU_TYPE_RALIASES 4U
#define	MPU_TYPE_IREGION_Pos 16U
	MPU TYPE: IREGION Position.
#define	MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
	MPU TYPE: IREGION Mask.
#define	MPU_TYPE_DREGION_Pos 8U
	MPU TYPE: DREGION Position.
#define	MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
	MPU TYPE: DREGION Mask.
#define	MPU_TYPE_SEPARATE_Pos 0U
	MPU TYPE: SEPARATE Position.
#define	MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/)
	MPU TYPE: SEPARATE Mask.
#define	MPU_CTRL_PRIVDEFENA_Pos 2U
	MPU CTRL: PRIVDEFENA Position.
#define	MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
	MPU CTRL: PRIVDEFENA Mask.
#define	MPU_CTRL_HFNMIENA_Pos 1U
	MPU CTRL: HFNMIENA Position.
#define	MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
	MPU CTRL: HFNMIENA Mask.
#define	MPU_CTRL_ENABLE_Pos 0U
	MPU CTRL: ENABLE Position.
#define	MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/)
	MPU CTRL: ENABLE Mask.
#define	MPU_RNR_REGION_Pos 0U
	MPU RNR: REGION Position.
#define	MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/)
	MPU RNR: REGION Mask.
#define	MPU_TYPE_RALIASES 4U
#define	MPU_TYPE_IREGION_Pos 16U
	MPU TYPE: IREGION Position.
#define	MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
	MPU TYPE: IREGION Mask.
#define	MPU_TYPE_DREGION_Pos 8U
	MPU TYPE: DREGION Position.
#define	MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
	MPU TYPE: DREGION Mask.
#define	MPU_TYPE_SEPARATE_Pos 0U
	MPU TYPE: SEPARATE Position.
#define	MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/)
	MPU TYPE: SEPARATE Mask.
#define	MPU_CTRL_PRIVDEFENA_Pos 2U
	MPU CTRL: PRIVDEFENA Position.
#define	MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
	MPU CTRL: PRIVDEFENA Mask.
#define	MPU_CTRL_HFNMIENA_Pos 1U
	MPU CTRL: HFNMIENA Position.
#define	MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
	MPU CTRL: HFNMIENA Mask.
#define	MPU_CTRL_ENABLE_Pos 0U
	MPU CTRL: ENABLE Position.
#define	MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/)
	MPU CTRL: ENABLE Mask.
#define	MPU_RNR_REGION_Pos 0U
	MPU RNR: REGION Position.
#define	MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/)
	MPU RNR: REGION Mask.
#define	MPU_RBAR_BASE_Pos 5U
	MPU RBAR: BASE Position.
#define	MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
	MPU RBAR: BASE Mask.
#define	MPU_RBAR_SH_Pos 3U
	MPU RBAR: SH Position.
#define	MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
	MPU RBAR: SH Mask.
#define	MPU_RBAR_AP_Pos 1U
	MPU RBAR: AP Position.
#define	MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
	MPU RBAR: AP Mask.
#define	MPU_RBAR_XN_Pos 0U
	MPU RBAR: XN Position.
#define	MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/)
	MPU RBAR: XN Mask.
#define	MPU_RLAR_LIMIT_Pos 5U
	MPU RLAR: LIMIT Position.
#define	MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
	MPU RLAR: LIMIT Mask.
#define	MPU_RLAR_AttrIndx_Pos 1U
	MPU RLAR: AttrIndx Position.
#define	MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
	MPU RLAR: AttrIndx Mask.
#define	MPU_RLAR_EN_Pos 0U
	MPU RLAR: Region enable bit Position.
#define	MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/)
	MPU RLAR: Region enable bit Disable Mask.
#define	MPU_MAIR0_Attr3_Pos 24U
	MPU MAIR0: Attr3 Position.
#define	MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
	MPU MAIR0: Attr3 Mask.
#define	MPU_MAIR0_Attr2_Pos 16U
	MPU MAIR0: Attr2 Position.
#define	MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
	MPU MAIR0: Attr2 Mask.
#define	MPU_MAIR0_Attr1_Pos 8U
	MPU MAIR0: Attr1 Position.
#define	MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
	MPU MAIR0: Attr1 Mask.
#define	MPU_MAIR0_Attr0_Pos 0U
	MPU MAIR0: Attr0 Position.
#define	MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/)
	MPU MAIR0: Attr0 Mask.
#define	MPU_MAIR1_Attr7_Pos 24U
	MPU MAIR1: Attr7 Position.
#define	MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
	MPU MAIR1: Attr7 Mask.
#define	MPU_MAIR1_Attr6_Pos 16U
	MPU MAIR1: Attr6 Position.
#define	MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
	MPU MAIR1: Attr6 Mask.
#define	MPU_MAIR1_Attr5_Pos 8U
	MPU MAIR1: Attr5 Position.
#define	MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
	MPU MAIR1: Attr5 Mask.
#define	MPU_MAIR1_Attr4_Pos 0U
	MPU MAIR1: Attr4 Position.
#define	MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/)
	MPU MAIR1: Attr4 Mask.
#define	MPU_TYPE_RALIASES 4U
#define	MPU_TYPE_IREGION_Pos 16U
	MPU TYPE: IREGION Position.
#define	MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
	MPU TYPE: IREGION Mask.
#define	MPU_TYPE_DREGION_Pos 8U
	MPU TYPE: DREGION Position.
#define	MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
	MPU TYPE: DREGION Mask.
#define	MPU_TYPE_SEPARATE_Pos 0U
	MPU TYPE: SEPARATE Position.
#define	MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/)
	MPU TYPE: SEPARATE Mask.
#define	MPU_CTRL_PRIVDEFENA_Pos 2U
	MPU CTRL: PRIVDEFENA Position.
#define	MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
	MPU CTRL: PRIVDEFENA Mask.
#define	MPU_CTRL_HFNMIENA_Pos 1U
	MPU CTRL: HFNMIENA Position.
#define	MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
	MPU CTRL: HFNMIENA Mask.
#define	MPU_CTRL_ENABLE_Pos 0U
	MPU CTRL: ENABLE Position.
#define	MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/)
	MPU CTRL: ENABLE Mask.
#define	MPU_RNR_REGION_Pos 0U
	MPU RNR: REGION Position.
#define	MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/)
	MPU RNR: REGION Mask.
#define	MPU_RBAR_BASE_Pos 5U
	MPU RBAR: BASE Position.
#define	MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
	MPU RBAR: BASE Mask.
#define	MPU_RBAR_SH_Pos 3U
	MPU RBAR: SH Position.
#define	MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
	MPU RBAR: SH Mask.
#define	MPU_RBAR_AP_Pos 1U
	MPU RBAR: AP Position.
#define	MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
	MPU RBAR: AP Mask.
#define	MPU_RBAR_XN_Pos 0U
	MPU RBAR: XN Position.
#define	MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/)
	MPU RBAR: XN Mask.
#define	MPU_RLAR_LIMIT_Pos 5U
	MPU RLAR: LIMIT Position.
#define	MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
	MPU RLAR: LIMIT Mask.
#define	MPU_RLAR_AttrIndx_Pos 1U
	MPU RLAR: AttrIndx Position.
#define	MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
	MPU RLAR: AttrIndx Mask.
#define	MPU_RLAR_EN_Pos 0U
	MPU RLAR: Region enable bit Position.
#define	MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/)
	MPU RLAR: Region enable bit Disable Mask.
#define	MPU_MAIR0_Attr3_Pos 24U
	MPU MAIR0: Attr3 Position.
#define	MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
	MPU MAIR0: Attr3 Mask.
#define	MPU_MAIR0_Attr2_Pos 16U
	MPU MAIR0: Attr2 Position.
#define	MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
	MPU MAIR0: Attr2 Mask.
#define	MPU_MAIR0_Attr1_Pos 8U
	MPU MAIR0: Attr1 Position.
#define	MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
	MPU MAIR0: Attr1 Mask.
#define	MPU_MAIR0_Attr0_Pos 0U
	MPU MAIR0: Attr0 Position.
#define	MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/)
	MPU MAIR0: Attr0 Mask.
#define	MPU_MAIR1_Attr7_Pos 24U
	MPU MAIR1: Attr7 Position.
#define	MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
	MPU MAIR1: Attr7 Mask.
#define	MPU_MAIR1_Attr6_Pos 16U
	MPU MAIR1: Attr6 Position.
#define	MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
	MPU MAIR1: Attr6 Mask.
#define	MPU_MAIR1_Attr5_Pos 8U
	MPU MAIR1: Attr5 Position.
#define	MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
	MPU MAIR1: Attr5 Mask.
#define	MPU_MAIR1_Attr4_Pos 0U
	MPU MAIR1: Attr4 Position.
#define	MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/)
	MPU MAIR1: Attr4 Mask.
#define	MPU_TYPE_RALIASES 4U
#define	MPU_TYPE_IREGION_Pos 16U
	MPU TYPE: IREGION Position.
#define	MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
	MPU TYPE: IREGION Mask.
#define	MPU_TYPE_DREGION_Pos 8U
	MPU TYPE: DREGION Position.
#define	MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
	MPU TYPE: DREGION Mask.
#define	MPU_TYPE_SEPARATE_Pos 0U
	MPU TYPE: SEPARATE Position.
#define	MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/)
	MPU TYPE: SEPARATE Mask.
#define	MPU_CTRL_PRIVDEFENA_Pos 2U
	MPU CTRL: PRIVDEFENA Position.
#define	MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
	MPU CTRL: PRIVDEFENA Mask.
#define	MPU_CTRL_HFNMIENA_Pos 1U
	MPU CTRL: HFNMIENA Position.
#define	MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
	MPU CTRL: HFNMIENA Mask.
#define	MPU_CTRL_ENABLE_Pos 0U
	MPU CTRL: ENABLE Position.
#define	MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/)
	MPU CTRL: ENABLE Mask.
#define	MPU_RNR_REGION_Pos 0U
	MPU RNR: REGION Position.
#define	MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/)
	MPU RNR: REGION Mask.
#define	MPU_TYPE_RALIASES 4U
#define	MPU_TYPE_IREGION_Pos 16U
	MPU TYPE: IREGION Position.
#define	MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
	MPU TYPE: IREGION Mask.
#define	MPU_TYPE_DREGION_Pos 8U
	MPU TYPE: DREGION Position.
#define	MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
	MPU TYPE: DREGION Mask.
#define	MPU_TYPE_SEPARATE_Pos 0U
	MPU TYPE: SEPARATE Position.
#define	MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/)
	MPU TYPE: SEPARATE Mask.
#define	MPU_CTRL_PRIVDEFENA_Pos 2U
	MPU CTRL: PRIVDEFENA Position.
#define	MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
	MPU CTRL: PRIVDEFENA Mask.
#define	MPU_CTRL_HFNMIENA_Pos 1U
	MPU CTRL: HFNMIENA Position.
#define	MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
	MPU CTRL: HFNMIENA Mask.
#define	MPU_CTRL_ENABLE_Pos 0U
	MPU CTRL: ENABLE Position.
#define	MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/)
	MPU CTRL: ENABLE Mask.
#define	MPU_RNR_REGION_Pos 0U
	MPU RNR: REGION Position.
#define	MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/)
	MPU RNR: REGION Mask.
#define	MPU_RBAR_BASE_Pos 5U
	MPU RBAR: BASE Position.
#define	MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
	MPU RBAR: BASE Mask.
#define	MPU_RBAR_SH_Pos 3U
	MPU RBAR: SH Position.
#define	MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
	MPU RBAR: SH Mask.
#define	MPU_RBAR_AP_Pos 1U
	MPU RBAR: AP Position.
#define	MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
	MPU RBAR: AP Mask.
#define	MPU_RBAR_XN_Pos 0U
	MPU RBAR: XN Position.
#define	MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/)
	MPU RBAR: XN Mask.
#define	MPU_RLAR_LIMIT_Pos 5U
	MPU RLAR: LIMIT Position.
#define	MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
	MPU RLAR: LIMIT Mask.
#define	MPU_RLAR_AttrIndx_Pos 1U
	MPU RLAR: AttrIndx Position.
#define	MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos)
	MPU RLAR: AttrIndx Mask.
#define	MPU_RLAR_EN_Pos 0U
	MPU RLAR: Region enable bit Position.
#define	MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/)
	MPU RLAR: Region enable bit Disable Mask.
#define	MPU_MAIR0_Attr3_Pos 24U
	MPU MAIR0: Attr3 Position.
#define	MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
	MPU MAIR0: Attr3 Mask.
#define	MPU_MAIR0_Attr2_Pos 16U
	MPU MAIR0: Attr2 Position.
#define	MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
	MPU MAIR0: Attr2 Mask.
#define	MPU_MAIR0_Attr1_Pos 8U
	MPU MAIR0: Attr1 Position.
#define	MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
	MPU MAIR0: Attr1 Mask.
#define	MPU_MAIR0_Attr0_Pos 0U
	MPU MAIR0: Attr0 Position.
#define	MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/)
	MPU MAIR0: Attr0 Mask.
#define	MPU_MAIR1_Attr7_Pos 24U
	MPU MAIR1: Attr7 Position.
#define	MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
	MPU MAIR1: Attr7 Mask.
#define	MPU_MAIR1_Attr6_Pos 16U
	MPU MAIR1: Attr6 Position.
#define	MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
	MPU MAIR1: Attr6 Mask.
#define	MPU_MAIR1_Attr5_Pos 8U
	MPU MAIR1: Attr5 Position.
#define	MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
	MPU MAIR1: Attr5 Mask.
#define	MPU_MAIR1_Attr4_Pos 0U
	MPU MAIR1: Attr4 Position.
#define	MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/)
	MPU MAIR1: Attr4 Mask.
#define	MPU_TYPE_RALIASES 4U
#define	MPU_TYPE_IREGION_Pos 16U
	MPU TYPE: IREGION Position.
#define	MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
	MPU TYPE: IREGION Mask.
#define	MPU_TYPE_DREGION_Pos 8U
	MPU TYPE: DREGION Position.
#define	MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
	MPU TYPE: DREGION Mask.
#define	MPU_TYPE_SEPARATE_Pos 0U
	MPU TYPE: SEPARATE Position.
#define	MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/)
	MPU TYPE: SEPARATE Mask.
#define	MPU_CTRL_PRIVDEFENA_Pos 2U
	MPU CTRL: PRIVDEFENA Position.
#define	MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
	MPU CTRL: PRIVDEFENA Mask.
#define	MPU_CTRL_HFNMIENA_Pos 1U
	MPU CTRL: HFNMIENA Position.
#define	MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
	MPU CTRL: HFNMIENA Mask.
#define	MPU_CTRL_ENABLE_Pos 0U
	MPU CTRL: ENABLE Position.
#define	MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/)
	MPU CTRL: ENABLE Mask.
#define	MPU_RNR_REGION_Pos 0U
	MPU RNR: REGION Position.
#define	MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/)
	MPU RNR: REGION Mask.
#define	MPU_TYPE_RALIASES 4U
#define	MPU_TYPE_IREGION_Pos 16U
	MPU TYPE: IREGION Position.
#define	MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
	MPU TYPE: IREGION Mask.
#define	MPU_TYPE_DREGION_Pos 8U
	MPU TYPE: DREGION Position.
#define	MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
	MPU TYPE: DREGION Mask.
#define	MPU_TYPE_SEPARATE_Pos 0U
	MPU TYPE: SEPARATE Position.
#define	MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/)
	MPU TYPE: SEPARATE Mask.
#define	MPU_CTRL_PRIVDEFENA_Pos 2U
	MPU CTRL: PRIVDEFENA Position.
#define	MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
	MPU CTRL: PRIVDEFENA Mask.
#define	MPU_CTRL_HFNMIENA_Pos 1U
	MPU CTRL: HFNMIENA Position.
#define	MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
	MPU CTRL: HFNMIENA Mask.
#define	MPU_CTRL_ENABLE_Pos 0U
	MPU CTRL: ENABLE Position.
#define	MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/)
	MPU CTRL: ENABLE Mask.
#define	MPU_RNR_REGION_Pos 0U
	MPU RNR: REGION Position.
#define	MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/)
	MPU RNR: REGION Mask.
#define	MPU_RBAR_BASE_Pos 5U
	MPU RBAR: BASE Position.
#define	MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
	MPU RBAR: BASE Mask.
#define	MPU_RBAR_SH_Pos 3U
	MPU RBAR: SH Position.
#define	MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
	MPU RBAR: SH Mask.
#define	MPU_RBAR_AP_Pos 1U
	MPU RBAR: AP Position.
#define	MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
	MPU RBAR: AP Mask.
#define	MPU_RBAR_XN_Pos 0U
	MPU RBAR: XN Position.
#define	MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/)
	MPU RBAR: XN Mask.
#define	MPU_RLAR_LIMIT_Pos 5U
	MPU RLAR: LIMIT Position.
#define	MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
	MPU RLAR: LIMIT Mask.
#define	MPU_RLAR_AttrIndx_Pos 1U
	MPU RLAR: AttrIndx Position.
#define	MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos)
	MPU RLAR: AttrIndx Mask.
#define	MPU_RLAR_EN_Pos 0U
	MPU RLAR: Region enable bit Position.
#define	MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/)
	MPU RLAR: Region enable bit Disable Mask.
#define	MPU_MAIR0_Attr3_Pos 24U
	MPU MAIR0: Attr3 Position.
#define	MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
	MPU MAIR0: Attr3 Mask.
#define	MPU_MAIR0_Attr2_Pos 16U
	MPU MAIR0: Attr2 Position.
#define	MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
	MPU MAIR0: Attr2 Mask.
#define	MPU_MAIR0_Attr1_Pos 8U
	MPU MAIR0: Attr1 Position.
#define	MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
	MPU MAIR0: Attr1 Mask.
#define	MPU_MAIR0_Attr0_Pos 0U
	MPU MAIR0: Attr0 Position.
#define	MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/)
	MPU MAIR0: Attr0 Mask.
#define	MPU_MAIR1_Attr7_Pos 24U
	MPU MAIR1: Attr7 Position.
#define	MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
	MPU MAIR1: Attr7 Mask.
#define	MPU_MAIR1_Attr6_Pos 16U
	MPU MAIR1: Attr6 Position.
#define	MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
	MPU MAIR1: Attr6 Mask.
#define	MPU_MAIR1_Attr5_Pos 8U
	MPU MAIR1: Attr5 Position.
#define	MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
	MPU MAIR1: Attr5 Mask.
#define	MPU_MAIR1_Attr4_Pos 0U
	MPU MAIR1: Attr4 Position.
#define	MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/)
	MPU MAIR1: Attr4 Mask.
#define	MPU_TYPE_IREGION_Pos 16U
	MPU TYPE: IREGION Position.
#define	MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
	MPU TYPE: IREGION Mask.
#define	MPU_TYPE_DREGION_Pos 8U
	MPU TYPE: DREGION Position.
#define	MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
	MPU TYPE: DREGION Mask.
#define	MPU_TYPE_SEPARATE_Pos 0U
	MPU TYPE: SEPARATE Position.
#define	MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/)
	MPU TYPE: SEPARATE Mask.
#define	MPU_CTRL_PRIVDEFENA_Pos 2U
	MPU CTRL: PRIVDEFENA Position.
#define	MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
	MPU CTRL: PRIVDEFENA Mask.
#define	MPU_CTRL_HFNMIENA_Pos 1U
	MPU CTRL: HFNMIENA Position.
#define	MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
	MPU CTRL: HFNMIENA Mask.
#define	MPU_CTRL_ENABLE_Pos 0U
	MPU CTRL: ENABLE Position.
#define	MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/)
	MPU CTRL: ENABLE Mask.
#define	MPU_RNR_REGION_Pos 0U
	MPU RNR: REGION Position.
#define	MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/)
	MPU RNR: REGION Mask.
#define	MPU_TYPE_IREGION_Pos 16U
	MPU TYPE: IREGION Position.
#define	MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
	MPU TYPE: IREGION Mask.
#define	MPU_TYPE_DREGION_Pos 8U
	MPU TYPE: DREGION Position.
#define	MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
	MPU TYPE: DREGION Mask.
#define	MPU_TYPE_SEPARATE_Pos 0U
	MPU TYPE: SEPARATE Position.
#define	MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/)
	MPU TYPE: SEPARATE Mask.
#define	MPU_CTRL_PRIVDEFENA_Pos 2U
	MPU CTRL: PRIVDEFENA Position.
#define	MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
	MPU CTRL: PRIVDEFENA Mask.
#define	MPU_CTRL_HFNMIENA_Pos 1U
	MPU CTRL: HFNMIENA Position.
#define	MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
	MPU CTRL: HFNMIENA Mask.
#define	MPU_CTRL_ENABLE_Pos 0U
	MPU CTRL: ENABLE Position.
#define	MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/)
	MPU CTRL: ENABLE Mask.
#define	MPU_RNR_REGION_Pos 0U
	MPU RNR: REGION Position.
#define	MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/)
	MPU RNR: REGION Mask.
#define	MPU_TYPE_RALIASES 4U
#define	MPU_TYPE_IREGION_Pos 16U
	MPU TYPE: IREGION Position.
#define	MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
	MPU TYPE: IREGION Mask.
#define	MPU_TYPE_DREGION_Pos 8U
	MPU TYPE: DREGION Position.
#define	MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
	MPU TYPE: DREGION Mask.
#define	MPU_TYPE_SEPARATE_Pos 0U
	MPU TYPE: SEPARATE Position.
#define	MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/)
	MPU TYPE: SEPARATE Mask.
#define	MPU_CTRL_PRIVDEFENA_Pos 2U
	MPU CTRL: PRIVDEFENA Position.
#define	MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
	MPU CTRL: PRIVDEFENA Mask.
#define	MPU_CTRL_HFNMIENA_Pos 1U
	MPU CTRL: HFNMIENA Position.
#define	MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
	MPU CTRL: HFNMIENA Mask.
#define	MPU_CTRL_ENABLE_Pos 0U
	MPU CTRL: ENABLE Position.
#define	MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/)
	MPU CTRL: ENABLE Mask.
#define	MPU_RNR_REGION_Pos 0U
	MPU RNR: REGION Position.
#define	MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/)
	MPU RNR: REGION Mask.
#define	MPU_RBAR_BASE_Pos 5U
	MPU RBAR: BASE Position.
#define	MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
	MPU RBAR: BASE Mask.
#define	MPU_RBAR_SH_Pos 3U
	MPU RBAR: SH Position.
#define	MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
	MPU RBAR: SH Mask.
#define	MPU_RBAR_AP_Pos 1U
	MPU RBAR: AP Position.
#define	MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
	MPU RBAR: AP Mask.
#define	MPU_RBAR_XN_Pos 0U
	MPU RBAR: XN Position.
#define	MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/)
	MPU RBAR: XN Mask.
#define	MPU_RLAR_LIMIT_Pos 5U
	MPU RLAR: LIMIT Position.
#define	MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
	MPU RLAR: LIMIT Mask.
#define	MPU_RLAR_AttrIndx_Pos 1U
	MPU RLAR: AttrIndx Position.
#define	MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
	MPU RLAR: AttrIndx Mask.
#define	MPU_RLAR_EN_Pos 0U
	MPU RLAR: Region enable bit Position.
#define	MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/)
	MPU RLAR: Region enable bit Disable Mask.
#define	MPU_MAIR0_Attr3_Pos 24U
	MPU MAIR0: Attr3 Position.
#define	MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
	MPU MAIR0: Attr3 Mask.
#define	MPU_MAIR0_Attr2_Pos 16U
	MPU MAIR0: Attr2 Position.
#define	MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
	MPU MAIR0: Attr2 Mask.
#define	MPU_MAIR0_Attr1_Pos 8U
	MPU MAIR0: Attr1 Position.
#define	MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
	MPU MAIR0: Attr1 Mask.
#define	MPU_MAIR0_Attr0_Pos 0U
	MPU MAIR0: Attr0 Position.
#define	MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/)
	MPU MAIR0: Attr0 Mask.
#define	MPU_MAIR1_Attr7_Pos 24U
	MPU MAIR1: Attr7 Position.
#define	MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
	MPU MAIR1: Attr7 Mask.
#define	MPU_MAIR1_Attr6_Pos 16U
	MPU MAIR1: Attr6 Position.
#define	MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
	MPU MAIR1: Attr6 Mask.
#define	MPU_MAIR1_Attr5_Pos 8U
	MPU MAIR1: Attr5 Position.
#define	MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
	MPU MAIR1: Attr5 Mask.
#define	MPU_MAIR1_Attr4_Pos 0U
	MPU MAIR1: Attr4 Position.
#define	MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/)
	MPU MAIR1: Attr4 Mask.
#define	MPU_RLAR_PXN_Pos 4U
	MPU RLAR: PXN Position.
#define	MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos)
	MPU RLAR: PXN Mask.
#define	MPU_RLAR_PXN_Pos 4U
	MPU RLAR: PXN Position.
#define	MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos)
	MPU RLAR: PXN Mask.
#define	MPU_RLAR_PXN_Pos 4U
	MPU RLAR: PXN Position.
#define	MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos)
	MPU RLAR: PXN Mask.
#define	MPU_RBAR_ADDR_Pos 8U
	MPU RBAR: ADDR Position.
#define	MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
	MPU RBAR: ADDR Mask.
#define	MPU_RBAR_VALID_Pos 4U
	MPU RBAR: VALID Position.
#define	MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
	MPU RBAR: VALID Mask.
#define	MPU_RBAR_REGION_Pos 0U
	MPU RBAR: REGION Position.
#define	MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/)
	MPU RBAR: REGION Mask.
#define	MPU_RASR_ATTRS_Pos 16U
	MPU RASR: MPU Region Attribute field Position.
#define	MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
	MPU RASR: MPU Region Attribute field Mask.
#define	MPU_RASR_XN_Pos 28U
	MPU RASR: ATTRS.XN Position.
#define	MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
	MPU RASR: ATTRS.XN Mask.
#define	MPU_RASR_AP_Pos 24U
	MPU RASR: ATTRS.AP Position.
#define	MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
	MPU RASR: ATTRS.AP Mask.
#define	MPU_RASR_TEX_Pos 19U
	MPU RASR: ATTRS.TEX Position.
#define	MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
	MPU RASR: ATTRS.TEX Mask.
#define	MPU_RASR_S_Pos 18U
	MPU RASR: ATTRS.S Position.
#define	MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
	MPU RASR: ATTRS.S Mask.
#define	MPU_RASR_C_Pos 17U
	MPU RASR: ATTRS.C Position.
#define	MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
	MPU RASR: ATTRS.C Mask.
#define	MPU_RASR_B_Pos 16U
	MPU RASR: ATTRS.B Position.
#define	MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
	MPU RASR: ATTRS.B Mask.
#define	MPU_RASR_SRD_Pos 8U
	MPU RASR: Sub-Region Disable Position.
#define	MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
	MPU RASR: Sub-Region Disable Mask.
#define	MPU_RASR_SIZE_Pos 1U
	MPU RASR: Region Size Field Position.
#define	MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
	MPU RASR: Region Size Field Mask.
#define	MPU_RASR_ENABLE_Pos 0U
	MPU RASR: Region enable bit Position.
#define	MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/)
	MPU RASR: Region enable bit Disable Mask.
#define	MPU_RBAR_ADDR_Pos 5U
	MPU RBAR: ADDR Position.
#define	MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
	MPU RBAR: ADDR Mask.
#define	MPU_RBAR_VALID_Pos 4U
	MPU RBAR: VALID Position.
#define	MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
	MPU RBAR: VALID Mask.
#define	MPU_RBAR_REGION_Pos 0U
	MPU RBAR: REGION Position.
#define	MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/)
	MPU RBAR: REGION Mask.
#define	MPU_RASR_ATTRS_Pos 16U
	MPU RASR: MPU Region Attribute field Position.
#define	MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
	MPU RASR: MPU Region Attribute field Mask.
#define	MPU_RASR_XN_Pos 28U
	MPU RASR: ATTRS.XN Position.
#define	MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
	MPU RASR: ATTRS.XN Mask.
#define	MPU_RASR_AP_Pos 24U
	MPU RASR: ATTRS.AP Position.
#define	MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
	MPU RASR: ATTRS.AP Mask.
#define	MPU_RASR_TEX_Pos 19U
	MPU RASR: ATTRS.TEX Position.
#define	MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
	MPU RASR: ATTRS.TEX Mask.
#define	MPU_RASR_S_Pos 18U
	MPU RASR: ATTRS.S Position.
#define	MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
	MPU RASR: ATTRS.S Mask.
#define	MPU_RASR_C_Pos 17U
	MPU RASR: ATTRS.C Position.
#define	MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
	MPU RASR: ATTRS.C Mask.
#define	MPU_RASR_B_Pos 16U
	MPU RASR: ATTRS.B Position.
#define	MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
	MPU RASR: ATTRS.B Mask.
#define	MPU_RASR_SRD_Pos 8U
	MPU RASR: Sub-Region Disable Position.
#define	MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
	MPU RASR: Sub-Region Disable Mask.
#define	MPU_RASR_SIZE_Pos 1U
	MPU RASR: Region Size Field Position.
#define	MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
	MPU RASR: Region Size Field Mask.
#define	MPU_RASR_ENABLE_Pos 0U
	MPU RASR: Region enable bit Position.
#define	MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/)
	MPU RASR: Region enable bit Disable Mask.
#define	MPU_RBAR_ADDR_Pos 5U
	MPU RBAR: ADDR Position.
#define	MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
	MPU RBAR: ADDR Mask.
#define	MPU_RBAR_VALID_Pos 4U
	MPU RBAR: VALID Position.
#define	MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
	MPU RBAR: VALID Mask.
#define	MPU_RBAR_REGION_Pos 0U
	MPU RBAR: REGION Position.
#define	MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/)
	MPU RBAR: REGION Mask.
#define	MPU_RASR_ATTRS_Pos 16U
	MPU RASR: MPU Region Attribute field Position.
#define	MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
	MPU RASR: MPU Region Attribute field Mask.
#define	MPU_RASR_XN_Pos 28U
	MPU RASR: ATTRS.XN Position.
#define	MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
	MPU RASR: ATTRS.XN Mask.
#define	MPU_RASR_AP_Pos 24U
	MPU RASR: ATTRS.AP Position.
#define	MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
	MPU RASR: ATTRS.AP Mask.
#define	MPU_RASR_TEX_Pos 19U
	MPU RASR: ATTRS.TEX Position.
#define	MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
	MPU RASR: ATTRS.TEX Mask.
#define	MPU_RASR_S_Pos 18U
	MPU RASR: ATTRS.S Position.
#define	MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
	MPU RASR: ATTRS.S Mask.
#define	MPU_RASR_C_Pos 17U
	MPU RASR: ATTRS.C Position.
#define	MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
	MPU RASR: ATTRS.C Mask.
#define	MPU_RASR_B_Pos 16U
	MPU RASR: ATTRS.B Position.
#define	MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
	MPU RASR: ATTRS.B Mask.
#define	MPU_RASR_SRD_Pos 8U
	MPU RASR: Sub-Region Disable Position.
#define	MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
	MPU RASR: Sub-Region Disable Mask.
#define	MPU_RASR_SIZE_Pos 1U
	MPU RASR: Region Size Field Position.
#define	MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
	MPU RASR: Region Size Field Mask.
#define	MPU_RASR_ENABLE_Pos 0U
	MPU RASR: Region enable bit Position.
#define	MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/)
	MPU RASR: Region enable bit Disable Mask.
#define	MPU_RBAR_ADDR_Pos 5U
	MPU RBAR: ADDR Position.
#define	MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
	MPU RBAR: ADDR Mask.
#define	MPU_RBAR_VALID_Pos 4U
	MPU RBAR: VALID Position.
#define	MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
	MPU RBAR: VALID Mask.
#define	MPU_RBAR_REGION_Pos 0U
	MPU RBAR: REGION Position.
#define	MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/)
	MPU RBAR: REGION Mask.
#define	MPU_RASR_ATTRS_Pos 16U
	MPU RASR: MPU Region Attribute field Position.
#define	MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
	MPU RASR: MPU Region Attribute field Mask.
#define	MPU_RASR_XN_Pos 28U
	MPU RASR: ATTRS.XN Position.
#define	MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
	MPU RASR: ATTRS.XN Mask.
#define	MPU_RASR_AP_Pos 24U
	MPU RASR: ATTRS.AP Position.
#define	MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
	MPU RASR: ATTRS.AP Mask.
#define	MPU_RASR_TEX_Pos 19U
	MPU RASR: ATTRS.TEX Position.
#define	MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
	MPU RASR: ATTRS.TEX Mask.
#define	MPU_RASR_S_Pos 18U
	MPU RASR: ATTRS.S Position.
#define	MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
	MPU RASR: ATTRS.S Mask.
#define	MPU_RASR_C_Pos 17U
	MPU RASR: ATTRS.C Position.
#define	MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
	MPU RASR: ATTRS.C Mask.
#define	MPU_RASR_B_Pos 16U
	MPU RASR: ATTRS.B Position.
#define	MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
	MPU RASR: ATTRS.B Mask.
#define	MPU_RASR_SRD_Pos 8U
	MPU RASR: Sub-Region Disable Position.
#define	MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
	MPU RASR: Sub-Region Disable Mask.
#define	MPU_RASR_SIZE_Pos 1U
	MPU RASR: Region Size Field Position.
#define	MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
	MPU RASR: Region Size Field Mask.
#define	MPU_RASR_ENABLE_Pos 0U
	MPU RASR: Region enable bit Position.
#define	MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/)
	MPU RASR: Region enable bit Disable Mask.
#define	MPU_RBAR_ADDR_Pos 8U
	MPU RBAR: ADDR Position.
#define	MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
	MPU RBAR: ADDR Mask.
#define	MPU_RBAR_VALID_Pos 4U
	MPU RBAR: VALID Position.
#define	MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
	MPU RBAR: VALID Mask.
#define	MPU_RBAR_REGION_Pos 0U
	MPU RBAR: REGION Position.
#define	MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/)
	MPU RBAR: REGION Mask.
#define	MPU_RASR_ATTRS_Pos 16U
	MPU RASR: MPU Region Attribute field Position.
#define	MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
	MPU RASR: MPU Region Attribute field Mask.
#define	MPU_RASR_XN_Pos 28U
	MPU RASR: ATTRS.XN Position.
#define	MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
	MPU RASR: ATTRS.XN Mask.
#define	MPU_RASR_AP_Pos 24U
	MPU RASR: ATTRS.AP Position.
#define	MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
	MPU RASR: ATTRS.AP Mask.
#define	MPU_RASR_TEX_Pos 19U
	MPU RASR: ATTRS.TEX Position.
#define	MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
	MPU RASR: ATTRS.TEX Mask.
#define	MPU_RASR_S_Pos 18U
	MPU RASR: ATTRS.S Position.
#define	MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
	MPU RASR: ATTRS.S Mask.
#define	MPU_RASR_C_Pos 17U
	MPU RASR: ATTRS.C Position.
#define	MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
	MPU RASR: ATTRS.C Mask.
#define	MPU_RASR_B_Pos 16U
	MPU RASR: ATTRS.B Position.
#define	MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
	MPU RASR: ATTRS.B Mask.
#define	MPU_RASR_SRD_Pos 8U
	MPU RASR: Sub-Region Disable Position.
#define	MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
	MPU RASR: Sub-Region Disable Mask.
#define	MPU_RASR_SIZE_Pos 1U
	MPU RASR: Region Size Field Position.
#define	MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
	MPU RASR: Region Size Field Mask.
#define	MPU_RASR_ENABLE_Pos 0U
	MPU RASR: Region enable bit Position.
#define	MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/)
	MPU RASR: Region enable bit Disable Mask.
#define	MPU_RBAR_ADDR_Pos 5U
	MPU RBAR: ADDR Position.
#define	MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
	MPU RBAR: ADDR Mask.
#define	MPU_RBAR_VALID_Pos 4U
	MPU RBAR: VALID Position.
#define	MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
	MPU RBAR: VALID Mask.
#define	MPU_RBAR_REGION_Pos 0U
	MPU RBAR: REGION Position.
#define	MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/)
	MPU RBAR: REGION Mask.
#define	MPU_RASR_ATTRS_Pos 16U
	MPU RASR: MPU Region Attribute field Position.
#define	MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
	MPU RASR: MPU Region Attribute field Mask.
#define	MPU_RASR_XN_Pos 28U
	MPU RASR: ATTRS.XN Position.
#define	MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
	MPU RASR: ATTRS.XN Mask.
#define	MPU_RASR_AP_Pos 24U
	MPU RASR: ATTRS.AP Position.
#define	MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
	MPU RASR: ATTRS.AP Mask.
#define	MPU_RASR_TEX_Pos 19U
	MPU RASR: ATTRS.TEX Position.
#define	MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
	MPU RASR: ATTRS.TEX Mask.
#define	MPU_RASR_S_Pos 18U
	MPU RASR: ATTRS.S Position.
#define	MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
	MPU RASR: ATTRS.S Mask.
#define	MPU_RASR_C_Pos 17U
	MPU RASR: ATTRS.C Position.
#define	MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
	MPU RASR: ATTRS.C Mask.
#define	MPU_RASR_B_Pos 16U
	MPU RASR: ATTRS.B Position.
#define	MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
	MPU RASR: ATTRS.B Mask.
#define	MPU_RASR_SRD_Pos 8U
	MPU RASR: Sub-Region Disable Position.
#define	MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
	MPU RASR: Sub-Region Disable Mask.
#define	MPU_RASR_SIZE_Pos 1U
	MPU RASR: Region Size Field Position.
#define	MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
	MPU RASR: Region Size Field Mask.
#define	MPU_RASR_ENABLE_Pos 0U
	MPU RASR: Region enable bit Position.
#define	MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/)
	MPU RASR: Region enable bit Disable Mask.

Detailed Description

Type definitions for the Memory Protection Unit (MPU).

Macro Definition Documentation

◆ MPU_CTRL_ENABLE_Msk [1/15]

#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask.

Definition at line 2323 of file core_armv81mml.h.

Referenced by ARM_MPU_Disable(), and ARM_MPU_Enable().

◆ MPU_CTRL_ENABLE_Msk [2/15]

#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask.

Definition at line 863 of file core_armv8mbl.h.

◆ MPU_CTRL_ENABLE_Msk [3/15]

#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask.

Definition at line 1445 of file core_armv8mml.h.

◆ MPU_CTRL_ENABLE_Msk [4/15]

#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask.

Definition at line 553 of file core_cm0plus.h.

◆ MPU_CTRL_ENABLE_Msk [5/15]

#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask.

Definition at line 938 of file core_cm23.h.

◆ MPU_CTRL_ENABLE_Msk [6/15]

#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask.

Definition at line 1190 of file core_cm3.h.

◆ MPU_CTRL_ENABLE_Msk [7/15]

#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask.

Definition at line 1520 of file core_cm33.h.

◆ MPU_CTRL_ENABLE_Msk [8/15]

#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask.

Definition at line 1520 of file core_cm35p.h.

◆ MPU_CTRL_ENABLE_Msk [9/15]

#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask.

Definition at line 1248 of file core_cm4.h.

◆ MPU_CTRL_ENABLE_Msk [10/15]

#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask.

Definition at line 2819 of file core_cm55.h.

◆ MPU_CTRL_ENABLE_Msk [11/15]

#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask.

Definition at line 1475 of file core_cm7.h.

◆ MPU_CTRL_ENABLE_Msk [12/15]

#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask.

Definition at line 2724 of file core_cm85.h.

◆ MPU_CTRL_ENABLE_Msk [13/15]

#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask.

Definition at line 567 of file core_sc000.h.

◆ MPU_CTRL_ENABLE_Msk [14/15]

#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask.

Definition at line 1173 of file core_sc300.h.

◆ MPU_CTRL_ENABLE_Msk [15/15]

#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)

MPU CTRL: ENABLE Mask.

Definition at line 1578 of file core_starmc1.h.

◆ MPU_CTRL_ENABLE_Pos [1/15]

#define MPU_CTRL_ENABLE_Pos 0U

MPU CTRL: ENABLE Position.

Definition at line 2322 of file core_armv81mml.h.

◆ MPU_CTRL_ENABLE_Pos [2/15]

#define MPU_CTRL_ENABLE_Pos 0U

MPU CTRL: ENABLE Position.

Definition at line 862 of file core_armv8mbl.h.

◆ MPU_CTRL_ENABLE_Pos [3/15]

#define MPU_CTRL_ENABLE_Pos 0U

MPU CTRL: ENABLE Position.

Definition at line 1444 of file core_armv8mml.h.

◆ MPU_CTRL_ENABLE_Pos [4/15]

#define MPU_CTRL_ENABLE_Pos 0U

MPU CTRL: ENABLE Position.

Definition at line 552 of file core_cm0plus.h.

◆ MPU_CTRL_ENABLE_Pos [5/15]

#define MPU_CTRL_ENABLE_Pos 0U

MPU CTRL: ENABLE Position.

Definition at line 937 of file core_cm23.h.

◆ MPU_CTRL_ENABLE_Pos [6/15]

#define MPU_CTRL_ENABLE_Pos 0U

MPU CTRL: ENABLE Position.

Definition at line 1189 of file core_cm3.h.

◆ MPU_CTRL_ENABLE_Pos [7/15]

#define MPU_CTRL_ENABLE_Pos 0U

MPU CTRL: ENABLE Position.

Definition at line 1519 of file core_cm33.h.

◆ MPU_CTRL_ENABLE_Pos [8/15]

#define MPU_CTRL_ENABLE_Pos 0U

MPU CTRL: ENABLE Position.

Definition at line 1519 of file core_cm35p.h.

◆ MPU_CTRL_ENABLE_Pos [9/15]

#define MPU_CTRL_ENABLE_Pos 0U

MPU CTRL: ENABLE Position.

Definition at line 1247 of file core_cm4.h.

◆ MPU_CTRL_ENABLE_Pos [10/15]

#define MPU_CTRL_ENABLE_Pos 0U

MPU CTRL: ENABLE Position.

Definition at line 2818 of file core_cm55.h.

◆ MPU_CTRL_ENABLE_Pos [11/15]

#define MPU_CTRL_ENABLE_Pos 0U

MPU CTRL: ENABLE Position.

Definition at line 1474 of file core_cm7.h.

◆ MPU_CTRL_ENABLE_Pos [12/15]

#define MPU_CTRL_ENABLE_Pos 0U

MPU CTRL: ENABLE Position.

Definition at line 2723 of file core_cm85.h.

◆ MPU_CTRL_ENABLE_Pos [13/15]

#define MPU_CTRL_ENABLE_Pos 0U

MPU CTRL: ENABLE Position.

Definition at line 566 of file core_sc000.h.

◆ MPU_CTRL_ENABLE_Pos [14/15]

#define MPU_CTRL_ENABLE_Pos 0U

MPU CTRL: ENABLE Position.

Definition at line 1172 of file core_sc300.h.

◆ MPU_CTRL_ENABLE_Pos [15/15]

#define MPU_CTRL_ENABLE_Pos 0U

MPU CTRL: ENABLE Position.

Definition at line 1577 of file core_starmc1.h.

◆ MPU_CTRL_HFNMIENA_Msk [1/15]

#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask.

Definition at line 2320 of file core_armv81mml.h.

◆ MPU_CTRL_HFNMIENA_Msk [2/15]

#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask.

Definition at line 860 of file core_armv8mbl.h.

◆ MPU_CTRL_HFNMIENA_Msk [3/15]

#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask.

Definition at line 1442 of file core_armv8mml.h.

◆ MPU_CTRL_HFNMIENA_Msk [4/15]

#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask.

Definition at line 550 of file core_cm0plus.h.

◆ MPU_CTRL_HFNMIENA_Msk [5/15]

#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask.

Definition at line 935 of file core_cm23.h.

◆ MPU_CTRL_HFNMIENA_Msk [6/15]

#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask.

Definition at line 1187 of file core_cm3.h.

◆ MPU_CTRL_HFNMIENA_Msk [7/15]

#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask.

Definition at line 1517 of file core_cm33.h.

◆ MPU_CTRL_HFNMIENA_Msk [8/15]

#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask.

Definition at line 1517 of file core_cm35p.h.

◆ MPU_CTRL_HFNMIENA_Msk [9/15]

#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask.

Definition at line 1245 of file core_cm4.h.

◆ MPU_CTRL_HFNMIENA_Msk [10/15]

#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask.

Definition at line 2816 of file core_cm55.h.

◆ MPU_CTRL_HFNMIENA_Msk [11/15]

#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask.

Definition at line 1472 of file core_cm7.h.

◆ MPU_CTRL_HFNMIENA_Msk [12/15]

#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask.

Definition at line 2721 of file core_cm85.h.

◆ MPU_CTRL_HFNMIENA_Msk [13/15]

#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask.

Definition at line 564 of file core_sc000.h.

◆ MPU_CTRL_HFNMIENA_Msk [14/15]

#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask.

Definition at line 1170 of file core_sc300.h.

◆ MPU_CTRL_HFNMIENA_Msk [15/15]

#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)

MPU CTRL: HFNMIENA Mask.

Definition at line 1575 of file core_starmc1.h.

◆ MPU_CTRL_HFNMIENA_Pos [1/15]

#define MPU_CTRL_HFNMIENA_Pos 1U

MPU CTRL: HFNMIENA Position.

Definition at line 2319 of file core_armv81mml.h.

◆ MPU_CTRL_HFNMIENA_Pos [2/15]

#define MPU_CTRL_HFNMIENA_Pos 1U

MPU CTRL: HFNMIENA Position.

Definition at line 859 of file core_armv8mbl.h.

◆ MPU_CTRL_HFNMIENA_Pos [3/15]

#define MPU_CTRL_HFNMIENA_Pos 1U

MPU CTRL: HFNMIENA Position.

Definition at line 1441 of file core_armv8mml.h.

◆ MPU_CTRL_HFNMIENA_Pos [4/15]

#define MPU_CTRL_HFNMIENA_Pos 1U

MPU CTRL: HFNMIENA Position.

Definition at line 549 of file core_cm0plus.h.

◆ MPU_CTRL_HFNMIENA_Pos [5/15]

#define MPU_CTRL_HFNMIENA_Pos 1U

MPU CTRL: HFNMIENA Position.

Definition at line 934 of file core_cm23.h.

◆ MPU_CTRL_HFNMIENA_Pos [6/15]

#define MPU_CTRL_HFNMIENA_Pos 1U

MPU CTRL: HFNMIENA Position.

Definition at line 1186 of file core_cm3.h.

◆ MPU_CTRL_HFNMIENA_Pos [7/15]

#define MPU_CTRL_HFNMIENA_Pos 1U

MPU CTRL: HFNMIENA Position.

Definition at line 1516 of file core_cm33.h.

◆ MPU_CTRL_HFNMIENA_Pos [8/15]

#define MPU_CTRL_HFNMIENA_Pos 1U

MPU CTRL: HFNMIENA Position.

Definition at line 1516 of file core_cm35p.h.

◆ MPU_CTRL_HFNMIENA_Pos [9/15]

#define MPU_CTRL_HFNMIENA_Pos 1U

MPU CTRL: HFNMIENA Position.

Definition at line 1244 of file core_cm4.h.

◆ MPU_CTRL_HFNMIENA_Pos [10/15]

#define MPU_CTRL_HFNMIENA_Pos 1U

MPU CTRL: HFNMIENA Position.

Definition at line 2815 of file core_cm55.h.

◆ MPU_CTRL_HFNMIENA_Pos [11/15]

#define MPU_CTRL_HFNMIENA_Pos 1U

MPU CTRL: HFNMIENA Position.

Definition at line 1471 of file core_cm7.h.

◆ MPU_CTRL_HFNMIENA_Pos [12/15]

#define MPU_CTRL_HFNMIENA_Pos 1U

MPU CTRL: HFNMIENA Position.

Definition at line 2720 of file core_cm85.h.

◆ MPU_CTRL_HFNMIENA_Pos [13/15]

#define MPU_CTRL_HFNMIENA_Pos 1U

MPU CTRL: HFNMIENA Position.

Definition at line 563 of file core_sc000.h.

◆ MPU_CTRL_HFNMIENA_Pos [14/15]

#define MPU_CTRL_HFNMIENA_Pos 1U

MPU CTRL: HFNMIENA Position.

Definition at line 1169 of file core_sc300.h.

◆ MPU_CTRL_HFNMIENA_Pos [15/15]

#define MPU_CTRL_HFNMIENA_Pos 1U

MPU CTRL: HFNMIENA Position.

Definition at line 1574 of file core_starmc1.h.

◆ MPU_CTRL_PRIVDEFENA_Msk [1/15]

#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask.

Definition at line 2317 of file core_armv81mml.h.

◆ MPU_CTRL_PRIVDEFENA_Msk [2/15]

#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask.

Definition at line 857 of file core_armv8mbl.h.

◆ MPU_CTRL_PRIVDEFENA_Msk [3/15]

#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask.

Definition at line 1439 of file core_armv8mml.h.

◆ MPU_CTRL_PRIVDEFENA_Msk [4/15]

#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask.

Definition at line 547 of file core_cm0plus.h.

◆ MPU_CTRL_PRIVDEFENA_Msk [5/15]

#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask.

Definition at line 932 of file core_cm23.h.

◆ MPU_CTRL_PRIVDEFENA_Msk [6/15]

#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask.

Definition at line 1184 of file core_cm3.h.

◆ MPU_CTRL_PRIVDEFENA_Msk [7/15]

#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask.

Definition at line 1514 of file core_cm33.h.

◆ MPU_CTRL_PRIVDEFENA_Msk [8/15]

#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask.

Definition at line 1514 of file core_cm35p.h.

◆ MPU_CTRL_PRIVDEFENA_Msk [9/15]

#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask.

Definition at line 1242 of file core_cm4.h.

◆ MPU_CTRL_PRIVDEFENA_Msk [10/15]

#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask.

Definition at line 2813 of file core_cm55.h.

◆ MPU_CTRL_PRIVDEFENA_Msk [11/15]

#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask.

Definition at line 1469 of file core_cm7.h.

◆ MPU_CTRL_PRIVDEFENA_Msk [12/15]

#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask.

Definition at line 2718 of file core_cm85.h.

◆ MPU_CTRL_PRIVDEFENA_Msk [13/15]

#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask.

Definition at line 561 of file core_sc000.h.

◆ MPU_CTRL_PRIVDEFENA_Msk [14/15]

#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask.

Definition at line 1167 of file core_sc300.h.

◆ MPU_CTRL_PRIVDEFENA_Msk [15/15]

#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)

MPU CTRL: PRIVDEFENA Mask.

Definition at line 1572 of file core_starmc1.h.