Type definitions for the Trace Port Interface (TPI). More...

Collaboration diagram for Trace Port Interface (TPI):

Topics
	Memory Protection Unit (MPU)
	Type definitions for the Memory Protection Unit (MPU).

Classes
struct	TPI_Type
	Structure type to access the Trace Port Interface Register (TPI). More...
#define	TPI_ACPR_SWOSCALER_Pos 0U
	TPI ACPR: SWOSCALER Position.
#define	TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/)
	TPI ACPR: SWOSCALER Mask.
#define	TPI_FFCR_EnFmt_Pos 0U
	TPI FFCR: EnFmt Position.
#define	TPI_FFCR_EnFmt_Msk (0x3UL << /TPI_FFCR_EnFmt_Pos/)
	TPI FFCR: EnFmt Mask.
#define	TPI_PSCR_PSCount_Pos 0U
	TPI PSCR: PSCount Position.
#define	TPI_PSCR_PSCount_Msk (0x1FUL /<< TPI_PSCR_PSCount_Pos/)
	TPI PSCR: TPSCount Mask.
#define	TPI_LSR_nTT_Pos 1U
	TPI LSR: Not thirty-two bit.
#define	TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)
	TPI LSR: Not thirty-two bit.
#define	TPI_LSR_SLK_Pos 1U
	TPI LSR: Software Lock status Position.
#define	TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)
	TPI LSR: Software Lock status Mask.
#define	TPI_LSR_SLI_Pos 0U
	TPI LSR: Software Lock implemented Position.
#define	TPI_LSR_SLI_Msk (0x1UL /<< TPI_LSR_SLI_Pos/)
	TPI LSR: Software Lock implemented Mask.
#define	TPI_ACPR_SWOSCALER_Pos 0U
	TPI ACPR: SWOSCALER Position.
#define	TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/)
	TPI ACPR: SWOSCALER Mask.
#define	TPI_PSCR_PSCount_Pos 0U
	TPI PSCR: PSCount Position.
#define	TPI_PSCR_PSCount_Msk (0x1FUL /<< TPI_PSCR_PSCount_Pos/)
	TPI PSCR: TPSCount Mask.
#define	TPI_LSR_nTT_Pos 1U
	TPI LSR: Not thirty-two bit.
#define	TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)
	TPI LSR: Not thirty-two bit.
#define	TPI_LSR_SLK_Pos 1U
	TPI LSR: Software Lock status Position.
#define	TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)
	TPI LSR: Software Lock status Mask.
#define	TPI_LSR_SLI_Pos 0U
	TPI LSR: Software Lock implemented Position.
#define	TPI_LSR_SLI_Msk (0x1UL /<< TPI_LSR_SLI_Pos/)
	TPI LSR: Software Lock implemented Mask.
#define	TPI_ACPR_SWOSCALER_Pos 0U
	TPI ACPR: SWOSCALER Position.
#define	TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/)
	TPI ACPR: SWOSCALER Mask.
#define	TPI_PSCR_PSCount_Pos 0U
	TPI PSCR: PSCount Position.
#define	TPI_PSCR_PSCount_Msk (0x1FUL /<< TPI_PSCR_PSCount_Pos/)
	TPI PSCR: TPSCount Mask.
#define	TPI_LSR_nTT_Pos 1U
	TPI LSR: Not thirty-two bit.
#define	TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)
	TPI LSR: Not thirty-two bit.
#define	TPI_LSR_SLK_Pos 1U
	TPI LSR: Software Lock status Position.
#define	TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)
	TPI LSR: Software Lock status Mask.
#define	TPI_LSR_SLI_Pos 0U
	TPI LSR: Software Lock implemented Position.
#define	TPI_LSR_SLI_Msk (0x1UL /<< TPI_LSR_SLI_Pos/)
	TPI LSR: Software Lock implemented Mask.
#define	TPI_ACPR_SWOSCALER_Pos 0U
	TPI ACPR: SWOSCALER Position.
#define	TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/)
	TPI ACPR: SWOSCALER Mask.
#define	TPI_FFCR_EnFmt_Pos 0U
	TPI FFCR: EnFmt Position.
#define	TPI_FFCR_EnFmt_Msk (0x3UL << /TPI_FFCR_EnFmt_Pos/)
	TPI FFCR: EnFmt Mask.
#define	TPI_PSCR_PSCount_Pos 0U
	TPI PSCR: PSCount Position.
#define	TPI_PSCR_PSCount_Msk (0x1FUL /<< TPI_PSCR_PSCount_Pos/)
	TPI PSCR: TPSCount Mask.
#define	TPI_LSR_nTT_Pos 1U
	TPI LSR: Not thirty-two bit.
#define	TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)
	TPI LSR: Not thirty-two bit.
#define	TPI_LSR_SLK_Pos 1U
	TPI LSR: Software Lock status Position.
#define	TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)
	TPI LSR: Software Lock status Mask.
#define	TPI_LSR_SLI_Pos 0U
	TPI LSR: Software Lock implemented Position.
#define	TPI_LSR_SLI_Msk (0x1UL /<< TPI_LSR_SLI_Pos/)
	TPI LSR: Software Lock implemented Mask.
#define	TPI_ACPR_SWOSCALER_Pos 0U
	TPI ACPR: SWOSCALER Position.
#define	TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/)
	TPI ACPR: SWOSCALER Mask.
#define	TPI_FFCR_EnFmt_Pos 0U
	TPI FFCR: EnFmt Position.
#define	TPI_FFCR_EnFmt_Msk (0x3UL << /TPI_FFCR_EnFmt_Pos/)
	TPI FFCR: EnFmt Mask.
#define	TPI_PSCR_PSCount_Pos 0U
	TPI PSCR: PSCount Position.
#define	TPI_PSCR_PSCount_Msk (0x1FUL /<< TPI_PSCR_PSCount_Pos/)
	TPI PSCR: TPSCount Mask.
#define	TPI_LSR_nTT_Pos 1U
	TPI LSR: Not thirty-two bit.
#define	TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)
	TPI LSR: Not thirty-two bit.
#define	TPI_LSR_SLK_Pos 1U
	TPI LSR: Software Lock status Position.
#define	TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)
	TPI LSR: Software Lock status Mask.
#define	TPI_LSR_SLI_Pos 0U
	TPI LSR: Software Lock implemented Position.
#define	TPI_LSR_SLI_Msk (0x1UL /<< TPI_LSR_SLI_Pos/)
	TPI LSR: Software Lock implemented Mask.
#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U
#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U
#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U
#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U
#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U
#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)
#define	CoreDebug_DSCSR_CDS_Pos 16U
#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)
#define	CoreDebug_DSCSR_SBRSEL_Pos 1U
#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U
#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)
#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U
#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U
#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U
#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U
#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U
#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)
#define	CoreDebug_DSCSR_CDS_Pos 16U
#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)
#define	CoreDebug_DSCSR_SBRSEL_Pos 1U
#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U
#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)
#define	TPI_SPPR_TXMODE_Pos 0U
	TPI SPPR: TXMODE Position.
#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)
	TPI SPPR: TXMODE Mask.
#define	TPI_FFSR_FtNonStop_Pos 3U
	TPI FFSR: FtNonStop Position.
#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
	TPI FFSR: FtNonStop Mask.
#define	TPI_FFSR_TCPresent_Pos 2U
	TPI FFSR: TCPresent Position.
#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
	TPI FFSR: TCPresent Mask.
#define	TPI_FFSR_FtStopped_Pos 1U
	TPI FFSR: FtStopped Position.
#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
	TPI FFSR: FtStopped Mask.
#define	TPI_FFSR_FlInProg_Pos 0U
	TPI FFSR: FlInProg Position.
#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)
	TPI FFSR: FlInProg Mask.
#define	TPI_FFCR_TrigIn_Pos 8U
	TPI FFCR: TrigIn Position.
#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
	TPI FFCR: TrigIn Mask.
#define	TPI_FFCR_FOnMan_Pos 6U
	TPI FFCR: FOnMan Position.
#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
	TPI FFCR: FOnMan Mask.
#define	TPI_DEVID_NRZVALID_Pos 11U
	TPI DEVID: NRZVALID Position.
#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
	TPI DEVID: NRZVALID Mask.
#define	TPI_DEVID_MANCVALID_Pos 10U
	TPI DEVID: MANCVALID Position.
#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
	TPI DEVID: MANCVALID Mask.
#define	TPI_DEVID_PTINVALID_Pos 9U
	TPI DEVID: PTINVALID Position.
#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
	TPI DEVID: PTINVALID Mask.
#define	TPI_DEVID_FIFOSZ_Pos 6U
	TPI DEVID: FIFO depth Position.
#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
	TPI DEVID: FIFO depth Mask.
#define	TPI_DEVTYPE_SubType_Pos 4U
	TPI DEVTYPE: SubType Position.
#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)
	TPI DEVTYPE: SubType Mask.
#define	TPI_DEVTYPE_MajorType_Pos 0U
	TPI DEVTYPE: MajorType Position.
#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
	TPI DEVTYPE: MajorType Mask.
#define	TPI_SPPR_TXMODE_Pos 0U
	TPI SPPR: TXMODE Position.
#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)
	TPI SPPR: TXMODE Mask.
#define	TPI_FFSR_FtNonStop_Pos 3U
	TPI FFSR: FtNonStop Position.
#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
	TPI FFSR: FtNonStop Mask.
#define	TPI_FFSR_TCPresent_Pos 2U
	TPI FFSR: TCPresent Position.
#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
	TPI FFSR: TCPresent Mask.
#define	TPI_FFSR_FtStopped_Pos 1U
	TPI FFSR: FtStopped Position.
#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
	TPI FFSR: FtStopped Mask.
#define	TPI_FFSR_FlInProg_Pos 0U
	TPI FFSR: FlInProg Position.
#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)
	TPI FFSR: FlInProg Mask.
#define	TPI_FFCR_TrigIn_Pos 8U
	TPI FFCR: TrigIn Position.
#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
	TPI FFCR: TrigIn Mask.
#define	TPI_FFCR_FOnMan_Pos 6U
	TPI FFCR: FOnMan Position.
#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
	TPI FFCR: FOnMan Mask.
#define	TPI_FFCR_EnFCont_Pos 1U
	TPI FFCR: EnFCont Position.
#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
	TPI FFCR: EnFCont Mask.
#define	TPI_DEVID_NRZVALID_Pos 11U
	TPI DEVID: NRZVALID Position.
#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
	TPI DEVID: NRZVALID Mask.
#define	TPI_DEVID_MANCVALID_Pos 10U
	TPI DEVID: MANCVALID Position.
#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
	TPI DEVID: MANCVALID Mask.
#define	TPI_DEVID_PTINVALID_Pos 9U
	TPI DEVID: PTINVALID Position.
#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
	TPI DEVID: PTINVALID Mask.
#define	TPI_DEVID_FIFOSZ_Pos 6U
	TPI DEVID: FIFO depth Position.
#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
	TPI DEVID: FIFO depth Mask.
#define	TPI_DEVTYPE_SubType_Pos 4U
	TPI DEVTYPE: SubType Position.
#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)
	TPI DEVTYPE: SubType Mask.
#define	TPI_DEVTYPE_MajorType_Pos 0U
	TPI DEVTYPE: MajorType Position.
#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
	TPI DEVTYPE: MajorType Mask.
#define	TPI_SPPR_TXMODE_Pos 0U
	TPI SPPR: TXMODE Position.
#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)
	TPI SPPR: TXMODE Mask.
#define	TPI_FFSR_FtNonStop_Pos 3U
	TPI FFSR: FtNonStop Position.
#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
	TPI FFSR: FtNonStop Mask.
#define	TPI_FFSR_TCPresent_Pos 2U
	TPI FFSR: TCPresent Position.
#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
	TPI FFSR: TCPresent Mask.
#define	TPI_FFSR_FtStopped_Pos 1U
	TPI FFSR: FtStopped Position.
#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
	TPI FFSR: FtStopped Mask.
#define	TPI_FFSR_FlInProg_Pos 0U
	TPI FFSR: FlInProg Position.
#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)
	TPI FFSR: FlInProg Mask.
#define	TPI_FFCR_TrigIn_Pos 8U
	TPI FFCR: TrigIn Position.
#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
	TPI FFCR: TrigIn Mask.
#define	TPI_FFCR_FOnMan_Pos 6U
	TPI FFCR: FOnMan Position.
#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
	TPI FFCR: FOnMan Mask.
#define	TPI_FFCR_EnFCont_Pos 1U
	TPI FFCR: EnFCont Position.
#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
	TPI FFCR: EnFCont Mask.
#define	TPI_DEVID_NRZVALID_Pos 11U
	TPI DEVID: NRZVALID Position.
#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
	TPI DEVID: NRZVALID Mask.
#define	TPI_DEVID_MANCVALID_Pos 10U
	TPI DEVID: MANCVALID Position.
#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
	TPI DEVID: MANCVALID Mask.
#define	TPI_DEVID_PTINVALID_Pos 9U
	TPI DEVID: PTINVALID Position.
#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
	TPI DEVID: PTINVALID Mask.
#define	TPI_DEVID_FIFOSZ_Pos 6U
	TPI DEVID: FIFO depth Position.
#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
	TPI DEVID: FIFO depth Mask.
#define	TPI_DEVTYPE_SubType_Pos 4U
	TPI DEVTYPE: SubType Position.
#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)
	TPI DEVTYPE: SubType Mask.
#define	TPI_DEVTYPE_MajorType_Pos 0U
	TPI DEVTYPE: MajorType Position.
#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
	TPI DEVTYPE: MajorType Mask.
#define	TPI_ACPR_PRESCALER_Pos 0U
	TPI ACPR: PRESCALER Position.
#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)
	TPI ACPR: PRESCALER Mask.
#define	TPI_SPPR_TXMODE_Pos 0U
	TPI SPPR: TXMODE Position.
#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)
	TPI SPPR: TXMODE Mask.
#define	TPI_FFSR_FtNonStop_Pos 3U
	TPI FFSR: FtNonStop Position.
#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
	TPI FFSR: FtNonStop Mask.
#define	TPI_FFSR_TCPresent_Pos 2U
	TPI FFSR: TCPresent Position.
#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
	TPI FFSR: TCPresent Mask.
#define	TPI_FFSR_FtStopped_Pos 1U
	TPI FFSR: FtStopped Position.
#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
	TPI FFSR: FtStopped Mask.
#define	TPI_FFSR_FlInProg_Pos 0U
	TPI FFSR: FlInProg Position.
#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)
	TPI FFSR: FlInProg Mask.
#define	TPI_FFCR_TrigIn_Pos 8U
	TPI FFCR: TrigIn Position.
#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
	TPI FFCR: TrigIn Mask.
#define	TPI_FFCR_FOnMan_Pos 6U
	TPI FFCR: FOnMan Position.
#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
	TPI FFCR: FOnMan Mask.
#define	TPI_FFCR_EnFCont_Pos 1U
	TPI FFCR: EnFCont Position.
#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
	TPI FFCR: EnFCont Mask.
#define	TPI_TRIGGER_TRIGGER_Pos 0U
	TPI TRIGGER: TRIGGER Position.
#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)
	TPI TRIGGER: TRIGGER Mask.
#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U
	TPI ITFTTD0: ATB Interface 2 ATVALIDPosition.
#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)
	TPI ITFTTD0: ATB Interface 2 ATVALID Mask.
#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U
	TPI ITFTTD0: ATB Interface 2 byte count Position.
#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)
	TPI ITFTTD0: ATB Interface 2 byte count Mask.
#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U
	TPI ITFTTD0: ATB Interface 1 ATVALID Position.
#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)
	TPI ITFTTD0: ATB Interface 1 ATVALID Mask.
#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U
	TPI ITFTTD0: ATB Interface 1 byte count Position.
#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)
	TPI ITFTTD0: ATB Interface 1 byte countt Mask.
#define	TPI_ITFTTD0_ATB_IF1_data2_Pos 16U
	TPI ITFTTD0: ATB Interface 1 data2 Position.
#define	TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
	TPI ITFTTD0: ATB Interface 1 data2 Mask.
#define	TPI_ITFTTD0_ATB_IF1_data1_Pos 8U
	TPI ITFTTD0: ATB Interface 1 data1 Position.
#define	TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
	TPI ITFTTD0: ATB Interface 1 data1 Mask.
#define	TPI_ITFTTD0_ATB_IF1_data0_Pos 0U
	TPI ITFTTD0: ATB Interface 1 data0 Position.
#define	TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /<< TPI_ITFTTD0_ATB_IF1_data0_Pos/)
	TPI ITFTTD0: ATB Interface 1 data0 Mask.
#define	TPI_ITATBCTR2_AFVALID2S_Pos 1U
	TPI ITATBCTR2: AFVALID2S Position.
#define	TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)
	TPI ITATBCTR2: AFVALID2SS Mask.
#define	TPI_ITATBCTR2_AFVALID1S_Pos 1U
	TPI ITATBCTR2: AFVALID1S Position.
#define	TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)
	TPI ITATBCTR2: AFVALID1SS Mask.
#define	TPI_ITATBCTR2_ATREADY2S_Pos 0U
	TPI ITATBCTR2: ATREADY2S Position.
#define	TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2S_Pos/)
	TPI ITATBCTR2: ATREADY2S Mask.
#define	TPI_ITATBCTR2_ATREADY1S_Pos 0U
	TPI ITATBCTR2: ATREADY1S Position.
#define	TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1S_Pos/)
	TPI ITATBCTR2: ATREADY1S Mask.
#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U
	TPI ITFTTD1: ATB Interface 2 ATVALID Position.
#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)
	TPI ITFTTD1: ATB Interface 2 ATVALID Mask.
#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U
	TPI ITFTTD1: ATB Interface 2 byte count Position.
#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)
	TPI ITFTTD1: ATB Interface 2 byte count Mask.
#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U
	TPI ITFTTD1: ATB Interface 1 ATVALID Position.
#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)
	TPI ITFTTD1: ATB Interface 1 ATVALID Mask.
#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U
	TPI ITFTTD1: ATB Interface 1 byte count Position.
#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)
	TPI ITFTTD1: ATB Interface 1 byte countt Mask.
#define	TPI_ITFTTD1_ATB_IF2_data2_Pos 16U
	TPI ITFTTD1: ATB Interface 2 data2 Position.
#define	TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
	TPI ITFTTD1: ATB Interface 2 data2 Mask.
#define	TPI_ITFTTD1_ATB_IF2_data1_Pos 8U
	TPI ITFTTD1: ATB Interface 2 data1 Position.
#define	TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
	TPI ITFTTD1: ATB Interface 2 data1 Mask.
#define	TPI_ITFTTD1_ATB_IF2_data0_Pos 0U
	TPI ITFTTD1: ATB Interface 2 data0 Position.
#define	TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /<< TPI_ITFTTD1_ATB_IF2_data0_Pos/)
	TPI ITFTTD1: ATB Interface 2 data0 Mask.
#define	TPI_ITATBCTR0_AFVALID2S_Pos 1U
	TPI ITATBCTR0: AFVALID2S Position.
#define	TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)
	TPI ITATBCTR0: AFVALID2SS Mask.
#define	TPI_ITATBCTR0_AFVALID1S_Pos 1U
	TPI ITATBCTR0: AFVALID1S Position.
#define	TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)
	TPI ITATBCTR0: AFVALID1SS Mask.
#define	TPI_ITATBCTR0_ATREADY2S_Pos 0U
	TPI ITATBCTR0: ATREADY2S Position.
#define	TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2S_Pos/)
	TPI ITATBCTR0: ATREADY2S Mask.
#define	TPI_ITATBCTR0_ATREADY1S_Pos 0U
	TPI ITATBCTR0: ATREADY1S Position.
#define	TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1S_Pos/)
	TPI ITATBCTR0: ATREADY1S Mask.
#define	TPI_ITCTRL_Mode_Pos 0U
	TPI ITCTRL: Mode Position.
#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)
	TPI ITCTRL: Mode Mask.
#define	TPI_DEVID_NRZVALID_Pos 11U
	TPI DEVID: NRZVALID Position.
#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
	TPI DEVID: NRZVALID Mask.
#define	TPI_DEVID_MANCVALID_Pos 10U
	TPI DEVID: MANCVALID Position.
#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
	TPI DEVID: MANCVALID Mask.
#define	TPI_DEVID_PTINVALID_Pos 9U
	TPI DEVID: PTINVALID Position.
#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
	TPI DEVID: PTINVALID Mask.
#define	TPI_DEVID_FIFOSZ_Pos 6U
	TPI DEVID: FIFOSZ Position.
#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
	TPI DEVID: FIFOSZ Mask.
#define	TPI_DEVID_NrTraceInput_Pos 0U
	TPI DEVID: NrTraceInput Position.
#define	TPI_DEVID_NrTraceInput_Msk (0x3FUL /<< TPI_DEVID_NrTraceInput_Pos/)
	TPI DEVID: NrTraceInput Mask.
#define	TPI_DEVTYPE_SubType_Pos 4U
	TPI DEVTYPE: SubType Position.
#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)
	TPI DEVTYPE: SubType Mask.
#define	TPI_DEVTYPE_MajorType_Pos 0U
	TPI DEVTYPE: MajorType Position.
#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
	TPI DEVTYPE: MajorType Mask.
#define	TPI_ACPR_PRESCALER_Pos 0U
	TPI ACPR: PRESCALER Position.
#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)
	TPI ACPR: PRESCALER Mask.
#define	TPI_SPPR_TXMODE_Pos 0U
	TPI SPPR: TXMODE Position.
#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)
	TPI SPPR: TXMODE Mask.
#define	TPI_FFSR_FtNonStop_Pos 3U
	TPI FFSR: FtNonStop Position.
#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
	TPI FFSR: FtNonStop Mask.
#define	TPI_FFSR_TCPresent_Pos 2U
	TPI FFSR: TCPresent Position.
#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
	TPI FFSR: TCPresent Mask.
#define	TPI_FFSR_FtStopped_Pos 1U
	TPI FFSR: FtStopped Position.
#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
	TPI FFSR: FtStopped Mask.
#define	TPI_FFSR_FlInProg_Pos 0U
	TPI FFSR: FlInProg Position.
#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)
	TPI FFSR: FlInProg Mask.
#define	TPI_FFCR_TrigIn_Pos 8U
	TPI FFCR: TrigIn Position.
#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
	TPI FFCR: TrigIn Mask.
#define	TPI_FFCR_EnFCont_Pos 1U
	TPI FFCR: EnFCont Position.
#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
	TPI FFCR: EnFCont Mask.
#define	TPI_TRIGGER_TRIGGER_Pos 0U
	TPI TRIGGER: TRIGGER Position.
#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)
	TPI TRIGGER: TRIGGER Mask.
#define	TPI_ITCTRL_Mode_Pos 0U
	TPI ITCTRL: Mode Position.
#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)
	TPI ITCTRL: Mode Mask.
#define	TPI_DEVID_NRZVALID_Pos 11U
	TPI DEVID: NRZVALID Position.
#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
	TPI DEVID: NRZVALID Mask.
#define	TPI_DEVID_MANCVALID_Pos 10U
	TPI DEVID: MANCVALID Position.
#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
	TPI DEVID: MANCVALID Mask.
#define	TPI_DEVID_PTINVALID_Pos 9U
	TPI DEVID: PTINVALID Position.
#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
	TPI DEVID: PTINVALID Mask.
#define	TPI_DEVID_NrTraceInput_Pos 0U
	TPI DEVID: NrTraceInput Position.
#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)
	TPI DEVID: NrTraceInput Mask.
#define	TPI_DEVTYPE_SubType_Pos 4U
	TPI DEVTYPE: SubType Position.
#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)
	TPI DEVTYPE: SubType Mask.
#define	TPI_DEVTYPE_MajorType_Pos 0U
	TPI DEVTYPE: MajorType Position.
#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
	TPI DEVTYPE: MajorType Mask.
#define	TPI_ACPR_PRESCALER_Pos 0U
	TPI ACPR: PRESCALER Position.
#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)
	TPI ACPR: PRESCALER Mask.
#define	TPI_SPPR_TXMODE_Pos 0U
	TPI SPPR: TXMODE Position.
#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)
	TPI SPPR: TXMODE Mask.
#define	TPI_FFSR_FtNonStop_Pos 3U
	TPI FFSR: FtNonStop Position.
#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
	TPI FFSR: FtNonStop Mask.
#define	TPI_FFSR_TCPresent_Pos 2U
	TPI FFSR: TCPresent Position.
#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
	TPI FFSR: TCPresent Mask.
#define	TPI_FFSR_FtStopped_Pos 1U
	TPI FFSR: FtStopped Position.
#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
	TPI FFSR: FtStopped Mask.
#define	TPI_FFSR_FlInProg_Pos 0U
	TPI FFSR: FlInProg Position.
#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)
	TPI FFSR: FlInProg Mask.
#define	TPI_FFCR_TrigIn_Pos 8U
	TPI FFCR: TrigIn Position.
#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
	TPI FFCR: TrigIn Mask.
#define	TPI_FFCR_FOnMan_Pos 6U
	TPI FFCR: FOnMan Position.
#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
	TPI FFCR: FOnMan Mask.
#define	TPI_FFCR_EnFCont_Pos 1U
	TPI FFCR: EnFCont Position.
#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
	TPI FFCR: EnFCont Mask.
#define	TPI_TRIGGER_TRIGGER_Pos 0U
	TPI TRIGGER: TRIGGER Position.
#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)
	TPI TRIGGER: TRIGGER Mask.
#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U
	TPI ITFTTD0: ATB Interface 2 ATVALIDPosition.
#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)
	TPI ITFTTD0: ATB Interface 2 ATVALID Mask.
#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U
	TPI ITFTTD0: ATB Interface 2 byte count Position.
#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)
	TPI ITFTTD0: ATB Interface 2 byte count Mask.
#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U
	TPI ITFTTD0: ATB Interface 1 ATVALID Position.
#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)
	TPI ITFTTD0: ATB Interface 1 ATVALID Mask.
#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U
	TPI ITFTTD0: ATB Interface 1 byte count Position.
#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)
	TPI ITFTTD0: ATB Interface 1 byte countt Mask.
#define	TPI_ITFTTD0_ATB_IF1_data2_Pos 16U
	TPI ITFTTD0: ATB Interface 1 data2 Position.
#define	TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
	TPI ITFTTD0: ATB Interface 1 data2 Mask.
#define	TPI_ITFTTD0_ATB_IF1_data1_Pos 8U
	TPI ITFTTD0: ATB Interface 1 data1 Position.
#define	TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
	TPI ITFTTD0: ATB Interface 1 data1 Mask.
#define	TPI_ITFTTD0_ATB_IF1_data0_Pos 0U
	TPI ITFTTD0: ATB Interface 1 data0 Position.
#define	TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /<< TPI_ITFTTD0_ATB_IF1_data0_Pos/)
	TPI ITFTTD0: ATB Interface 1 data0 Mask.
#define	TPI_ITATBCTR2_AFVALID2S_Pos 1U
	TPI ITATBCTR2: AFVALID2S Position.
#define	TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)
	TPI ITATBCTR2: AFVALID2SS Mask.
#define	TPI_ITATBCTR2_AFVALID1S_Pos 1U
	TPI ITATBCTR2: AFVALID1S Position.
#define	TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)
	TPI ITATBCTR2: AFVALID1SS Mask.
#define	TPI_ITATBCTR2_ATREADY2S_Pos 0U
	TPI ITATBCTR2: ATREADY2S Position.
#define	TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2S_Pos/)
	TPI ITATBCTR2: ATREADY2S Mask.
#define	TPI_ITATBCTR2_ATREADY1S_Pos 0U
	TPI ITATBCTR2: ATREADY1S Position.
#define	TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1S_Pos/)
	TPI ITATBCTR2: ATREADY1S Mask.
#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U
	TPI ITFTTD1: ATB Interface 2 ATVALID Position.
#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)
	TPI ITFTTD1: ATB Interface 2 ATVALID Mask.
#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U
	TPI ITFTTD1: ATB Interface 2 byte count Position.
#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)
	TPI ITFTTD1: ATB Interface 2 byte count Mask.
#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U
	TPI ITFTTD1: ATB Interface 1 ATVALID Position.
#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)
	TPI ITFTTD1: ATB Interface 1 ATVALID Mask.
#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U
	TPI ITFTTD1: ATB Interface 1 byte count Position.
#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)
	TPI ITFTTD1: ATB Interface 1 byte countt Mask.
#define	TPI_ITFTTD1_ATB_IF2_data2_Pos 16U
	TPI ITFTTD1: ATB Interface 2 data2 Position.
#define	TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
	TPI ITFTTD1: ATB Interface 2 data2 Mask.
#define	TPI_ITFTTD1_ATB_IF2_data1_Pos 8U
	TPI ITFTTD1: ATB Interface 2 data1 Position.
#define	TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
	TPI ITFTTD1: ATB Interface 2 data1 Mask.
#define	TPI_ITFTTD1_ATB_IF2_data0_Pos 0U
	TPI ITFTTD1: ATB Interface 2 data0 Position.
#define	TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /<< TPI_ITFTTD1_ATB_IF2_data0_Pos/)
	TPI ITFTTD1: ATB Interface 2 data0 Mask.
#define	TPI_ITATBCTR0_AFVALID2S_Pos 1U
	TPI ITATBCTR0: AFVALID2S Position.
#define	TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)
	TPI ITATBCTR0: AFVALID2SS Mask.
#define	TPI_ITATBCTR0_AFVALID1S_Pos 1U
	TPI ITATBCTR0: AFVALID1S Position.
#define	TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)
	TPI ITATBCTR0: AFVALID1SS Mask.
#define	TPI_ITATBCTR0_ATREADY2S_Pos 0U
	TPI ITATBCTR0: ATREADY2S Position.
#define	TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2S_Pos/)
	TPI ITATBCTR0: ATREADY2S Mask.
#define	TPI_ITATBCTR0_ATREADY1S_Pos 0U
	TPI ITATBCTR0: ATREADY1S Position.
#define	TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1S_Pos/)
	TPI ITATBCTR0: ATREADY1S Mask.
#define	TPI_ITCTRL_Mode_Pos 0U
	TPI ITCTRL: Mode Position.
#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)
	TPI ITCTRL: Mode Mask.
#define	TPI_DEVID_NRZVALID_Pos 11U
	TPI DEVID: NRZVALID Position.
#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
	TPI DEVID: NRZVALID Mask.
#define	TPI_DEVID_MANCVALID_Pos 10U
	TPI DEVID: MANCVALID Position.
#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
	TPI DEVID: MANCVALID Mask.
#define	TPI_DEVID_PTINVALID_Pos 9U
	TPI DEVID: PTINVALID Position.
#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
	TPI DEVID: PTINVALID Mask.
#define	TPI_DEVID_FIFOSZ_Pos 6U
	TPI DEVID: FIFOSZ Position.
#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
	TPI DEVID: FIFOSZ Mask.
#define	TPI_DEVID_NrTraceInput_Pos 0U
	TPI DEVID: NrTraceInput Position.
#define	TPI_DEVID_NrTraceInput_Msk (0x3FUL /<< TPI_DEVID_NrTraceInput_Pos/)
	TPI DEVID: NrTraceInput Mask.
#define	TPI_DEVTYPE_SubType_Pos 4U
	TPI DEVTYPE: SubType Position.
#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)
	TPI DEVTYPE: SubType Mask.
#define	TPI_DEVTYPE_MajorType_Pos 0U
	TPI DEVTYPE: MajorType Position.
#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
	TPI DEVTYPE: MajorType Mask.
#define	TPI_ACPR_PRESCALER_Pos 0U
	TPI ACPR: PRESCALER Position.
#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)
	TPI ACPR: PRESCALER Mask.
#define	TPI_SPPR_TXMODE_Pos 0U
	TPI SPPR: TXMODE Position.
#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)
	TPI SPPR: TXMODE Mask.
#define	TPI_FFSR_FtNonStop_Pos 3U
	TPI FFSR: FtNonStop Position.
#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
	TPI FFSR: FtNonStop Mask.
#define	TPI_FFSR_TCPresent_Pos 2U
	TPI FFSR: TCPresent Position.
#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
	TPI FFSR: TCPresent Mask.
#define	TPI_FFSR_FtStopped_Pos 1U
	TPI FFSR: FtStopped Position.
#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
	TPI FFSR: FtStopped Mask.
#define	TPI_FFSR_FlInProg_Pos 0U
	TPI FFSR: FlInProg Position.
#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)
	TPI FFSR: FlInProg Mask.
#define	TPI_FFCR_TrigIn_Pos 8U
	TPI FFCR: TrigIn Position.
#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
	TPI FFCR: TrigIn Mask.
#define	TPI_FFCR_FOnMan_Pos 6U
	TPI FFCR: FOnMan Position.
#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
	TPI FFCR: FOnMan Mask.
#define	TPI_FFCR_EnFCont_Pos 1U
	TPI FFCR: EnFCont Position.
#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
	TPI FFCR: EnFCont Mask.
#define	TPI_TRIGGER_TRIGGER_Pos 0U
	TPI TRIGGER: TRIGGER Position.
#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)
	TPI TRIGGER: TRIGGER Mask.
#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U
	TPI ITFTTD0: ATB Interface 2 ATVALIDPosition.
#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)
	TPI ITFTTD0: ATB Interface 2 ATVALID Mask.
#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U
	TPI ITFTTD0: ATB Interface 2 byte count Position.
#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)
	TPI ITFTTD0: ATB Interface 2 byte count Mask.
#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U
	TPI ITFTTD0: ATB Interface 1 ATVALID Position.
#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)
	TPI ITFTTD0: ATB Interface 1 ATVALID Mask.
#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U
	TPI ITFTTD0: ATB Interface 1 byte count Position.
#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)
	TPI ITFTTD0: ATB Interface 1 byte countt Mask.
#define	TPI_ITFTTD0_ATB_IF1_data2_Pos 16U
	TPI ITFTTD0: ATB Interface 1 data2 Position.
#define	TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
	TPI ITFTTD0: ATB Interface 1 data2 Mask.
#define	TPI_ITFTTD0_ATB_IF1_data1_Pos 8U
	TPI ITFTTD0: ATB Interface 1 data1 Position.
#define	TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
	TPI ITFTTD0: ATB Interface 1 data1 Mask.
#define	TPI_ITFTTD0_ATB_IF1_data0_Pos 0U
	TPI ITFTTD0: ATB Interface 1 data0 Position.
#define	TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /<< TPI_ITFTTD0_ATB_IF1_data0_Pos/)
	TPI ITFTTD0: ATB Interface 1 data0 Mask.
#define	TPI_ITATBCTR2_AFVALID2S_Pos 1U
	TPI ITATBCTR2: AFVALID2S Position.
#define	TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)
	TPI ITATBCTR2: AFVALID2SS Mask.
#define	TPI_ITATBCTR2_AFVALID1S_Pos 1U
	TPI ITATBCTR2: AFVALID1S Position.
#define	TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)
	TPI ITATBCTR2: AFVALID1SS Mask.
#define	TPI_ITATBCTR2_ATREADY2S_Pos 0U
	TPI ITATBCTR2: ATREADY2S Position.
#define	TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2S_Pos/)
	TPI ITATBCTR2: ATREADY2S Mask.
#define	TPI_ITATBCTR2_ATREADY1S_Pos 0U
	TPI ITATBCTR2: ATREADY1S Position.
#define	TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1S_Pos/)
	TPI ITATBCTR2: ATREADY1S Mask.
#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U
	TPI ITFTTD1: ATB Interface 2 ATVALID Position.
#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)
	TPI ITFTTD1: ATB Interface 2 ATVALID Mask.
#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U
	TPI ITFTTD1: ATB Interface 2 byte count Position.
#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)
	TPI ITFTTD1: ATB Interface 2 byte count Mask.
#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U
	TPI ITFTTD1: ATB Interface 1 ATVALID Position.
#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)
	TPI ITFTTD1: ATB Interface 1 ATVALID Mask.
#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U
	TPI ITFTTD1: ATB Interface 1 byte count Position.
#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)
	TPI ITFTTD1: ATB Interface 1 byte countt Mask.
#define	TPI_ITFTTD1_ATB_IF2_data2_Pos 16U
	TPI ITFTTD1: ATB Interface 2 data2 Position.
#define	TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
	TPI ITFTTD1: ATB Interface 2 data2 Mask.
#define	TPI_ITFTTD1_ATB_IF2_data1_Pos 8U
	TPI ITFTTD1: ATB Interface 2 data1 Position.
#define	TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
	TPI ITFTTD1: ATB Interface 2 data1 Mask.
#define	TPI_ITFTTD1_ATB_IF2_data0_Pos 0U
	TPI ITFTTD1: ATB Interface 2 data0 Position.
#define	TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /<< TPI_ITFTTD1_ATB_IF2_data0_Pos/)
	TPI ITFTTD1: ATB Interface 2 data0 Mask.
#define	TPI_ITATBCTR0_AFVALID2S_Pos 1U
	TPI ITATBCTR0: AFVALID2S Position.
#define	TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)
	TPI ITATBCTR0: AFVALID2SS Mask.
#define	TPI_ITATBCTR0_AFVALID1S_Pos 1U
	TPI ITATBCTR0: AFVALID1S Position.
#define	TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)
	TPI ITATBCTR0: AFVALID1SS Mask.
#define	TPI_ITATBCTR0_ATREADY2S_Pos 0U
	TPI ITATBCTR0: ATREADY2S Position.
#define	TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2S_Pos/)
	TPI ITATBCTR0: ATREADY2S Mask.
#define	TPI_ITATBCTR0_ATREADY1S_Pos 0U
	TPI ITATBCTR0: ATREADY1S Position.
#define	TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1S_Pos/)
	TPI ITATBCTR0: ATREADY1S Mask.
#define	TPI_ITCTRL_Mode_Pos 0U
	TPI ITCTRL: Mode Position.
#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)
	TPI ITCTRL: Mode Mask.
#define	TPI_DEVID_NRZVALID_Pos 11U
	TPI DEVID: NRZVALID Position.
#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
	TPI DEVID: NRZVALID Mask.
#define	TPI_DEVID_MANCVALID_Pos 10U
	TPI DEVID: MANCVALID Position.
#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
	TPI DEVID: MANCVALID Mask.
#define	TPI_DEVID_PTINVALID_Pos 9U
	TPI DEVID: PTINVALID Position.
#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
	TPI DEVID: PTINVALID Mask.
#define	TPI_DEVID_FIFOSZ_Pos 6U
	TPI DEVID: FIFOSZ Position.
#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
	TPI DEVID: FIFOSZ Mask.
#define	TPI_DEVID_NrTraceInput_Pos 0U
	TPI DEVID: NrTraceInput Position.
#define	TPI_DEVID_NrTraceInput_Msk (0x3FUL /<< TPI_DEVID_NrTraceInput_Pos/)
	TPI DEVID: NrTraceInput Mask.
#define	TPI_DEVTYPE_SubType_Pos 4U
	TPI DEVTYPE: SubType Position.
#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)
	TPI DEVTYPE: SubType Mask.
#define	TPI_DEVTYPE_MajorType_Pos 0U
	TPI DEVTYPE: MajorType Position.
#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
	TPI DEVTYPE: MajorType Mask.
#define	TPI_ACPR_PRESCALER_Pos 0U
	TPI ACPR: PRESCALER Position.
#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)
	TPI ACPR: PRESCALER Mask.
#define	TPI_SPPR_TXMODE_Pos 0U
	TPI SPPR: TXMODE Position.
#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)
	TPI SPPR: TXMODE Mask.
#define	TPI_FFSR_FtNonStop_Pos 3U
	TPI FFSR: FtNonStop Position.
#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
	TPI FFSR: FtNonStop Mask.
#define	TPI_FFSR_TCPresent_Pos 2U
	TPI FFSR: TCPresent Position.
#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
	TPI FFSR: TCPresent Mask.
#define	TPI_FFSR_FtStopped_Pos 1U
	TPI FFSR: FtStopped Position.
#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
	TPI FFSR: FtStopped Mask.
#define	TPI_FFSR_FlInProg_Pos 0U
	TPI FFSR: FlInProg Position.
#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)
	TPI FFSR: FlInProg Mask.
#define	TPI_FFCR_TrigIn_Pos 8U
	TPI FFCR: TrigIn Position.
#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
	TPI FFCR: TrigIn Mask.
#define	TPI_FFCR_EnFCont_Pos 1U
	TPI FFCR: EnFCont Position.
#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
	TPI FFCR: EnFCont Mask.
#define	TPI_TRIGGER_TRIGGER_Pos 0U
	TPI TRIGGER: TRIGGER Position.
#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)
	TPI TRIGGER: TRIGGER Mask.
#define	TPI_ITCTRL_Mode_Pos 0U
	TPI ITCTRL: Mode Position.
#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)
	TPI ITCTRL: Mode Mask.
#define	TPI_DEVID_NRZVALID_Pos 11U
	TPI DEVID: NRZVALID Position.
#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
	TPI DEVID: NRZVALID Mask.
#define	TPI_DEVID_MANCVALID_Pos 10U
	TPI DEVID: MANCVALID Position.
#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
	TPI DEVID: MANCVALID Mask.
#define	TPI_DEVID_PTINVALID_Pos 9U
	TPI DEVID: PTINVALID Position.
#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
	TPI DEVID: PTINVALID Mask.
#define	TPI_DEVID_NrTraceInput_Pos 0U
	TPI DEVID: NrTraceInput Position.
#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)
	TPI DEVID: NrTraceInput Mask.
#define	TPI_DEVTYPE_SubType_Pos 4U
	TPI DEVTYPE: SubType Position.
#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)
	TPI DEVTYPE: SubType Mask.
#define	TPI_DEVTYPE_MajorType_Pos 0U
	TPI DEVTYPE: MajorType Position.
#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
	TPI DEVTYPE: MajorType Mask.
#define	TPI_SPPR_TXMODE_Pos 0U
	TPI SPPR: TXMODE Position.
#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)
	TPI SPPR: TXMODE Mask.
#define	TPI_FFSR_FtNonStop_Pos 3U
	TPI FFSR: FtNonStop Position.
#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
	TPI FFSR: FtNonStop Mask.
#define	TPI_FFSR_TCPresent_Pos 2U
	TPI FFSR: TCPresent Position.
#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
	TPI FFSR: TCPresent Mask.
#define	TPI_FFSR_FtStopped_Pos 1U
	TPI FFSR: FtStopped Position.
#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
	TPI FFSR: FtStopped Mask.
#define	TPI_FFSR_FlInProg_Pos 0U
	TPI FFSR: FlInProg Position.
#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)
	TPI FFSR: FlInProg Mask.
#define	TPI_FFCR_TrigIn_Pos 8U
	TPI FFCR: TrigIn Position.
#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
	TPI FFCR: TrigIn Mask.
#define	TPI_FFCR_FOnMan_Pos 6U
	TPI FFCR: FOnMan Position.
#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
	TPI FFCR: FOnMan Mask.
#define	TPI_DEVID_NRZVALID_Pos 11U
	TPI DEVID: NRZVALID Position.
#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
	TPI DEVID: NRZVALID Mask.
#define	TPI_DEVID_MANCVALID_Pos 10U
	TPI DEVID: MANCVALID Position.
#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
	TPI DEVID: MANCVALID Mask.
#define	TPI_DEVID_PTINVALID_Pos 9U
	TPI DEVID: PTINVALID Position.
#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
	TPI DEVID: PTINVALID Mask.
#define	TPI_DEVID_FIFOSZ_Pos 6U
	TPI DEVID: FIFO depth Position.
#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
	TPI DEVID: FIFO depth Mask.
#define	TPI_DEVTYPE_SubType_Pos 4U
	TPI DEVTYPE: SubType Position.
#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)
	TPI DEVTYPE: SubType Mask.
#define	TPI_DEVTYPE_MajorType_Pos 0U
	TPI DEVTYPE: MajorType Position.
#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
	TPI DEVTYPE: MajorType Mask.
#define	TPI_ACPR_PRESCALER_Pos 0U
	TPI ACPR: PRESCALER Position.
#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)
	TPI ACPR: PRESCALER Mask.
#define	TPI_SPPR_TXMODE_Pos 0U
	TPI SPPR: TXMODE Position.
#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)
	TPI SPPR: TXMODE Mask.
#define	TPI_FFSR_FtNonStop_Pos 3U
	TPI FFSR: FtNonStop Position.
#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
	TPI FFSR: FtNonStop Mask.
#define	TPI_FFSR_TCPresent_Pos 2U
	TPI FFSR: TCPresent Position.
#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
	TPI FFSR: TCPresent Mask.
#define	TPI_FFSR_FtStopped_Pos 1U
	TPI FFSR: FtStopped Position.
#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
	TPI FFSR: FtStopped Mask.
#define	TPI_FFSR_FlInProg_Pos 0U
	TPI FFSR: FlInProg Position.
#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)
	TPI FFSR: FlInProg Mask.
#define	TPI_FFCR_TrigIn_Pos 8U
	TPI FFCR: TrigIn Position.
#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
	TPI FFCR: TrigIn Mask.
#define	TPI_FFCR_EnFCont_Pos 1U
	TPI FFCR: EnFCont Position.
#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
	TPI FFCR: EnFCont Mask.
#define	TPI_TRIGGER_TRIGGER_Pos 0U
	TPI TRIGGER: TRIGGER Position.
#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)
	TPI TRIGGER: TRIGGER Mask.
#define	TPI_ITCTRL_Mode_Pos 0U
	TPI ITCTRL: Mode Position.
#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)
	TPI ITCTRL: Mode Mask.
#define	TPI_DEVID_NRZVALID_Pos 11U
	TPI DEVID: NRZVALID Position.
#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
	TPI DEVID: NRZVALID Mask.
#define	TPI_DEVID_MANCVALID_Pos 10U
	TPI DEVID: MANCVALID Position.
#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
	TPI DEVID: MANCVALID Mask.
#define	TPI_DEVID_PTINVALID_Pos 9U
	TPI DEVID: PTINVALID Position.
#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
	TPI DEVID: PTINVALID Mask.
#define	TPI_DEVID_NrTraceInput_Pos 0U
	TPI DEVID: NrTraceInput Position.
#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)
	TPI DEVID: NrTraceInput Mask.
#define	TPI_DEVTYPE_SubType_Pos 4U
	TPI DEVTYPE: SubType Position.
#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)
	TPI DEVTYPE: SubType Mask.
#define	TPI_DEVTYPE_MajorType_Pos 0U
	TPI DEVTYPE: MajorType Position.
#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
	TPI DEVTYPE: MajorType Mask.
#define	TPI_SPPR_TXMODE_Pos 0U
	TPI SPPR: TXMODE Position.
#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)
	TPI SPPR: TXMODE Mask.
#define	TPI_FFSR_FtNonStop_Pos 3U
	TPI FFSR: FtNonStop Position.
#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
	TPI FFSR: FtNonStop Mask.
#define	TPI_FFSR_TCPresent_Pos 2U
	TPI FFSR: TCPresent Position.
#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
	TPI FFSR: TCPresent Mask.
#define	TPI_FFSR_FtStopped_Pos 1U
	TPI FFSR: FtStopped Position.
#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
	TPI FFSR: FtStopped Mask.
#define	TPI_FFSR_FlInProg_Pos 0U
	TPI FFSR: FlInProg Position.
#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)
	TPI FFSR: FlInProg Mask.
#define	TPI_FFCR_TrigIn_Pos 8U
	TPI FFCR: TrigIn Position.
#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
	TPI FFCR: TrigIn Mask.
#define	TPI_FFCR_FOnMan_Pos 6U
	TPI FFCR: FOnMan Position.
#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
	TPI FFCR: FOnMan Mask.
#define	TPI_DEVID_NRZVALID_Pos 11U
	TPI DEVID: NRZVALID Position.
#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
	TPI DEVID: NRZVALID Mask.
#define	TPI_DEVID_MANCVALID_Pos 10U
	TPI DEVID: MANCVALID Position.
#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
	TPI DEVID: MANCVALID Mask.
#define	TPI_DEVID_PTINVALID_Pos 9U
	TPI DEVID: PTINVALID Position.
#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
	TPI DEVID: PTINVALID Mask.
#define	TPI_DEVID_FIFOSZ_Pos 6U
	TPI DEVID: FIFO depth Position.
#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
	TPI DEVID: FIFO depth Mask.
#define	TPI_DEVTYPE_SubType_Pos 4U
	TPI DEVTYPE: SubType Position.
#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)
	TPI DEVTYPE: SubType Mask.
#define	TPI_DEVTYPE_MajorType_Pos 0U
	TPI DEVTYPE: MajorType Position.
#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
	TPI DEVTYPE: MajorType Mask.
#define	TPI_ACPR_PRESCALER_Pos 0U
	TPI ACPR: PRESCALER Position.
#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)
	TPI ACPR: PRESCALER Mask.
#define	TPI_SPPR_TXMODE_Pos 0U
	TPI SPPR: TXMODE Position.
#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)
	TPI SPPR: TXMODE Mask.
#define	TPI_FFSR_FtNonStop_Pos 3U
	TPI FFSR: FtNonStop Position.
#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
	TPI FFSR: FtNonStop Mask.
#define	TPI_FFSR_TCPresent_Pos 2U
	TPI FFSR: TCPresent Position.
#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
	TPI FFSR: TCPresent Mask.
#define	TPI_FFSR_FtStopped_Pos 1U
	TPI FFSR: FtStopped Position.
#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
	TPI FFSR: FtStopped Mask.
#define	TPI_FFSR_FlInProg_Pos 0U
	TPI FFSR: FlInProg Position.
#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)
	TPI FFSR: FlInProg Mask.
#define	TPI_FFCR_TrigIn_Pos 8U
	TPI FFCR: TrigIn Position.
#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
	TPI FFCR: TrigIn Mask.
#define	TPI_FFCR_EnFCont_Pos 1U
	TPI FFCR: EnFCont Position.
#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
	TPI FFCR: EnFCont Mask.
#define	TPI_TRIGGER_TRIGGER_Pos 0U
	TPI TRIGGER: TRIGGER Position.
#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)
	TPI TRIGGER: TRIGGER Mask.
#define	TPI_ITCTRL_Mode_Pos 0U
	TPI ITCTRL: Mode Position.
#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)
	TPI ITCTRL: Mode Mask.
#define	TPI_DEVID_NRZVALID_Pos 11U
	TPI DEVID: NRZVALID Position.
#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
	TPI DEVID: NRZVALID Mask.
#define	TPI_DEVID_MANCVALID_Pos 10U
	TPI DEVID: MANCVALID Position.
#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
	TPI DEVID: MANCVALID Mask.
#define	TPI_DEVID_PTINVALID_Pos 9U
	TPI DEVID: PTINVALID Position.
#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
	TPI DEVID: PTINVALID Mask.
#define	TPI_DEVID_NrTraceInput_Pos 0U
	TPI DEVID: NrTraceInput Position.
#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)
	TPI DEVID: NrTraceInput Mask.
#define	TPI_DEVTYPE_SubType_Pos 4U
	TPI DEVTYPE: SubType Position.
#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)
	TPI DEVTYPE: SubType Mask.
#define	TPI_DEVTYPE_MajorType_Pos 0U
	TPI DEVTYPE: MajorType Position.
#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
	TPI DEVTYPE: MajorType Mask.
#define	TPI_ACPR_PRESCALER_Pos 0U
	TPI ACPR: PRESCALER Position.
#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)
	TPI ACPR: PRESCALER Mask.
#define	TPI_SPPR_TXMODE_Pos 0U
	TPI SPPR: TXMODE Position.
#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)
	TPI SPPR: TXMODE Mask.
#define	TPI_FFSR_FtNonStop_Pos 3U
	TPI FFSR: FtNonStop Position.
#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
	TPI FFSR: FtNonStop Mask.
#define	TPI_FFSR_TCPresent_Pos 2U
	TPI FFSR: TCPresent Position.
#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
	TPI FFSR: TCPresent Mask.
#define	TPI_FFSR_FtStopped_Pos 1U
	TPI FFSR: FtStopped Position.
#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
	TPI FFSR: FtStopped Mask.
#define	TPI_FFSR_FlInProg_Pos 0U
	TPI FFSR: FlInProg Position.
#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)
	TPI FFSR: FlInProg Mask.
#define	TPI_FFCR_TrigIn_Pos 8U
	TPI FFCR: TrigIn Position.
#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
	TPI FFCR: TrigIn Mask.
#define	TPI_FFCR_FOnMan_Pos 6U
	TPI FFCR: FOnMan Position.
#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
	TPI FFCR: FOnMan Mask.
#define	TPI_FFCR_EnFCont_Pos 1U
	TPI FFCR: EnFCont Position.
#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
	TPI FFCR: EnFCont Mask.
#define	TPI_TRIGGER_TRIGGER_Pos 0U
	TPI TRIGGER: TRIGGER Position.
#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)
	TPI TRIGGER: TRIGGER Mask.
#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U
	TPI ITFTTD0: ATB Interface 2 ATVALIDPosition.
#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)
	TPI ITFTTD0: ATB Interface 2 ATVALID Mask.
#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U
	TPI ITFTTD0: ATB Interface 2 byte count Position.
#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)
	TPI ITFTTD0: ATB Interface 2 byte count Mask.
#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U
	TPI ITFTTD0: ATB Interface 1 ATVALID Position.
#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)
	TPI ITFTTD0: ATB Interface 1 ATVALID Mask.
#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U
	TPI ITFTTD0: ATB Interface 1 byte count Position.
#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)
	TPI ITFTTD0: ATB Interface 1 byte countt Mask.
#define	TPI_ITFTTD0_ATB_IF1_data2_Pos 16U
	TPI ITFTTD0: ATB Interface 1 data2 Position.
#define	TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
	TPI ITFTTD0: ATB Interface 1 data2 Mask.
#define	TPI_ITFTTD0_ATB_IF1_data1_Pos 8U
	TPI ITFTTD0: ATB Interface 1 data1 Position.
#define	TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
	TPI ITFTTD0: ATB Interface 1 data1 Mask.
#define	TPI_ITFTTD0_ATB_IF1_data0_Pos 0U
	TPI ITFTTD0: ATB Interface 1 data0 Position.
#define	TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /<< TPI_ITFTTD0_ATB_IF1_data0_Pos/)
	TPI ITFTTD0: ATB Interface 1 data0 Mask.
#define	TPI_ITATBCTR2_AFVALID2S_Pos 1U
	TPI ITATBCTR2: AFVALID2S Position.
#define	TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)
	TPI ITATBCTR2: AFVALID2SS Mask.
#define	TPI_ITATBCTR2_AFVALID1S_Pos 1U
	TPI ITATBCTR2: AFVALID1S Position.
#define	TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)
	TPI ITATBCTR2: AFVALID1SS Mask.
#define	TPI_ITATBCTR2_ATREADY2S_Pos 0U
	TPI ITATBCTR2: ATREADY2S Position.
#define	TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2S_Pos/)
	TPI ITATBCTR2: ATREADY2S Mask.
#define	TPI_ITATBCTR2_ATREADY1S_Pos 0U
	TPI ITATBCTR2: ATREADY1S Position.
#define	TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1S_Pos/)
	TPI ITATBCTR2: ATREADY1S Mask.
#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U
	TPI ITFTTD1: ATB Interface 2 ATVALID Position.
#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)
	TPI ITFTTD1: ATB Interface 2 ATVALID Mask.
#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U
	TPI ITFTTD1: ATB Interface 2 byte count Position.
#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)
	TPI ITFTTD1: ATB Interface 2 byte count Mask.
#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U
	TPI ITFTTD1: ATB Interface 1 ATVALID Position.
#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)
	TPI ITFTTD1: ATB Interface 1 ATVALID Mask.
#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U
	TPI ITFTTD1: ATB Interface 1 byte count Position.
#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)
	TPI ITFTTD1: ATB Interface 1 byte countt Mask.
#define	TPI_ITFTTD1_ATB_IF2_data2_Pos 16U
	TPI ITFTTD1: ATB Interface 2 data2 Position.
#define	TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
	TPI ITFTTD1: ATB Interface 2 data2 Mask.
#define	TPI_ITFTTD1_ATB_IF2_data1_Pos 8U
	TPI ITFTTD1: ATB Interface 2 data1 Position.
#define	TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
	TPI ITFTTD1: ATB Interface 2 data1 Mask.
#define	TPI_ITFTTD1_ATB_IF2_data0_Pos 0U
	TPI ITFTTD1: ATB Interface 2 data0 Position.
#define	TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /<< TPI_ITFTTD1_ATB_IF2_data0_Pos/)
	TPI ITFTTD1: ATB Interface 2 data0 Mask.
#define	TPI_ITATBCTR0_AFVALID2S_Pos 1U
	TPI ITATBCTR0: AFVALID2S Position.
#define	TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)
	TPI ITATBCTR0: AFVALID2SS Mask.
#define	TPI_ITATBCTR0_AFVALID1S_Pos 1U
	TPI ITATBCTR0: AFVALID1S Position.
#define	TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)
	TPI ITATBCTR0: AFVALID1SS Mask.
#define	TPI_ITATBCTR0_ATREADY2S_Pos 0U
	TPI ITATBCTR0: ATREADY2S Position.
#define	TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2S_Pos/)
	TPI ITATBCTR0: ATREADY2S Mask.
#define	TPI_ITATBCTR0_ATREADY1S_Pos 0U
	TPI ITATBCTR0: ATREADY1S Position.
#define	TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1S_Pos/)
	TPI ITATBCTR0: ATREADY1S Mask.
#define	TPI_ITCTRL_Mode_Pos 0U
	TPI ITCTRL: Mode Position.
#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)
	TPI ITCTRL: Mode Mask.
#define	TPI_DEVID_NRZVALID_Pos 11U
	TPI DEVID: NRZVALID Position.
#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
	TPI DEVID: NRZVALID Mask.
#define	TPI_DEVID_MANCVALID_Pos 10U
	TPI DEVID: MANCVALID Position.
#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
	TPI DEVID: MANCVALID Mask.
#define	TPI_DEVID_PTINVALID_Pos 9U
	TPI DEVID: PTINVALID Position.
#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
	TPI DEVID: PTINVALID Mask.
#define	TPI_DEVID_FIFOSZ_Pos 6U
	TPI DEVID: FIFOSZ Position.
#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
	TPI DEVID: FIFOSZ Mask.
#define	TPI_DEVID_NrTraceInput_Pos 0U
	TPI DEVID: NrTraceInput Position.
#define	TPI_DEVID_NrTraceInput_Msk (0x3FUL /<< TPI_DEVID_NrTraceInput_Pos/)
	TPI DEVID: NrTraceInput Mask.
#define	TPI_DEVTYPE_SubType_Pos 4U
	TPI DEVTYPE: SubType Position.
#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)
	TPI DEVTYPE: SubType Mask.
#define	TPI_DEVTYPE_MajorType_Pos 0U
	TPI DEVTYPE: MajorType Position.
#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
	TPI DEVTYPE: MajorType Mask.
#define	TPI_FIFO0_ITM_ATVALID_Pos 29U
	TPI FIFO0: ITM_ATVALID Position.
#define	TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)
	TPI FIFO0: ITM_ATVALID Mask.
#define	TPI_FIFO0_ITM_bytecount_Pos 27U
	TPI FIFO0: ITM_bytecount Position.
#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
	TPI FIFO0: ITM_bytecount Mask.
#define	TPI_FIFO0_ETM_ATVALID_Pos 26U
	TPI FIFO0: ETM_ATVALID Position.
#define	TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)
	TPI FIFO0: ETM_ATVALID Mask.
#define	TPI_FIFO0_ETM_bytecount_Pos 24U
	TPI FIFO0: ETM_bytecount Position.
#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
	TPI FIFO0: ETM_bytecount Mask.
#define	TPI_FIFO0_ETM2_Pos 16U
	TPI FIFO0: ETM2 Position.
#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
	TPI FIFO0: ETM2 Mask.
#define	TPI_FIFO0_ETM1_Pos 8U
	TPI FIFO0: ETM1 Position.
#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
	TPI FIFO0: ETM1 Mask.
#define	TPI_FIFO0_ETM0_Pos 0U
	TPI FIFO0: ETM0 Position.
#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)
	TPI FIFO0: ETM0 Mask.
#define	TPI_ITATBCTR2_ATREADY2_Pos 0U
	TPI ITATBCTR2: ATREADY2 Position.
#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)
	TPI ITATBCTR2: ATREADY2 Mask.
#define	TPI_ITATBCTR2_ATREADY1_Pos 0U
	TPI ITATBCTR2: ATREADY1 Position.
#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)
	TPI ITATBCTR2: ATREADY1 Mask.
#define	TPI_FIFO1_ITM_ATVALID_Pos 29U
	TPI FIFO1: ITM_ATVALID Position.
#define	TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)
	TPI FIFO1: ITM_ATVALID Mask.
#define	TPI_FIFO1_ITM_bytecount_Pos 27U
	TPI FIFO1: ITM_bytecount Position.
#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
	TPI FIFO1: ITM_bytecount Mask.
#define	TPI_FIFO1_ETM_ATVALID_Pos 26U
	TPI FIFO1: ETM_ATVALID Position.
#define	TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)
	TPI FIFO1: ETM_ATVALID Mask.
#define	TPI_FIFO1_ETM_bytecount_Pos 24U
	TPI FIFO1: ETM_bytecount Position.
#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
	TPI FIFO1: ETM_bytecount Mask.
#define	TPI_FIFO1_ITM2_Pos 16U
	TPI FIFO1: ITM2 Position.
#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
	TPI FIFO1: ITM2 Mask.
#define	TPI_FIFO1_ITM1_Pos 8U
	TPI FIFO1: ITM1 Position.
#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
	TPI FIFO1: ITM1 Mask.
#define	TPI_FIFO1_ITM0_Pos 0U
	TPI FIFO1: ITM0 Position.
#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)
	TPI FIFO1: ITM0 Mask.
#define	TPI_ITATBCTR0_ATREADY2_Pos 0U
	TPI ITATBCTR0: ATREADY2 Position.
#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)
	TPI ITATBCTR0: ATREADY2 Mask.
#define	TPI_ITATBCTR0_ATREADY1_Pos 0U
	TPI ITATBCTR0: ATREADY1 Position.
#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)
	TPI ITATBCTR0: ATREADY1 Mask.
#define	TPI_DEVID_MinBufSz_Pos 6U
	TPI DEVID: MinBufSz Position.
#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
	TPI DEVID: MinBufSz Mask.
#define	TPI_DEVID_AsynClkIn_Pos 5U
	TPI DEVID: AsynClkIn Position.
#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
	TPI DEVID: AsynClkIn Mask.
#define	TPI_FIFO0_ITM_ATVALID_Pos 29U
	TPI FIFO0: ITM_ATVALID Position.
#define	TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)
	TPI FIFO0: ITM_ATVALID Mask.
#define	TPI_FIFO0_ITM_bytecount_Pos 27U
	TPI FIFO0: ITM_bytecount Position.
#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
	TPI FIFO0: ITM_bytecount Mask.
#define	TPI_FIFO0_ETM_ATVALID_Pos 26U
	TPI FIFO0: ETM_ATVALID Position.
#define	TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)
	TPI FIFO0: ETM_ATVALID Mask.
#define	TPI_FIFO0_ETM_bytecount_Pos 24U
	TPI FIFO0: ETM_bytecount Position.
#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
	TPI FIFO0: ETM_bytecount Mask.
#define	TPI_FIFO0_ETM2_Pos 16U
	TPI FIFO0: ETM2 Position.
#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
	TPI FIFO0: ETM2 Mask.
#define	TPI_FIFO0_ETM1_Pos 8U
	TPI FIFO0: ETM1 Position.
#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
	TPI FIFO0: ETM1 Mask.
#define	TPI_FIFO0_ETM0_Pos 0U
	TPI FIFO0: ETM0 Position.
#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)
	TPI FIFO0: ETM0 Mask.
#define	TPI_ITATBCTR2_ATREADY2_Pos 0U
	TPI ITATBCTR2: ATREADY2 Position.
#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)
	TPI ITATBCTR2: ATREADY2 Mask.
#define	TPI_ITATBCTR2_ATREADY1_Pos 0U
	TPI ITATBCTR2: ATREADY1 Position.
#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)
	TPI ITATBCTR2: ATREADY1 Mask.
#define	TPI_FIFO1_ITM_ATVALID_Pos 29U
	TPI FIFO1: ITM_ATVALID Position.
#define	TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)
	TPI FIFO1: ITM_ATVALID Mask.
#define	TPI_FIFO1_ITM_bytecount_Pos 27U
	TPI FIFO1: ITM_bytecount Position.
#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
	TPI FIFO1: ITM_bytecount Mask.
#define	TPI_FIFO1_ETM_ATVALID_Pos 26U
	TPI FIFO1: ETM_ATVALID Position.
#define	TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)
	TPI FIFO1: ETM_ATVALID Mask.
#define	TPI_FIFO1_ETM_bytecount_Pos 24U
	TPI FIFO1: ETM_bytecount Position.
#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
	TPI FIFO1: ETM_bytecount Mask.
#define	TPI_FIFO1_ITM2_Pos 16U
	TPI FIFO1: ITM2 Position.
#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
	TPI FIFO1: ITM2 Mask.
#define	TPI_FIFO1_ITM1_Pos 8U
	TPI FIFO1: ITM1 Position.
#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
	TPI FIFO1: ITM1 Mask.
#define	TPI_FIFO1_ITM0_Pos 0U
	TPI FIFO1: ITM0 Position.
#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)
	TPI FIFO1: ITM0 Mask.
#define	TPI_ITATBCTR0_ATREADY2_Pos 0U
	TPI ITATBCTR0: ATREADY2 Position.
#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)
	TPI ITATBCTR0: ATREADY2 Mask.
#define	TPI_ITATBCTR0_ATREADY1_Pos 0U
	TPI ITATBCTR0: ATREADY1 Position.
#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)
	TPI ITATBCTR0: ATREADY1 Mask.
#define	TPI_DEVID_MinBufSz_Pos 6U
	TPI DEVID: MinBufSz Position.
#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
	TPI DEVID: MinBufSz Mask.
#define	TPI_DEVID_AsynClkIn_Pos 5U
	TPI DEVID: AsynClkIn Position.
#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
	TPI DEVID: AsynClkIn Mask.
#define	TPI_FIFO0_ITM_ATVALID_Pos 29U
	TPI FIFO0: ITM_ATVALID Position.
#define	TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)
	TPI FIFO0: ITM_ATVALID Mask.
#define	TPI_FIFO0_ITM_bytecount_Pos 27U
	TPI FIFO0: ITM_bytecount Position.
#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
	TPI FIFO0: ITM_bytecount Mask.
#define	TPI_FIFO0_ETM_ATVALID_Pos 26U
	TPI FIFO0: ETM_ATVALID Position.
#define	TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)
	TPI FIFO0: ETM_ATVALID Mask.
#define	TPI_FIFO0_ETM_bytecount_Pos 24U
	TPI FIFO0: ETM_bytecount Position.
#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
	TPI FIFO0: ETM_bytecount Mask.
#define	TPI_FIFO0_ETM2_Pos 16U
	TPI FIFO0: ETM2 Position.
#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
	TPI FIFO0: ETM2 Mask.
#define	TPI_FIFO0_ETM1_Pos 8U
	TPI FIFO0: ETM1 Position.
#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
	TPI FIFO0: ETM1 Mask.
#define	TPI_FIFO0_ETM0_Pos 0U
	TPI FIFO0: ETM0 Position.
#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)
	TPI FIFO0: ETM0 Mask.
#define	TPI_ITATBCTR2_ATREADY2_Pos 0U
	TPI ITATBCTR2: ATREADY2 Position.
#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)
	TPI ITATBCTR2: ATREADY2 Mask.
#define	TPI_ITATBCTR2_ATREADY1_Pos 0U
	TPI ITATBCTR2: ATREADY1 Position.
#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)
	TPI ITATBCTR2: ATREADY1 Mask.
#define	TPI_FIFO1_ITM_ATVALID_Pos 29U
	TPI FIFO1: ITM_ATVALID Position.
#define	TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)
	TPI FIFO1: ITM_ATVALID Mask.
#define	TPI_FIFO1_ITM_bytecount_Pos 27U
	TPI FIFO1: ITM_bytecount Position.
#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
	TPI FIFO1: ITM_bytecount Mask.
#define	TPI_FIFO1_ETM_ATVALID_Pos 26U
	TPI FIFO1: ETM_ATVALID Position.
#define	TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)
	TPI FIFO1: ETM_ATVALID Mask.
#define	TPI_FIFO1_ETM_bytecount_Pos 24U
	TPI FIFO1: ETM_bytecount Position.
#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
	TPI FIFO1: ETM_bytecount Mask.
#define	TPI_FIFO1_ITM2_Pos 16U
	TPI FIFO1: ITM2 Position.
#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
	TPI FIFO1: ITM2 Mask.
#define	TPI_FIFO1_ITM1_Pos 8U
	TPI FIFO1: ITM1 Position.
#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
	TPI FIFO1: ITM1 Mask.
#define	TPI_FIFO1_ITM0_Pos 0U
	TPI FIFO1: ITM0 Position.
#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)
	TPI FIFO1: ITM0 Mask.
#define	TPI_ITATBCTR0_ATREADY2_Pos 0U
	TPI ITATBCTR0: ATREADY2 Position.
#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)
	TPI ITATBCTR0: ATREADY2 Mask.
#define	TPI_ITATBCTR0_ATREADY1_Pos 0U
	TPI ITATBCTR0: ATREADY1 Position.
#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)
	TPI ITATBCTR0: ATREADY1 Mask.
#define	TPI_DEVID_MinBufSz_Pos 6U
	TPI DEVID: MinBufSz Position.
#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
	TPI DEVID: MinBufSz Mask.
#define	TPI_DEVID_AsynClkIn_Pos 5U
	TPI DEVID: AsynClkIn Position.
#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
	TPI DEVID: AsynClkIn Mask.
#define	TPI_FIFO0_ITM_ATVALID_Pos 29U
	TPI FIFO0: ITM_ATVALID Position.
#define	TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)
	TPI FIFO0: ITM_ATVALID Mask.
#define	TPI_FIFO0_ITM_bytecount_Pos 27U
	TPI FIFO0: ITM_bytecount Position.
#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
	TPI FIFO0: ITM_bytecount Mask.
#define	TPI_FIFO0_ETM_ATVALID_Pos 26U
	TPI FIFO0: ETM_ATVALID Position.
#define	TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)
	TPI FIFO0: ETM_ATVALID Mask.
#define	TPI_FIFO0_ETM_bytecount_Pos 24U
	TPI FIFO0: ETM_bytecount Position.
#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
	TPI FIFO0: ETM_bytecount Mask.
#define	TPI_FIFO0_ETM2_Pos 16U
	TPI FIFO0: ETM2 Position.
#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
	TPI FIFO0: ETM2 Mask.
#define	TPI_FIFO0_ETM1_Pos 8U
	TPI FIFO0: ETM1 Position.
#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
	TPI FIFO0: ETM1 Mask.
#define	TPI_FIFO0_ETM0_Pos 0U
	TPI FIFO0: ETM0 Position.
#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)
	TPI FIFO0: ETM0 Mask.
#define	TPI_ITATBCTR2_ATREADY2_Pos 0U
	TPI ITATBCTR2: ATREADY2 Position.
#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)
	TPI ITATBCTR2: ATREADY2 Mask.
#define	TPI_ITATBCTR2_ATREADY1_Pos 0U
	TPI ITATBCTR2: ATREADY1 Position.
#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)
	TPI ITATBCTR2: ATREADY1 Mask.
#define	TPI_FIFO1_ITM_ATVALID_Pos 29U
	TPI FIFO1: ITM_ATVALID Position.
#define	TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)
	TPI FIFO1: ITM_ATVALID Mask.
#define	TPI_FIFO1_ITM_bytecount_Pos 27U
	TPI FIFO1: ITM_bytecount Position.
#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
	TPI FIFO1: ITM_bytecount Mask.
#define	TPI_FIFO1_ETM_ATVALID_Pos 26U
	TPI FIFO1: ETM_ATVALID Position.
#define	TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)
	TPI FIFO1: ETM_ATVALID Mask.
#define	TPI_FIFO1_ETM_bytecount_Pos 24U
	TPI FIFO1: ETM_bytecount Position.
#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
	TPI FIFO1: ETM_bytecount Mask.
#define	TPI_FIFO1_ITM2_Pos 16U
	TPI FIFO1: ITM2 Position.
#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
	TPI FIFO1: ITM2 Mask.
#define	TPI_FIFO1_ITM1_Pos 8U
	TPI FIFO1: ITM1 Position.
#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
	TPI FIFO1: ITM1 Mask.
#define	TPI_FIFO1_ITM0_Pos 0U
	TPI FIFO1: ITM0 Position.
#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)
	TPI FIFO1: ITM0 Mask.
#define	TPI_ITATBCTR0_ATREADY2_Pos 0U
	TPI ITATBCTR0: ATREADY2 Position.
#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)
	TPI ITATBCTR0: ATREADY2 Mask.
#define	TPI_ITATBCTR0_ATREADY1_Pos 0U
	TPI ITATBCTR0: ATREADY1 Position.
#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)
	TPI ITATBCTR0: ATREADY1 Mask.
#define	TPI_DEVID_MinBufSz_Pos 6U
	TPI DEVID: MinBufSz Position.
#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
	TPI DEVID: MinBufSz Mask.
#define	TPI_DEVID_AsynClkIn_Pos 5U
	TPI DEVID: AsynClkIn Position.
#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
	TPI DEVID: AsynClkIn Mask.

Detailed Description

Type definitions for the Trace Port Interface (TPI).

Macro Definition Documentation

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [1/2]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Mask

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Mask

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Mask

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Mask

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Mask

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Mask

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1064 of file core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [2/2]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Mask

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Mask

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Mask

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Mask

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Mask

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1842 of file core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [1/2]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Position

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Position

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Position

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Position

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Position

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Position

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1063 of file core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [2/2]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Position

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Position

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Position

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Position

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Position

Deprecated: CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1841 of file core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [1/2]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1058 of file core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [2/2]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1836 of file core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [1/2]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1057 of file core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [2/2]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Deprecated: CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1835 of file core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [1/2]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Mask

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Mask

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Mask

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Mask

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Mask

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Mask

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1067 of file core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [2/2]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Mask

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Mask

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Mask

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Mask

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Mask

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1845 of file core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [1/2]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Position

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Position

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Position

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Position

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Position

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Position

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1066 of file core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [2/2]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Position

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Position

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Position

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Position

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Position

Deprecated: CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1844 of file core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [1/2]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1061 of file core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [2/2]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1839 of file core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [1/2]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Position

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Position

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Position

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Position

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Position

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Position

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1060 of file core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [2/2]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Position

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Position

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Position

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Position

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Position

Deprecated: CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1838 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [1/2]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

Deprecated: CoreDebug DHCSR: S_RESTART_ST Mask

Deprecated: CoreDebug DHCSR: S_RESTART_ST Mask

Deprecated: CoreDebug DHCSR: S_RESTART_ST Mask

Deprecated: CoreDebug DHCSR: S_RESTART_ST Mask

Deprecated: CoreDebug DHCSR: S_RESTART_ST Mask

Deprecated: CoreDebug DHCSR: S_RESTART_ST Mask

Deprecated: CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1007 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [2/2]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

Deprecated: CoreDebug DHCSR: S_RESTART_ST Mask

Deprecated: CoreDebug DHCSR: S_RESTART_ST Mask

Deprecated: CoreDebug DHCSR: S_RESTART_ST Mask

Deprecated: CoreDebug DHCSR: S_RESTART_ST Mask

Deprecated: CoreDebug DHCSR: S_RESTART_ST Mask

Deprecated: CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1752 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [1/2]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

Deprecated: CoreDebug DHCSR: S_RESTART_ST Position

Deprecated: CoreDebug DHCSR: S_RESTART_ST Position

Deprecated: CoreDebug DHCSR: S_RESTART_ST Position

Deprecated: CoreDebug DHCSR: S_RESTART_ST Position

Deprecated: CoreDebug DHCSR: S_RESTART_ST Position

Deprecated: CoreDebug DHCSR: S_RESTART_ST Position

Deprecated: CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1006 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [2/2]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

Deprecated: CoreDebug DHCSR: S_RESTART_ST Position

Deprecated: CoreDebug DHCSR: S_RESTART_ST Position

Deprecated: CoreDebug DHCSR: S_RESTART_ST Position

Deprecated: CoreDebug DHCSR: S_RESTART_ST Position

Deprecated: CoreDebug DHCSR: S_RESTART_ST Position

Deprecated: CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1751 of file core_armv8mml.h.

◆ CoreDebug_DSCSR_CDS_Msk [1/2]

#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

Deprecated: CoreDebug DSCSR: CDS Mask

Deprecated: CoreDebug DSCSR: CDS Mask

Deprecated: CoreDebug DSCSR: CDS Mask

Deprecated: CoreDebug DSCSR: CDS Mask

Deprecated: CoreDebug DSCSR: CDS Mask

Deprecated: CoreDebug DSCSR: CDS Mask

Deprecated: CoreDebug DSCSR: CDS Mask

Definition at line 1071 of file core_armv8mbl.h.

◆ CoreDebug_DSCSR_CDS_Msk [2/2]

#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

Deprecated: CoreDebug DSCSR: CDS Mask

Deprecated: CoreDebug DSCSR: CDS Mask

Deprecated: CoreDebug DSCSR: CDS Mask

Deprecated: CoreDebug DSCSR: CDS Mask

Deprecated: CoreDebug DSCSR: CDS Mask

Deprecated: CoreDebug DSCSR: CDS Mask

Definition at line 1849 of file core_armv8mml.h.

◆ CoreDebug_DSCSR_CDS_Pos [1/2]

#define CoreDebug_DSCSR_CDS_Pos 16U

Deprecated: CoreDebug DSCSR: CDS Position

Deprecated: CoreDebug DSCSR: CDS Position

Deprecated: CoreDebug DSCSR: CDS Position

Deprecated: CoreDebug DSCSR: CDS Position

Deprecated: CoreDebug DSCSR: CDS Position

Deprecated: CoreDebug DSCSR: CDS Position

Deprecated: CoreDebug DSCSR: CDS Position

Definition at line 1070 of file core_armv8mbl.h.

◆ CoreDebug_DSCSR_CDS_Pos [2/2]

#define CoreDebug_DSCSR_CDS_Pos 16U

Deprecated: CoreDebug DSCSR: CDS Position

Deprecated: CoreDebug DSCSR: CDS Position

Deprecated: CoreDebug DSCSR: CDS Position

Deprecated: CoreDebug DSCSR: CDS Position

Deprecated: CoreDebug DSCSR: CDS Position

Deprecated: CoreDebug DSCSR: CDS Position

Definition at line 1848 of file core_armv8mml.h.

◆ CoreDebug_DSCSR_SBRSEL_Msk [1/2]

#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

Deprecated: CoreDebug DSCSR: SBRSEL Mask

Deprecated: CoreDebug DSCSR: SBRSEL Mask

Deprecated: CoreDebug DSCSR: SBRSEL Mask

Deprecated: CoreDebug DSCSR: SBRSEL Mask

Deprecated: CoreDebug DSCSR: SBRSEL Mask

Deprecated: CoreDebug DSCSR: SBRSEL Mask

Deprecated: CoreDebug DSCSR: SBRSEL Mask

Definition at line 1074 of file core_armv8mbl.h.

◆ CoreDebug_DSCSR_SBRSEL_Msk [2/2]

#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

Deprecated: CoreDebug DSCSR: SBRSEL Mask

Deprecated: CoreDebug DSCSR: SBRSEL Mask

Deprecated: CoreDebug DSCSR: SBRSEL Mask

Deprecated: CoreDebug DSCSR: SBRSEL Mask

Deprecated: CoreDebug DSCSR: SBRSEL Mask

Deprecated: CoreDebug DSCSR: SBRSEL Mask

Definition at line 1852 of file core_armv8mml.h.

◆ CoreDebug_DSCSR_SBRSEL_Pos [1/2]

#define CoreDebug_DSCSR_SBRSEL_Pos 1U

Deprecated: CoreDebug DSCSR: SBRSEL Position

Deprecated: CoreDebug DSCSR: SBRSEL Position

Deprecated: CoreDebug DSCSR: SBRSEL Position

Deprecated: CoreDebug DSCSR: SBRSEL Position

Deprecated: CoreDebug DSCSR: SBRSEL Position

Deprecated: CoreDebug DSCSR: SBRSEL Position

Deprecated: CoreDebug DSCSR: SBRSEL Position

Definition at line 1073 of file core_armv8mbl.h.

◆ CoreDebug_DSCSR_SBRSEL_Pos [2/2]

#define CoreDebug_DSCSR_SBRSEL_Pos 1U

Deprecated: CoreDebug DSCSR: SBRSEL Position

Deprecated: CoreDebug DSCSR: SBRSEL Position

Deprecated: CoreDebug DSCSR: SBRSEL Position

Deprecated: CoreDebug DSCSR: SBRSEL Position

Deprecated: CoreDebug DSCSR: SBRSEL Position

Deprecated: CoreDebug DSCSR: SBRSEL Position

Definition at line 1851 of file core_armv8mml.h.

◆ CoreDebug_DSCSR_SBRSELEN_Msk [1/2]

#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)

Deprecated: CoreDebug DSCSR: SBRSELEN Mask

Deprecated: CoreDebug DSCSR: SBRSELEN Mask

Deprecated: CoreDebug DSCSR: SBRSELEN Mask

Deprecated: CoreDebug DSCSR: SBRSELEN Mask

Deprecated: CoreDebug DSCSR: SBRSELEN Mask

Deprecated: CoreDebug DSCSR: SBRSELEN Mask

Deprecated: CoreDebug DSCSR: SBRSELEN Mask

Definition at line 1077 of file core_armv8mbl.h.

◆ CoreDebug_DSCSR_SBRSELEN_Msk [2/2]

#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)

Deprecated: CoreDebug DSCSR: SBRSELEN Mask

Deprecated: CoreDebug DSCSR: SBRSELEN Mask

Deprecated: CoreDebug DSCSR: SBRSELEN Mask

Deprecated: CoreDebug DSCSR: SBRSELEN Mask

Deprecated: CoreDebug DSCSR: SBRSELEN Mask

Deprecated: CoreDebug DSCSR: SBRSELEN Mask

Definition at line 1855 of file core_armv8mml.h.

◆ CoreDebug_DSCSR_SBRSELEN_Pos [1/2]

#define CoreDebug_DSCSR_SBRSELEN_Pos 0U

Deprecated: CoreDebug DSCSR: SBRSELEN Position

Deprecated: CoreDebug DSCSR: SBRSELEN Position

Deprecated: CoreDebug DSCSR: SBRSELEN Position

Deprecated: CoreDebug DSCSR: SBRSELEN Position

Deprecated: CoreDebug DSCSR: SBRSELEN Position

Deprecated: CoreDebug DSCSR: SBRSELEN Position

Deprecated: CoreDebug DSCSR: SBRSELEN Position

Definition at line 1076 of file core_armv8mbl.h.

◆ CoreDebug_DSCSR_SBRSELEN_Pos [2/2]

#define CoreDebug_DSCSR_SBRSELEN_Pos 0U

Deprecated: CoreDebug DSCSR: SBRSELEN Position

Deprecated: CoreDebug DSCSR: SBRSELEN Position

Deprecated: CoreDebug DSCSR: SBRSELEN Position

Deprecated: CoreDebug DSCSR: SBRSELEN Position

Deprecated: CoreDebug DSCSR: SBRSELEN Position

Deprecated: CoreDebug DSCSR: SBRSELEN Position

Definition at line 1854 of file core_armv8mml.h.

◆ TPI_ACPR_PRESCALER_Msk [1/8]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask.

Definition at line 757 of file core_cm23.h.

◆ TPI_ACPR_PRESCALER_Msk [2/8]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask.

Definition at line 1023 of file core_cm3.h.

◆ TPI_ACPR_PRESCALER_Msk [3/8]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask.

Definition at line 1333 of file core_cm33.h.

◆ TPI_ACPR_PRESCALER_Msk [4/8]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask.

Definition at line 1333 of file core_cm35p.h.

◆ TPI_ACPR_PRESCALER_Msk [5/8]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask.

Definition at line 1081 of file core_cm4.h.

◆ TPI_ACPR_PRESCALER_Msk [6/8]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask.

Definition at line 1308 of file core_cm7.h.

◆ TPI_ACPR_PRESCALER_Msk [7/8]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask.

Definition at line 1008 of file core_sc300.h.

◆ TPI_ACPR_PRESCALER_Msk [8/8]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask.

Definition at line 1391 of file core_starmc1.h.

◆ TPI_ACPR_PRESCALER_Pos [1/8]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position.

Definition at line 756 of file core_cm23.h.

◆ TPI_ACPR_PRESCALER_Pos [2/8]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position.

Definition at line 1022 of file core_cm3.h.

◆ TPI_ACPR_PRESCALER_Pos [3/8]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position.

Definition at line 1332 of file core_cm33.h.

◆ TPI_ACPR_PRESCALER_Pos [4/8]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position.

Definition at line 1332 of file core_cm35p.h.

◆ TPI_ACPR_PRESCALER_Pos [5/8]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position.

Definition at line 1080 of file core_cm4.h.

◆ TPI_ACPR_PRESCALER_Pos [6/8]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position.

Definition at line 1307 of file core_cm7.h.

◆ TPI_ACPR_PRESCALER_Pos [7/8]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position.

Definition at line 1007 of file core_sc300.h.

◆ TPI_ACPR_PRESCALER_Pos [8/8]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position.

Definition at line 1390 of file core_starmc1.h.

◆ TPI_ACPR_SWOSCALER_Msk [1/5]

#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask.

Definition at line 1387 of file core_armv81mml.h.

◆ TPI_ACPR_SWOSCALER_Msk [2/5]

#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask.

Definition at line 749 of file core_armv8mbl.h.

◆ TPI_ACPR_SWOSCALER_Msk [3/5]

#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask.

Definition at line 1325 of file core_armv8mml.h.

◆ TPI_ACPR_SWOSCALER_Msk [4/5]

#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask.

Definition at line 1882 of file core_cm55.h.

◆ TPI_ACPR_SWOSCALER_Msk [5/5]

#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask.

Definition at line 1787 of file core_cm85.h.

◆ TPI_ACPR_SWOSCALER_Pos [1/5]

#define TPI_ACPR_SWOSCALER_Pos 0U

TPI ACPR: SWOSCALER Position.

Definition at line 1386 of file core_armv81mml.h.

◆ TPI_ACPR_SWOSCALER_Pos [2/5]

#define TPI_ACPR_SWOSCALER_Pos 0U

TPI ACPR: SWOSCALER Position.

Definition at line 748 of file core_armv8mbl.h.

◆ TPI_ACPR_SWOSCALER_Pos [3/5]

#define TPI_ACPR_SWOSCALER_Pos 0U

TPI ACPR: SWOSCALER Position.

Definition at line 1324 of file core_armv8mml.h.

◆ TPI_ACPR_SWOSCALER_Pos [4/5]

#define TPI_ACPR_SWOSCALER_Pos 0U

TPI ACPR: SWOSCALER Position.

Definition at line 1881 of file core_cm55.h.

◆ TPI_ACPR_SWOSCALER_Pos [5/5]

#define TPI_ACPR_SWOSCALER_Pos 0U

TPI ACPR: SWOSCALER Position.

Definition at line 1786 of file core_cm85.h.

◆ TPI_DEVID_AsynClkIn_Msk [1/4]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask.

Definition at line 1129 of file core_cm3.h.

◆ TPI_DEVID_AsynClkIn_Msk [2/4]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask.

Definition at line 1187 of file core_cm4.h.

◆ TPI_DEVID_AsynClkIn_Msk [3/4]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask.

Definition at line 1414 of file core_cm7.h.

◆ TPI_DEVID_AsynClkIn_Msk [4/4]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask.

Definition at line 1114 of file core_sc300.h.

◆ TPI_DEVID_AsynClkIn_Pos [1/4]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position.

Definition at line 1128 of file core_cm3.h.

◆ TPI_DEVID_AsynClkIn_Pos [2/4]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position.

Definition at line 1186 of file core_cm4.h.

◆ TPI_DEVID_AsynClkIn_Pos [3/4]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position.

Definition at line 1413 of file core_cm7.h.

◆ TPI_DEVID_AsynClkIn_Pos [4/4]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position.

Definition at line 1113 of file core_sc300.h.

◆ TPI_DEVID_FIFOSZ_Msk [1/9]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask.

TPI DEVID: FIFOSZ Mask.

Definition at line 1441 of file core_armv81mml.h.

◆ TPI_DEVID_FIFOSZ_Msk [2/9]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask.

TPI DEVID: FIFOSZ Mask.

Definition at line 803 of file core_armv8mbl.h.

◆ TPI_DEVID_FIFOSZ_Msk [3/9]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask.

TPI DEVID: FIFOSZ Mask.

Definition at line 1379 of file core_armv8mml.h.

◆ TPI_DEVID_FIFOSZ_Msk [4/9]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFOSZ Mask.

TPI DEVID: FIFO depth Mask.

Definition at line 875 of file core_cm23.h.

◆ TPI_DEVID_FIFOSZ_Msk [5/9]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFOSZ Mask.

TPI DEVID: FIFO depth Mask.

Definition at line 1451 of file core_cm33.h.

◆ TPI_DEVID_FIFOSZ_Msk [6/9]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFOSZ Mask.

TPI DEVID: FIFO depth Mask.

Definition at line 1451 of file core_cm35p.h.

◆ TPI_DEVID_FIFOSZ_Msk [7/9]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask.

TPI DEVID: FIFOSZ Mask.

Definition at line 1936 of file core_cm55.h.

◆ TPI_DEVID_FIFOSZ_Msk [8/9]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask.

TPI DEVID: FIFOSZ Mask.

Definition at line 1841 of file core_cm85.h.

◆ TPI_DEVID_FIFOSZ_Msk [9/9]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFOSZ Mask.

Definition at line 1509 of file core_starmc1.h.

◆ TPI_DEVID_FIFOSZ_Pos [1/9]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFO depth Position.

TPI DEVID: FIFOSZ Position.

Definition at line 1440 of file core_armv81mml.h.

◆ TPI_DEVID_FIFOSZ_Pos [2/9]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFO depth Position.

TPI DEVID: FIFOSZ Position.

Definition at line 802 of file core_armv8mbl.h.

◆ TPI_DEVID_FIFOSZ_Pos [3/9]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFO depth Position.

TPI DEVID: FIFOSZ Position.

Definition at line 1378 of file core_armv8mml.h.

◆ TPI_DEVID_FIFOSZ_Pos [4/9]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFOSZ Position.

TPI DEVID: FIFO depth Position.

Definition at line 874 of file core_cm23.h.

◆ TPI_DEVID_FIFOSZ_Pos [5/9]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFOSZ Position.

TPI DEVID: FIFO depth Position.

Definition at line 1450 of file core_cm33.h.

◆ TPI_DEVID_FIFOSZ_Pos [6/9]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFOSZ Position.

TPI DEVID: FIFO depth Position.

Definition at line 1450 of file core_cm35p.h.

◆ TPI_DEVID_FIFOSZ_Pos [7/9]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFO depth Position.

TPI DEVID: FIFOSZ Position.

Definition at line 1935 of file core_cm55.h.

◆ TPI_DEVID_FIFOSZ_Pos [8/9]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFO depth Position.

TPI DEVID: FIFOSZ Position.

Definition at line 1840 of file core_cm85.h.

◆ TPI_DEVID_FIFOSZ_Pos [9/9]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFOSZ Position.

Definition at line 1508 of file core_starmc1.h.

◆ TPI_DEVID_MANCVALID_Msk [1/13]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask.

Definition at line 1435 of file core_armv81mml.h.

◆ TPI_DEVID_MANCVALID_Msk [2/13]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask.

Definition at line 797 of file core_armv8mbl.h.

◆ TPI_DEVID_MANCVALID_Msk [3/13]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask.

Definition at line 1373 of file core_armv8mml.h.

◆ TPI_DEVID_MANCVALID_Msk [4/13]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask.

Definition at line 869 of file core_cm23.h.

◆ TPI_DEVID_MANCVALID_Msk [5/13]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask.

Definition at line 1120 of file core_cm3.h.

◆ TPI_DEVID_MANCVALID_Msk [6/13]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask.

Definition at line 1445 of file core_cm33.h.

◆ TPI_DEVID_MANCVALID_Msk [7/13]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask.

Definition at line 1445 of file core_cm35p.h.

◆ TPI_DEVID_MANCVALID_Msk [8/13]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask.

Definition at line 1178 of file core_cm4.h.

◆ TPI_DEVID_MANCVALID_Msk [9/13]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask.

Definition at line 1930 of file core_cm55.h.

◆ TPI_DEVID_MANCVALID_Msk [10/13]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask.

Definition at line 1405 of file core_cm7.h.

◆ TPI_DEVID_MANCVALID_Msk [11/13]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask.

Definition at line 1835 of file core_cm85.h.

◆ TPI_DEVID_MANCVALID_Msk [12/13]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask.

Definition at line 1105 of file core_sc300.h.

◆ TPI_DEVID_MANCVALID_Msk [13/13]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask.

Definition at line 1503 of file core_starmc1.h.

◆ TPI_DEVID_MANCVALID_Pos [1/13]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position.

Definition at line 1434 of file core_armv81mml.h.

◆ TPI_DEVID_MANCVALID_Pos [2/13]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position.

Definition at line 796 of file core_armv8mbl.h.

◆ TPI_DEVID_MANCVALID_Pos [3/13]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position.

Definition at line 1372 of file core_armv8mml.h.

◆ TPI_DEVID_MANCVALID_Pos [4/13]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position.

Definition at line 868 of file core_cm23.h.

◆ TPI_DEVID_MANCVALID_Pos [5/13]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position.

Definition at line 1119 of file core_cm3.h.

◆ TPI_DEVID_MANCVALID_Pos [6/13]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position.

Definition at line 1444 of file core_cm33.h.

◆ TPI_DEVID_MANCVALID_Pos [7/13]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position.

Definition at line 1444 of file core_cm35p.h.

◆ TPI_DEVID_MANCVALID_Pos [8/13]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position.

Definition at line 1177 of file core_cm4.h.

◆ TPI_DEVID_MANCVALID_Pos [9/13]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position.

Definition at line 1929 of file core_cm55.h.

◆ TPI_DEVID_MANCVALID_Pos [10/13]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position.

Definition at line 1404 of file core_cm7.h.

◆ TPI_DEVID_MANCVALID_Pos [11/13]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position.

Definition at line 1834 of file core_cm85.h.

◆ TPI_DEVID_MANCVALID_Pos [12/13]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position.

Definition at line 1104 of file core_sc300.h.

◆ TPI_DEVID_MANCVALID_Pos [13/13]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position.

Definition at line 1502 of file core_starmc1.h.

◆ TPI_DEVID_MinBufSz_Msk [1/4]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask.

Definition at line 1126 of file core_cm3.h.

◆ TPI_DEVID_MinBufSz_Msk [2/4]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask.

Definition at line 1184 of file core_cm4.h.

◆ TPI_DEVID_MinBufSz_Msk [3/4]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask.

Definition at line 1411 of file core_cm7.h.

◆ TPI_DEVID_MinBufSz_Msk [4/4]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask.

Definition at line 1111 of file core_sc300.h.

◆ TPI_DEVID_MinBufSz_Pos [1/4]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position.

Definition at line 1125 of file core_cm3.h.

◆ TPI_DEVID_MinBufSz_Pos [2/4]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position.

Definition at line 1183 of file core_cm4.h.

◆ TPI_DEVID_MinBufSz_Pos [3/4]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position.

Definition at line 1410 of file core_cm7.h.

◆ TPI_DEVID_MinBufSz_Pos [4/4]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position.

Definition at line 1110 of file core_sc300.h.

◆ TPI_DEVID_NrTraceInput_Msk [1/8]

#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask.

Definition at line 878 of file core_cm23.h.

◆ TPI_DEVID_NrTraceInput_Msk [2/8]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask.

Definition at line 1132 of file core_cm3.h.

◆ TPI_DEVID_NrTraceInput_Msk [3/8]

#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask.

Definition at line 1454 of file core_cm33.h.

◆ TPI_DEVID_NrTraceInput_Msk [4/8]

#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask.

Definition at line 1454 of file core_cm35p.h.

◆ TPI_DEVID_NrTraceInput_Msk [5/8]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask.

Definition at line 1190 of file core_cm4.h.

◆ TPI_DEVID_NrTraceInput_Msk [6/8]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask.

Definition at line 1417 of file core_cm7.h.

◆ TPI_DEVID_NrTraceInput_Msk [7/8]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask.

Definition at line 1117 of file core_sc300.h.

◆ TPI_DEVID_NrTraceInput_Msk [8/8]

#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask.

Definition at line 1512 of file core_starmc1.h.

◆ TPI_DEVID_NrTraceInput_Pos [1/8]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position.

Definition at line 877 of file core_cm23.h.

◆ TPI_DEVID_NrTraceInput_Pos [2/8]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position.

Definition at line 1131 of file core_cm3.h.

◆ TPI_DEVID_NrTraceInput_Pos [3/8]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position.

Definition at line 1453 of file core_cm33.h.

◆ TPI_DEVID_NrTraceInput_Pos [4/8]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position.

Definition at line 1453 of file core_cm35p.h.

◆ TPI_DEVID_NrTraceInput_Pos [5/8]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position.

Definition at line 1189 of file core_cm4.h.

◆ TPI_DEVID_NrTraceInput_Pos [6/8]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position.

Definition at line 1416 of file core_cm7.h.

◆ TPI_DEVID_NrTraceInput_Pos [7/8]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position.

Definition at line 1116 of file core_sc300.h.

◆ TPI_DEVID_NrTraceInput_Pos [8/8]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position.

Definition at line 1511 of file core_starmc1.h.

◆ TPI_DEVID_NRZVALID_Msk [1/13]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask.

Definition at line 1432 of file core_armv81mml.h.

◆ TPI_DEVID_NRZVALID_Msk [2/13]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask.

Definition at line 794 of file core_armv8mbl.h.

◆ TPI_DEVID_NRZVALID_Msk [3/13]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask.

Definition at line 1370 of file core_armv8mml.h.

◆ TPI_DEVID_NRZVALID_Msk [4/13]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask.

Definition at line 866 of file core_cm23.h.

◆ TPI_DEVID_NRZVALID_Msk [5/13]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask.

Definition at line 1117 of file core_cm3.h.

◆ TPI_DEVID_NRZVALID_Msk [6/13]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask.

Definition at line 1442 of file core_cm33.h.

◆ TPI_DEVID_NRZVALID_Msk [7/13]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask.

Definition at line 1442 of file core_cm35p.h.

◆ TPI_DEVID_NRZVALID_Msk [8/13]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask.

Definition at line 1175 of file core_cm4.h.

◆ TPI_DEVID_NRZVALID_Msk [9/13]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask.

Definition at line 1927 of file core_cm55.h.

◆ TPI_DEVID_NRZVALID_Msk [10/13]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask.

Definition at line 1402 of file core_cm7.h.

◆ TPI_DEVID_NRZVALID_Msk [11/13]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask.

Definition at line 1832 of file core_cm85.h.

◆ TPI_DEVID_NRZVALID_Msk [12/13]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask.

Definition at line 1102 of file core_sc300.h.

◆ TPI_DEVID_NRZVALID_Msk [13/13]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask.

Definition at line 1500 of file core_starmc1.h.

◆ TPI_DEVID_NRZVALID_Pos [1/13]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position.

Definition at line 1431 of file core_armv81mml.h.

◆ TPI_DEVID_NRZVALID_Pos [2/13]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position.

Definition at line 793 of file core_armv8mbl.h.

◆ TPI_DEVID_NRZVALID_Pos [3/13]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position.

Definition at line 1369 of file core_armv8mml.h.

◆ TPI_DEVID_NRZVALID_Pos [4/13]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position.

Definition at line 865 of file core_cm23.h.

◆ TPI_DEVID_NRZVALID_Pos [5/13]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position.

Definition at line 1116 of file core_cm3.h.

◆ TPI_DEVID_NRZVALID_Pos [6/13]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position.

Definition at line 1441 of file core_cm33.h.

◆ TPI_DEVID_NRZVALID_Pos [7/13]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position.

Definition at line 1441 of file core_cm35p.h.

◆ TPI_DEVID_NRZVALID_Pos [8/13]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position.

Definition at line 1174 of file core_cm4.h.

◆ TPI_DEVID_NRZVALID_Pos [9/13]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position.

Definition at line 1926 of file core_cm55.h.

◆ TPI_DEVID_NRZVALID_Pos [10/13]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position.

Definition at line 1401 of file core_cm7.h.

◆ TPI_DEVID_NRZVALID_Pos [11/13]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position.

Definition at line 1831 of file core_cm85.h.

◆ TPI_DEVID_NRZVALID_Pos [12/13]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position.

Definition at line 1101 of file core_sc300.h.

◆ TPI_DEVID_NRZVALID_Pos [13/13]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position.

Definition at line 1499 of file core_starmc1.h.

◆ TPI_DEVID_PTINVALID_Msk [1/13]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask.

Definition at line 1438 of file core_armv81mml.h.

◆ TPI_DEVID_PTINVALID_Msk [2/13]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask.

Definition at line 800 of file core_armv8mbl.h.

◆ TPI_DEVID_PTINVALID_Msk [3/13]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask.

Definition at line 1376 of file core_armv8mml.h.

◆ TPI_DEVID_PTINVALID_Msk [4/13]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask.

Definition at line 872 of file core_cm23.h.

◆ TPI_DEVID_PTINVALID_Msk [5/13]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask.

Definition at line 1123 of file core_cm3.h.

◆ TPI_DEVID_PTINVALID_Msk [6/13]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask.

Definition at line 1448 of file core_cm33.h.

◆ TPI_DEVID_PTINVALID_Msk [7/13]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask.

Definition at line 1448 of file core_cm35p.h.

◆ TPI_DEVID_PTINVALID_Msk [8/13]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask.

Definition at line 1181 of file core_cm4.h.

◆ TPI_DEVID_PTINVALID_Msk [9/13]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask.

Definition at line 1933 of file core_cm55.h.

◆ TPI_DEVID_PTINVALID_Msk [10/13]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask.

Definition at line 1408 of file core_cm7.h.

◆ TPI_DEVID_PTINVALID_Msk [11/13]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask.

Definition at line 1838 of file core_cm85.h.

◆ TPI_DEVID_PTINVALID_Msk [12/13]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask.

Definition at line 1108 of file core_sc300.h.

◆ TPI_DEVID_PTINVALID_Msk [13/13]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask.

Definition at line 1506 of file core_starmc1.h.

◆ TPI_DEVID_PTINVALID_Pos [1/13]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position.

Definition at line 1437 of file core_armv81mml.h.

◆ TPI_DEVID_PTINVALID_Pos [2/13]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position.

Definition at line 799 of file core_armv8mbl.h.

◆ TPI_DEVID_PTINVALID_Pos [3/13]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position.

Definition at line 1375 of file core_armv8mml.h.

◆ TPI_DEVID_PTINVALID_Pos [4/13]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position.

Definition at line 871 of file core_cm23.h.

◆ TPI_DEVID_PTINVALID_Pos [5/13]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position.

Definition at line 1122 of file core_cm3.h.

◆ TPI_DEVID_PTINVALID_Pos [6/13]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position.

Definition at line 1447 of file core_cm33.h.

◆ TPI_DEVID_PTINVALID_Pos [7/13]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position.

Definition at line 1447 of file core_cm35p.h.

◆ TPI_DEVID_PTINVALID_Pos [8/13]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position.

Definition at line 1180 of file core_cm4.h.

◆ TPI_DEVID_PTINVALID_Pos [9/13]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position.

Definition at line 1932 of file core_cm55.h.

◆ TPI_DEVID_PTINVALID_Pos [10/13]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position.

Definition at line 1407 of file core_cm7.h.

◆ TPI_DEVID_PTINVALID_Pos [11/13]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position.

Definition at line 1837 of file core_cm85.h.

◆ TPI_DEVID_PTINVALID_Pos [12/13]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position.

Definition at line 1107 of file core_sc300.h.

◆ TPI_DEVID_PTINVALID_Pos [13/13]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position.

Definition at line 1505 of file core_starmc1.h.

◆ TPI_DEVTYPE_MajorType_Msk [1/13]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask.

Definition at line 1448 of file core_armv81mml.h.

◆ TPI_DEVTYPE_MajorType_Msk [2/13]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask.

Definition at line 810 of file core_armv8mbl.h.

◆ TPI_DEVTYPE_MajorType_Msk [3/13]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask.

Definition at line 1386 of file core_armv8mml.h.

◆ TPI_DEVTYPE_MajorType_Msk [4/13]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask.

Definition at line 885 of file core_cm23.h.

◆ TPI_DEVTYPE_MajorType_Msk [5/13]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask.

Definition at line 1139 of file core_cm3.h.

◆ TPI_DEVTYPE_MajorType_Msk [6/13]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask.

Definition at line 1461 of file core_cm33.h.

◆ TPI_DEVTYPE_MajorType_Msk [7/13]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask.

Definition at line 1461 of file core_cm35p.h.

◆ TPI_DEVTYPE_MajorType_Msk [8/13]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask.

Definition at line 1197 of file core_cm4.h.

◆ TPI_DEVTYPE_MajorType_Msk [9/13]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask.

Definition at line 1943 of file core_cm55.h.

◆ TPI_DEVTYPE_MajorType_Msk [10/13]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask.

Definition at line 1424 of file core_cm7.h.

◆ TPI_DEVTYPE_MajorType_Msk [11/13]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask.

Definition at line 1848 of file core_cm85.h.

◆ TPI_DEVTYPE_MajorType_Msk [12/13]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask.

Definition at line 1124 of file core_sc300.h.

◆ TPI_DEVTYPE_MajorType_Msk [13/13]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask.

Definition at line 1519 of file core_starmc1.h.

◆ TPI_DEVTYPE_MajorType_Pos [1/13]

#define TPI_DEVTYPE_MajorType_Pos 0U

TPI DEVTYPE: MajorType Position.

Definition at line 1447 of file core_armv81mml.h.

◆ TPI_DEVTYPE_MajorType_Pos [2/13]

#define TPI_DEVTYPE_MajorType_Pos 0U

TPI DEVTYPE: MajorType Position.

Definition at line 809 of file core_armv8mbl.h.

◆ TPI_DEVTYPE_MajorType_Pos [3/13]

#define TPI_DEVTYPE_MajorType_Pos 0U

TPI DEVTYPE: MajorType Position.

Definition at line 1385 of file core_armv8mml.h.

◆ TPI_DEVTYPE_MajorType_Pos [4/13]

#define TPI_DEVTYPE_MajorType_Pos 0U

TPI DEVTYPE: MajorType Position.

Definition at line 884 of file core_cm23.h.

◆ TPI_DEVTYPE_MajorType_Pos [5/13]

#define TPI_DEVTYPE_MajorType_Pos 0U

TPI DEVTYPE: MajorType Position.

Definition at line 1138 of file core_cm3.h.

◆ TPI_DEVTYPE_MajorType_Pos [6/13]

#define TPI_DEVTYPE_MajorType_Pos 0U

TPI DEVTYPE: MajorType Position.

Definition at line 1460 of file core_cm33.h.

◆ TPI_DEVTYPE_MajorType_Pos [7/13]

#define TPI_DEVTYPE_MajorType_Pos 0U

TPI DEVTYPE: MajorType Position.

Definition at line 1460 of file core_cm35p.h.

◆ TPI_DEVTYPE_MajorType_Pos [8/13]

#define TPI_DEVTYPE_MajorType_Pos 0U

TPI DEVTYPE: MajorType Position.

Definition at line 1196 of file core_cm4.h.

◆ TPI_DEVTYPE_MajorType_Pos [9/13]

#define TPI_DEVTYPE_MajorType_Pos 0U

TPI DEVTYPE: MajorType Position.

Definition at line 1942 of file core_cm55.h.

◆ TPI_DEVTYPE_MajorType_Pos [10/13]

#define TPI_DEVTYPE_MajorType_Pos 0U

TPI DEVTYPE: MajorType Position.

Definition at line 1423 of file core_cm7.h.

◆ TPI_DEVTYPE_MajorType_Pos [11/13]

#define TPI_DEVTYPE_MajorType_Pos 0U

TPI DEVTYPE: MajorType Position.

Definition at line 1847 of file core_cm85.h.

◆ TPI_DEVTYPE_MajorType_Pos [12/13]

#define TPI_DEVTYPE_MajorType_Pos 0U

TPI DEVTYPE: MajorType Position.

Definition at line 1123 of file core_sc300.h.

◆ TPI_DEVTYPE_MajorType_Pos [13/13]

#define TPI_DEVTYPE_MajorType_Pos 0U

TPI DEVTYPE: MajorType Position.

Definition at line 1518 of file core_starmc1.h.

◆ TPI_DEVTYPE_SubType_Msk [1/13]

#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask.

Definition at line 1445 of file core_armv81mml.h.

◆ TPI_DEVTYPE_SubType_Msk [2/13]

#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask.

Definition at line 807 of file core_armv8mbl.h.

◆ TPI_DEVTYPE_SubType_Msk [3/13]

#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask.

Definition at line 1383 of file core_armv8mml.h.

◆ TPI_DEVTYPE_SubType_Msk [4/13]

#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask.

Definition at line 882 of file core_cm23.h.

◆ TPI_DEVTYPE_SubType_Msk [5/13]

#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask.

Definition at line 1136 of file core_cm3.h.

◆ TPI_DEVTYPE_SubType_Msk [6/13]

#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask.

Definition at line 1458 of file core_cm33.h.

◆ TPI_DEVTYPE_SubType_Msk [7/13]

#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask.

Definition at line 1458 of file core_cm35p.h.

◆ TPI_DEVTYPE_SubType_Msk [8/13]

#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask.

Definition at line 1194 of file core_cm4.h.

◆ TPI_DEVTYPE_SubType_Msk [9/13]

#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask.

Definition at line 1940 of file core_cm55.h.

◆ TPI_DEVTYPE_SubType_Msk [10/13]

#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask.

Definition at line 1421 of file core_cm7.h.

◆ TPI_DEVTYPE_SubType_Msk [11/13]

#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask.

Definition at line 1845 of file core_cm85.h.

◆ TPI_DEVTYPE_SubType_Msk [12/13]

#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask.

Definition at line 1121 of file core_sc300.h.

◆ TPI_DEVTYPE_SubType_Msk [13/13]

#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask.

Definition at line 1516 of file core_starmc1.h.