Header file of TIM HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_tim_ex.h"

Include dependency graph for stm32h7xx_hal_tim.h:

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Classes
struct	TIM_Base_InitTypeDef
	TIM Time base Configuration Structure definition. More...
struct	TIM_OC_InitTypeDef
	TIM Output Compare Configuration Structure definition. More...
struct	TIM_OnePulse_InitTypeDef
	TIM One Pulse Mode Configuration Structure definition. More...
struct	TIM_IC_InitTypeDef
	TIM Input Capture Configuration Structure definition. More...
struct	TIM_Encoder_InitTypeDef
	TIM Encoder Configuration Structure definition. More...
struct	TIM_ClockConfigTypeDef
	Clock Configuration Handle Structure definition. More...
struct	TIM_ClearInputConfigTypeDef
	TIM Clear Input Configuration Handle Structure definition. More...
struct	TIM_MasterConfigTypeDef
	TIM Master configuration Structure definition. More...
struct	TIM_SlaveConfigTypeDef
	TIM Slave configuration Structure definition. More...
struct	TIM_BreakDeadTimeConfigTypeDef
	TIM Break input(s) and Dead time configuration Structure definition. More...
struct	TIM_HandleTypeDef
	TIM Time Base Handle Structure definition. More...

Macros
#define	TIM_CLEARINPUTSOURCE_NONE 0x00000000U
	OCREF_CLR is disabled.
#define	TIM_CLEARINPUTSOURCE_ETR 0x00000001U
	OCREF_CLR is connected to ETRF input.
#define	TIM_DMABASE_CR1 0x00000000U
#define	TIM_DMABASE_CR2 0x00000001U
#define	TIM_DMABASE_SMCR 0x00000002U
#define	TIM_DMABASE_DIER 0x00000003U
#define	TIM_DMABASE_SR 0x00000004U
#define	TIM_DMABASE_EGR 0x00000005U
#define	TIM_DMABASE_CCMR1 0x00000006U
#define	TIM_DMABASE_CCMR2 0x00000007U
#define	TIM_DMABASE_CCER 0x00000008U
#define	TIM_DMABASE_CNT 0x00000009U
#define	TIM_DMABASE_PSC 0x0000000AU
#define	TIM_DMABASE_ARR 0x0000000BU
#define	TIM_DMABASE_RCR 0x0000000CU
#define	TIM_DMABASE_CCR1 0x0000000DU
#define	TIM_DMABASE_CCR2 0x0000000EU
#define	TIM_DMABASE_CCR3 0x0000000FU
#define	TIM_DMABASE_CCR4 0x00000010U
#define	TIM_DMABASE_BDTR 0x00000011U
#define	TIM_DMABASE_DCR 0x00000012U
#define	TIM_DMABASE_DMAR 0x00000013U
#define	TIM_DMABASE_CCMR3 0x00000015U
#define	TIM_DMABASE_CCR5 0x00000016U
#define	TIM_DMABASE_CCR6 0x00000017U
#define	TIM_DMABASE_TISEL 0x0000001AU
#define	TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
	Reinitialize the counter and generates an update of the registers.
#define	TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
	A capture/compare event is generated on channel 1.
#define	TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
	A capture/compare event is generated on channel 2.
#define	TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
	A capture/compare event is generated on channel 3.
#define	TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
	A capture/compare event is generated on channel 4.
#define	TIM_EVENTSOURCE_COM TIM_EGR_COMG
	A commutation event is generated.
#define	TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
	A trigger event is generated.
#define	TIM_EVENTSOURCE_BREAK TIM_EGR_BG
	A break event is generated.
#define	TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G
	A break 2 event is generated.
#define	TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U
	Polarity for TIx source.
#define	TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P
	Polarity for TIx source.
#define	TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP)
	Polarity for TIx source.
#define	TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP
	Polarity for ETR source.
#define	TIM_ETRPOLARITY_NONINVERTED 0x00000000U
	Polarity for ETR source.
#define	TIM_ETRPRESCALER_DIV1 0x00000000U
	No prescaler is used.
#define	TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0
	ETR input source is divided by 2.
#define	TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1
	ETR input source is divided by 4.
#define	TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS
	ETR input source is divided by 8.
#define	TIM_COUNTERMODE_UP 0x00000000U
	Counter used as up-counter.
#define	TIM_COUNTERMODE_DOWN TIM_CR1_DIR
	Counter used as down-counter.
#define	TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
	Center-aligned mode 1.
#define	TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
	Center-aligned mode 2.
#define	TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
	Center-aligned mode 3.
#define	TIM_UIFREMAP_DISABLE 0x00000000U
	Update interrupt flag remap disabled.
#define	TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP
	Update interrupt flag remap enabled.
#define	TIM_CLOCKDIVISION_DIV1 0x00000000U
	Clock division: tDTS=tCK_INT.
#define	TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
	Clock division: tDTS=2*tCK_INT.
#define	TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1
	Clock division: tDTS=4*tCK_INT.
#define	TIM_OUTPUTSTATE_DISABLE 0x00000000U
	Capture/Compare 1 output disabled.
#define	TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E
	Capture/Compare 1 output enabled.
#define	TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U
	TIMx_ARR register is not buffered.
#define	TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE
	TIMx_ARR register is buffered.
#define	TIM_OCFAST_DISABLE 0x00000000U
	Output Compare fast disable.
#define	TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE
	Output Compare fast enable.
#define	TIM_OUTPUTNSTATE_DISABLE 0x00000000U
	OCxN is disabled.
#define	TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE
	OCxN is enabled.
#define	TIM_OCPOLARITY_HIGH 0x00000000U
	Capture/Compare output polarity.
#define	TIM_OCPOLARITY_LOW TIM_CCER_CC1P
	Capture/Compare output polarity.
#define	TIM_OCNPOLARITY_HIGH 0x00000000U
	Capture/Compare complementary output polarity.
#define	TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP
	Capture/Compare complementary output polarity.
#define	TIM_OCIDLESTATE_SET TIM_CR2_OIS1
	Output Idle state: OCx=1 when MOE=0.
#define	TIM_OCIDLESTATE_RESET 0x00000000U
	Output Idle state: OCx=0 when MOE=0.
#define	TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N
	Complementary output Idle state: OCxN=1 when MOE=0.
#define	TIM_OCNIDLESTATE_RESET 0x00000000U
	Complementary output Idle state: OCxN=0 when MOE=0.
#define	TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
	Capture triggered by rising edge on timer input.
#define	TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
	Capture triggered by falling edge on timer input.
#define	TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
	Capture triggered by both rising and falling edges on timer input.
#define	TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
	Encoder input with rising edge polarity.
#define	TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
	Encoder input with falling edge polarity.
#define	TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0
	TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively.
#define	TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1
	TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively.
#define	TIM_ICSELECTION_TRC TIM_CCMR1_CC1S
	TIM Input 1, 2, 3 or 4 is selected to be connected to TRC.
#define	TIM_ICPSC_DIV1 0x00000000U
	Capture performed each time an edge is detected on the capture input.
#define	TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0
	Capture performed once every 2 events.
#define	TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1
	Capture performed once every 4 events.
#define	TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC
	Capture performed once every 8 events.
#define	TIM_OPMODE_SINGLE TIM_CR1_OPM
	Counter stops counting at the next update event.
#define	TIM_OPMODE_REPETITIVE 0x00000000U
	Counter is not stopped at update event.
#define	TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0
	Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level.
#define	TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1
	Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level.
#define	TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
	Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
#define	TIM_IT_UPDATE TIM_DIER_UIE
	Update interrupt.
#define	TIM_IT_CC1 TIM_DIER_CC1IE
	Capture/Compare 1 interrupt.
#define	TIM_IT_CC2 TIM_DIER_CC2IE
	Capture/Compare 2 interrupt.
#define	TIM_IT_CC3 TIM_DIER_CC3IE
	Capture/Compare 3 interrupt.
#define	TIM_IT_CC4 TIM_DIER_CC4IE
	Capture/Compare 4 interrupt.
#define	TIM_IT_COM TIM_DIER_COMIE
	Commutation interrupt.
#define	TIM_IT_TRIGGER TIM_DIER_TIE
	Trigger interrupt.
#define	TIM_IT_BREAK TIM_DIER_BIE
	Break interrupt.
#define	TIM_COMMUTATION_TRGI TIM_CR2_CCUS
	When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input.
#define	TIM_COMMUTATION_SOFTWARE 0x00000000U
	When Capture/compare control bits are preloaded, they are updated by setting the COMG bit.
#define	TIM_DMA_UPDATE TIM_DIER_UDE
	DMA request is triggered by the update event.
#define	TIM_DMA_CC1 TIM_DIER_CC1DE
	DMA request is triggered by the capture/compare macth 1 event.
#define	TIM_DMA_CC2 TIM_DIER_CC2DE
	DMA request is triggered by the capture/compare macth 2 event event.
#define	TIM_DMA_CC3 TIM_DIER_CC3DE
	DMA request is triggered by the capture/compare macth 3 event event.
#define	TIM_DMA_CC4 TIM_DIER_CC4DE
	DMA request is triggered by the capture/compare macth 4 event event.
#define	TIM_DMA_COM TIM_DIER_COMDE
	DMA request is triggered by the commutation event.
#define	TIM_DMA_TRIGGER TIM_DIER_TDE
	DMA request is triggered by the trigger event.
#define	TIM_CCDMAREQUEST_CC 0x00000000U
	CCx DMA request sent when capture or compare match event occurs.
#define	TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS
	CCx DMA requests sent when update event occurs.
#define	TIM_FLAG_UPDATE TIM_SR_UIF
	Update interrupt flag.
#define	TIM_FLAG_CC1 TIM_SR_CC1IF
	Capture/Compare 1 interrupt flag.
#define	TIM_FLAG_CC2 TIM_SR_CC2IF
	Capture/Compare 2 interrupt flag.
#define	TIM_FLAG_CC3 TIM_SR_CC3IF
	Capture/Compare 3 interrupt flag.
#define	TIM_FLAG_CC4 TIM_SR_CC4IF
	Capture/Compare 4 interrupt flag.
#define	TIM_FLAG_CC5 TIM_SR_CC5IF
	Capture/Compare 5 interrupt flag.
#define	TIM_FLAG_CC6 TIM_SR_CC6IF
	Capture/Compare 6 interrupt flag.
#define	TIM_FLAG_COM TIM_SR_COMIF
	Commutation interrupt flag.
#define	TIM_FLAG_TRIGGER TIM_SR_TIF
	Trigger interrupt flag.
#define	TIM_FLAG_BREAK TIM_SR_BIF
	Break interrupt flag.
#define	TIM_FLAG_BREAK2 TIM_SR_B2IF
	Break 2 interrupt flag.
#define	TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF
	System Break interrupt flag.
#define	TIM_FLAG_CC1OF TIM_SR_CC1OF
	Capture 1 overcapture flag.
#define	TIM_FLAG_CC2OF TIM_SR_CC2OF
	Capture 2 overcapture flag.
#define	TIM_FLAG_CC3OF TIM_SR_CC3OF
	Capture 3 overcapture flag.
#define	TIM_FLAG_CC4OF TIM_SR_CC4OF
	Capture 4 overcapture flag.
#define	TIM_CHANNEL_1 0x00000000U
	Capture/compare channel 1 identifier.
#define	TIM_CHANNEL_2 0x00000004U
	Capture/compare channel 2 identifier.
#define	TIM_CHANNEL_3 0x00000008U
	Capture/compare channel 3 identifier.
#define	TIM_CHANNEL_4 0x0000000CU
	Capture/compare channel 4 identifier.
#define	TIM_CHANNEL_5 0x00000010U
	Compare channel 5 identifier.
#define	TIM_CHANNEL_6 0x00000014U
	Compare channel 6 identifier.
#define	TIM_CHANNEL_ALL 0x0000003CU
	Global Capture/compare channel identifier.
#define	TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0
	Internal clock source.
#define	TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF
	External clock source mode 1 (ETRF).
#define	TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1
	External clock source mode 2.
#define	TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED
	External clock source mode 1 (TTI1FP1 + edge detect.).
#define	TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1
	External clock source mode 1 (TTI1FP1).
#define	TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2
	External clock source mode 1 (TTI2FP2).
#define	TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0
	External clock source mode 1 (ITR0).
#define	TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1
	External clock source mode 1 (ITR1).
#define	TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2
	External clock source mode 1 (ITR2).
#define	TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3
	External clock source mode 1 (ITR3).
#define	TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4
	External clock source mode 1 (ITR4).
#define	TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5
	External clock source mode 1 (ITR5).
#define	TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6
	External clock source mode 1 (ITR6).
#define	TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7
	External clock source mode 1 (ITR7).
#define	TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8
	External clock source mode 1 (ITR8).
#define	TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
	Polarity for ETRx clock sources.
#define	TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
	Polarity for ETRx clock sources.
#define	TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
	Polarity for TIx clock sources.
#define	TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
	Polarity for TIx clock sources.
#define	TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
	Polarity for TIx clock sources.
#define	TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
	No prescaler is used.
#define	TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
	Prescaler for External ETR Clock: Capture performed once every 2 events.
#define	TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
	Prescaler for External ETR Clock: Capture performed once every 4 events.
#define	TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
	Prescaler for External ETR Clock: Capture performed once every 8 events.
#define	TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
	Polarity for ETRx pin.
#define	TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
	Polarity for ETRx pin.
#define	TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
	No prescaler is used.
#define	TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
	Prescaler for External ETR pin: Capture performed once every 2 events.
#define	TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
	Prescaler for External ETR pin: Capture performed once every 4 events.
#define	TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
	Prescaler for External ETR pin: Capture performed once every 8 events.
#define	TIM_OSSR_ENABLE TIM_BDTR_OSSR
	When inactive, OC/OCN outputs are enabled (still controlled by the timer).
#define	TIM_OSSR_DISABLE 0x00000000U
	When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer).
#define	TIM_OSSI_ENABLE TIM_BDTR_OSSI
	When inactive, OC/OCN outputs are enabled (still controlled by the timer).
#define	TIM_OSSI_DISABLE 0x00000000U
	When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer).
#define	TIM_LOCKLEVEL_OFF 0x00000000U
	LOCK OFF.
#define	TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
	LOCK Level 1.
#define	TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
	LOCK Level 2.
#define	TIM_LOCKLEVEL_3 TIM_BDTR_LOCK
	LOCK Level 3.
#define	TIM_BREAK_ENABLE TIM_BDTR_BKE
	Break input BRK is enabled.
#define	TIM_BREAK_DISABLE 0x00000000U
	Break input BRK is disabled.
#define	TIM_BREAKPOLARITY_LOW 0x00000000U
	Break input BRK is active low.
#define	TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP
	Break input BRK is active high.
#define	TIM_BREAK2_DISABLE 0x00000000U
	Break input BRK2 is disabled.
#define	TIM_BREAK2_ENABLE TIM_BDTR_BK2E
	Break input BRK2 is enabled.
#define	TIM_BREAK2POLARITY_LOW 0x00000000U
	Break input BRK2 is active low.
#define	TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P
	Break input BRK2 is active high.
#define	TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
	MOE can be set only by software.
#define	TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE
	MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active).
#define	TIM_GROUPCH5_NONE 0x00000000U
	No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC.
#define	TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1
	OC1REFC is the logical AND of OC1REFC and OC5REF.
#define	TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2
	OC2REFC is the logical AND of OC2REFC and OC5REF.
#define	TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3
	OC3REFC is the logical AND of OC3REFC and OC5REF.
#define	TIM_TRGO_RESET 0x00000000U
	TIMx_EGR.UG bit is used as trigger output (TRGO).
#define	TIM_TRGO_ENABLE TIM_CR2_MMS_0
	TIMx_CR1.CEN bit is used as trigger output (TRGO).
#define	TIM_TRGO_UPDATE TIM_CR2_MMS_1
	Update event is used as trigger output (TRGO).
#define	TIM_TRGO_OC1 (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0)
	Capture or a compare match 1 is used as trigger output (TRGO).
#define	TIM_TRGO_OC1REF TIM_CR2_MMS_2
	OC1REF signal is used as trigger output (TRGO).
#define	TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0)
	OC2REF signal is used as trigger output(TRGO).
#define	TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1)
	OC3REF signal is used as trigger output(TRGO).
#define	TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0)
	OC4REF signal is used as trigger output(TRGO).
#define	TIM_TRGO2_RESET 0x00000000U
	TIMx_EGR.UG bit is used as trigger output (TRGO2).
#define	TIM_TRGO2_ENABLE TIM_CR2_MMS2_0
	TIMx_CR1.CEN bit is used as trigger output (TRGO2).
#define	TIM_TRGO2_UPDATE TIM_CR2_MMS2_1
	Update event is used as trigger output (TRGO2).
#define	TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0)
	Capture or a compare match 1 is used as trigger output (TRGO2).
#define	TIM_TRGO2_OC1REF TIM_CR2_MMS2_2
	OC1REF signal is used as trigger output (TRGO2).
#define	TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0)
	OC2REF signal is used as trigger output (TRGO2).
#define	TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1)
	OC3REF signal is used as trigger output (TRGO2).
#define	TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0)
	OC4REF signal is used as trigger output (TRGO2).
#define	TIM_TRGO2_OC5REF TIM_CR2_MMS2_3
	OC5REF signal is used as trigger output (TRGO2).
#define	TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_0)
	OC6REF signal is used as trigger output (TRGO2).
#define	TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1)
	OC4REF rising or falling edges generate pulses on TRGO2.
#define	TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0)
	OC6REF rising or falling edges generate pulses on TRGO2.
#define	TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2)
	OC4REF or OC6REF rising edges generate pulses on TRGO2.
#define	TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0)
	OC4REF rising or OC6REF falling edges generate pulses on TRGO2.
#define	TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \|TIM_CR2_MMS2_1)
	OC5REF or OC6REF rising edges generate pulses on TRGO2.
#define	TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0)
	OC5REF or OC6REF rising edges generate pulses on TRGO2.
#define	TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM
	No action.
#define	TIM_MASTERSLAVEMODE_DISABLE 0x00000000U
	Master/slave mode is selected.
#define	TIM_SLAVEMODE_DISABLE 0x00000000U
	Slave mode disabled.
#define	TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
	Reset Mode.
#define	TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0)
	Gated Mode.
#define	TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1)
	Trigger Mode.
#define	TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
	External Clock Mode 1.
#define	TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3
	Combined reset + trigger mode.
#define	TIM_OCMODE_TIMING 0x00000000U
	Frozen.
#define	TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
	Set channel to active level on match.
#define	TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
	Set channel to inactive level on match.
#define	TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0)
	Toggle.
#define	TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1)
	PWM mode 1.
#define	TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0)
	PWM mode 2.
#define	TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0)
	Force active level.
#define	TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
	Force inactive level.
#define	TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3
	Retrigerrable OPM mode 1.
#define	TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0)
	Retrigerrable OPM mode 2.
#define	TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_2)
	Combined PWM mode 1.
#define	TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
	Combined PWM mode 2.
#define	TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
	Asymmetric PWM mode 1.
#define	TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M
	Asymmetric PWM mode 2.
#define	TIM_TS_ITR0 0x00000000U
	Internal Trigger 0 (ITR0).
#define	TIM_TS_ITR1 TIM_SMCR_TS_0
	Internal Trigger 1 (ITR1).
#define	TIM_TS_ITR2 TIM_SMCR_TS_1
	Internal Trigger 2 (ITR2).
#define	TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
	Internal Trigger 3 (ITR3).
#define	TIM_TS_ITR4 (TIM_SMCR_TS_3)
	Internal Trigger 4 (ITR4).
#define	TIM_TS_ITR5 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_3)
	Internal Trigger 5 (ITR5).
#define	TIM_TS_ITR6 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_3)
	Internal Trigger 6 (ITR6).
#define	TIM_TS_ITR7 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_3)
	Internal Trigger 7 (ITR7).
#define	TIM_TS_ITR8 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_3)
	Internal Trigger 8 (ITR8).
#define	TIM_TS_ITR9 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2 \| TIM_SMCR_TS_3)
	Internal Trigger 9 (ITR9).
#define	TIM_TS_ITR10 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2 \| TIM_SMCR_TS_3)
	Internal Trigger 10 (ITR10).
#define	TIM_TS_ITR11 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_2 \| TIM_SMCR_TS_3)
	Internal Trigger 11 (ITR11).
#define	TIM_TS_ITR12 (TIM_SMCR_TS_4)
	Internal Trigger 12 (ITR12).
#define	TIM_TS_ITR13 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_4)
	Internal Trigger 13 (ITR13).
#define	TIM_TS_TI1F_ED TIM_SMCR_TS_2
	TI1 Edge Detector (TI1F_ED).
#define	TIM_TS_TI1FP1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
	Filtered Timer Input 1 (TI1FP1).
#define	TIM_TS_TI2FP2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
	Filtered Timer Input 2 (TI2FP2).
#define	TIM_TS_ETRF (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
	Filtered External Trigger input (ETRF).
#define	TIM_TS_NONE 0x0000FFFFU
	No trigger selected.
#define	TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
	Polarity for ETRx trigger sources.
#define	TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
	Polarity for ETRx trigger sources.
#define	TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
	Polarity for TIxFPx or TI1_ED trigger sources.
#define	TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
	Polarity for TIxFPx or TI1_ED trigger sources.
#define	TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
	Polarity for TIxFPx or TI1_ED trigger sources.
#define	TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
	No prescaler is used.
#define	TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
	Prescaler for External ETR Trigger: Capture performed once every 2 events.
#define	TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
	Prescaler for External ETR Trigger: Capture performed once every 4 events.
#define	TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
	Prescaler for External ETR Trigger: Capture performed once every 8 events.
#define	TIM_TI1SELECTION_CH1 0x00000000U
	The TIMx_CH1 pin is connected to TI1 input.
#define	TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S
	The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination).
#define	TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
	The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA.
#define	TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
	The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA.
#define	TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
	The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA.
#define	TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
	The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA.
#define	TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
	The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA.
#define	TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
	The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA.
#define	TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
	The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA.
#define	TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
	The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA.
#define	TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
	The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA.
#define	TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
	The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA.
#define	TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
	The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA.
#define	TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
	The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA.
#define	TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
	The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA.
#define	TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
	The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA.
#define	TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
	The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA.
#define	TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
	The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA.
#define	TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
	The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA.
#define	TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
	The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA.
#define	TIM_DMA_ID_UPDATE ((uint16_t) 0x0000)
	Index of the DMA handle used for Update DMA requests.
#define	TIM_DMA_ID_CC1 ((uint16_t) 0x0001)
	Index of the DMA handle used for Capture/Compare 1 DMA requests.
#define	TIM_DMA_ID_CC2 ((uint16_t) 0x0002)
	Index of the DMA handle used for Capture/Compare 2 DMA requests.
#define	TIM_DMA_ID_CC3 ((uint16_t) 0x0003)
	Index of the DMA handle used for Capture/Compare 3 DMA requests.
#define	TIM_DMA_ID_CC4 ((uint16_t) 0x0004)
	Index of the DMA handle used for Capture/Compare 4 DMA requests.
#define	TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005)
	Index of the DMA handle used for Commutation DMA requests.
#define	TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006)
	Index of the DMA handle used for Trigger DMA requests.
#define	TIM_CCx_ENABLE 0x00000001U
	Input or output channel is enabled.
#define	TIM_CCx_DISABLE 0x00000000U
	Input or output channel is disabled.
#define	TIM_CCxN_ENABLE 0x00000004U
	Complementary output channel is enabled.
#define	TIM_CCxN_DISABLE 0x00000000U
	Complementary output channel is enabled.
#define	TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL
	Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17.
#define	TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL
	Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface.
#define	TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL
	Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17.
#define	TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL
	Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17.
#define	__HAL_TIM_RESET_HANDLE_STATE(__HANDLE__)
	Reset TIM handle state.
#define	__HAL_TIM_ENABLE(__HANDLE__)
	Enable the TIM peripheral.
#define	__HAL_TIM_MOE_ENABLE(__HANDLE__)
	Enable the TIM main Output.
#define	__HAL_TIM_DISABLE(__HANDLE__)
	Disable the TIM peripheral.
#define	__HAL_TIM_MOE_DISABLE(__HANDLE__)
	Disable the TIM main Output.
#define	__HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)
	Disable the TIM main Output.
#define	__HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)
	Enable the specified TIM interrupt.
#define	__HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)
	Disable the specified TIM interrupt.
#define	__HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)
	Enable the specified DMA request.
#define	__HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)
	Disable the specified DMA request.
#define	__HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)
	Check whether the specified TIM interrupt flag is set or not.
#define	__HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)
	Clear the specified TIM interrupt flag.
#define	__HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)
	Check whether the specified TIM interrupt source is enabled or not.
#define	__HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)
	Clear the TIM interrupt pending bits.
#define	__HAL_TIM_UIFREMAP_ENABLE(__HANDLE__)
#define	__HAL_TIM_UIFREMAP_DISABLE(__HANDLE__)
#define	__HAL_TIM_GET_UIFCPY(__COUNTER__)
#define	__HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)
	Indicates whether or not the TIM Counter is used as downcounter.
#define	__HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)
	Set the TIM Prescaler on runtime.
#define	__HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)
	Set the TIM Counter Register value on runtime.
#define	__HAL_TIM_GET_COUNTER(__HANDLE__)
	Get the TIM Counter Register value on runtime.
#define	__HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)
	Set the TIM Autoreload Register value on runtime without calling another time any Init function.
#define	__HAL_TIM_GET_AUTORELOAD(__HANDLE__)
	Get the TIM Autoreload Register value on runtime.
#define	__HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__)
	Set the TIM Clock Division value on runtime without calling another time any Init function.
#define	__HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)
	Get the TIM Clock Division value on runtime.
#define	__HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__)
	Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
#define	__HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)
	Get the TIM Input Capture prescaler on runtime.
#define	__HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__)
	Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
#define	__HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__)
	Get the TIM Capture Compare Register value on runtime.
#define	__HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
	Set the TIM Output compare preload.
#define	__HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
	Reset the TIM Output compare preload.
#define	__HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)
	Enable fast mode for a given channel.
#define	__HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)
	Disable fast mode for a given channel.
#define	__HAL_TIM_URS_ENABLE(__HANDLE__)
	Set the Update Request Source (URS) bit of the TIMx_CR1 register.
#define	__HAL_TIM_URS_DISABLE(__HANDLE__)
	Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
#define	__HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
	Set the TIM Capture x input polarity on runtime.
#define	__HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__)
	Select the Capture/compare DMA request source.
#define	TIM_CCER_CCxE_MASK
#define	TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
#define	IS_TIM_CLEARINPUT_SOURCE(__MODE__)
#define	IS_TIM_DMA_BASE(__BASE__)
#define	IS_TIM_EVENT_SOURCE(__SOURCE__)
#define	IS_TIM_COUNTER_MODE(__MODE__)
#define	IS_TIM_UIFREMAP_MODE(__MODE__)
#define	IS_TIM_CLOCKDIVISION_DIV(__DIV__)
#define	IS_TIM_AUTORELOAD_PRELOAD(PRELOAD)
#define	IS_TIM_FAST_STATE(__STATE__)
#define	IS_TIM_OC_POLARITY(__POLARITY__)
#define	IS_TIM_OCN_POLARITY(__POLARITY__)
#define	IS_TIM_OCIDLE_STATE(__STATE__)
#define	IS_TIM_OCNIDLE_STATE(__STATE__)
#define	IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)
#define	IS_TIM_IC_POLARITY(__POLARITY__)
#define	IS_TIM_IC_SELECTION(__SELECTION__)
#define	IS_TIM_IC_PRESCALER(__PRESCALER__)
#define	IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__)
#define	IS_TIM_OPM_MODE(__MODE__)
#define	IS_TIM_ENCODER_MODE(__MODE__)
#define	IS_TIM_DMA_SOURCE(__SOURCE__)
#define	IS_TIM_CHANNELS(__CHANNEL__)
#define	IS_TIM_OPM_CHANNELS(__CHANNEL__)
#define	IS_TIM_PERIOD(__HANDLE__, __PERIOD__)
#define	IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__)
#define	IS_TIM_CLOCKSOURCE(__CLOCK__)
#define	IS_TIM_CLOCKPOLARITY(__POLARITY__)
#define	IS_TIM_CLOCKPRESCALER(__PRESCALER__)
#define	IS_TIM_CLOCKFILTER(__ICFILTER__)
#define	IS_TIM_CLEARINPUT_POLARITY(__POLARITY__)
#define	IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__)
#define	IS_TIM_CLEARINPUT_FILTER(__ICFILTER__)
#define	IS_TIM_OSSR_STATE(__STATE__)
#define	IS_TIM_OSSI_STATE(__STATE__)
#define	IS_TIM_LOCK_LEVEL(__LEVEL__)
#define	IS_TIM_BREAK_FILTER(__BRKFILTER__)
#define	IS_TIM_BREAK_STATE(__STATE__)
#define	IS_TIM_BREAK_POLARITY(__POLARITY__)
#define	IS_TIM_BREAK2_STATE(__STATE__)
#define	IS_TIM_BREAK2_POLARITY(__POLARITY__)
#define	IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__)
#define	IS_TIM_GROUPCH5(__OCREF__)
#define	IS_TIM_TRGO_SOURCE(__SOURCE__)
#define	IS_TIM_TRGO2_SOURCE(__SOURCE__)
#define	IS_TIM_MSM_STATE(__STATE__)
#define	IS_TIM_SLAVE_MODE(__MODE__)
#define	IS_TIM_PWM_MODE(__MODE__)
#define	IS_TIM_OC_MODE(__MODE__)
#define	IS_TIM_TRIGGER_SELECTION(__SELECTION__)
#define	IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__)
#define	IS_TIM_TRIGGERPOLARITY(__POLARITY__)
#define	IS_TIM_TRIGGERPRESCALER(__PRESCALER__)
#define	IS_TIM_TRIGGERFILTER(__ICFILTER__)
#define	IS_TIM_TI1SELECTION(__TI1SELECTION__)
#define	IS_TIM_DMA_LENGTH(__LENGTH__)
#define	IS_TIM_DMA_DATA_LENGTH(LENGTH)
#define	IS_TIM_IC_FILTER(__ICFILTER__)
#define	IS_TIM_DEADTIME(__DEADTIME__)
#define	IS_TIM_BREAK_SYSTEM(__CONFIG__)
#define	IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__)
#define	TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__)
#define	TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__)
#define	TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
#define	TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__)
#define	TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)
#define	TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__)
#define	TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)
#define	TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)
#define	TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__)
#define	TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)

Enumerations
enum	HAL_TIM_StateTypeDef { HAL_TIM_STATE_RESET = 0x00U , HAL_TIM_STATE_READY = 0x01U , HAL_TIM_STATE_BUSY = 0x02U , HAL_TIM_STATE_TIMEOUT = 0x03U , HAL_TIM_STATE_ERROR = 0x04U }
	HAL State structures definition. More...
enum	HAL_TIM_ChannelStateTypeDef { HAL_TIM_CHANNEL_STATE_RESET = 0x00U , HAL_TIM_CHANNEL_STATE_READY = 0x01U , HAL_TIM_CHANNEL_STATE_BUSY = 0x02U }
	TIM Channel States definition. More...
enum	HAL_TIM_DMABurstStateTypeDef { HAL_DMA_BURST_STATE_RESET = 0x00U , HAL_DMA_BURST_STATE_READY = 0x01U , HAL_DMA_BURST_STATE_BUSY = 0x02U }
	DMA Burst States definition. More...
enum	HAL_TIM_ActiveChannel { HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U , HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U , HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U , HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U , HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U , HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U , HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U }
	HAL Active channel structures definition. More...

Functions
HAL_StatusTypeDef	HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
HAL_StatusTypeDef	HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
void	HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
	TIM_Base MSP Initialization This function configures the hardware resources used in this example.
void	HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
	TIM_Base MSP De-Initialization This function freeze the hardware resources used in this example.
HAL_StatusTypeDef	HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
HAL_StatusTypeDef	HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
HAL_StatusTypeDef	HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
HAL_StatusTypeDef	HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
HAL_StatusTypeDef	HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef htim, const uint32_t pData, uint16_t Length)
HAL_StatusTypeDef	HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
HAL_StatusTypeDef	HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
HAL_StatusTypeDef	HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
void	HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
void	HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
HAL_StatusTypeDef	HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef	HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef	HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef	HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef	HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef htim, uint32_t Channel, const uint32_t pData, uint16_t Length)
HAL_StatusTypeDef	HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef	HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
HAL_StatusTypeDef	HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
void	HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
	TIM_PWM MSP Initialization This function configures the hardware resources used in this example.
void	HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
	TIM_PWM MSP De-Initialization This function freeze the hardware resources used in this example.
HAL_StatusTypeDef	HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef	HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef	HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef	HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef	HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef htim, uint32_t Channel, const uint32_t pData, uint16_t Length)
HAL_StatusTypeDef	HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef	HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
HAL_StatusTypeDef	HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
void	HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
void	HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
HAL_StatusTypeDef	HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef	HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef	HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef	HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef	HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
HAL_StatusTypeDef	HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef	HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
HAL_StatusTypeDef	HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
void	HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
void	HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
HAL_StatusTypeDef	HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
HAL_StatusTypeDef	HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
HAL_StatusTypeDef	HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
HAL_StatusTypeDef	HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
HAL_StatusTypeDef	HAL_TIM_Encoder_Init (TIM_HandleTypeDef htim, const TIM_Encoder_InitTypeDef sConfig)
HAL_StatusTypeDef	HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
void	HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
void	HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
HAL_StatusTypeDef	HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef	HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef	HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef	HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef	HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length)
HAL_StatusTypeDef	HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
void	HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
HAL_StatusTypeDef	HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef htim, const TIM_OC_InitTypeDef sConfig, uint32_t Channel)
HAL_StatusTypeDef	HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef htim, const TIM_OC_InitTypeDef sConfig, uint32_t Channel)
HAL_StatusTypeDef	HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef htim, const TIM_IC_InitTypeDef sConfig, uint32_t Channel)
HAL_StatusTypeDef	HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel)
HAL_StatusTypeDef	HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef htim, const TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel)
HAL_StatusTypeDef	HAL_TIM_ConfigClockSource (TIM_HandleTypeDef htim, const TIM_ClockConfigTypeDef sClockSourceConfig)
HAL_StatusTypeDef	HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
HAL_StatusTypeDef	HAL_TIM_SlaveConfigSynchro (TIM_HandleTypeDef htim, const TIM_SlaveConfigTypeDef sSlaveConfig)
HAL_StatusTypeDef	HAL_TIM_SlaveConfigSynchro_IT (TIM_HandleTypeDef htim, const TIM_SlaveConfigTypeDef sSlaveConfig)
HAL_StatusTypeDef	HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t BurstBuffer, uint32_t BurstLength)
HAL_StatusTypeDef	HAL_TIM_DMABurst_MultiWriteStart (TIM_HandleTypeDef htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
HAL_StatusTypeDef	HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
HAL_StatusTypeDef	HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t BurstBuffer, uint32_t BurstLength)
HAL_StatusTypeDef	HAL_TIM_DMABurst_MultiReadStart (TIM_HandleTypeDef htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
HAL_StatusTypeDef	HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
HAL_StatusTypeDef	HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
uint32_t	HAL_TIM_ReadCapturedValue (const TIM_HandleTypeDef *htim, uint32_t Channel)
void	HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
	Period elapsed callback in non blocking mode.
void	HAL_TIM_PeriodElapsedHalfCpltCallback (TIM_HandleTypeDef *htim)
void	HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
void	HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
void	HAL_TIM_IC_CaptureHalfCpltCallback (TIM_HandleTypeDef *htim)
void	HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
void	HAL_TIM_PWM_PulseFinishedHalfCpltCallback (TIM_HandleTypeDef *htim)
void	HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
void	HAL_TIM_TriggerHalfCpltCallback (TIM_HandleTypeDef *htim)
void	HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
HAL_TIM_StateTypeDef	HAL_TIM_Base_GetState (const TIM_HandleTypeDef *htim)
HAL_TIM_StateTypeDef	HAL_TIM_OC_GetState (const TIM_HandleTypeDef *htim)
HAL_TIM_StateTypeDef	HAL_TIM_PWM_GetState (const TIM_HandleTypeDef *htim)
HAL_TIM_StateTypeDef	HAL_TIM_IC_GetState (const TIM_HandleTypeDef *htim)
HAL_TIM_StateTypeDef	HAL_TIM_OnePulse_GetState (const TIM_HandleTypeDef *htim)
HAL_TIM_StateTypeDef	HAL_TIM_Encoder_GetState (const TIM_HandleTypeDef *htim)
HAL_TIM_ActiveChannel	HAL_TIM_GetActiveChannel (const TIM_HandleTypeDef *htim)
HAL_TIM_ChannelStateTypeDef	HAL_TIM_GetChannelState (const TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_TIM_DMABurstStateTypeDef	HAL_TIM_DMABurstState (const TIM_HandleTypeDef *htim)
void	TIM_Base_SetConfig (TIM_TypeDef TIMx, const TIM_Base_InitTypeDef Structure)
void	TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
void	TIM_OC2_SetConfig (TIM_TypeDef TIMx, const TIM_OC_InitTypeDef OC_Config)
void	TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
void	TIM_DMADelayPulseHalfCplt (DMA_HandleTypeDef *hdma)
void	TIM_DMAError (DMA_HandleTypeDef *hdma)
void	TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
void	TIM_DMACaptureHalfCplt (DMA_HandleTypeDef *hdma)
void	TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)

Detailed Description

Header file of TIM HAL module.

Author: MCD Application Team

Attention

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32h7xx_hal_tim.h.

Classes

Macros

Enumerations

Functions

Detailed Description