stm32h723xx.h File Reference

CMSIS STM32H723xx Device Peripheral Access Layer Header File. More...

#include "core_cm7.h"
#include "system_stm32h7xx.h"
#include <stdint.h>

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Classes
struct	ADC_TypeDef
	Analog to Digital Converter. More...
struct	ADC_Common_TypeDef
struct	VREFBUF_TypeDef
	VREFBUF. More...
struct	FDCAN_GlobalTypeDef
	FD Controller Area Network. More...
struct	TTCAN_TypeDef
	TTFD Controller Area Network. More...
struct	FDCAN_ClockCalibrationUnit_TypeDef
	FD Controller Area Network. More...
struct	CEC_TypeDef
	Consumer Electronics Control. More...
struct	CORDIC_TypeDef
	COordincate Rotation DIgital Computer. More...
struct	CRC_TypeDef
	CRC calculation unit. More...
struct	CRS_TypeDef
	Clock Recovery System. More...
struct	DAC_TypeDef
	Digital to Analog Converter. More...
struct	DFSDM_Filter_TypeDef
	DFSDM module registers. More...
struct	DFSDM_Channel_TypeDef
	DFSDM channel configuration registers. More...
struct	DBGMCU_TypeDef
	Debug MCU. More...
struct	DCMI_TypeDef
	DCMI. More...
struct	PSSI_TypeDef
	PSSI. More...
struct	DMA_Stream_TypeDef
	DMA Controller. More...
struct	DMA_TypeDef
struct	BDMA_Channel_TypeDef
struct	BDMA_TypeDef
struct	DMAMUX_Channel_TypeDef
struct	DMAMUX_ChannelStatus_TypeDef
struct	DMAMUX_RequestGen_TypeDef
struct	DMAMUX_RequestGenStatus_TypeDef
struct	MDMA_TypeDef
	MDMA Controller. More...
struct	MDMA_Channel_TypeDef
struct	DMA2D_TypeDef
	DMA2D Controller. More...
struct	ETH_TypeDef
	Ethernet MAC. More...
struct	EXTI_TypeDef
	External Interrupt/Event Controller. More...
struct	EXTI_Core_TypeDef
	This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. More...
struct	FLASH_TypeDef
	FLASH Registers. More...
struct	FMAC_TypeDef
	Filter and Mathematical ACcelerator. More...
struct	FMC_Bank1_TypeDef
	Flexible Memory Controller. More...
struct	FMC_Bank1E_TypeDef
	Flexible Memory Controller Bank1E. More...
struct	FMC_Bank2_TypeDef
	Flexible Memory Controller Bank2. More...
struct	FMC_Bank3_TypeDef
	Flexible Memory Controller Bank3. More...
struct	FMC_Bank5_6_TypeDef
	Flexible Memory Controller Bank5 and 6. More...
struct	GPIO_TypeDef
	General Purpose I/O. More...
struct	OPAMP_TypeDef
	Operational Amplifier (OPAMP). More...
struct	SYSCFG_TypeDef
	System configuration controller. More...
struct	I2C_TypeDef
	Inter-integrated Circuit Interface. More...
struct	IWDG_TypeDef
	Independent WATCHDOG. More...
struct	LTDC_TypeDef
	LCD-TFT Display Controller. More...
struct	LTDC_Layer_TypeDef
	LCD-TFT Display layer x Controller. More...
struct	PWR_TypeDef
	Power Control. More...
struct	RCC_TypeDef
	Reset and Clock Control. More...
struct	RTC_TypeDef
	Real-Time Clock. More...
struct	SAI_TypeDef
	Serial Audio Interface. More...
struct	SAI_Block_TypeDef
struct	SPDIFRX_TypeDef
	SPDIF-RX Interface. More...
struct	SDMMC_TypeDef
	Secure digital input/output Interface. More...
struct	DLYB_TypeDef
	Delay Block DLYB. More...
struct	HSEM_TypeDef
	HW Semaphore HSEM. More...
struct	HSEM_Common_TypeDef
struct	SPI_TypeDef
	Serial Peripheral Interface. More...
struct	DTS_TypeDef
	DTS. More...
struct	TIM_TypeDef
	TIM. More...
struct	LPTIM_TypeDef
	LPTIMIMER. More...
struct	COMPOPT_TypeDef
	Comparator. More...
struct	COMP_TypeDef
struct	COMP_Common_TypeDef
struct	USART_TypeDef
	Universal Synchronous Asynchronous Receiver Transmitter. More...
struct	SWPMI_TypeDef
	Single Wire Protocol Master Interface SPWMI. More...
struct	WWDG_TypeDef
	Window WATCHDOG. More...
struct	RAMECC_MonitorTypeDef
	RAM_ECC_Specific_Registers. More...
struct	RAMECC_TypeDef
struct	RNG_TypeDef
	RNG. More...
struct	MDIOS_TypeDef
	MDIOS. More...
struct	USB_OTG_GlobalTypeDef
	USB_OTG_Core_Registers. More...
struct	USB_OTG_DeviceTypeDef
	USB_OTG_device_Registers. More...
struct	USB_OTG_INEndpointTypeDef
	USB_OTG_IN_Endpoint-Specific_Register. More...
struct	USB_OTG_OUTEndpointTypeDef
	USB_OTG_OUT_Endpoint-Specific_Registers. More...
struct	USB_OTG_HostTypeDef
	USB_OTG_Host_Mode_Register_Structures. More...
struct	USB_OTG_HostChannelTypeDef
	USB_OTG_Host_Channel_Specific_Registers. More...
struct	OCTOSPI_TypeDef
	OCTO Serial Peripheral Interface. More...
struct	OCTOSPIM_TypeDef
	OCTO Serial Peripheral Interface IO Manager. More...
struct	GPV_TypeDef
	Global Programmer View. More...

Macros
#define	__CM7_REV   0x0110U
	Configuration of the Cortex-M7 Processor and Core Peripherals.
#define	__MPU_PRESENT   1U
	CM7 provides an MPU.
#define	__NVIC_PRIO_BITS   4U
	CM7 uses 4 Bits for the Priority Levels.
#define	__Vendor_SysTickConfig   0U
	Set to 1 if different SysTick Config is used.
#define	__FPU_PRESENT   1U
	FPU present.
#define	__ICACHE_PRESENT   1U
	CM7 instruction cache present.
#define	__DCACHE_PRESENT   1U
	CM7 data cache present.
#define	D1_ITCMRAM_BASE   (0x00000000UL)
	Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM.
#define	D1_ITCMICP_BASE   (0x00100000UL)
	Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM.
#define	D1_DTCMRAM_BASE   (0x20000000UL)
	Base address of : 128KB system data RAM accessible over DTCM.
#define	D1_AXIFLASH_BASE   (0x08000000UL)
	Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI.
#define	D1_AXIICP_BASE   (0x1FF00000UL)
	Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI.
#define	D1_AXISRAM1_BASE   (0x24000000UL)
	Base address of : (up to 128KB) system data RAM1 accessible over over AXI.
#define	D1_AXISRAM2_BASE   (0x24020000UL)
	Base address of : (up to 192KB) system data RAM2 accessible over over AXI to be shared with ITCM (64K granularity).
#define	D1_AXISRAM_BASE   D1_AXISRAM1_BASE
	Base address of : (up to 320KB) system data RAM1/2 accessible over over AXI.
#define	D2_AHBSRAM1_BASE   (0x30000000UL)
	Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge.
#define	D2_AHBSRAM2_BASE   (0x30004000UL)
	Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge.
#define	D2_AHBSRAM_BASE   D2_AHBSRAM1_BASE
	Base address of : (up to 32KB) system data RAM1/2 accessible over over AXI->AHB Bridge.
#define	D3_BKPSRAM_BASE   (0x38800000UL)
	Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge.
#define	D3_SRAM_BASE   (0x38000000UL)
	Base address of : Backup SRAM(16 KB) over AXI->AHB Bridge.
#define	PERIPH_BASE   (0x40000000UL)
	Base address of : AHB/APB Peripherals.
#define	OCTOSPI1_BASE   (0x90000000UL)
	Base address of : OCTOSPI1 memories accessible over AXI.
#define	OCTOSPI2_BASE   (0x70000000UL)
	Base address of : OCTOSPI2 memories accessible over AXI.
#define	FLASH_BANK1_BASE   (0x08000000UL)
	Base address of : (up to 1 MB) Flash Bank1 accessible over AXI.
#define	FLASH_END   (0x080FFFFFUL)
	FLASH end address.
#define	FLASH_BASE   FLASH_BANK1_BASE
	Device electronic signature memory map.
#define	UID_BASE   (0x1FF1E800UL)
	Unique device ID register base address.
#define	FLASHSIZE_BASE   (0x1FF1E880UL)
	FLASH Size register base address.
#define	D2_APB1PERIPH_BASE   PERIPH_BASE
#define	D2_APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000UL)
#define	D2_AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000UL)
#define	D2_AHB2PERIPH_BASE   (PERIPH_BASE + 0x08020000UL)
#define	D1_APB1PERIPH_BASE   (PERIPH_BASE + 0x10000000UL)
#define	D1_AHB1PERIPH_BASE   (PERIPH_BASE + 0x12000000UL)
#define	D3_APB1PERIPH_BASE   (PERIPH_BASE + 0x18000000UL)
#define	D3_AHB1PERIPH_BASE   (PERIPH_BASE + 0x18020000UL)
	Legacy Peripheral memory map.
#define	APB1PERIPH_BASE   PERIPH_BASE
#define	APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000UL)
#define	AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000UL)
#define	AHB2PERIPH_BASE   (PERIPH_BASE + 0x08000000UL)
	D1_AHB1PERIPH peripherals.
#define	MDMA_BASE   (D1_AHB1PERIPH_BASE + 0x0000UL)
#define	DMA2D_BASE   (D1_AHB1PERIPH_BASE + 0x1000UL)
#define	FLASH_R_BASE   (D1_AHB1PERIPH_BASE + 0x2000UL)
#define	FMC_R_BASE   (D1_AHB1PERIPH_BASE + 0x4000UL)
#define	OCTOSPI1_R_BASE   (D1_AHB1PERIPH_BASE + 0x5000UL)
#define	DLYB_OCTOSPI1_BASE   (D1_AHB1PERIPH_BASE + 0x6000UL)
#define	SDMMC1_BASE   (D1_AHB1PERIPH_BASE + 0x7000UL)
#define	DLYB_SDMMC1_BASE   (D1_AHB1PERIPH_BASE + 0x8000UL)
#define	RAMECC1_BASE   (D1_AHB1PERIPH_BASE + 0x9000UL)
#define	OCTOSPI2_R_BASE   (D1_AHB1PERIPH_BASE + 0xA000UL)
#define	DLYB_OCTOSPI2_BASE   (D1_AHB1PERIPH_BASE + 0xB000UL)
#define	OCTOSPIM_BASE   (D1_AHB1PERIPH_BASE + 0xB400UL)
	D2_AHB1PERIPH peripherals.
#define	DMA1_BASE   (D2_AHB1PERIPH_BASE + 0x0000UL)
#define	DMA2_BASE   (D2_AHB1PERIPH_BASE + 0x0400UL)
#define	DMAMUX1_BASE   (D2_AHB1PERIPH_BASE + 0x0800UL)
#define	ADC1_BASE   (D2_AHB1PERIPH_BASE + 0x2000UL)
#define	ADC2_BASE   (D2_AHB1PERIPH_BASE + 0x2100UL)
#define	ADC12_COMMON_BASE   (D2_AHB1PERIPH_BASE + 0x2300UL)
#define	ETH_BASE   (D2_AHB1PERIPH_BASE + 0x8000UL)
#define	ETH_MAC_BASE   (ETH_BASE)
	USB registers base address.
#define	USB1_OTG_HS_PERIPH_BASE   (0x40040000UL)
#define	USB_OTG_GLOBAL_BASE   (0x000UL)
#define	USB_OTG_DEVICE_BASE   (0x800UL)
#define	USB_OTG_IN_ENDPOINT_BASE   (0x900UL)
#define	USB_OTG_OUT_ENDPOINT_BASE   (0xB00UL)
#define	USB_OTG_EP_REG_SIZE   (0x20UL)
#define	USB_OTG_HOST_BASE   (0x400UL)
#define	USB_OTG_HOST_PORT_BASE   (0x440UL)
#define	USB_OTG_HOST_CHANNEL_BASE   (0x500UL)
#define	USB_OTG_HOST_CHANNEL_SIZE   (0x20UL)
#define	USB_OTG_PCGCCTL_BASE   (0xE00UL)
#define	USB_OTG_FIFO_BASE   (0x1000UL)
#define	USB_OTG_FIFO_SIZE   (0x1000UL)
	D2_AHB2PERIPH peripherals.
#define	DCMI_BASE   (D2_AHB2PERIPH_BASE + 0x0000UL)
#define	PSSI_BASE   (D2_AHB2PERIPH_BASE + 0x0400UL)
#define	RNG_BASE   (D2_AHB2PERIPH_BASE + 0x1800UL)
#define	SDMMC2_BASE   (D2_AHB2PERIPH_BASE + 0x2400UL)
#define	DLYB_SDMMC2_BASE   (D2_AHB2PERIPH_BASE + 0x2800UL)
#define	RAMECC2_BASE   (D2_AHB2PERIPH_BASE + 0x3000UL)
#define	FMAC_BASE   (D2_AHB2PERIPH_BASE + 0x4000UL)
#define	CORDIC_BASE   (D2_AHB2PERIPH_BASE + 0x4400UL)
	D3_AHB1PERIPH peripherals.
#define	GPIOA_BASE   (D3_AHB1PERIPH_BASE + 0x0000UL)
#define	GPIOB_BASE   (D3_AHB1PERIPH_BASE + 0x0400UL)
#define	GPIOC_BASE   (D3_AHB1PERIPH_BASE + 0x0800UL)
#define	GPIOD_BASE   (D3_AHB1PERIPH_BASE + 0x0C00UL)
#define	GPIOE_BASE   (D3_AHB1PERIPH_BASE + 0x1000UL)
#define	GPIOF_BASE   (D3_AHB1PERIPH_BASE + 0x1400UL)
#define	GPIOG_BASE   (D3_AHB1PERIPH_BASE + 0x1800UL)
#define	GPIOH_BASE   (D3_AHB1PERIPH_BASE + 0x1C00UL)
#define	GPIOJ_BASE   (D3_AHB1PERIPH_BASE + 0x2400UL)
#define	GPIOK_BASE   (D3_AHB1PERIPH_BASE + 0x2800UL)
#define	RCC_BASE   (D3_AHB1PERIPH_BASE + 0x4400UL)
#define	PWR_BASE   (D3_AHB1PERIPH_BASE + 0x4800UL)
#define	CRC_BASE   (D3_AHB1PERIPH_BASE + 0x4C00UL)
#define	BDMA_BASE   (D3_AHB1PERIPH_BASE + 0x5400UL)
#define	DMAMUX2_BASE   (D3_AHB1PERIPH_BASE + 0x5800UL)
#define	ADC3_BASE   (D3_AHB1PERIPH_BASE + 0x6000UL)
#define	ADC3_COMMON_BASE   (D3_AHB1PERIPH_BASE + 0x6300UL)
#define	HSEM_BASE   (D3_AHB1PERIPH_BASE + 0x6400UL)
#define	RAMECC3_BASE   (D3_AHB1PERIPH_BASE + 0x7000UL)
	D1_APB1PERIPH peripherals.
#define	LTDC_BASE   (D1_APB1PERIPH_BASE + 0x1000UL)
#define	LTDC_Layer1_BASE   (LTDC_BASE + 0x84UL)
#define	LTDC_Layer2_BASE   (LTDC_BASE + 0x104UL)
#define	WWDG1_BASE   (D1_APB1PERIPH_BASE + 0x3000UL)
	D2_APB1PERIPH peripherals.
#define	TIM2_BASE   (D2_APB1PERIPH_BASE + 0x0000UL)
#define	TIM3_BASE   (D2_APB1PERIPH_BASE + 0x0400UL)
#define	TIM4_BASE   (D2_APB1PERIPH_BASE + 0x0800UL)
#define	TIM5_BASE   (D2_APB1PERIPH_BASE + 0x0C00UL)
#define	TIM6_BASE   (D2_APB1PERIPH_BASE + 0x1000UL)
#define	TIM7_BASE   (D2_APB1PERIPH_BASE + 0x1400UL)
#define	TIM12_BASE   (D2_APB1PERIPH_BASE + 0x1800UL)
#define	TIM13_BASE   (D2_APB1PERIPH_BASE + 0x1C00UL)
#define	TIM14_BASE   (D2_APB1PERIPH_BASE + 0x2000UL)
#define	LPTIM1_BASE   (D2_APB1PERIPH_BASE + 0x2400UL)
#define	SPI2_BASE   (D2_APB1PERIPH_BASE + 0x3800UL)
#define	SPI3_BASE   (D2_APB1PERIPH_BASE + 0x3C00UL)
#define	SPDIFRX_BASE   (D2_APB1PERIPH_BASE + 0x4000UL)
#define	USART2_BASE   (D2_APB1PERIPH_BASE + 0x4400UL)
#define	USART3_BASE   (D2_APB1PERIPH_BASE + 0x4800UL)
#define	UART4_BASE   (D2_APB1PERIPH_BASE + 0x4C00UL)
#define	UART5_BASE   (D2_APB1PERIPH_BASE + 0x5000UL)
#define	I2C1_BASE   (D2_APB1PERIPH_BASE + 0x5400UL)
#define	I2C2_BASE   (D2_APB1PERIPH_BASE + 0x5800UL)
#define	I2C3_BASE   (D2_APB1PERIPH_BASE + 0x5C00UL)
#define	I2C5_BASE   (D2_APB1PERIPH_BASE + 0x6400UL)
#define	CEC_BASE   (D2_APB1PERIPH_BASE + 0x6C00UL)
#define	DAC1_BASE   (D2_APB1PERIPH_BASE + 0x7400UL)
#define	UART7_BASE   (D2_APB1PERIPH_BASE + 0x7800UL)
#define	UART8_BASE   (D2_APB1PERIPH_BASE + 0x7C00UL)
#define	CRS_BASE   (D2_APB1PERIPH_BASE + 0x8400UL)
#define	SWPMI1_BASE   (D2_APB1PERIPH_BASE + 0x8800UL)
#define	OPAMP_BASE   (D2_APB1PERIPH_BASE + 0x9000UL)
#define	OPAMP1_BASE   (D2_APB1PERIPH_BASE + 0x9000UL)
#define	OPAMP2_BASE   (D2_APB1PERIPH_BASE + 0x9010UL)
#define	MDIOS_BASE   (D2_APB1PERIPH_BASE + 0x9400UL)
#define	FDCAN1_BASE   (D2_APB1PERIPH_BASE + 0xA000UL)
#define	FDCAN2_BASE   (D2_APB1PERIPH_BASE + 0xA400UL)
#define	FDCAN_CCU_BASE   (D2_APB1PERIPH_BASE + 0xA800UL)
#define	SRAMCAN_BASE   (D2_APB1PERIPH_BASE + 0xAC00UL)
#define	FDCAN3_BASE   (D2_APB1PERIPH_BASE + 0xD400UL)
#define	TIM23_BASE   (D2_APB1PERIPH_BASE + 0xE000UL)
#define	TIM24_BASE   (D2_APB1PERIPH_BASE + 0xE400UL)
	D2_APB2PERIPH peripherals.
#define	TIM1_BASE   (D2_APB2PERIPH_BASE + 0x0000UL)
#define	TIM8_BASE   (D2_APB2PERIPH_BASE + 0x0400UL)
#define	USART1_BASE   (D2_APB2PERIPH_BASE + 0x1000UL)
#define	USART6_BASE   (D2_APB2PERIPH_BASE + 0x1400UL)
#define	UART9_BASE   (D2_APB2PERIPH_BASE + 0x1800UL)
#define	USART10_BASE   (D2_APB2PERIPH_BASE + 0x1C00UL)
#define	SPI1_BASE   (D2_APB2PERIPH_BASE + 0x3000UL)
#define	SPI4_BASE   (D2_APB2PERIPH_BASE + 0x3400UL)
#define	TIM15_BASE   (D2_APB2PERIPH_BASE + 0x4000UL)
#define	TIM16_BASE   (D2_APB2PERIPH_BASE + 0x4400UL)
#define	TIM17_BASE   (D2_APB2PERIPH_BASE + 0x4800UL)
#define	SPI5_BASE   (D2_APB2PERIPH_BASE + 0x5000UL)
#define	SAI1_BASE   (D2_APB2PERIPH_BASE + 0x5800UL)
#define	SAI1_Block_A_BASE   (SAI1_BASE + 0x004UL)
#define	SAI1_Block_B_BASE   (SAI1_BASE + 0x024UL)
#define	DFSDM1_BASE   (D2_APB2PERIPH_BASE + 0x7800UL)
#define	DFSDM1_Channel0_BASE   (DFSDM1_BASE + 0x00UL)
#define	DFSDM1_Channel1_BASE   (DFSDM1_BASE + 0x20UL)
#define	DFSDM1_Channel2_BASE   (DFSDM1_BASE + 0x40UL)
#define	DFSDM1_Channel3_BASE   (DFSDM1_BASE + 0x60UL)
#define	DFSDM1_Channel4_BASE   (DFSDM1_BASE + 0x80UL)
#define	DFSDM1_Channel5_BASE   (DFSDM1_BASE + 0xA0UL)
#define	DFSDM1_Channel6_BASE   (DFSDM1_BASE + 0xC0UL)
#define	DFSDM1_Channel7_BASE   (DFSDM1_BASE + 0xE0UL)
#define	DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)
#define	DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)
#define	DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)
#define	DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)
	D3_APB1PERIPH peripherals.
#define	EXTI_BASE   (D3_APB1PERIPH_BASE + 0x0000UL)
#define	EXTI_D1_BASE   (EXTI_BASE + 0x0080UL)
#define	EXTI_D2_BASE   (EXTI_BASE + 0x00C0UL)
#define	SYSCFG_BASE   (D3_APB1PERIPH_BASE + 0x0400UL)
#define	LPUART1_BASE   (D3_APB1PERIPH_BASE + 0x0C00UL)
#define	SPI6_BASE   (D3_APB1PERIPH_BASE + 0x1400UL)
#define	I2C4_BASE   (D3_APB1PERIPH_BASE + 0x1C00UL)
#define	LPTIM2_BASE   (D3_APB1PERIPH_BASE + 0x2400UL)
#define	LPTIM3_BASE   (D3_APB1PERIPH_BASE + 0x2800UL)
#define	LPTIM4_BASE   (D3_APB1PERIPH_BASE + 0x2C00UL)
#define	LPTIM5_BASE   (D3_APB1PERIPH_BASE + 0x3000UL)
#define	COMP12_BASE   (D3_APB1PERIPH_BASE + 0x3800UL)
#define	COMP1_BASE   (COMP12_BASE + 0x0CUL)
#define	COMP2_BASE   (COMP12_BASE + 0x10UL)
#define	VREFBUF_BASE   (D3_APB1PERIPH_BASE + 0x3C00UL)
#define	RTC_BASE   (D3_APB1PERIPH_BASE + 0x4000UL)
#define	IWDG1_BASE   (D3_APB1PERIPH_BASE + 0x4800UL)
#define	SAI4_BASE   (D3_APB1PERIPH_BASE + 0x5400UL)
#define	SAI4_Block_A_BASE   (SAI4_BASE + 0x004UL)
#define	SAI4_Block_B_BASE   (SAI4_BASE + 0x024UL)
#define	DTS_BASE   (D3_APB1PERIPH_BASE + 0x6800UL)
#define	BDMA_Channel0_BASE   (BDMA_BASE + 0x0008UL)
#define	BDMA_Channel1_BASE   (BDMA_BASE + 0x001CUL)
#define	BDMA_Channel2_BASE   (BDMA_BASE + 0x0030UL)
#define	BDMA_Channel3_BASE   (BDMA_BASE + 0x0044UL)
#define	BDMA_Channel4_BASE   (BDMA_BASE + 0x0058UL)
#define	BDMA_Channel5_BASE   (BDMA_BASE + 0x006CUL)
#define	BDMA_Channel6_BASE   (BDMA_BASE + 0x0080UL)
#define	BDMA_Channel7_BASE   (BDMA_BASE + 0x0094UL)
#define	DMAMUX2_Channel0_BASE   (DMAMUX2_BASE)
#define	DMAMUX2_Channel1_BASE   (DMAMUX2_BASE + 0x0004UL)
#define	DMAMUX2_Channel2_BASE   (DMAMUX2_BASE + 0x0008UL)
#define	DMAMUX2_Channel3_BASE   (DMAMUX2_BASE + 0x000CUL)
#define	DMAMUX2_Channel4_BASE   (DMAMUX2_BASE + 0x0010UL)
#define	DMAMUX2_Channel5_BASE   (DMAMUX2_BASE + 0x0014UL)
#define	DMAMUX2_Channel6_BASE   (DMAMUX2_BASE + 0x0018UL)
#define	DMAMUX2_Channel7_BASE   (DMAMUX2_BASE + 0x001CUL)
#define	DMAMUX2_RequestGenerator0_BASE   (DMAMUX2_BASE + 0x0100UL)
#define	DMAMUX2_RequestGenerator1_BASE   (DMAMUX2_BASE + 0x0104UL)
#define	DMAMUX2_RequestGenerator2_BASE   (DMAMUX2_BASE + 0x0108UL)
#define	DMAMUX2_RequestGenerator3_BASE   (DMAMUX2_BASE + 0x010CUL)
#define	DMAMUX2_RequestGenerator4_BASE   (DMAMUX2_BASE + 0x0110UL)
#define	DMAMUX2_RequestGenerator5_BASE   (DMAMUX2_BASE + 0x0114UL)
#define	DMAMUX2_RequestGenerator6_BASE   (DMAMUX2_BASE + 0x0118UL)
#define	DMAMUX2_RequestGenerator7_BASE   (DMAMUX2_BASE + 0x011CUL)
#define	DMAMUX2_ChannelStatus_BASE   (DMAMUX2_BASE + 0x0080UL)
#define	DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)
#define	DMA1_Stream0_BASE   (DMA1_BASE + 0x010UL)
#define	DMA1_Stream1_BASE   (DMA1_BASE + 0x028UL)
#define	DMA1_Stream2_BASE   (DMA1_BASE + 0x040UL)
#define	DMA1_Stream3_BASE   (DMA1_BASE + 0x058UL)
#define	DMA1_Stream4_BASE   (DMA1_BASE + 0x070UL)
#define	DMA1_Stream5_BASE   (DMA1_BASE + 0x088UL)
#define	DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0UL)
#define	DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8UL)
#define	DMA2_Stream0_BASE   (DMA2_BASE + 0x010UL)
#define	DMA2_Stream1_BASE   (DMA2_BASE + 0x028UL)
#define	DMA2_Stream2_BASE   (DMA2_BASE + 0x040UL)
#define	DMA2_Stream3_BASE   (DMA2_BASE + 0x058UL)
#define	DMA2_Stream4_BASE   (DMA2_BASE + 0x070UL)
#define	DMA2_Stream5_BASE   (DMA2_BASE + 0x088UL)
#define	DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0UL)
#define	DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8UL)
#define	DMAMUX1_Channel0_BASE   (DMAMUX1_BASE)
#define	DMAMUX1_Channel1_BASE   (DMAMUX1_BASE + 0x0004UL)
#define	DMAMUX1_Channel2_BASE   (DMAMUX1_BASE + 0x0008UL)
#define	DMAMUX1_Channel3_BASE   (DMAMUX1_BASE + 0x000CUL)
#define	DMAMUX1_Channel4_BASE   (DMAMUX1_BASE + 0x0010UL)
#define	DMAMUX1_Channel5_BASE   (DMAMUX1_BASE + 0x0014UL)
#define	DMAMUX1_Channel6_BASE   (DMAMUX1_BASE + 0x0018UL)
#define	DMAMUX1_Channel7_BASE   (DMAMUX1_BASE + 0x001CUL)
#define	DMAMUX1_Channel8_BASE   (DMAMUX1_BASE + 0x0020UL)
#define	DMAMUX1_Channel9_BASE   (DMAMUX1_BASE + 0x0024UL)
#define	DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)
#define	DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)
#define	DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)
#define	DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)
#define	DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)
#define	DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)
#define	DMAMUX1_RequestGenerator0_BASE   (DMAMUX1_BASE + 0x0100UL)
#define	DMAMUX1_RequestGenerator1_BASE   (DMAMUX1_BASE + 0x0104UL)
#define	DMAMUX1_RequestGenerator2_BASE   (DMAMUX1_BASE + 0x0108UL)
#define	DMAMUX1_RequestGenerator3_BASE   (DMAMUX1_BASE + 0x010CUL)
#define	DMAMUX1_RequestGenerator4_BASE   (DMAMUX1_BASE + 0x0110UL)
#define	DMAMUX1_RequestGenerator5_BASE   (DMAMUX1_BASE + 0x0114UL)
#define	DMAMUX1_RequestGenerator6_BASE   (DMAMUX1_BASE + 0x0118UL)
#define	DMAMUX1_RequestGenerator7_BASE   (DMAMUX1_BASE + 0x011CUL)
#define	DMAMUX1_ChannelStatus_BASE   (DMAMUX1_BASE + 0x0080UL)
#define	DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)
	FMC Banks registers base address.
#define	FMC_Bank1_R_BASE   (FMC_R_BASE + 0x0000UL)
#define	FMC_Bank1E_R_BASE   (FMC_R_BASE + 0x0104UL)
#define	FMC_Bank2_R_BASE   (FMC_R_BASE + 0x0060UL)
#define	FMC_Bank3_R_BASE   (FMC_R_BASE + 0x0080UL)
#define	FMC_Bank5_6_R_BASE   (FMC_R_BASE + 0x0140UL)
#define	DBGMCU_BASE   (0x5C001000UL)
#define	MDMA_Channel0_BASE   (MDMA_BASE + 0x00000040UL)
#define	MDMA_Channel1_BASE   (MDMA_BASE + 0x00000080UL)
#define	MDMA_Channel2_BASE   (MDMA_BASE + 0x000000C0UL)
#define	MDMA_Channel3_BASE   (MDMA_BASE + 0x00000100UL)
#define	MDMA_Channel4_BASE   (MDMA_BASE + 0x00000140UL)
#define	MDMA_Channel5_BASE   (MDMA_BASE + 0x00000180UL)
#define	MDMA_Channel6_BASE   (MDMA_BASE + 0x000001C0UL)
#define	MDMA_Channel7_BASE   (MDMA_BASE + 0x00000200UL)
#define	MDMA_Channel8_BASE   (MDMA_BASE + 0x00000240UL)
#define	MDMA_Channel9_BASE   (MDMA_BASE + 0x00000280UL)
#define	MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)
#define	MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)
#define	MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)
#define	MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)
#define	MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)
#define	MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)
#define	RAMECC1_Monitor1_BASE   (RAMECC1_BASE + 0x20UL)
#define	RAMECC1_Monitor2_BASE   (RAMECC1_BASE + 0x40UL)
#define	RAMECC1_Monitor3_BASE   (RAMECC1_BASE + 0x60UL)
#define	RAMECC1_Monitor4_BASE   (RAMECC1_BASE + 0x80UL)
#define	RAMECC1_Monitor5_BASE   (RAMECC1_BASE + 0xA0UL)
#define	RAMECC1_Monitor6_BASE   (RAMECC1_BASE + 0xC0UL)
#define	RAMECC2_Monitor1_BASE   (RAMECC2_BASE + 0x20UL)
#define	RAMECC2_Monitor2_BASE   (RAMECC2_BASE + 0x40UL)
#define	RAMECC2_Monitor3_BASE   (RAMECC2_BASE + 0x60UL)
#define	RAMECC3_Monitor1_BASE   (RAMECC3_BASE + 0x20UL)
#define	RAMECC3_Monitor2_BASE   (RAMECC3_BASE + 0x40UL)
#define	GPV_BASE   (PERIPH_BASE + 0x11000000UL)
	GPV_BASE (PERIPH_BASE + 0x11000000UL).
#define	TIM2   ((TIM_TypeDef *) TIM2_BASE)
#define	TIM3   ((TIM_TypeDef *) TIM3_BASE)
#define	TIM4   ((TIM_TypeDef *) TIM4_BASE)
#define	TIM5   ((TIM_TypeDef *) TIM5_BASE)
#define	TIM6   ((TIM_TypeDef *) TIM6_BASE)
#define	TIM7   ((TIM_TypeDef *) TIM7_BASE)
#define	TIM13   ((TIM_TypeDef *) TIM13_BASE)
#define	TIM14   ((TIM_TypeDef *) TIM14_BASE)
#define	VREFBUF   ((VREFBUF_TypeDef *) VREFBUF_BASE)
#define	RTC   ((RTC_TypeDef *) RTC_BASE)
#define	WWDG1   ((WWDG_TypeDef *) WWDG1_BASE)
#define	IWDG1   ((IWDG_TypeDef *) IWDG1_BASE)
#define	SPI2   ((SPI_TypeDef *) SPI2_BASE)
#define	SPI3   ((SPI_TypeDef *) SPI3_BASE)
#define	SPI4   ((SPI_TypeDef *) SPI4_BASE)
#define	SPI5   ((SPI_TypeDef *) SPI5_BASE)
#define	SPI6   ((SPI_TypeDef *) SPI6_BASE)
#define	USART2   ((USART_TypeDef *) USART2_BASE)
#define	USART3   ((USART_TypeDef *) USART3_BASE)
#define	USART6   ((USART_TypeDef *) USART6_BASE)
#define	USART10   ((USART_TypeDef *) USART10_BASE)
#define	UART7   ((USART_TypeDef *) UART7_BASE)
#define	UART8   ((USART_TypeDef *) UART8_BASE)
#define	UART9   ((USART_TypeDef *) UART9_BASE)
#define	CRS   ((CRS_TypeDef *) CRS_BASE)
#define	UART4   ((USART_TypeDef *) UART4_BASE)
#define	UART5   ((USART_TypeDef *) UART5_BASE)
#define	I2C1   ((I2C_TypeDef *) I2C1_BASE)
#define	I2C2   ((I2C_TypeDef *) I2C2_BASE)
#define	I2C3   ((I2C_TypeDef *) I2C3_BASE)
#define	I2C4   ((I2C_TypeDef *) I2C4_BASE)
#define	I2C5   ((I2C_TypeDef *) I2C5_BASE)
#define	FDCAN1   ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
#define	FDCAN2   ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
#define	FDCAN_CCU   ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
#define	FDCAN3   ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)
#define	TIM23   ((TIM_TypeDef *) TIM23_BASE)
#define	TIM24   ((TIM_TypeDef *) TIM24_BASE)
#define	CEC   ((CEC_TypeDef *) CEC_BASE)
#define	LPTIM1   ((LPTIM_TypeDef *) LPTIM1_BASE)
#define	PWR   ((PWR_TypeDef *) PWR_BASE)
#define	DAC1   ((DAC_TypeDef *) DAC1_BASE)
#define	LPUART1   ((USART_TypeDef *) LPUART1_BASE)
#define	SWPMI1   ((SWPMI_TypeDef *) SWPMI1_BASE)
#define	LPTIM2   ((LPTIM_TypeDef *) LPTIM2_BASE)
#define	LPTIM3   ((LPTIM_TypeDef *) LPTIM3_BASE)
#define	DTS   ((DTS_TypeDef *) DTS_BASE)
#define	LPTIM4   ((LPTIM_TypeDef *) LPTIM4_BASE)
#define	LPTIM5   ((LPTIM_TypeDef *) LPTIM5_BASE)
#define	SYSCFG   ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define	COMP12   ((COMPOPT_TypeDef *) COMP12_BASE)
#define	COMP1   ((COMP_TypeDef *) COMP1_BASE)
#define	COMP2   ((COMP_TypeDef *) COMP2_BASE)
#define	COMP12_COMMON   ((COMP_Common_TypeDef *) COMP2_BASE)
#define	OPAMP   ((OPAMP_TypeDef *) OPAMP_BASE)
#define	OPAMP1   ((OPAMP_TypeDef *) OPAMP1_BASE)
#define	OPAMP2   ((OPAMP_TypeDef *) OPAMP2_BASE)
#define	EXTI   ((EXTI_TypeDef *) EXTI_BASE)
#define	EXTI_D1   ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
#define	EXTI_D2   ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
#define	TIM1   ((TIM_TypeDef *) TIM1_BASE)
#define	SPI1   ((SPI_TypeDef *) SPI1_BASE)
#define	TIM8   ((TIM_TypeDef *) TIM8_BASE)
#define	USART1   ((USART_TypeDef *) USART1_BASE)
#define	TIM12   ((TIM_TypeDef *) TIM12_BASE)
#define	TIM15   ((TIM_TypeDef *) TIM15_BASE)
#define	TIM16   ((TIM_TypeDef *) TIM16_BASE)
#define	TIM17   ((TIM_TypeDef *) TIM17_BASE)
#define	SAI1   ((SAI_TypeDef *) SAI1_BASE)
#define	SAI1_Block_A   ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
#define	SAI1_Block_B   ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
#define	SAI4   ((SAI_TypeDef *) SAI4_BASE)
#define	SAI4_Block_A   ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
#define	SAI4_Block_B   ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
#define	SPDIFRX   ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
#define	DFSDM1_Channel0   ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
#define	DFSDM1_Channel1   ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
#define	DFSDM1_Channel2   ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
#define	DFSDM1_Channel3   ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
#define	DFSDM1_Channel4   ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
#define	DFSDM1_Channel5   ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
#define	DFSDM1_Channel6   ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
#define	DFSDM1_Channel7   ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
#define	DFSDM1_Filter0   ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
#define	DFSDM1_Filter1   ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
#define	DFSDM1_Filter2   ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
#define	DFSDM1_Filter3   ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
#define	DMA2D   ((DMA2D_TypeDef *) DMA2D_BASE)
#define	DCMI   ((DCMI_TypeDef *) DCMI_BASE)
#define	PSSI   ((PSSI_TypeDef *) PSSI_BASE)
#define	RCC   ((RCC_TypeDef *) RCC_BASE)
#define	FLASH   ((FLASH_TypeDef *) FLASH_R_BASE)
#define	CRC   ((CRC_TypeDef *) CRC_BASE)
#define	GPIOA   ((GPIO_TypeDef *) GPIOA_BASE)
#define	GPIOB   ((GPIO_TypeDef *) GPIOB_BASE)
#define	GPIOC   ((GPIO_TypeDef *) GPIOC_BASE)
#define	GPIOD   ((GPIO_TypeDef *) GPIOD_BASE)
#define	GPIOE   ((GPIO_TypeDef *) GPIOE_BASE)
#define	GPIOF   ((GPIO_TypeDef *) GPIOF_BASE)
#define	GPIOG   ((GPIO_TypeDef *) GPIOG_BASE)
#define	GPIOH   ((GPIO_TypeDef *) GPIOH_BASE)
#define	GPIOJ   ((GPIO_TypeDef *) GPIOJ_BASE)
#define	GPIOK   ((GPIO_TypeDef *) GPIOK_BASE)
#define	ADC1   ((ADC_TypeDef *) ADC1_BASE)
#define	ADC2   ((ADC_TypeDef *) ADC2_BASE)
#define	ADC3   ((ADC_TypeDef *) ADC3_BASE)
#define	ADC3_COMMON   ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
#define	ADC12_COMMON   ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
#define	RNG   ((RNG_TypeDef *) RNG_BASE)
#define	SDMMC2   ((SDMMC_TypeDef *) SDMMC2_BASE)
#define	DLYB_SDMMC2   ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
#define	FMAC   ((FMAC_TypeDef *) FMAC_BASE)
#define	CORDIC   ((CORDIC_TypeDef *) CORDIC_BASE)
#define	BDMA   ((BDMA_TypeDef *) BDMA_BASE)
#define	BDMA_Channel0   ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
#define	BDMA_Channel1   ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
#define	BDMA_Channel2   ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
#define	BDMA_Channel3   ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
#define	BDMA_Channel4   ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
#define	BDMA_Channel5   ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
#define	BDMA_Channel6   ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
#define	BDMA_Channel7   ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
#define	RAMECC1   ((RAMECC_TypeDef *)RAMECC1_BASE)
#define	RAMECC1_Monitor1   ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)
#define	RAMECC1_Monitor2   ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)
#define	RAMECC1_Monitor3   ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)
#define	RAMECC1_Monitor4   ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)
#define	RAMECC1_Monitor5   ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)
#define	RAMECC1_Monitor6   ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor6_BASE)
#define	RAMECC2   ((RAMECC_TypeDef *)RAMECC2_BASE)
#define	RAMECC2_Monitor1   ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)
#define	RAMECC2_Monitor2   ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)
#define	RAMECC2_Monitor3   ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)
#define	RAMECC3   ((RAMECC_TypeDef *)RAMECC3_BASE)
#define	RAMECC3_Monitor1   ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)
#define	RAMECC3_Monitor2   ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)
#define	DMAMUX2   ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
#define	DMAMUX2_Channel0   ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
#define	DMAMUX2_Channel1   ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
#define	DMAMUX2_Channel2   ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
#define	DMAMUX2_Channel3   ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
#define	DMAMUX2_Channel4   ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
#define	DMAMUX2_Channel5   ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
#define	DMAMUX2_Channel6   ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
#define	DMAMUX2_Channel7   ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
#define	DMAMUX2_RequestGenerator0   ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
#define	DMAMUX2_RequestGenerator1   ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
#define	DMAMUX2_RequestGenerator2   ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
#define	DMAMUX2_RequestGenerator3   ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
#define	DMAMUX2_RequestGenerator4   ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
#define	DMAMUX2_RequestGenerator5   ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
#define	DMAMUX2_RequestGenerator6   ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
#define	DMAMUX2_RequestGenerator7   ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
#define	DMAMUX2_ChannelStatus   ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
#define	DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
#define	DMA2   ((DMA_TypeDef *) DMA2_BASE)
#define	DMA2_Stream0   ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
#define	DMA2_Stream1   ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
#define	DMA2_Stream2   ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
#define	DMA2_Stream3   ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
#define	DMA2_Stream4   ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
#define	DMA2_Stream5   ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
#define	DMA2_Stream6   ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
#define	DMA2_Stream7   ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
#define	DMA1   ((DMA_TypeDef *) DMA1_BASE)
#define	DMA1_Stream0   ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
#define	DMA1_Stream1   ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
#define	DMA1_Stream2   ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
#define	DMA1_Stream3   ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
#define	DMA1_Stream4   ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
#define	DMA1_Stream5   ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
#define	DMA1_Stream6   ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
#define	DMA1_Stream7   ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
#define	DMAMUX1   ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
#define	DMAMUX1_Channel0   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define	DMAMUX1_Channel1   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
#define	DMAMUX1_Channel2   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
#define	DMAMUX1_Channel3   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
#define	DMAMUX1_Channel4   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
#define	DMAMUX1_Channel5   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
#define	DMAMUX1_Channel6   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
#define	DMAMUX1_Channel7   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
#define	DMAMUX1_Channel8   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
#define	DMAMUX1_Channel9   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
#define	DMAMUX1_Channel10   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
#define	DMAMUX1_Channel11   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
#define	DMAMUX1_Channel12   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
#define	DMAMUX1_Channel13   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
#define	DMAMUX1_Channel14   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
#define	DMAMUX1_Channel15   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
#define	DMAMUX1_RequestGenerator0   ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
#define	DMAMUX1_RequestGenerator1   ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
#define	DMAMUX1_RequestGenerator2   ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
#define	DMAMUX1_RequestGenerator3   ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
#define	DMAMUX1_RequestGenerator4   ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
#define	DMAMUX1_RequestGenerator5   ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
#define	DMAMUX1_RequestGenerator6   ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
#define	DMAMUX1_RequestGenerator7   ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
#define	DMAMUX1_ChannelStatus   ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
#define	DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
#define	FMC_Bank1_R   ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
#define	FMC_Bank1E_R   ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
#define	FMC_Bank2_R   ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
#define	FMC_Bank3_R   ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
#define	FMC_Bank5_6_R   ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
#define	OCTOSPI1   ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)
#define	DLYB_OCTOSPI1   ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)
#define	OCTOSPI2   ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)
#define	DLYB_OCTOSPI2   ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)
#define	OCTOSPIM   ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)
#define	SDMMC1   ((SDMMC_TypeDef *) SDMMC1_BASE)
#define	DLYB_SDMMC1   ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
#define	DBGMCU   ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define	HSEM   ((HSEM_TypeDef *) HSEM_BASE)
#define	HSEM_COMMON   ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
#define	LTDC   ((LTDC_TypeDef *)LTDC_BASE)
#define	LTDC_Layer1   ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
#define	LTDC_Layer2   ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
#define	MDIOS   ((MDIOS_TypeDef *) MDIOS_BASE)
#define	ETH   ((ETH_TypeDef *)ETH_BASE)
#define	MDMA   ((MDMA_TypeDef *)MDMA_BASE)
#define	MDMA_Channel0   ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
#define	MDMA_Channel1   ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
#define	MDMA_Channel2   ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
#define	MDMA_Channel3   ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
#define	MDMA_Channel4   ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
#define	MDMA_Channel5   ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
#define	MDMA_Channel6   ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
#define	MDMA_Channel7   ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
#define	MDMA_Channel8   ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
#define	MDMA_Channel9   ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
#define	MDMA_Channel10   ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
#define	MDMA_Channel11   ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
#define	MDMA_Channel12   ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
#define	MDMA_Channel13   ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
#define	MDMA_Channel14   ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
#define	MDMA_Channel15   ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
#define	USB1_OTG_HS   ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
#define	USB_OTG_HS   USB1_OTG_HS
#define	USB_OTG_HS_PERIPH_BASE   USB1_OTG_HS_PERIPH_BASE
#define	GPV   ((GPV_TypeDef *) GPV_BASE)
#define	LSI_STARTUP_TIME   130U
	LSI Maximum startup time in us.
#define	ADC_VER_V5_V90
#define	ADC_ISR_ADRDY_Pos   (0U)
#define	ADC_ISR_ADRDY_Msk   (0x1UL << ADC_ISR_ADRDY_Pos)
	0x00000001
#define	ADC_ISR_ADRDY   ADC_ISR_ADRDY_Msk
	ADC Ready (ADRDY) flag.
#define	ADC_ISR_EOSMP_Pos   (1U)
#define	ADC_ISR_EOSMP_Msk   (0x1UL << ADC_ISR_EOSMP_Pos)
	0x00000002
#define	ADC_ISR_EOSMP   ADC_ISR_EOSMP_Msk
	ADC End of Sampling flag.
#define	ADC_ISR_EOC_Pos   (2U)
#define	ADC_ISR_EOC_Msk   (0x1UL << ADC_ISR_EOC_Pos)
	0x00000004
#define	ADC_ISR_EOC   ADC_ISR_EOC_Msk
	ADC End of Regular Conversion flag.
#define	ADC_ISR_EOS_Pos   (3U)
#define	ADC_ISR_EOS_Msk   (0x1UL << ADC_ISR_EOS_Pos)
	0x00000008
#define	ADC_ISR_EOS   ADC_ISR_EOS_Msk
	ADC End of Regular sequence of Conversions flag.
#define	ADC_ISR_OVR_Pos   (4U)
#define	ADC_ISR_OVR_Msk   (0x1UL << ADC_ISR_OVR_Pos)
	0x00000010
#define	ADC_ISR_OVR   ADC_ISR_OVR_Msk
	ADC overrun flag.
#define	ADC_ISR_JEOC_Pos   (5U)
#define	ADC_ISR_JEOC_Msk   (0x1UL << ADC_ISR_JEOC_Pos)
	0x00000020
#define	ADC_ISR_JEOC   ADC_ISR_JEOC_Msk
	ADC End of Injected Conversion flag.
#define	ADC_ISR_JEOS_Pos   (6U)
#define	ADC_ISR_JEOS_Msk   (0x1UL << ADC_ISR_JEOS_Pos)
	0x00000040
#define	ADC_ISR_JEOS   ADC_ISR_JEOS_Msk
	ADC End of Injected sequence of Conversions flag.
#define	ADC_ISR_AWD1_Pos   (7U)
#define	ADC_ISR_AWD1_Msk   (0x1UL << ADC_ISR_AWD1_Pos)
	0x00000080
#define	ADC_ISR_AWD1   ADC_ISR_AWD1_Msk
	ADC Analog watchdog 1 flag.
#define	ADC_ISR_AWD2_Pos   (8U)
#define	ADC_ISR_AWD2_Msk   (0x1UL << ADC_ISR_AWD2_Pos)
	0x00000100
#define	ADC_ISR_AWD2   ADC_ISR_AWD2_Msk
	ADC Analog watchdog 2 flag.
#define	ADC_ISR_AWD3_Pos   (9U)
#define	ADC_ISR_AWD3_Msk   (0x1UL << ADC_ISR_AWD3_Pos)
	0x00000200
#define	ADC_ISR_AWD3   ADC_ISR_AWD3_Msk
	ADC Analog watchdog 3 flag.
#define	ADC_ISR_JQOVF_Pos   (10U)
#define	ADC_ISR_JQOVF_Msk   (0x1UL << ADC_ISR_JQOVF_Pos)
	0x00000400
#define	ADC_ISR_JQOVF   ADC_ISR_JQOVF_Msk
	ADC Injected Context Queue Overflow flag.
#define	ADC_ISR_LDORDY_Pos   (12U)
#define	ADC_ISR_LDORDY_Msk   (0x1UL << ADC_ISR_LDORDY_Pos)
	0x00001000
#define	ADC_ISR_LDORDY   ADC_ISR_LDORDY_Msk
	ADC LDO output voltage ready bit.
#define	ADC_IER_ADRDYIE_Pos   (0U)
#define	ADC_IER_ADRDYIE_Msk   (0x1UL << ADC_IER_ADRDYIE_Pos)
	0x00000001
#define	ADC_IER_ADRDYIE   ADC_IER_ADRDYIE_Msk
	ADC Ready (ADRDY) interrupt source.
#define	ADC_IER_EOSMPIE_Pos   (1U)
#define	ADC_IER_EOSMPIE_Msk   (0x1UL << ADC_IER_EOSMPIE_Pos)
	0x00000002
#define	ADC_IER_EOSMPIE   ADC_IER_EOSMPIE_Msk
	ADC End of Sampling interrupt source.
#define	ADC_IER_EOCIE_Pos   (2U)
#define	ADC_IER_EOCIE_Msk   (0x1UL << ADC_IER_EOCIE_Pos)
	0x00000004
#define	ADC_IER_EOCIE   ADC_IER_EOCIE_Msk
	ADC End of Regular Conversion interrupt source.
#define	ADC_IER_EOSIE_Pos   (3U)
#define	ADC_IER_EOSIE_Msk   (0x1UL << ADC_IER_EOSIE_Pos)
	0x00000008
#define	ADC_IER_EOSIE   ADC_IER_EOSIE_Msk
	ADC End of Regular sequence of Conversions interrupt source.
#define	ADC_IER_OVRIE_Pos   (4U)
#define	ADC_IER_OVRIE_Msk   (0x1UL << ADC_IER_OVRIE_Pos)
	0x00000010
#define	ADC_IER_OVRIE   ADC_IER_OVRIE_Msk
	ADC overrun interrupt source.
#define	ADC_IER_JEOCIE_Pos   (5U)
#define	ADC_IER_JEOCIE_Msk   (0x1UL << ADC_IER_JEOCIE_Pos)
	0x00000020
#define	ADC_IER_JEOCIE   ADC_IER_JEOCIE_Msk
	ADC End of Injected Conversion interrupt source.
#define	ADC_IER_JEOSIE_Pos   (6U)
#define	ADC_IER_JEOSIE_Msk   (0x1UL << ADC_IER_JEOSIE_Pos)
	0x00000040
#define	ADC_IER_JEOSIE   ADC_IER_JEOSIE_Msk
	ADC End of Injected sequence of Conversions interrupt source.
#define	ADC_IER_AWD1IE_Pos   (7U)
#define	ADC_IER_AWD1IE_Msk   (0x1UL << ADC_IER_AWD1IE_Pos)
	0x00000080
#define	ADC_IER_AWD1IE   ADC_IER_AWD1IE_Msk
	ADC Analog watchdog 1 interrupt source.
#define	ADC_IER_AWD2IE_Pos   (8U)
#define	ADC_IER_AWD2IE_Msk   (0x1UL << ADC_IER_AWD2IE_Pos)
	0x00000100
#define	ADC_IER_AWD2IE   ADC_IER_AWD2IE_Msk
	ADC Analog watchdog 2 interrupt source.
#define	ADC_IER_AWD3IE_Pos   (9U)
#define	ADC_IER_AWD3IE_Msk   (0x1UL << ADC_IER_AWD3IE_Pos)
	0x00000200
#define	ADC_IER_AWD3IE   ADC_IER_AWD3IE_Msk
	ADC Analog watchdog 3 interrupt source.
#define	ADC_IER_JQOVFIE_Pos   (10U)
#define	ADC_IER_JQOVFIE_Msk   (0x1UL << ADC_IER_JQOVFIE_Pos)
	0x00000400
#define	ADC_IER_JQOVFIE   ADC_IER_JQOVFIE_Msk
	ADC Injected Context Queue Overflow interrupt source.
#define	ADC_CR_ADEN_Pos   (0U)
#define	ADC_CR_ADEN_Msk   (0x1UL << ADC_CR_ADEN_Pos)
	0x00000001
#define	ADC_CR_ADEN   ADC_CR_ADEN_Msk
	ADC Enable control.
#define	ADC_CR_ADDIS_Pos   (1U)
#define	ADC_CR_ADDIS_Msk   (0x1UL << ADC_CR_ADDIS_Pos)
	0x00000002
#define	ADC_CR_ADDIS   ADC_CR_ADDIS_Msk
	ADC Disable command.
#define	ADC_CR_ADSTART_Pos   (2U)
#define	ADC_CR_ADSTART_Msk   (0x1UL << ADC_CR_ADSTART_Pos)
	0x00000004
#define	ADC_CR_ADSTART   ADC_CR_ADSTART_Msk
	ADC Start of Regular conversion.
#define	ADC_CR_JADSTART_Pos   (3U)
#define	ADC_CR_JADSTART_Msk   (0x1UL << ADC_CR_JADSTART_Pos)
	0x00000008
#define	ADC_CR_JADSTART   ADC_CR_JADSTART_Msk
	ADC Start of injected conversion.
#define	ADC_CR_ADSTP_Pos   (4U)
#define	ADC_CR_ADSTP_Msk   (0x1UL << ADC_CR_ADSTP_Pos)
	0x00000010
#define	ADC_CR_ADSTP   ADC_CR_ADSTP_Msk
	ADC Stop of Regular conversion.
#define	ADC_CR_JADSTP_Pos   (5U)
#define	ADC_CR_JADSTP_Msk   (0x1UL << ADC_CR_JADSTP_Pos)
	0x00000020
#define	ADC_CR_JADSTP   ADC_CR_JADSTP_Msk
	ADC Stop of injected conversion.
#define	ADC_CR_BOOST_Pos   (8U)
#define	ADC_CR_BOOST_Msk   (0x3UL << ADC_CR_BOOST_Pos)
	0x00000300
#define	ADC_CR_BOOST   ADC_CR_BOOST_Msk
	ADC Boost Mode configuration.
#define	ADC_CR_BOOST_0   (0x1UL << ADC_CR_BOOST_Pos)
	0x00000100
#define	ADC_CR_BOOST_1   (0x2UL << ADC_CR_BOOST_Pos)
	0x00000200
#define	ADC_CR_ADCALLIN_Pos   (16U)
#define	ADC_CR_ADCALLIN_Msk   (0x1UL << ADC_CR_ADCALLIN_Pos)
	0x00010000
#define	ADC_CR_ADCALLIN   ADC_CR_ADCALLIN_Msk
	ADC Linearity calibration.
#define	ADC_CR_LINCALRDYW1_Pos   (22U)
#define	ADC_CR_LINCALRDYW1_Msk   (0x1UL << ADC_CR_LINCALRDYW1_Pos)
	0x00400000
#define	ADC_CR_LINCALRDYW1   ADC_CR_LINCALRDYW1_Msk
	ADC Linearity calibration ready Word 1.
#define	ADC_CR_LINCALRDYW2_Pos   (23U)
#define	ADC_CR_LINCALRDYW2_Msk   (0x1UL << ADC_CR_LINCALRDYW2_Pos)
	0x00800000
#define	ADC_CR_LINCALRDYW2   ADC_CR_LINCALRDYW2_Msk
	ADC Linearity calibration ready Word 2.
#define	ADC_CR_LINCALRDYW3_Pos   (24U)
#define	ADC_CR_LINCALRDYW3_Msk   (0x1UL << ADC_CR_LINCALRDYW3_Pos)
	0x01000000
#define	ADC_CR_LINCALRDYW3   ADC_CR_LINCALRDYW3_Msk
	ADC Linearity calibration ready Word 3.
#define	ADC_CR_LINCALRDYW4_Pos   (25U)
#define	ADC_CR_LINCALRDYW4_Msk   (0x1UL << ADC_CR_LINCALRDYW4_Pos)
	0x02000000
#define	ADC_CR_LINCALRDYW4   ADC_CR_LINCALRDYW4_Msk
	ADC Linearity calibration ready Word 4.
#define	ADC_CR_LINCALRDYW5_Pos   (26U)
#define	ADC_CR_LINCALRDYW5_Msk   (0x1UL << ADC_CR_LINCALRDYW5_Pos)
	0x04000000
#define	ADC_CR_LINCALRDYW5   ADC_CR_LINCALRDYW5_Msk
	ADC Linearity calibration ready Word 5.
#define	ADC_CR_LINCALRDYW6_Pos   (27U)
#define	ADC_CR_LINCALRDYW6_Msk   (0x1UL << ADC_CR_LINCALRDYW6_Pos)
	0x08000000
#define	ADC_CR_LINCALRDYW6   ADC_CR_LINCALRDYW6_Msk
	ADC Linearity calibration ready Word 6.
#define	ADC_CR_ADVREGEN_Pos   (28U)
#define	ADC_CR_ADVREGEN_Msk   (0x1UL << ADC_CR_ADVREGEN_Pos)
	0x10000000
#define	ADC_CR_ADVREGEN   ADC_CR_ADVREGEN_Msk
	ADC Voltage regulator Enable.
#define	ADC_CR_DEEPPWD_Pos   (29U)
#define	ADC_CR_DEEPPWD_Msk   (0x1UL << ADC_CR_DEEPPWD_Pos)
	0x20000000
#define	ADC_CR_DEEPPWD   ADC_CR_DEEPPWD_Msk
	ADC Deep power down Enable.
#define	ADC_CR_ADCALDIF_Pos   (30U)
#define	ADC_CR_ADCALDIF_Msk   (0x1UL << ADC_CR_ADCALDIF_Pos)
	0x40000000
#define	ADC_CR_ADCALDIF   ADC_CR_ADCALDIF_Msk
	ADC Differential Mode for calibration.
#define	ADC_CR_ADCAL_Pos   (31U)
#define	ADC_CR_ADCAL_Msk   (0x1UL << ADC_CR_ADCAL_Pos)
	0x80000000
#define	ADC_CR_ADCAL   ADC_CR_ADCAL_Msk
	ADC Calibration.
#define	ADC_CFGR_DMNGT_Pos   (0U)
#define	ADC_CFGR_DMNGT_Msk   (0x3UL << ADC_CFGR_DMNGT_Pos)
	0x00000003
#define	ADC_CFGR_DMNGT   ADC_CFGR_DMNGT_Msk
	ADC Data Management configuration.
#define	ADC_CFGR_DMNGT_0   (0x1UL << ADC_CFGR_DMNGT_Pos)
	0x00000001
#define	ADC_CFGR_DMNGT_1   (0x2UL << ADC_CFGR_DMNGT_Pos)
	0x00000002
#define	ADC_CFGR_RES_Pos   (2U)
#define	ADC_CFGR_RES_Msk   (0x7UL << ADC_CFGR_RES_Pos)
	0x0000001C
#define	ADC_CFGR_RES   ADC_CFGR_RES_Msk
	ADC Data resolution.
#define	ADC_CFGR_RES_0   (0x1UL << ADC_CFGR_RES_Pos)
	0x00000004
#define	ADC_CFGR_RES_1   (0x2UL << ADC_CFGR_RES_Pos)
	0x00000008
#define	ADC_CFGR_RES_2   (0x4UL << ADC_CFGR_RES_Pos)
	0x00000010
#define	ADC_CFGR_EXTSEL_Pos   (5U)
#define	ADC_CFGR_EXTSEL_Msk   (0x1FUL << ADC_CFGR_EXTSEL_Pos)
	0x000003E0
#define	ADC_CFGR_EXTSEL   ADC_CFGR_EXTSEL_Msk
	ADC External trigger selection for regular group.
#define	ADC_CFGR_EXTSEL_0   (0x01UL << ADC_CFGR_EXTSEL_Pos)
	0x00000020
#define	ADC_CFGR_EXTSEL_1   (0x02UL << ADC_CFGR_EXTSEL_Pos)
	0x00000040
#define	ADC_CFGR_EXTSEL_2   (0x04UL << ADC_CFGR_EXTSEL_Pos)
	0x00000080
#define	ADC_CFGR_EXTSEL_3   (0x08UL << ADC_CFGR_EXTSEL_Pos)
	0x00000100
#define	ADC_CFGR_EXTSEL_4   (0x10UL << ADC_CFGR_EXTSEL_Pos)
	0x00000200
#define	ADC_CFGR_EXTEN_Pos   (10U)
#define	ADC_CFGR_EXTEN_Msk   (0x3UL << ADC_CFGR_EXTEN_Pos)
	0x00000C00
#define	ADC_CFGR_EXTEN   ADC_CFGR_EXTEN_Msk
	ADC External trigger enable and polarity selection for regular channels.
#define	ADC_CFGR_EXTEN_0   (0x1UL << ADC_CFGR_EXTEN_Pos)
	0x00000400
#define	ADC_CFGR_EXTEN_1   (0x2UL << ADC_CFGR_EXTEN_Pos)
	0x00000800
#define	ADC_CFGR_OVRMOD_Pos   (12U)
#define	ADC_CFGR_OVRMOD_Msk   (0x1UL << ADC_CFGR_OVRMOD_Pos)
	0x00001000
#define	ADC_CFGR_OVRMOD   ADC_CFGR_OVRMOD_Msk
	ADC overrun mode.
#define	ADC_CFGR_CONT_Pos   (13U)
#define	ADC_CFGR_CONT_Msk   (0x1UL << ADC_CFGR_CONT_Pos)
	0x00002000
#define	ADC_CFGR_CONT   ADC_CFGR_CONT_Msk
	ADC Single/continuous conversion mode for regular conversion.
#define	ADC_CFGR_AUTDLY_Pos   (14U)
#define	ADC_CFGR_AUTDLY_Msk   (0x1UL << ADC_CFGR_AUTDLY_Pos)
	0x00004000
#define	ADC_CFGR_AUTDLY   ADC_CFGR_AUTDLY_Msk
	ADC Delayed conversion mode.
#define	ADC_CFGR_DISCEN_Pos   (16U)
#define	ADC_CFGR_DISCEN_Msk   (0x1UL << ADC_CFGR_DISCEN_Pos)
	0x00010000
#define	ADC_CFGR_DISCEN   ADC_CFGR_DISCEN_Msk
	ADC Discontinuous mode for regular channels.
#define	ADC_CFGR_DISCNUM_Pos   (17U)
#define	ADC_CFGR_DISCNUM_Msk   (0x7UL << ADC_CFGR_DISCNUM_Pos)
	0x000E0000
#define	ADC_CFGR_DISCNUM   ADC_CFGR_DISCNUM_Msk
	ADC Discontinuous mode channel count.
#define	ADC_CFGR_DISCNUM_0   (0x1UL << ADC_CFGR_DISCNUM_Pos)
	0x00020000
#define	ADC_CFGR_DISCNUM_1   (0x2UL << ADC_CFGR_DISCNUM_Pos)
	0x00040000
#define	ADC_CFGR_DISCNUM_2   (0x4UL << ADC_CFGR_DISCNUM_Pos)
	0x00080000
#define	ADC_CFGR_JDISCEN_Pos   (20U)
#define	ADC_CFGR_JDISCEN_Msk   (0x1UL << ADC_CFGR_JDISCEN_Pos)
	0x00100000
#define	ADC_CFGR_JDISCEN   ADC_CFGR_JDISCEN_Msk
	ADC Discontinuous mode on injected channels.
#define	ADC_CFGR_JQM_Pos   (21U)
#define	ADC_CFGR_JQM_Msk   (0x1UL << ADC_CFGR_JQM_Pos)
	0x00200000
#define	ADC_CFGR_JQM   ADC_CFGR_JQM_Msk
	ADC JSQR Queue mode.
#define	ADC_CFGR_AWD1SGL_Pos   (22U)
#define	ADC_CFGR_AWD1SGL_Msk   (0x1UL << ADC_CFGR_AWD1SGL_Pos)
	0x00400000
#define	ADC_CFGR_AWD1SGL   ADC_CFGR_AWD1SGL_Msk
	Enable the watchdog 1 on a single channel or on all channels.
#define	ADC_CFGR_AWD1EN_Pos   (23U)
#define	ADC_CFGR_AWD1EN_Msk   (0x1UL << ADC_CFGR_AWD1EN_Pos)
	0x00800000
#define	ADC_CFGR_AWD1EN   ADC_CFGR_AWD1EN_Msk
	ADC Analog watchdog 1 enable on regular Channels.
#define	ADC_CFGR_JAWD1EN_Pos   (24U)
#define	ADC_CFGR_JAWD1EN_Msk   (0x1UL << ADC_CFGR_JAWD1EN_Pos)
	0x01000000
#define	ADC_CFGR_JAWD1EN   ADC_CFGR_JAWD1EN_Msk
	ADC Analog watchdog 1 enable on injected Channels.
#define	ADC_CFGR_JAUTO_Pos   (25U)
#define	ADC_CFGR_JAUTO_Msk   (0x1UL << ADC_CFGR_JAUTO_Pos)
	0x02000000
#define	ADC_CFGR_JAUTO   ADC_CFGR_JAUTO_Msk
	ADC Automatic injected group conversion.
#define	ADC_CFGR_AWD1CH_Pos   (26U)
#define	ADC_CFGR_AWD1CH_Msk   (0x1FUL << ADC_CFGR_AWD1CH_Pos)
	0x7C000000
#define	ADC_CFGR_AWD1CH   ADC_CFGR_AWD1CH_Msk
	ADC Analog watchdog 1 Channel selection.
#define	ADC_CFGR_AWD1CH_0   (0x01UL << ADC_CFGR_AWD1CH_Pos)
	0x04000000
#define	ADC_CFGR_AWD1CH_1   (0x02UL << ADC_CFGR_AWD1CH_Pos)
	0x08000000
#define	ADC_CFGR_AWD1CH_2   (0x04UL << ADC_CFGR_AWD1CH_Pos)
	0x10000000
#define	ADC_CFGR_AWD1CH_3   (0x08UL << ADC_CFGR_AWD1CH_Pos)
	0x20000000
#define	ADC_CFGR_AWD1CH_4   (0x10UL << ADC_CFGR_AWD1CH_Pos)
	0x40000000
#define	ADC_CFGR_JQDIS_Pos   (31U)
#define	ADC_CFGR_JQDIS_Msk   (0x1UL << ADC_CFGR_JQDIS_Pos)
	0x80000000
#define	ADC_CFGR_JQDIS   ADC_CFGR_JQDIS_Msk
	ADC Injected queue disable.
#define	ADC3_CFGR_DMAEN_Pos   (0U)
#define	ADC3_CFGR_DMAEN_Msk   (0x1UL << ADC3_CFGR_DMAEN_Pos)
	0x00000001
#define	ADC3_CFGR_DMAEN   ADC3_CFGR_DMAEN_Msk
	ADC DMA transfer enable.
#define	ADC3_CFGR_DMACFG_Pos   (1U)
#define	ADC3_CFGR_DMACFG_Msk   (0x1UL << ADC3_CFGR_DMACFG_Pos)
	0x00000002
#define	ADC3_CFGR_DMACFG   ADC3_CFGR_DMACFG_Msk
	ADC DMA transfer configuration.
#define	ADC3_CFGR_RES_Pos   (3U)
#define	ADC3_CFGR_RES_Msk   (0x3UL << ADC3_CFGR_RES_Pos)
	0x00000018
#define	ADC3_CFGR_RES   ADC3_CFGR_RES_Msk
	ADC data resolution.
#define	ADC3_CFGR_RES_0   (0x1UL << ADC3_CFGR_RES_Pos)
	0x00000008
#define	ADC3_CFGR_RES_1   (0x2UL << ADC3_CFGR_RES_Pos)
	0x00000010
#define	ADC3_CFGR_ALIGN_Pos   (15U)
#define	ADC3_CFGR_ALIGN_Msk   (0x1UL << ADC3_CFGR_ALIGN_Pos)
	0x00008000
#define	ADC3_CFGR_ALIGN   ADC3_CFGR_ALIGN_Msk
	ADC data alignment.
#define	ADC_CFGR2_ROVSE_Pos   (0U)
#define	ADC_CFGR2_ROVSE_Msk   (0x1UL << ADC_CFGR2_ROVSE_Pos)
	0x00000001
#define	ADC_CFGR2_ROVSE   ADC_CFGR2_ROVSE_Msk
	ADC Regular group oversampler enable.
#define	ADC_CFGR2_JOVSE_Pos   (1U)
#define	ADC_CFGR2_JOVSE_Msk   (0x1UL << ADC_CFGR2_JOVSE_Pos)
	0x00000002
#define	ADC_CFGR2_JOVSE   ADC_CFGR2_JOVSE_Msk
	ADC Injected group oversampler enable.
#define	ADC_CFGR2_OVSS_Pos   (5U)
#define	ADC_CFGR2_OVSS_Msk   (0xFUL << ADC_CFGR2_OVSS_Pos)
	0x000001E0
#define	ADC_CFGR2_OVSS   ADC_CFGR2_OVSS_Msk
	ADC Regular Oversampling shift.
#define	ADC_CFGR2_OVSS_0   (0x1UL << ADC_CFGR2_OVSS_Pos)
	0x00000020
#define	ADC_CFGR2_OVSS_1   (0x2UL << ADC_CFGR2_OVSS_Pos)
	0x00000040
#define	ADC_CFGR2_OVSS_2   (0x4UL << ADC_CFGR2_OVSS_Pos)
	0x00000080
#define	ADC_CFGR2_OVSS_3   (0x8UL << ADC_CFGR2_OVSS_Pos)
	0x00000100
#define	ADC_CFGR2_TROVS_Pos   (9U)
#define	ADC_CFGR2_TROVS_Msk   (0x1UL << ADC_CFGR2_TROVS_Pos)
	0x00000200
#define	ADC_CFGR2_TROVS   ADC_CFGR2_TROVS_Msk
	ADC Triggered regular Oversampling.
#define	ADC_CFGR2_ROVSM_Pos   (10U)
#define	ADC_CFGR2_ROVSM_Msk   (0x1UL << ADC_CFGR2_ROVSM_Pos)
	0x00000400
#define	ADC_CFGR2_ROVSM   ADC_CFGR2_ROVSM_Msk
	ADC Regular oversampling mode.
#define	ADC_CFGR2_RSHIFT1_Pos   (11U)
#define	ADC_CFGR2_RSHIFT1_Msk   (0x1UL << ADC_CFGR2_RSHIFT1_Pos)
	0x00000800
#define	ADC_CFGR2_RSHIFT1   ADC_CFGR2_RSHIFT1_Msk
	ADC Right-shift data after Offset 1 correction.
#define	ADC_CFGR2_RSHIFT2_Pos   (12U)
#define	ADC_CFGR2_RSHIFT2_Msk   (0x1UL << ADC_CFGR2_RSHIFT2_Pos)
	0x00001000
#define	ADC_CFGR2_RSHIFT2   ADC_CFGR2_RSHIFT2_Msk
	ADC Right-shift data after Offset 2 correction.
#define	ADC_CFGR2_RSHIFT3_Pos   (13U)
#define	ADC_CFGR2_RSHIFT3_Msk   (0x1UL << ADC_CFGR2_RSHIFT3_Pos)
	0x00002000
#define	ADC_CFGR2_RSHIFT3   ADC_CFGR2_RSHIFT3_Msk
	ADC Right-shift data after Offset 3 correction.
#define	ADC_CFGR2_RSHIFT4_Pos   (14U)
#define	ADC_CFGR2_RSHIFT4_Msk   (0x1UL << ADC_CFGR2_RSHIFT4_Pos)
	0x00004000
#define	ADC_CFGR2_RSHIFT4   ADC_CFGR2_RSHIFT4_Msk
	ADC Right-shift data after Offset 4 correction.
#define	ADC_CFGR2_OVSR_Pos   (16U)
#define	ADC_CFGR2_OVSR_Msk   (0x3FFUL << ADC_CFGR2_OVSR_Pos)
	0x03FF0000
#define	ADC_CFGR2_OVSR   ADC_CFGR2_OVSR_Msk
	ADC oversampling Ratio.
#define	ADC_CFGR2_OVSR_0   (0x001UL << ADC_CFGR2_OVSR_Pos)
	0x00010000
#define	ADC_CFGR2_OVSR_1   (0x002UL << ADC_CFGR2_OVSR_Pos)
	0x00020000
#define	ADC_CFGR2_OVSR_2   (0x004UL << ADC_CFGR2_OVSR_Pos)
	0x00040000
#define	ADC_CFGR2_OVSR_3   (0x008UL << ADC_CFGR2_OVSR_Pos)
	0x00080000
#define	ADC_CFGR2_OVSR_4   (0x010UL << ADC_CFGR2_OVSR_Pos)
	0x00100000
#define	ADC_CFGR2_OVSR_5   (0x020UL << ADC_CFGR2_OVSR_Pos)
	0x00200000
#define	ADC_CFGR2_OVSR_6   (0x040UL << ADC_CFGR2_OVSR_Pos)
	0x00400000
#define	ADC_CFGR2_OVSR_7   (0x080UL << ADC_CFGR2_OVSR_Pos)
	0x00800000
#define	ADC_CFGR2_OVSR_8   (0x100UL << ADC_CFGR2_OVSR_Pos)
	0x01000000
#define	ADC_CFGR2_OVSR_9   (0x200UL << ADC_CFGR2_OVSR_Pos)
	0x02000000
#define	ADC_CFGR2_LSHIFT_Pos   (28U)
#define	ADC_CFGR2_LSHIFT_Msk   (0xFUL << ADC_CFGR2_LSHIFT_Pos)
	0xF0000000
#define	ADC_CFGR2_LSHIFT   ADC_CFGR2_LSHIFT_Msk
	ADC Left shift factor.
#define	ADC_CFGR2_LSHIFT_0   (0x1UL << ADC_CFGR2_LSHIFT_Pos)
	0x10000000
#define	ADC_CFGR2_LSHIFT_1   (0x2UL << ADC_CFGR2_LSHIFT_Pos)
	0x20000000
#define	ADC_CFGR2_LSHIFT_2   (0x4UL << ADC_CFGR2_LSHIFT_Pos)
	0x40000000
#define	ADC_CFGR2_LSHIFT_3   (0x8UL << ADC_CFGR2_LSHIFT_Pos)
	0x80000000
#define	ADC3_CFGR2_OVSR_Pos   (2U)
#define	ADC3_CFGR2_OVSR_Msk   (0x7UL << ADC3_CFGR2_OVSR_Pos)
	0x0000001C
#define	ADC3_CFGR2_OVSR   ADC3_CFGR2_OVSR_Msk
	ADC oversampling ratio.
#define	ADC3_CFGR2_OVSR_0   (0x1UL << ADC3_CFGR2_OVSR_Pos)
	0x00000004
#define	ADC3_CFGR2_OVSR_1   (0x2UL << ADC3_CFGR2_OVSR_Pos)
	0x00000008
#define	ADC3_CFGR2_OVSR_2   (0x4UL << ADC3_CFGR2_OVSR_Pos)
	0x00000010
#define	ADC3_CFGR2_SWTRIG_Pos   (25U)
#define	ADC3_CFGR2_SWTRIG_Msk   (0x1UL << ADC3_CFGR2_SWTRIG_Pos)
	0x02000000
#define	ADC3_CFGR2_SWTRIG   ADC3_CFGR2_SWTRIG_Msk
	ADC Software Trigger Bit for Sample time control trigger mode.
#define	ADC3_CFGR2_BULB_Pos   (26U)
#define	ADC3_CFGR2_BULB_Msk   (0x1UL << ADC3_CFGR2_BULB_Pos)
	0x04000000
#define	ADC3_CFGR2_BULB   ADC3_CFGR2_BULB_Msk
	ADC Bulb sampling mode.
#define	ADC3_CFGR2_SMPTRIG_Pos   (27U)
#define	ADC3_CFGR2_SMPTRIG_Msk   (0x1UL << ADC3_CFGR2_SMPTRIG_Pos)
	0x08000000
#define	ADC3_CFGR2_SMPTRIG   ADC3_CFGR2_SMPTRIG_Msk
	ADC Sample Time Control Trigger mode.
#define	ADC_SMPR1_SMP0_Pos   (0U)
#define	ADC_SMPR1_SMP0_Msk   (0x7UL << ADC_SMPR1_SMP0_Pos)
	0x00000007
#define	ADC_SMPR1_SMP0   ADC_SMPR1_SMP0_Msk
	ADC Channel 0 Sampling time selection.
#define	ADC_SMPR1_SMP0_0   (0x1UL << ADC_SMPR1_SMP0_Pos)
	0x00000001
#define	ADC_SMPR1_SMP0_1   (0x2UL << ADC_SMPR1_SMP0_Pos)
	0x00000002
#define	ADC_SMPR1_SMP0_2   (0x4UL << ADC_SMPR1_SMP0_Pos)
	0x00000004
#define	ADC_SMPR1_SMP1_Pos   (3U)
#define	ADC_SMPR1_SMP1_Msk   (0x7UL << ADC_SMPR1_SMP1_Pos)
	0x00000038
#define	ADC_SMPR1_SMP1   ADC_SMPR1_SMP1_Msk
	ADC Channel 1 Sampling time selection.
#define	ADC_SMPR1_SMP1_0   (0x1UL << ADC_SMPR1_SMP1_Pos)
	0x00000008
#define	ADC_SMPR1_SMP1_1   (0x2UL << ADC_SMPR1_SMP1_Pos)
	0x00000010
#define	ADC_SMPR1_SMP1_2   (0x4UL << ADC_SMPR1_SMP1_Pos)
	0x00000020
#define	ADC_SMPR1_SMP2_Pos   (6U)
#define	ADC_SMPR1_SMP2_Msk   (0x7UL << ADC_SMPR1_SMP2_Pos)
	0x000001C0
#define	ADC_SMPR1_SMP2   ADC_SMPR1_SMP2_Msk
	ADC Channel 2 Sampling time selection.
#define	ADC_SMPR1_SMP2_0   (0x1UL << ADC_SMPR1_SMP2_Pos)
	0x00000040
#define	ADC_SMPR1_SMP2_1   (0x2UL << ADC_SMPR1_SMP2_Pos)
	0x00000080
#define	ADC_SMPR1_SMP2_2   (0x4UL << ADC_SMPR1_SMP2_Pos)
	0x00000100
#define	ADC_SMPR1_SMP3_Pos   (9U)
#define	ADC_SMPR1_SMP3_Msk   (0x7UL << ADC_SMPR1_SMP3_Pos)
	0x00000E00
#define	ADC_SMPR1_SMP3   ADC_SMPR1_SMP3_Msk
	ADC Channel 3 Sampling time selection.
#define	ADC_SMPR1_SMP3_0   (0x1UL << ADC_SMPR1_SMP3_Pos)
	0x00000200
#define	ADC_SMPR1_SMP3_1   (0x2UL << ADC_SMPR1_SMP3_Pos)
	0x00000400
#define	ADC_SMPR1_SMP3_2   (0x4UL << ADC_SMPR1_SMP3_Pos)
	0x00000800
#define	ADC_SMPR1_SMP4_Pos   (12U)
#define	ADC_SMPR1_SMP4_Msk   (0x7UL << ADC_SMPR1_SMP4_Pos)
	0x00007000
#define	ADC_SMPR1_SMP4   ADC_SMPR1_SMP4_Msk
	ADC Channel 4 Sampling time selection.
#define	ADC_SMPR1_SMP4_0   (0x1UL << ADC_SMPR1_SMP4_Pos)
	0x00001000
#define	ADC_SMPR1_SMP4_1   (0x2UL << ADC_SMPR1_SMP4_Pos)
	0x00002000
#define	ADC_SMPR1_SMP4_2   (0x4UL << ADC_SMPR1_SMP4_Pos)
	0x00004000
#define	ADC_SMPR1_SMP5_Pos   (15U)
#define	ADC_SMPR1_SMP5_Msk   (0x7UL << ADC_SMPR1_SMP5_Pos)
	0x00038000
#define	ADC_SMPR1_SMP5   ADC_SMPR1_SMP5_Msk
	ADC Channel 5 Sampling time selection.
#define	ADC_SMPR1_SMP5_0   (0x1UL << ADC_SMPR1_SMP5_Pos)
	0x00008000
#define	ADC_SMPR1_SMP5_1   (0x2UL << ADC_SMPR1_SMP5_Pos)
	0x00010000
#define	ADC_SMPR1_SMP5_2   (0x4UL << ADC_SMPR1_SMP5_Pos)
	0x00020000
#define	ADC_SMPR1_SMP6_Pos   (18U)
#define	ADC_SMPR1_SMP6_Msk   (0x7UL << ADC_SMPR1_SMP6_Pos)
	0x001C0000
#define	ADC_SMPR1_SMP6   ADC_SMPR1_SMP6_Msk
	ADC Channel 6 Sampling time selection.
#define	ADC_SMPR1_SMP6_0   (0x1UL << ADC_SMPR1_SMP6_Pos)
	0x00040000
#define	ADC_SMPR1_SMP6_1   (0x2UL << ADC_SMPR1_SMP6_Pos)
	0x00080000
#define	ADC_SMPR1_SMP6_2   (0x4UL << ADC_SMPR1_SMP6_Pos)
	0x00100000
#define	ADC_SMPR1_SMP7_Pos   (21U)
#define	ADC_SMPR1_SMP7_Msk   (0x7UL << ADC_SMPR1_SMP7_Pos)
	0x00E00000
#define	ADC_SMPR1_SMP7   ADC_SMPR1_SMP7_Msk
	ADC Channel 7 Sampling time selection.
#define	ADC_SMPR1_SMP7_0   (0x1UL << ADC_SMPR1_SMP7_Pos)
	0x00200000
#define	ADC_SMPR1_SMP7_1   (0x2UL << ADC_SMPR1_SMP7_Pos)
	0x00400000
#define	ADC_SMPR1_SMP7_2   (0x4UL << ADC_SMPR1_SMP7_Pos)
	0x00800000
#define	ADC_SMPR1_SMP8_Pos   (24U)
#define	ADC_SMPR1_SMP8_Msk   (0x7UL << ADC_SMPR1_SMP8_Pos)
	0x07000000
#define	ADC_SMPR1_SMP8   ADC_SMPR1_SMP8_Msk
	ADC Channel 8 Sampling time selection.
#define	ADC_SMPR1_SMP8_0   (0x1UL << ADC_SMPR1_SMP8_Pos)
	0x01000000
#define	ADC_SMPR1_SMP8_1   (0x2UL << ADC_SMPR1_SMP8_Pos)
	0x02000000
#define	ADC_SMPR1_SMP8_2   (0x4UL << ADC_SMPR1_SMP8_Pos)
	0x04000000
#define	ADC_SMPR1_SMP9_Pos   (27U)
#define	ADC_SMPR1_SMP9_Msk   (0x7UL << ADC_SMPR1_SMP9_Pos)
	0x38000000
#define	ADC_SMPR1_SMP9   ADC_SMPR1_SMP9_Msk
	ADC Channel 9 Sampling time selection.
#define	ADC_SMPR1_SMP9_0   (0x1UL << ADC_SMPR1_SMP9_Pos)
	0x08000000
#define	ADC_SMPR1_SMP9_1   (0x2UL << ADC_SMPR1_SMP9_Pos)
	0x10000000
#define	ADC_SMPR1_SMP9_2   (0x4UL << ADC_SMPR1_SMP9_Pos)
	0x20000000
#define	ADC_SMPR2_SMP10_Pos   (0U)
#define	ADC_SMPR2_SMP10_Msk   (0x7UL << ADC_SMPR2_SMP10_Pos)
	0x00000007
#define	ADC_SMPR2_SMP10   ADC_SMPR2_SMP10_Msk
	ADC Channel 10 Sampling time selection.
#define	ADC_SMPR2_SMP10_0   (0x1UL << ADC_SMPR2_SMP10_Pos)
	0x00000001
#define	ADC_SMPR2_SMP10_1   (0x2UL << ADC_SMPR2_SMP10_Pos)
	0x00000002
#define	ADC_SMPR2_SMP10_2   (0x4UL << ADC_SMPR2_SMP10_Pos)
	0x00000004
#define	ADC_SMPR2_SMP11_Pos   (3U)
#define	ADC_SMPR2_SMP11_Msk   (0x7UL << ADC_SMPR2_SMP11_Pos)
	0x00000038
#define	ADC_SMPR2_SMP11   ADC_SMPR2_SMP11_Msk
	ADC Channel 11 Sampling time selection.
#define	ADC_SMPR2_SMP11_0   (0x1UL << ADC_SMPR2_SMP11_Pos)
	0x00000008
#define	ADC_SMPR2_SMP11_1   (0x2UL << ADC_SMPR2_SMP11_Pos)
	0x00000010
#define	ADC_SMPR2_SMP11_2   (0x4UL << ADC_SMPR2_SMP11_Pos)
	0x00000020
#define	ADC_SMPR2_SMP12_Pos   (6U)
#define	ADC_SMPR2_SMP12_Msk   (0x7UL << ADC_SMPR2_SMP12_Pos)
	0x000001C0
#define	ADC_SMPR2_SMP12   ADC_SMPR2_SMP12_Msk
	ADC Channel 12 Sampling time selection.
#define	ADC_SMPR2_SMP12_0   (0x1UL << ADC_SMPR2_SMP12_Pos)
	0x00000040
#define	ADC_SMPR2_SMP12_1   (0x2UL << ADC_SMPR2_SMP12_Pos)
	0x00000080
#define	ADC_SMPR2_SMP12_2   (0x4UL << ADC_SMPR2_SMP12_Pos)
	0x00000100
#define	ADC_SMPR2_SMP13_Pos   (9U)
#define	ADC_SMPR2_SMP13_Msk   (0x7UL << ADC_SMPR2_SMP13_Pos)
	0x00000E00
#define	ADC_SMPR2_SMP13   ADC_SMPR2_SMP13_Msk
	ADC Channel 13 Sampling time selection.
#define	ADC_SMPR2_SMP13_0   (0x1UL << ADC_SMPR2_SMP13_Pos)
	0x00000200
#define	ADC_SMPR2_SMP13_1   (0x2UL << ADC_SMPR2_SMP13_Pos)
	0x00000400
#define	ADC_SMPR2_SMP13_2   (0x4UL << ADC_SMPR2_SMP13_Pos)
	0x00000800
#define	ADC_SMPR2_SMP14_Pos   (12U)
#define	ADC_SMPR2_SMP14_Msk   (0x7UL << ADC_SMPR2_SMP14_Pos)
	0x00007000
#define	ADC_SMPR2_SMP14   ADC_SMPR2_SMP14_Msk
	ADC Channel 14 Sampling time selection.
#define	ADC_SMPR2_SMP14_0   (0x1UL << ADC_SMPR2_SMP14_Pos)
	0x00001000
#define	ADC_SMPR2_SMP14_1   (0x2UL << ADC_SMPR2_SMP14_Pos)
	0x00002000
#define	ADC_SMPR2_SMP14_2   (0x4UL << ADC_SMPR2_SMP14_Pos)
	0x00004000
#define	ADC_SMPR2_SMP15_Pos   (15U)
#define	ADC_SMPR2_SMP15_Msk   (0x7UL << ADC_SMPR2_SMP15_Pos)
	0x00038000
#define	ADC_SMPR2_SMP15   ADC_SMPR2_SMP15_Msk
	ADC Channel 15 Sampling time selection.
#define	ADC_SMPR2_SMP15_0   (0x1UL << ADC_SMPR2_SMP15_Pos)
	0x00008000
#define	ADC_SMPR2_SMP15_1   (0x2UL << ADC_SMPR2_SMP15_Pos)
	0x00010000
#define	ADC_SMPR2_SMP15_2   (0x4UL << ADC_SMPR2_SMP15_Pos)
	0x00020000
#define	ADC_SMPR2_SMP16_Pos   (18U)
#define	ADC_SMPR2_SMP16_Msk   (0x7UL << ADC_SMPR2_SMP16_Pos)
	0x001C0000
#define	ADC_SMPR2_SMP16   ADC_SMPR2_SMP16_Msk
	ADC Channel 16 Sampling time selection.
#define	ADC_SMPR2_SMP16_0   (0x1UL << ADC_SMPR2_SMP16_Pos)
	0x00040000
#define	ADC_SMPR2_SMP16_1   (0x2UL << ADC_SMPR2_SMP16_Pos)
	0x00080000
#define	ADC_SMPR2_SMP16_2   (0x4UL << ADC_SMPR2_SMP16_Pos)
	0x00100000
#define	ADC_SMPR2_SMP17_Pos   (21U)
#define	ADC_SMPR2_SMP17_Msk   (0x7UL << ADC_SMPR2_SMP17_Pos)
	0x00E00000
#define	ADC_SMPR2_SMP17   ADC_SMPR2_SMP17_Msk
	ADC Channel 17 Sampling time selection.
#define	ADC_SMPR2_SMP17_0   (0x1UL << ADC_SMPR2_SMP17_Pos)
	0x00200000
#define	ADC_SMPR2_SMP17_1   (0x2UL << ADC_SMPR2_SMP17_Pos)
	0x00400000
#define	ADC_SMPR2_SMP17_2   (0x4UL << ADC_SMPR2_SMP17_Pos)
	0x00800000
#define	ADC_SMPR2_SMP18_Pos   (24U)
#define	ADC_SMPR2_SMP18_Msk   (0x7UL << ADC_SMPR2_SMP18_Pos)
	0x07000000
#define	ADC_SMPR2_SMP18   ADC_SMPR2_SMP18_Msk
	ADC Channel 18 Sampling time selection.
#define	ADC_SMPR2_SMP18_0   (0x1UL << ADC_SMPR2_SMP18_Pos)
	0x01000000
#define	ADC_SMPR2_SMP18_1   (0x2UL << ADC_SMPR2_SMP18_Pos)
	0x02000000
#define	ADC_SMPR2_SMP18_2   (0x4UL << ADC_SMPR2_SMP18_Pos)
	0x04000000
#define	ADC_SMPR2_SMP19_Pos   (27U)
#define	ADC_SMPR2_SMP19_Msk   (0x7UL << ADC_SMPR2_SMP19_Pos)
	0x38000000
#define	ADC_SMPR2_SMP19   ADC_SMPR2_SMP19_Msk
	ADC Channel 19 Sampling time selection.
#define	ADC_SMPR2_SMP19_0   (0x1UL << ADC_SMPR2_SMP19_Pos)
	0x08000000
#define	ADC_SMPR2_SMP19_1   (0x2UL << ADC_SMPR2_SMP19_Pos)
	0x10000000
#define	ADC_SMPR2_SMP19_2   (0x4UL << ADC_SMPR2_SMP19_Pos)
	0x20000000
#define	ADC_PCSEL_PCSEL_Pos   (0U)
#define	ADC_PCSEL_PCSEL_Msk   (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)
	0x000FFFFF
#define	ADC_PCSEL_PCSEL   ADC_PCSEL_PCSEL_Msk
	ADC pre channel selection.
#define	ADC_PCSEL_PCSEL_0   (0x00001UL << ADC_PCSEL_PCSEL_Pos)
	0x00000001
#define	ADC_PCSEL_PCSEL_1   (0x00002UL << ADC_PCSEL_PCSEL_Pos)
	0x00000002
#define	ADC_PCSEL_PCSEL_2   (0x00004UL << ADC_PCSEL_PCSEL_Pos)
	0x00000004
#define	ADC_PCSEL_PCSEL_3   (0x00008UL << ADC_PCSEL_PCSEL_Pos)
	0x00000008
#define	ADC_PCSEL_PCSEL_4   (0x00010UL << ADC_PCSEL_PCSEL_Pos)
	0x00000010
#define	ADC_PCSEL_PCSEL_5   (0x00020UL << ADC_PCSEL_PCSEL_Pos)
	0x00000020
#define	ADC_PCSEL_PCSEL_6   (0x00040UL << ADC_PCSEL_PCSEL_Pos)
	0x00000040
#define	ADC_PCSEL_PCSEL_7   (0x00080UL << ADC_PCSEL_PCSEL_Pos)
	0x00000080
#define	ADC_PCSEL_PCSEL_8   (0x00100UL << ADC_PCSEL_PCSEL_Pos)
	0x00000100
#define	ADC_PCSEL_PCSEL_9   (0x00200UL << ADC_PCSEL_PCSEL_Pos)
	0x00000200
#define	ADC_PCSEL_PCSEL_10   (0x00400UL << ADC_PCSEL_PCSEL_Pos)
	0x00000400
#define	ADC_PCSEL_PCSEL_11   (0x00800UL << ADC_PCSEL_PCSEL_Pos)
	0x00000800
#define	ADC_PCSEL_PCSEL_12   (0x01000UL << ADC_PCSEL_PCSEL_Pos)
	0x00001000
#define	ADC_PCSEL_PCSEL_13   (0x02000UL << ADC_PCSEL_PCSEL_Pos)
	0x00002000
#define	ADC_PCSEL_PCSEL_14   (0x04000UL << ADC_PCSEL_PCSEL_Pos)
	0x00004000
#define	ADC_PCSEL_PCSEL_15   (0x08000UL << ADC_PCSEL_PCSEL_Pos)
	0x00008000
#define	ADC_PCSEL_PCSEL_16   (0x10000UL << ADC_PCSEL_PCSEL_Pos)
	0x00010000
#define	ADC_PCSEL_PCSEL_17   (0x20000UL << ADC_PCSEL_PCSEL_Pos)
	0x00020000
#define	ADC_PCSEL_PCSEL_18   (0x40000UL << ADC_PCSEL_PCSEL_Pos)
	0x00040000
#define	ADC_PCSEL_PCSEL_19   (0x80000UL << ADC_PCSEL_PCSEL_Pos)
	0x00080000
#define	ADC_LTR_LT_Pos   (0U)
#define	ADC_LTR_LT_Msk   (0x3FFFFFFUL << ADC_LTR_LT_Pos)
	0x03FFFFFF
#define	ADC_LTR_LT   ADC_LTR_LT_Msk
	ADC Analog watchdog 1, 2 and 3 lower threshold.
#define	ADC_HTR_HT_Pos   (0U)
#define	ADC_HTR_HT_Msk   (0x3FFFFFFUL << ADC_HTR_HT_Pos)
	0x03FFFFFF
#define	ADC_HTR_HT   ADC_HTR_HT_Msk
	ADC Analog watchdog 1,2 and 3 higher threshold.
#define	ADC3_TR1_LT1_Pos   (0U)
#define	ADC3_TR1_LT1_Msk   (0xFFFUL << ADC3_TR1_LT1_Pos)
	0x00000FFF
#define	ADC3_TR1_LT1   ADC3_TR1_LT1_Msk
	ADC analog watchdog 1 threshold low.
#define	ADC3_TR1_AWDFILT_Pos   (12U)
#define	ADC3_TR1_AWDFILT_Msk   (0x7UL << ADC3_TR1_AWDFILT_Pos)
	0x00007000
#define	ADC3_TR1_AWDFILT   ADC3_TR1_AWDFILT_Msk
	ADC analog watchdog filtering parameter.
#define	ADC3_TR1_AWDFILT_0   (0x1UL << ADC3_TR1_AWDFILT_Pos)
	0x00001000
#define	ADC3_TR1_AWDFILT_1   (0x2UL << ADC3_TR1_AWDFILT_Pos)
	0x00002000
#define	ADC3_TR1_AWDFILT_2   (0x4UL << ADC3_TR1_AWDFILT_Pos)
	0x00004000
#define	ADC3_TR1_HT1_Pos   (16U)
#define	ADC3_TR1_HT1_Msk   (0xFFFUL << ADC3_TR1_HT1_Pos)
	0x0FFF0000
#define	ADC3_TR1_HT1   ADC3_TR1_HT1_Msk
	ADC analog watchdog 1 threshold high.
#define	ADC3_TR2_LT2_Pos   (0U)
#define	ADC3_TR2_LT2_Msk   (0xFFUL << ADC3_TR2_LT2_Pos)
	0x000000FF
#define	ADC3_TR2_LT2   ADC3_TR2_LT2_Msk
	ADC analog watchdog 2 threshold low.
#define	ADC3_TR2_HT2_Pos   (16U)
#define	ADC3_TR2_HT2_Msk   (0xFFUL << ADC3_TR2_HT2_Pos)
	0x00FF0000
#define	ADC3_TR2_HT2   ADC3_TR2_HT2_Msk
	ADC analog watchdog 2 threshold high.
#define	ADC3_TR3_LT3_Pos   (0U)
#define	ADC3_TR3_LT3_Msk   (0xFFUL << ADC3_TR3_LT3_Pos)
	0x000000FF
#define	ADC3_TR3_LT3   ADC3_TR3_LT3_Msk
	ADC analog watchdog 3 threshold low.
#define	ADC3_TR3_HT3_Pos   (16U)
#define	ADC3_TR3_HT3_Msk   (0xFFUL << ADC3_TR3_HT3_Pos)
	0x00FF0000
#define	ADC3_TR3_HT3   ADC3_TR3_HT3_Msk
	ADC analog watchdog 3 threshold high.
#define	ADC_SQR1_L_Pos   (0U)
#define	ADC_SQR1_L_Msk   (0xFUL << ADC_SQR1_L_Pos)
	0x0000000F
#define	ADC_SQR1_L   ADC_SQR1_L_Msk
	ADC regular channel sequence length.
#define	ADC_SQR1_L_0   (0x1UL << ADC_SQR1_L_Pos)
	0x00000001
#define	ADC_SQR1_L_1   (0x2UL << ADC_SQR1_L_Pos)
	0x00000002
#define	ADC_SQR1_L_2   (0x4UL << ADC_SQR1_L_Pos)
	0x00000004
#define	ADC_SQR1_L_3   (0x8UL << ADC_SQR1_L_Pos)
	0x00000008
#define	ADC_SQR1_SQ1_Pos   (6U)
#define	ADC_SQR1_SQ1_Msk   (0x1FUL << ADC_SQR1_SQ1_Pos)
	0x000007C0
#define	ADC_SQR1_SQ1   ADC_SQR1_SQ1_Msk
	ADC 1st conversion in regular sequence.
#define	ADC_SQR1_SQ1_0   (0x01UL << ADC_SQR1_SQ1_Pos)
	0x00000040
#define	ADC_SQR1_SQ1_1   (0x02UL << ADC_SQR1_SQ1_Pos)
	0x00000080
#define	ADC_SQR1_SQ1_2   (0x04UL << ADC_SQR1_SQ1_Pos)
	0x00000100
#define	ADC_SQR1_SQ1_3   (0x08UL << ADC_SQR1_SQ1_Pos)
	0x00000200
#define	ADC_SQR1_SQ1_4   (0x10UL << ADC_SQR1_SQ1_Pos)
	0x00000400
#define	ADC_SQR1_SQ2_Pos   (12U)
#define	ADC_SQR1_SQ2_Msk   (0x1FUL << ADC_SQR1_SQ2_Pos)
	0x0001F000
#define	ADC_SQR1_SQ2   ADC_SQR1_SQ2_Msk
	ADC 2nd conversion in regular sequence.
#define	ADC_SQR1_SQ2_0   (0x01UL << ADC_SQR1_SQ2_Pos)
	0x00001000
#define	ADC_SQR1_SQ2_1   (0x02UL << ADC_SQR1_SQ2_Pos)
	0x00002000
#define	ADC_SQR1_SQ2_2   (0x04UL << ADC_SQR1_SQ2_Pos)
	0x00004000
#define	ADC_SQR1_SQ2_3   (0x08UL << ADC_SQR1_SQ2_Pos)
	0x00008000
#define	ADC_SQR1_SQ2_4   (0x10UL << ADC_SQR1_SQ2_Pos)
	0x00010000
#define	ADC_SQR1_SQ3_Pos   (18U)
#define	ADC_SQR1_SQ3_Msk   (0x1FUL << ADC_SQR1_SQ3_Pos)
	0x007C0000
#define	ADC_SQR1_SQ3   ADC_SQR1_SQ3_Msk
	ADC 3rd conversion in regular sequence.
#define	ADC_SQR1_SQ3_0   (0x01UL << ADC_SQR1_SQ3_Pos)
	0x00040000
#define	ADC_SQR1_SQ3_1   (0x02UL << ADC_SQR1_SQ3_Pos)
	0x00080000
#define	ADC_SQR1_SQ3_2   (0x04UL << ADC_SQR1_SQ3_Pos)
	0x00100000
#define	ADC_SQR1_SQ3_3   (0x08UL << ADC_SQR1_SQ3_Pos)
	0x00200000
#define	ADC_SQR1_SQ3_4   (0x10UL << ADC_SQR1_SQ3_Pos)
	0x00400000
#define	ADC_SQR1_SQ4_Pos   (24U)
#define	ADC_SQR1_SQ4_Msk   (0x1FUL << ADC_SQR1_SQ4_Pos)
	0x1F000000
#define	ADC_SQR1_SQ4   ADC_SQR1_SQ4_Msk
	ADC 4th conversion in regular sequence.
#define	ADC_SQR1_SQ4_0   (0x01UL << ADC_SQR1_SQ4_Pos)
	0x01000000
#define	ADC_SQR1_SQ4_1   (0x02UL << ADC_SQR1_SQ4_Pos)
	0x02000000
#define	ADC_SQR1_SQ4_2   (0x04UL << ADC_SQR1_SQ4_Pos)
	0x04000000
#define	ADC_SQR1_SQ4_3   (0x08UL << ADC_SQR1_SQ4_Pos)
	0x08000000
#define	ADC_SQR1_SQ4_4   (0x10UL << ADC_SQR1_SQ4_Pos)
	0x10000000
#define	ADC_SQR2_SQ5_Pos   (0U)
#define	ADC_SQR2_SQ5_Msk   (0x1FUL << ADC_SQR2_SQ5_Pos)
	0x0000001F
#define	ADC_SQR2_SQ5   ADC_SQR2_SQ5_Msk
	ADC 5th conversion in regular sequence.
#define	ADC_SQR2_SQ5_0   (0x01UL << ADC_SQR2_SQ5_Pos)
	0x00000001
#define	ADC_SQR2_SQ5_1   (0x02UL << ADC_SQR2_SQ5_Pos)
	0x00000002
#define	ADC_SQR2_SQ5_2   (0x04UL << ADC_SQR2_SQ5_Pos)
	0x00000004
#define	ADC_SQR2_SQ5_3   (0x08UL << ADC_SQR2_SQ5_Pos)
	0x00000008
#define	ADC_SQR2_SQ5_4   (0x10UL << ADC_SQR2_SQ5_Pos)
	0x00000010
#define	ADC_SQR2_SQ6_Pos   (6U)
#define	ADC_SQR2_SQ6_Msk   (0x1FUL << ADC_SQR2_SQ6_Pos)
	0x000007C0
#define	ADC_SQR2_SQ6   ADC_SQR2_SQ6_Msk
	ADC 6th conversion in regular sequence.
#define	ADC_SQR2_SQ6_0   (0x01UL << ADC_SQR2_SQ6_Pos)
	0x00000040
#define	ADC_SQR2_SQ6_1   (0x02UL << ADC_SQR2_SQ6_Pos)
	0x00000080
#define	ADC_SQR2_SQ6_2   (0x04UL << ADC_SQR2_SQ6_Pos)
	0x00000100
#define	ADC_SQR2_SQ6_3   (0x08UL << ADC_SQR2_SQ6_Pos)
	0x00000200
#define	ADC_SQR2_SQ6_4   (0x10UL << ADC_SQR2_SQ6_Pos)
	0x00000400
#define	ADC_SQR2_SQ7_Pos   (12U)
#define	ADC_SQR2_SQ7_Msk   (0x1FUL << ADC_SQR2_SQ7_Pos)
	0x0001F000
#define	ADC_SQR2_SQ7   ADC_SQR2_SQ7_Msk
	ADC 7th conversion in regular sequence.
#define	ADC_SQR2_SQ7_0   (0x01UL << ADC_SQR2_SQ7_Pos)
	0x00001000
#define	ADC_SQR2_SQ7_1   (0x02UL << ADC_SQR2_SQ7_Pos)
	0x00002000
#define	ADC_SQR2_SQ7_2   (0x04UL << ADC_SQR2_SQ7_Pos)
	0x00004000
#define	ADC_SQR2_SQ7_3   (0x08UL << ADC_SQR2_SQ7_Pos)
	0x00008000
#define	ADC_SQR2_SQ7_4   (0x10UL << ADC_SQR2_SQ7_Pos)
	0x00010000
#define	ADC_SQR2_SQ8_Pos   (18U)
#define	ADC_SQR2_SQ8_Msk   (0x1FUL << ADC_SQR2_SQ8_Pos)
	0x007C0000
#define	ADC_SQR2_SQ8   ADC_SQR2_SQ8_Msk
	ADC 8th conversion in regular sequence.
#define	ADC_SQR2_SQ8_0   (0x01UL << ADC_SQR2_SQ8_Pos)
	0x00040000
#define	ADC_SQR2_SQ8_1   (0x02UL << ADC_SQR2_SQ8_Pos)
	0x00080000
#define	ADC_SQR2_SQ8_2   (0x04UL << ADC_SQR2_SQ8_Pos)
	0x00100000
#define	ADC_SQR2_SQ8_3   (0x08UL << ADC_SQR2_SQ8_Pos)
	0x00200000
#define	ADC_SQR2_SQ8_4   (0x10UL << ADC_SQR2_SQ8_Pos)
	0x00400000
#define	ADC_SQR2_SQ9_Pos   (24U)
#define	ADC_SQR2_SQ9_Msk   (0x1FUL << ADC_SQR2_SQ9_Pos)
	0x1F000000
#define	ADC_SQR2_SQ9   ADC_SQR2_SQ9_Msk
	ADC 9th conversion in regular sequence.
#define	ADC_SQR2_SQ9_0   (0x01UL << ADC_SQR2_SQ9_Pos)
	0x01000000
#define	ADC_SQR2_SQ9_1   (0x02UL << ADC_SQR2_SQ9_Pos)
	0x02000000
#define	ADC_SQR2_SQ9_2   (0x04UL << ADC_SQR2_SQ9_Pos)
	0x04000000
#define	ADC_SQR2_SQ9_3   (0x08UL << ADC_SQR2_SQ9_Pos)
	0x08000000
#define	ADC_SQR2_SQ9_4   (0x10UL << ADC_SQR2_SQ9_Pos)
	0x10000000
#define	ADC_SQR3_SQ10_Pos   (0U)
#define	ADC_SQR3_SQ10_Msk   (0x1FUL << ADC_SQR3_SQ10_Pos)
	0x0000001F
#define	ADC_SQR3_SQ10   ADC_SQR3_SQ10_Msk
	ADC 10th conversion in regular sequence.
#define	ADC_SQR3_SQ10_0   (0x01UL << ADC_SQR3_SQ10_Pos)
	0x00000001
#define	ADC_SQR3_SQ10_1   (0x02UL << ADC_SQR3_SQ10_Pos)
	0x00000002
#define	ADC_SQR3_SQ10_2   (0x04UL << ADC_SQR3_SQ10_Pos)
	0x00000004
#define	ADC_SQR3_SQ10_3   (0x08UL << ADC_SQR3_SQ10_Pos)
	0x00000008
#define	ADC_SQR3_SQ10_4   (0x10UL << ADC_SQR3_SQ10_Pos)
	0x00000010
#define	ADC_SQR3_SQ11_Pos   (6U)
#define	ADC_SQR3_SQ11_Msk   (0x1FUL << ADC_SQR3_SQ11_Pos)
	0x000007C0
#define	ADC_SQR3_SQ11   ADC_SQR3_SQ11_Msk
	ADC 11th conversion in regular sequence.
#define	ADC_SQR3_SQ11_0   (0x01UL << ADC_SQR3_SQ11_Pos)
	0x00000040
#define	ADC_SQR3_SQ11_1   (0x02UL << ADC_SQR3_SQ11_Pos)
	0x00000080
#define	ADC_SQR3_SQ11_2   (0x04UL << ADC_SQR3_SQ11_Pos)
	0x00000100
#define	ADC_SQR3_SQ11_3   (0x08UL << ADC_SQR3_SQ11_Pos)
	0x00000200
#define	ADC_SQR3_SQ11_4   (0x10UL << ADC_SQR3_SQ11_Pos)
	0x00000400
#define	ADC_SQR3_SQ12_Pos   (12U)
#define	ADC_SQR3_SQ12_Msk   (0x1FUL << ADC_SQR3_SQ12_Pos)
	0x0001F000
#define	ADC_SQR3_SQ12   ADC_SQR3_SQ12_Msk
	ADC 12th conversion in regular sequence.
#define	ADC_SQR3_SQ12_0   (0x01UL << ADC_SQR3_SQ12_Pos)
	0x00001000
#define	ADC_SQR3_SQ12_1   (0x02UL << ADC_SQR3_SQ12_Pos)
	0x00002000
#define	ADC_SQR3_SQ12_2   (0x04UL << ADC_SQR3_SQ12_Pos)
	0x00004000
#define	ADC_SQR3_SQ12_3   (0x08UL << ADC_SQR3_SQ12_Pos)
	0x00008000
#define	ADC_SQR3_SQ12_4   (0x10UL << ADC_SQR3_SQ12_Pos)
	0x00010000
#define	ADC_SQR3_SQ13_Pos   (18U)
#define	ADC_SQR3_SQ13_Msk   (0x1FUL << ADC_SQR3_SQ13_Pos)
	0x007C0000
#define	ADC_SQR3_SQ13   ADC_SQR3_SQ13_Msk
	ADC 13th conversion in regular sequence.
#define	ADC_SQR3_SQ13_0   (0x01UL << ADC_SQR3_SQ13_Pos)
	0x00040000
#define	ADC_SQR3_SQ13_1   (0x02UL << ADC_SQR3_SQ13_Pos)
	0x00080000
#define	ADC_SQR3_SQ13_2   (0x04UL << ADC_SQR3_SQ13_Pos)
	0x00100000
#define	ADC_SQR3_SQ13_3   (0x08UL << ADC_SQR3_SQ13_Pos)
	0x00200000
#define	ADC_SQR3_SQ13_4   (0x10UL << ADC_SQR3_SQ13_Pos)
	0x00400000
#define	ADC_SQR3_SQ14_Pos   (24U)
#define	ADC_SQR3_SQ14_Msk   (0x1FUL << ADC_SQR3_SQ14_Pos)
	0x1F000000
#define	ADC_SQR3_SQ14   ADC_SQR3_SQ14_Msk
	ADC 14th conversion in regular sequence.
#define	ADC_SQR3_SQ14_0   (0x01UL << ADC_SQR3_SQ14_Pos)
	0x01000000
#define	ADC_SQR3_SQ14_1   (0x02UL << ADC_SQR3_SQ14_Pos)
	0x02000000
#define	ADC_SQR3_SQ14_2   (0x04UL << ADC_SQR3_SQ14_Pos)
	0x04000000
#define	ADC_SQR3_SQ14_3   (0x08UL << ADC_SQR3_SQ14_Pos)
	0x08000000
#define	ADC_SQR3_SQ14_4   (0x10UL << ADC_SQR3_SQ14_Pos)
	0x10000000
#define	ADC_SQR4_SQ15_Pos   (0U)
#define	ADC_SQR4_SQ15_Msk   (0x1FUL << ADC_SQR4_SQ15_Pos)
	0x0000001F
#define	ADC_SQR4_SQ15   ADC_SQR4_SQ15_Msk
	ADC 15th conversion in regular sequence.
#define	ADC_SQR4_SQ15_0   (0x01UL << ADC_SQR4_SQ15_Pos)
	0x00000001
#define	ADC_SQR4_SQ15_1   (0x02UL << ADC_SQR4_SQ15_Pos)
	0x00000002
#define	ADC_SQR4_SQ15_2   (0x04UL << ADC_SQR4_SQ15_Pos)
	0x00000004
#define	ADC_SQR4_SQ15_3   (0x08UL << ADC_SQR4_SQ15_Pos)
	0x00000008
#define	ADC_SQR4_SQ15_4   (0x10UL << ADC_SQR4_SQ15_Pos)
	0x00000010
#define	ADC_SQR4_SQ16_Pos   (6U)
#define	ADC_SQR4_SQ16_Msk   (0x1FUL << ADC_SQR4_SQ16_Pos)
	0x000007C0
#define	ADC_SQR4_SQ16   ADC_SQR4_SQ16_Msk
	ADC 16th conversion in regular sequence.
#define	ADC_SQR4_SQ16_0   (0x01UL << ADC_SQR4_SQ16_Pos)
	0x00000040
#define	ADC_SQR4_SQ16_1   (0x02UL << ADC_SQR4_SQ16_Pos)
	0x00000080
#define	ADC_SQR4_SQ16_2   (0x04UL << ADC_SQR4_SQ16_Pos)
	0x00000100
#define	ADC_SQR4_SQ16_3   (0x08UL << ADC_SQR4_SQ16_Pos)
	0x00000200
#define	ADC_SQR4_SQ16_4   (0x10UL << ADC_SQR4_SQ16_Pos)
	0x00000400
#define	ADC_DR_RDATA_Pos   (0U)
#define	ADC_DR_RDATA_Msk   (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)
	0xFFFFFFFF
#define	ADC_DR_RDATA   ADC_DR_RDATA_Msk
	ADC regular Data converted.
#define	ADC_JSQR_JL_Pos   (0U)
#define	ADC_JSQR_JL_Msk   (0x3UL << ADC_JSQR_JL_Pos)
	0x00000003
#define	ADC_JSQR_JL   ADC_JSQR_JL_Msk
	ADC injected channel sequence length.
#define	ADC_JSQR_JL_0   (0x1UL << ADC_JSQR_JL_Pos)
	0x00000001
#define	ADC_JSQR_JL_1   (0x2UL << ADC_JSQR_JL_Pos)
	0x00000002
#define	ADC_JSQR_JEXTSEL_Pos   (2U)
#define	ADC_JSQR_JEXTSEL_Msk   (0x1FUL << ADC_JSQR_JEXTSEL_Pos)
	0x0000007C
#define	ADC_JSQR_JEXTSEL   ADC_JSQR_JEXTSEL_Msk
	ADC external trigger selection for injected group.
#define	ADC_JSQR_JEXTSEL_0   (0x01UL << ADC_JSQR_JEXTSEL_Pos)
	0x00000004
#define	ADC_JSQR_JEXTSEL_1   (0x02UL << ADC_JSQR_JEXTSEL_Pos)
	0x00000008
#define	ADC_JSQR_JEXTSEL_2   (0x04UL << ADC_JSQR_JEXTSEL_Pos)
	0x00000010
#define	ADC_JSQR_JEXTSEL_3   (0x08UL << ADC_JSQR_JEXTSEL_Pos)
	0x00000020
#define	ADC_JSQR_JEXTSEL_4   (0x10UL << ADC_JSQR_JEXTSEL_Pos)
	0x00000040
#define	ADC_JSQR_JEXTEN_Pos   (7U)
#define	ADC_JSQR_JEXTEN_Msk   (0x3UL << ADC_JSQR_JEXTEN_Pos)
	0x00000180
#define	ADC_JSQR_JEXTEN   ADC_JSQR_JEXTEN_Msk
	ADC external trigger enable and polarity selection for injected channels.
#define	ADC_JSQR_JEXTEN_0   (0x1UL << ADC_JSQR_JEXTEN_Pos)
	0x00000080
#define	ADC_JSQR_JEXTEN_1   (0x2UL << ADC_JSQR_JEXTEN_Pos)
	0x00000100
#define	ADC_JSQR_JSQ1_Pos   (9U)
#define	ADC_JSQR_JSQ1_Msk   (0x1FUL << ADC_JSQR_JSQ1_Pos)
	0x00003E00
#define	ADC_JSQR_JSQ1   ADC_JSQR_JSQ1_Msk
	ADC 1st conversion in injected sequence.
#define	ADC_JSQR_JSQ1_0   (0x01UL << ADC_JSQR_JSQ1_Pos)
	0x00000200
#define	ADC_JSQR_JSQ1_1   (0x02UL << ADC_JSQR_JSQ1_Pos)
	0x00000400
#define	ADC_JSQR_JSQ1_2   (0x04UL << ADC_JSQR_JSQ1_Pos)
	0x00000800
#define	ADC_JSQR_JSQ1_3   (0x08UL << ADC_JSQR_JSQ1_Pos)
	0x00001000
#define	ADC_JSQR_JSQ1_4   (0x10UL << ADC_JSQR_JSQ1_Pos)
	0x00002000
#define	ADC_JSQR_JSQ2_Pos   (15U)
#define	ADC_JSQR_JSQ2_Msk   (0x1FUL << ADC_JSQR_JSQ2_Pos)
	0x000F8000
#define	ADC_JSQR_JSQ2   ADC_JSQR_JSQ2_Msk
	ADC 2nd conversion in injected sequence.
#define	ADC_JSQR_JSQ2_0   (0x01UL << ADC_JSQR_JSQ2_Pos)
	0x00008000
#define	ADC_JSQR_JSQ2_1   (0x02UL << ADC_JSQR_JSQ2_Pos)
	0x00010000
#define	ADC_JSQR_JSQ2_2   (0x04UL << ADC_JSQR_JSQ2_Pos)
	0x00020000
#define	ADC_JSQR_JSQ2_3   (0x08UL << ADC_JSQR_JSQ2_Pos)
	0x00040000
#define	ADC_JSQR_JSQ2_4   (0x10UL << ADC_JSQR_JSQ2_Pos)
	0x00080000
#define	ADC_JSQR_JSQ3_Pos   (21U)
#define	ADC_JSQR_JSQ3_Msk   (0x1FUL << ADC_JSQR_JSQ3_Pos)
	0x03E00000
#define	ADC_JSQR_JSQ3   ADC_JSQR_JSQ3_Msk
	ADC 3rd conversion in injected sequence.
#define	ADC_JSQR_JSQ3_0   (0x01UL << ADC_JSQR_JSQ3_Pos)
	0x00200000
#define	ADC_JSQR_JSQ3_1   (0x02UL << ADC_JSQR_JSQ3_Pos)
	0x00400000
#define	ADC_JSQR_JSQ3_2   (0x04UL << ADC_JSQR_JSQ3_Pos)
	0x00800000
#define	ADC_JSQR_JSQ3_3   (0x08UL << ADC_JSQR_JSQ3_Pos)
	0x01000000
#define	ADC_JSQR_JSQ3_4   (0x10UL << ADC_JSQR_JSQ3_Pos)
	0x02000000
#define	ADC_JSQR_JSQ4_Pos   (27U)
#define	ADC_JSQR_JSQ4_Msk   (0x1FUL << ADC_JSQR_JSQ4_Pos)
	0xF8000000
#define	ADC_JSQR_JSQ4   ADC_JSQR_JSQ4_Msk
	ADC 4th conversion in injected sequence.
#define	ADC_JSQR_JSQ4_0   (0x01UL << ADC_JSQR_JSQ4_Pos)
	0x08000000
#define	ADC_JSQR_JSQ4_1   (0x02UL << ADC_JSQR_JSQ4_Pos)
	0x10000000
#define	ADC_JSQR_JSQ4_2   (0x04UL << ADC_JSQR_JSQ4_Pos)
	0x20000000
#define	ADC_JSQR_JSQ4_3   (0x08UL << ADC_JSQR_JSQ4_Pos)
	0x40000000
#define	ADC_JSQR_JSQ4_4   (0x10UL << ADC_JSQR_JSQ4_Pos)
	0x80000000
#define	ADC_OFR1_OFFSET1_Pos   (0U)
#define	ADC_OFR1_OFFSET1_Msk   (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos)
	0x03FFFFFF
#define	ADC_OFR1_OFFSET1   ADC_OFR1_OFFSET1_Msk
	ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0].
#define	ADC_OFR1_OFFSET1_0   (0x0000001UL << ADC_OFR1_OFFSET1_Pos)
	0x00000001
#define	ADC_OFR1_OFFSET1_1   (0x0000002UL << ADC_OFR1_OFFSET1_Pos)
	0x00000002
#define	ADC_OFR1_OFFSET1_2   (0x0000004UL << ADC_OFR1_OFFSET1_Pos)
	0x00000004
#define	ADC_OFR1_OFFSET1_3   (0x0000008UL << ADC_OFR1_OFFSET1_Pos)
	0x00000008
#define	ADC_OFR1_OFFSET1_4   (0x0000010UL << ADC_OFR1_OFFSET1_Pos)
	0x00000010
#define	ADC_OFR1_OFFSET1_5   (0x0000020UL << ADC_OFR1_OFFSET1_Pos)
	0x00000020
#define	ADC_OFR1_OFFSET1_6   (0x0000040UL << ADC_OFR1_OFFSET1_Pos)
	0x00000040
#define	ADC_OFR1_OFFSET1_7   (0x0000080UL << ADC_OFR1_OFFSET1_Pos)
	0x00000080
#define	ADC_OFR1_OFFSET1_8   (0x0000100UL << ADC_OFR1_OFFSET1_Pos)
	0x00000100
#define	ADC_OFR1_OFFSET1_9   (0x0000200UL << ADC_OFR1_OFFSET1_Pos)
	0x00000200
#define	ADC_OFR1_OFFSET1_10   (0x0000400UL << ADC_OFR1_OFFSET1_Pos)
	0x00000400
#define	ADC_OFR1_OFFSET1_11   (0x0000800UL << ADC_OFR1_OFFSET1_Pos)
	0x00000800
#define	ADC_OFR1_OFFSET1_12   (0x0001000UL << ADC_OFR1_OFFSET1_Pos)
	0x00001000
#define	ADC_OFR1_OFFSET1_13   (0x0002000UL << ADC_OFR1_OFFSET1_Pos)
	0x00002000
#define	ADC_OFR1_OFFSET1_14   (0x0004000UL << ADC_OFR1_OFFSET1_Pos)
	0x00004000
#define	ADC_OFR1_OFFSET1_15   (0x0008000UL << ADC_OFR1_OFFSET1_Pos)
	0x00008000
#define	ADC_OFR1_OFFSET1_16   (0x0010000UL << ADC_OFR1_OFFSET1_Pos)
	0x00010000
#define	ADC_OFR1_OFFSET1_17   (0x0020000UL << ADC_OFR1_OFFSET1_Pos)
	0x00020000
#define	ADC_OFR1_OFFSET1_18   (0x0040000UL << ADC_OFR1_OFFSET1_Pos)
	0x00040000
#define	ADC_OFR1_OFFSET1_19   (0x0080000UL << ADC_OFR1_OFFSET1_Pos)
	0x00080000
#define	ADC_OFR1_OFFSET1_20   (0x0100000UL << ADC_OFR1_OFFSET1_Pos)
	0x00100000
#define	ADC_OFR1_OFFSET1_21   (0x0200000UL << ADC_OFR1_OFFSET1_Pos)
	0x00200000
#define	ADC_OFR1_OFFSET1_22   (0x0400000UL << ADC_OFR1_OFFSET1_Pos)
	0x00400000
#define	ADC_OFR1_OFFSET1_23   (0x0800000UL << ADC_OFR1_OFFSET1_Pos)
	0x00800000
#define	ADC_OFR1_OFFSET1_24   (0x1000000UL << ADC_OFR1_OFFSET1_Pos)
	0x01000000
#define	ADC_OFR1_OFFSET1_25   (0x2000000UL << ADC_OFR1_OFFSET1_Pos)
	0x02000000
#define	ADC_OFR1_OFFSET1_CH_Pos   (26U)
#define	ADC_OFR1_OFFSET1_CH_Msk   (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)
	0x7C000000
#define	ADC_OFR1_OFFSET1_CH   ADC_OFR1_OFFSET1_CH_Msk
	ADC Channel selection for the data offset 1.
#define	ADC_OFR1_OFFSET1_CH_0   (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)
	0x04000000
#define	ADC_OFR1_OFFSET1_CH_1   (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)
	0x08000000
#define	ADC_OFR1_OFFSET1_CH_2   (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)
	0x10000000
#define	ADC_OFR1_OFFSET1_CH_3   (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)
	0x20000000
#define	ADC_OFR1_OFFSET1_CH_4   (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)
	0x40000000
#define	ADC_OFR1_SSATE_Pos   (31U)
#define	ADC_OFR1_SSATE_Msk   (0x1UL << ADC_OFR1_SSATE_Pos)
	0x80000000
#define	ADC_OFR1_SSATE   ADC_OFR1_SSATE_Msk
	ADC Signed saturation Enable.
#define	ADC3_OFR1_OFFSET1_Pos   (0U)
#define	ADC3_OFR1_OFFSET1_Msk   (0xFFFUL << ADC3_OFR1_OFFSET1_Pos)
	0x00000FFF
#define	ADC3_OFR1_OFFSET1   ADC3_OFR1_OFFSET1_Msk
	ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0].
#define	ADC3_OFR1_OFFSETPOS_Pos   (24U)
#define	ADC3_OFR1_OFFSETPOS_Msk   (0x1UL << ADC3_OFR1_OFFSETPOS_Pos)
	0x01000000
#define	ADC3_OFR1_OFFSETPOS   ADC3_OFR1_OFFSETPOS_Msk
	ADC offset number 1 positive.
#define	ADC3_OFR1_SATEN_Pos   (25U)
#define	ADC3_OFR1_SATEN_Msk   (0x1UL << ADC3_OFR1_SATEN_Pos)
	0x02000000
#define	ADC3_OFR1_SATEN   ADC3_OFR1_SATEN_Msk
	ADC offset number 1 saturation enable.
#define	ADC3_OFR1_OFFSET1_EN_Pos   (31U)
#define	ADC3_OFR1_OFFSET1_EN_Msk   (0x1UL << ADC3_OFR1_OFFSET1_EN_Pos)
	0x80000000
#define	ADC3_OFR1_OFFSET1_EN   ADC3_OFR1_OFFSET1_EN_Msk
	ADC offset number 1 enable.
#define	ADC_OFR2_OFFSET2_Pos   (0U)
#define	ADC_OFR2_OFFSET2_Msk   (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos)
	0x03FFFFFF
#define	ADC_OFR2_OFFSET2   ADC_OFR2_OFFSET2_Msk
	ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0].
#define	ADC_OFR2_OFFSET2_0   (0x0000001UL << ADC_OFR2_OFFSET2_Pos)
	0x00000001
#define	ADC_OFR2_OFFSET2_1   (0x0000002UL << ADC_OFR2_OFFSET2_Pos)
	0x00000002
#define	ADC_OFR2_OFFSET2_2   (0x0000004UL << ADC_OFR2_OFFSET2_Pos)
	0x00000004
#define	ADC_OFR2_OFFSET2_3   (0x0000008UL << ADC_OFR2_OFFSET2_Pos)
	0x00000008
#define	ADC_OFR2_OFFSET2_4   (0x0000010UL << ADC_OFR2_OFFSET2_Pos)
	0x00000010
#define	ADC_OFR2_OFFSET2_5   (0x0000020UL << ADC_OFR2_OFFSET2_Pos)
	0x00000020
#define	ADC_OFR2_OFFSET2_6   (0x0000040UL << ADC_OFR2_OFFSET2_Pos)
	0x00000040
#define	ADC_OFR2_OFFSET2_7   (0x0000080UL << ADC_OFR2_OFFSET2_Pos)
	0x00000080
#define	ADC_OFR2_OFFSET2_8   (0x0000100UL << ADC_OFR2_OFFSET2_Pos)
	0x00000100
#define	ADC_OFR2_OFFSET2_9   (0x0000200UL << ADC_OFR2_OFFSET2_Pos)
	0x00000200
#define	ADC_OFR2_OFFSET2_10   (0x0000400UL << ADC_OFR2_OFFSET2_Pos)
	0x00000400
#define	ADC_OFR2_OFFSET2_11   (0x0000800UL << ADC_OFR2_OFFSET2_Pos)
	0x00000800
#define	ADC_OFR2_OFFSET2_12   (0x0001000UL << ADC_OFR2_OFFSET2_Pos)
	0x00001000
#define	ADC_OFR2_OFFSET2_13   (0x0002000UL << ADC_OFR2_OFFSET2_Pos)
	0x00002000
#define	ADC_OFR2_OFFSET2_14   (0x0004000UL << ADC_OFR2_OFFSET2_Pos)
	0x00004000
#define	ADC_OFR2_OFFSET2_15   (0x0008000UL << ADC_OFR2_OFFSET2_Pos)
	0x00008000
#define	ADC_OFR2_OFFSET2_16   (0x0010000UL << ADC_OFR2_OFFSET2_Pos)
	0x00010000
#define	ADC_OFR2_OFFSET2_17   (0x0020000UL << ADC_OFR2_OFFSET2_Pos)
	0x00020000
#define	ADC_OFR2_OFFSET2_18   (0x0040000UL << ADC_OFR2_OFFSET2_Pos)
	0x00040000
#define	ADC_OFR2_OFFSET2_19   (0x0080000UL << ADC_OFR2_OFFSET2_Pos)
	0x00080000
#define	ADC_OFR2_OFFSET2_20   (0x0100000UL << ADC_OFR2_OFFSET2_Pos)
	0x00100000
#define	ADC_OFR2_OFFSET2_21   (0x0200000UL << ADC_OFR2_OFFSET2_Pos)
	0x00200000
#define	ADC_OFR2_OFFSET2_22   (0x0400000UL << ADC_OFR2_OFFSET2_Pos)
	0x00400000
#define	ADC_OFR2_OFFSET2_23   (0x0800000UL << ADC_OFR2_OFFSET2_Pos)
	0x00800000
#define	ADC_OFR2_OFFSET2_24   (0x1000000UL << ADC_OFR2_OFFSET2_Pos)
	0x01000000
#define	ADC_OFR2_OFFSET2_25   (0x2000000UL << ADC_OFR2_OFFSET2_Pos)
	0x02000000
#define	ADC_OFR2_OFFSET2_CH_Pos   (26U)
#define	ADC_OFR2_OFFSET2_CH_Msk   (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)
	0x7C000000
#define	ADC_OFR2_OFFSET2_CH   ADC_OFR2_OFFSET2_CH_Msk
	ADC Channel selection for the data offset 2.
#define	ADC_OFR2_OFFSET2_CH_0   (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)
	0x04000000
#define	ADC_OFR2_OFFSET2_CH_1   (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)
	0x08000000
#define	ADC_OFR2_OFFSET2_CH_2   (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)
	0x10000000
#define	ADC_OFR2_OFFSET2_CH_3   (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)
	0x20000000
#define	ADC_OFR2_OFFSET2_CH_4   (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)
	0x40000000
#define	ADC_OFR2_SSATE_Pos   (31U)
#define	ADC_OFR2_SSATE_Msk   (0x1UL << ADC_OFR2_SSATE_Pos)
	0x80000000
#define	ADC_OFR2_SSATE   ADC_OFR2_SSATE_Msk
	ADC Signed saturation Enable.
#define	ADC3_OFR2_OFFSET2_Pos   (0U)
#define	ADC3_OFR2_OFFSET2_Msk   (0xFFFUL << ADC3_OFR2_OFFSET2_Pos)
	0x00000FFF
#define	ADC3_OFR2_OFFSET2   ADC3_OFR2_OFFSET2_Msk
	ADC data offset 2 for channel programmed into bits OFFSET1_CH[4:0].
#define	ADC3_OFR2_OFFSETPOS_Pos   (24U)
#define	ADC3_OFR2_OFFSETPOS_Msk   (0x1UL << ADC3_OFR2_OFFSETPOS_Pos)
	0x01000000
#define	ADC3_OFR2_OFFSETPOS   ADC3_OFR2_OFFSETPOS_Msk
	ADC offset number 2 positive.
#define	ADC3_OFR2_SATEN_Pos   (25U)
#define	ADC3_OFR2_SATEN_Msk   (0x1UL << ADC3_OFR2_SATEN_Pos)
	0x02000000
#define	ADC3_OFR2_SATEN   ADC3_OFR2_SATEN_Msk
	ADC offset number 2 saturation enable.
#define	ADC3_OFR2_OFFSET2_EN_Pos   (31U)
#define	ADC3_OFR2_OFFSET2_EN_Msk   (0x1UL << ADC3_OFR2_OFFSET2_EN_Pos)
	0x80000000
#define	ADC3_OFR2_OFFSET2_EN   ADC3_OFR2_OFFSET2_EN_Msk
	ADC offset number 2 enable.
#define	ADC_OFR3_OFFSET3_Pos   (0U)
#define	ADC_OFR3_OFFSET3_Msk   (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos)
	0x03FFFFFF
#define	ADC_OFR3_OFFSET3   ADC_OFR3_OFFSET3_Msk
	ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0].
#define	ADC_OFR3_OFFSET3_0   (0x0000001UL << ADC_OFR3_OFFSET3_Pos)
	0x00000001
#define	ADC_OFR3_OFFSET3_1   (0x0000002UL << ADC_OFR3_OFFSET3_Pos)
	0x00000002
#define	ADC_OFR3_OFFSET3_2   (0x0000004UL << ADC_OFR3_OFFSET3_Pos)
	0x00000004
#define	ADC_OFR3_OFFSET3_3   (0x0000008UL << ADC_OFR3_OFFSET3_Pos)
	0x00000008
#define	ADC_OFR3_OFFSET3_4   (0x0000010UL << ADC_OFR3_OFFSET3_Pos)
	0x00000010
#define	ADC_OFR3_OFFSET3_5   (0x0000020UL << ADC_OFR3_OFFSET3_Pos)
	0x00000020
#define	ADC_OFR3_OFFSET3_6   (0x0000040UL << ADC_OFR3_OFFSET3_Pos)
	0x00000040
#define	ADC_OFR3_OFFSET3_7   (0x0000080UL << ADC_OFR3_OFFSET3_Pos)
	0x00000080
#define	ADC_OFR3_OFFSET3_8   (0x0000100UL << ADC_OFR3_OFFSET3_Pos)
	0x00000100
#define	ADC_OFR3_OFFSET3_9   (0x0000200UL << ADC_OFR3_OFFSET3_Pos)
	0x00000200
#define	ADC_OFR3_OFFSET3_10   (0x0000400UL << ADC_OFR3_OFFSET3_Pos)
	0x00000400
#define	ADC_OFR3_OFFSET3_11   (0x0000800UL << ADC_OFR3_OFFSET3_Pos)
	0x00000800
#define	ADC_OFR3_OFFSET3_12   (0x0001000UL << ADC_OFR3_OFFSET3_Pos)
	0x00001000
#define	ADC_OFR3_OFFSET3_13   (0x0002000UL << ADC_OFR3_OFFSET3_Pos)
	0x00002000
#define	ADC_OFR3_OFFSET3_14   (0x0004000UL << ADC_OFR3_OFFSET3_Pos)
	0x00004000
#define	ADC_OFR3_OFFSET3_15   (0x0008000UL << ADC_OFR3_OFFSET3_Pos)
	0x00008000
#define	ADC_OFR3_OFFSET3_16   (0x0010000UL << ADC_OFR3_OFFSET3_Pos)
	0x00010000
#define	ADC_OFR3_OFFSET3_17   (0x0020000UL << ADC_OFR3_OFFSET3_Pos)
	0x00020000
#define	ADC_OFR3_OFFSET3_18   (0x0040000UL << ADC_OFR3_OFFSET3_Pos)
	0x00040000
#define	ADC_OFR3_OFFSET3_19   (0x0080000UL << ADC_OFR3_OFFSET3_Pos)
	0x00080000
#define	ADC_OFR3_OFFSET3_20   (0x0100000UL << ADC_OFR3_OFFSET3_Pos)
	0x00100000
#define	ADC_OFR3_OFFSET3_21   (0x0200000UL << ADC_OFR3_OFFSET3_Pos)
	0x00200000
#define	ADC_OFR3_OFFSET3_22   (0x0400000UL << ADC_OFR3_OFFSET3_Pos)
	0x00400000
#define	ADC_OFR3_OFFSET3_23   (0x0800000UL << ADC_OFR3_OFFSET3_Pos)
	0x00800000
#define	ADC_OFR3_OFFSET3_24   (0x1000000UL << ADC_OFR3_OFFSET3_Pos)
	0x01000000
#define	ADC_OFR3_OFFSET3_25   (0x2000000UL << ADC_OFR3_OFFSET3_Pos)
	0x02000000
#define	ADC_OFR3_OFFSET3_CH_Pos   (26U)
#define	ADC_OFR3_OFFSET3_CH_Msk   (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)
	0x7C000000
#define	ADC_OFR3_OFFSET3_CH   ADC_OFR3_OFFSET3_CH_Msk
	ADC Channel selection for the data offset 3.
#define	ADC_OFR3_OFFSET3_CH_0   (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)
	0x04000000
#define	ADC_OFR3_OFFSET3_CH_1   (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)
	0x08000000
#define	ADC_OFR3_OFFSET3_CH_2   (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)
	0x10000000
#define	ADC_OFR3_OFFSET3_CH_3   (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)
	0x20000000
#define	ADC_OFR3_OFFSET3_CH_4   (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)
	0x40000000
#define	ADC_OFR3_SSATE_Pos   (31U)
#define	ADC_OFR3_SSATE_Msk   (0x1UL << ADC_OFR3_SSATE_Pos)
	0x80000000
#define	ADC_OFR3_SSATE   ADC_OFR3_SSATE_Msk
	ADC Signed saturation Enable.
#define	ADC3_OFR3_OFFSET3_Pos   (0U)
#define	ADC3_OFR3_OFFSET3_Msk   (0xFFFUL << ADC3_OFR3_OFFSET3_Pos)
	0x00000FFF
#define	ADC3_OFR3_OFFSET3   ADC3_OFR3_OFFSET3_Msk
	ADC data offset 3 for channel programmed into bits OFFSET1_CH[4:0].
#define	ADC3_OFR3_OFFSETPOS_Pos   (24U)
#define	ADC3_OFR3_OFFSETPOS_Msk   (0x1UL << ADC3_OFR3_OFFSETPOS_Pos)
	0x01000000
#define	ADC3_OFR3_OFFSETPOS   ADC3_OFR3_OFFSETPOS_Msk
	ADC offset number 3 positive.
#define	ADC3_OFR3_SATEN_Pos   (25U)
#define	ADC3_OFR3_SATEN_Msk   (0x1UL << ADC3_OFR3_SATEN_Pos)
	0x02000000
#define	ADC3_OFR3_SATEN   ADC3_OFR3_SATEN_Msk
	ADC offset number 3 saturation enable.
#define	ADC3_OFR3_OFFSET3_EN_Pos   (31U)
#define	ADC3_OFR3_OFFSET3_EN_Msk   (0x1UL << ADC3_OFR3_OFFSET3_EN_Pos)
	0x80000000
#define	ADC3_OFR3_OFFSET3_EN   ADC3_OFR3_OFFSET3_EN_Msk
	ADC offset number 3 enable.
#define	ADC_OFR4_OFFSET4_Pos   (0U)
#define	ADC_OFR4_OFFSET4_Msk   (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos)
	0x03FFFFFF
#define	ADC_OFR4_OFFSET4   ADC_OFR4_OFFSET4_Msk
	ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0].
#define	ADC_OFR4_OFFSET4_0   (0x0000001UL << ADC_OFR4_OFFSET4_Pos)
	0x00000001
#define	ADC_OFR4_OFFSET4_1   (0x0000002UL << ADC_OFR4_OFFSET4_Pos)
	0x00000002
#define	ADC_OFR4_OFFSET4_2   (0x0000004UL << ADC_OFR4_OFFSET4_Pos)
	0x00000004
#define	ADC_OFR4_OFFSET4_3   (0x0000008UL << ADC_OFR4_OFFSET4_Pos)
	0x00000008
#define	ADC_OFR4_OFFSET4_4   (0x0000010UL << ADC_OFR4_OFFSET4_Pos)
	0x00000010
#define	ADC_OFR4_OFFSET4_5   (0x0000020UL << ADC_OFR4_OFFSET4_Pos)
	0x00000020
#define	ADC_OFR4_OFFSET4_6   (0x0000040UL << ADC_OFR4_OFFSET4_Pos)
	0x00000040
#define	ADC_OFR4_OFFSET4_7   (0x0000080UL << ADC_OFR4_OFFSET4_Pos)
	0x00000080
#define	ADC_OFR4_OFFSET4_8   (0x0000100UL << ADC_OFR4_OFFSET4_Pos)
	0x00000100
#define	ADC_OFR4_OFFSET4_9   (0x0000200UL << ADC_OFR4_OFFSET4_Pos)
	0x00000200
#define	ADC_OFR4_OFFSET4_10   (0x0000400UL << ADC_OFR4_OFFSET4_Pos)
	0x00000400
#define	ADC_OFR4_OFFSET4_11   (0x0000800UL << ADC_OFR4_OFFSET4_Pos)
	0x00000800
#define	ADC_OFR4_OFFSET4_12   (0x0001000UL << ADC_OFR4_OFFSET4_Pos)
	0x00001000
#define	ADC_OFR4_OFFSET4_13   (0x0002000UL << ADC_OFR4_OFFSET4_Pos)
	0x00002000
#define	ADC_OFR4_OFFSET4_14   (0x0004000UL << ADC_OFR4_OFFSET4_Pos)
	0x00004000
#define	ADC_OFR4_OFFSET4_15   (0x0008000UL << ADC_OFR4_OFFSET4_Pos)
	0x00008000
#define	ADC_OFR4_OFFSET4_16   (0x0010000UL << ADC_OFR4_OFFSET4_Pos)
	0x00010000
#define	ADC_OFR4_OFFSET4_17   (0x0020000UL << ADC_OFR4_OFFSET4_Pos)
	0x00020000
#define	ADC_OFR4_OFFSET4_18   (0x0040000UL << ADC_OFR4_OFFSET4_Pos)
	0x00040000
#define	ADC_OFR4_OFFSET4_19   (0x0080000UL << ADC_OFR4_OFFSET4_Pos)
	0x00080000
#define	ADC_OFR4_OFFSET4_20   (0x0100000UL << ADC_OFR4_OFFSET4_Pos)
	0x00100000
#define	ADC_OFR4_OFFSET4_21   (0x0200000UL << ADC_OFR4_OFFSET4_Pos)
	0x00200000
#define	ADC_OFR4_OFFSET4_22   (0x0400000UL << ADC_OFR4_OFFSET4_Pos)
	0x00400000
#define	ADC_OFR4_OFFSET4_23   (0x0800000UL << ADC_OFR4_OFFSET4_Pos)
	0x00800000
#define	ADC_OFR4_OFFSET4_24   (0x1000000UL << ADC_OFR4_OFFSET4_Pos)
	0x01000000
#define	ADC_OFR4_OFFSET4_25   (0x2000000UL << ADC_OFR4_OFFSET4_Pos)
	0x02000000
#define	ADC_OFR4_OFFSET4_CH_Pos   (26U)
#define	ADC_OFR4_OFFSET4_CH_Msk   (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)
	0x7C000000
#define	ADC_OFR4_OFFSET4_CH   ADC_OFR4_OFFSET4_CH_Msk
	ADC Channel selection for the data offset 4.
#define	ADC_OFR4_OFFSET4_CH_0   (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)
	0x04000000
#define	ADC_OFR4_OFFSET4_CH_1   (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)
	0x08000000
#define	ADC_OFR4_OFFSET4_CH_2   (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)
	0x10000000
#define	ADC_OFR4_OFFSET4_CH_3   (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)
	0x20000000
#define	ADC_OFR4_OFFSET4_CH_4   (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)
	0x40000000
#define	ADC_OFR4_SSATE_Pos   (31U)
#define	ADC_OFR4_SSATE_Msk   (0x1UL << ADC_OFR4_SSATE_Pos)
	0x80000000
#define	ADC_OFR4_SSATE   ADC_OFR4_SSATE_Msk
	ADC Signed saturation Enable.
#define	ADC3_OFR4_OFFSET4_Pos   (0U)
#define	ADC3_OFR4_OFFSET4_Msk   (0xFFFUL << ADC3_OFR4_OFFSET4_Pos)
	0x00000FFF
#define	ADC3_OFR4_OFFSET4   ADC3_OFR4_OFFSET4_Msk
	ADC data offset 4 for channel programmed into bits OFFSET1_CH[4:0].
#define	ADC3_OFR4_OFFSETPOS_Pos   (24U)
#define	ADC3_OFR4_OFFSETPOS_Msk   (0x1UL << ADC3_OFR4_OFFSETPOS_Pos)
	0x01000000
#define	ADC3_OFR4_OFFSETPOS   ADC3_OFR4_OFFSETPOS_Msk
	ADC offset number 4 positive.
#define	ADC3_OFR4_SATEN_Pos   (25U)
#define	ADC3_OFR4_SATEN_Msk   (0x1UL << ADC3_OFR4_SATEN_Pos)
	0x02000000
#define	ADC3_OFR4_SATEN   ADC3_OFR4_SATEN_Msk
	ADC offset number 4 saturation enable.
#define	ADC3_OFR4_OFFSET4_EN_Pos   (31U)
#define	ADC3_OFR4_OFFSET4_EN_Msk   (0x1UL << ADC3_OFR4_OFFSET4_EN_Pos)
	0x80000000
#define	ADC3_OFR4_OFFSET4_EN   ADC3_OFR4_OFFSET4_EN_Msk
	ADC offset number 4 enable.
#define	ADC_JDR1_JDATA_Pos   (0U)
#define	ADC_JDR1_JDATA_Msk   (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)
	0xFFFFFFFF
#define	ADC_JDR1_JDATA   ADC_JDR1_JDATA_Msk
	ADC Injected DATA.
#define	ADC_JDR1_JDATA_0   (0x00000001UL << ADC_JDR1_JDATA_Pos)
	0x00000001
#define	ADC_JDR1_JDATA_1   (0x00000002UL << ADC_JDR1_JDATA_Pos)
	0x00000002
#define	ADC_JDR1_JDATA_2   (0x00000004UL << ADC_JDR1_JDATA_Pos)
	0x00000004
#define	ADC_JDR1_JDATA_3   (0x00000008UL << ADC_JDR1_JDATA_Pos)
	0x00000008
#define	ADC_JDR1_JDATA_4   (0x00000010UL << ADC_JDR1_JDATA_Pos)
	0x00000010
#define	ADC_JDR1_JDATA_5   (0x00000020UL << ADC_JDR1_JDATA_Pos)
	0x00000020
#define	ADC_JDR1_JDATA_6   (0x00000040UL << ADC_JDR1_JDATA_Pos)
	0x00000040
#define	ADC_JDR1_JDATA_7   (0x00000080UL << ADC_JDR1_JDATA_Pos)
	0x00000080
#define	ADC_JDR1_JDATA_8   (0x00000100UL << ADC_JDR1_JDATA_Pos)
	0x00000100
#define	ADC_JDR1_JDATA_9   (0x00000200UL << ADC_JDR1_JDATA_Pos)
	0x00000200
#define	ADC_JDR1_JDATA_10   (0x00000400UL << ADC_JDR1_JDATA_Pos)
	0x00000400
#define	ADC_JDR1_JDATA_11   (0x00000800UL << ADC_JDR1_JDATA_Pos)
	0x00000800
#define	ADC_JDR1_JDATA_12   (0x00001000UL << ADC_JDR1_JDATA_Pos)
	0x00001000
#define	ADC_JDR1_JDATA_13   (0x00002000UL << ADC_JDR1_JDATA_Pos)
	0x00002000
#define	ADC_JDR1_JDATA_14   (0x00004000UL << ADC_JDR1_JDATA_Pos)
	0x00004000
#define	ADC_JDR1_JDATA_15   (0x00008000UL << ADC_JDR1_JDATA_Pos)
	0x00008000
#define	ADC_JDR1_JDATA_16   (0x00010000UL << ADC_JDR1_JDATA_Pos)
	0x00010000
#define	ADC_JDR1_JDATA_17   (0x00020000UL << ADC_JDR1_JDATA_Pos)
	0x00020000
#define	ADC_JDR1_JDATA_18   (0x00040000UL << ADC_JDR1_JDATA_Pos)
	0x00040000
#define	ADC_JDR1_JDATA_19   (0x00080000UL << ADC_JDR1_JDATA_Pos)
	0x00080000
#define	ADC_JDR1_JDATA_20   (0x00100000UL << ADC_JDR1_JDATA_Pos)
	0x00100000
#define	ADC_JDR1_JDATA_21   (0x00200000UL << ADC_JDR1_JDATA_Pos)
	0x00200000
#define	ADC_JDR1_JDATA_22   (0x00400000UL << ADC_JDR1_JDATA_Pos)
	0x00400000
#define	ADC_JDR1_JDATA_23   (0x00800000UL << ADC_JDR1_JDATA_Pos)
	0x00800000
#define	ADC_JDR1_JDATA_24   (0x01000000UL << ADC_JDR1_JDATA_Pos)
	0x01000000
#define	ADC_JDR1_JDATA_25   (0x02000000UL << ADC_JDR1_JDATA_Pos)
	0x02000000
#define	ADC_JDR1_JDATA_26   (0x04000000UL << ADC_JDR1_JDATA_Pos)
	0x04000000
#define	ADC_JDR1_JDATA_27   (0x08000000UL << ADC_JDR1_JDATA_Pos)
	0x08000000
#define	ADC_JDR1_JDATA_28   (0x10000000UL << ADC_JDR1_JDATA_Pos)
	0x10000000
#define	ADC_JDR1_JDATA_29   (0x20000000UL << ADC_JDR1_JDATA_Pos)
	0x20000000
#define	ADC_JDR1_JDATA_30   (0x40000000UL << ADC_JDR1_JDATA_Pos)
	0x40000000
#define	ADC_JDR1_JDATA_31   (0x80000000UL << ADC_JDR1_JDATA_Pos)
	0x80000000
#define	ADC_JDR2_JDATA_Pos   (0U)
#define	ADC_JDR2_JDATA_Msk   (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)
	0xFFFFFFFF
#define	ADC_JDR2_JDATA   ADC_JDR2_JDATA_Msk
	ADC Injected DATA.
#define	ADC_JDR2_JDATA_0   (0x00000001UL << ADC_JDR2_JDATA_Pos)
	0x00000001
#define	ADC_JDR2_JDATA_1   (0x00000002UL << ADC_JDR2_JDATA_Pos)
	0x00000002
#define	ADC_JDR2_JDATA_2   (0x00000004UL << ADC_JDR2_JDATA_Pos)
	0x00000004
#define	ADC_JDR2_JDATA_3   (0x00000008UL << ADC_JDR2_JDATA_Pos)
	0x00000008
#define	ADC_JDR2_JDATA_4   (0x00000010UL << ADC_JDR2_JDATA_Pos)
	0x00000010
#define	ADC_JDR2_JDATA_5   (0x00000020UL << ADC_JDR2_JDATA_Pos)
	0x00000020
#define	ADC_JDR2_JDATA_6   (0x00000040UL << ADC_JDR2_JDATA_Pos)
	0x00000040
#define	ADC_JDR2_JDATA_7   (0x00000080UL << ADC_JDR2_JDATA_Pos)
	0x00000080
#define	ADC_JDR2_JDATA_8   (0x00000100UL << ADC_JDR2_JDATA_Pos)
	0x00000100
#define	ADC_JDR2_JDATA_9   (0x00000200UL << ADC_JDR2_JDATA_Pos)
	0x00000200
#define	ADC_JDR2_JDATA_10   (0x00000400UL << ADC_JDR2_JDATA_Pos)
	0x00000400
#define	ADC_JDR2_JDATA_11   (0x00000800UL << ADC_JDR2_JDATA_Pos)
	0x00000800
#define	ADC_JDR2_JDATA_12   (0x00001000UL << ADC_JDR2_JDATA_Pos)
	0x00001000
#define	ADC_JDR2_JDATA_13   (0x00002000UL << ADC_JDR2_JDATA_Pos)
	0x00002000
#define	ADC_JDR2_JDATA_14   (0x00004000UL << ADC_JDR2_JDATA_Pos)
	0x00004000
#define	ADC_JDR2_JDATA_15   (0x00008000UL << ADC_JDR2_JDATA_Pos)
	0x00008000
#define	ADC_JDR2_JDATA_16   (0x00010000UL << ADC_JDR2_JDATA_Pos)
	0x00010000
#define	ADC_JDR2_JDATA_17   (0x00020000UL << ADC_JDR2_JDATA_Pos)
	0x00020000
#define	ADC_JDR2_JDATA_18   (0x00040000UL << ADC_JDR2_JDATA_Pos)
	0x00040000
#define	ADC_JDR2_JDATA_19   (0x00080000UL << ADC_JDR2_JDATA_Pos)
	0x00080000
#define	ADC_JDR2_JDATA_20   (0x00100000UL << ADC_JDR2_JDATA_Pos)
	0x00100000
#define	ADC_JDR2_JDATA_21   (0x00200000UL << ADC_JDR2_JDATA_Pos)
	0x00200000
#define	ADC_JDR2_JDATA_22   (0x00400000UL << ADC_JDR2_JDATA_Pos)
	0x00400000
#define	ADC_JDR2_JDATA_23   (0x00800000UL << ADC_JDR2_JDATA_Pos)
	0x00800000
#define	ADC_JDR2_JDATA_24   (0x01000000UL << ADC_JDR2_JDATA_Pos)
	0x01000000
#define	ADC_JDR2_JDATA_25   (0x02000000UL << ADC_JDR2_JDATA_Pos)
	0x02000000
#define	ADC_JDR2_JDATA_26   (0x04000000UL << ADC_JDR2_JDATA_Pos)
	0x04000000
#define	ADC_JDR2_JDATA_27   (0x08000000UL << ADC_JDR2_JDATA_Pos)
	0x08000000
#define	ADC_JDR2_JDATA_28   (0x10000000UL << ADC_JDR2_JDATA_Pos)
	0x10000000
#define	ADC_JDR2_JDATA_29   (0x20000000UL << ADC_JDR2_JDATA_Pos)
	0x20000000
#define	ADC_JDR2_JDATA_30   (0x40000000UL << ADC_JDR2_JDATA_Pos)
	0x40000000
#define	ADC_JDR2_JDATA_31   (0x80000000UL << ADC_JDR2_JDATA_Pos)
	0x80000000
#define	ADC_JDR3_JDATA_Pos   (0U)
#define	ADC_JDR3_JDATA_Msk   (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)
	0xFFFFFFFF
#define	ADC_JDR3_JDATA   ADC_JDR3_JDATA_Msk
	ADC Injected DATA.
#define	ADC_JDR3_JDATA_0   (0x00000001UL << ADC_JDR3_JDATA_Pos)
	0x00000001
#define	ADC_JDR3_JDATA_1   (0x00000002UL << ADC_JDR3_JDATA_Pos)
	0x00000002
#define	ADC_JDR3_JDATA_2   (0x00000004UL << ADC_JDR3_JDATA_Pos)
	0x00000004
#define	ADC_JDR3_JDATA_3   (0x00000008UL << ADC_JDR3_JDATA_Pos)
	0x00000008
#define	ADC_JDR3_JDATA_4   (0x00000010UL << ADC_JDR3_JDATA_Pos)
	0x00000010
#define	ADC_JDR3_JDATA_5   (0x00000020UL << ADC_JDR3_JDATA_Pos)
	0x00000020
#define	ADC_JDR3_JDATA_6   (0x00000040UL << ADC_JDR3_JDATA_Pos)
	0x00000040
#define	ADC_JDR3_JDATA_7   (0x00000080UL << ADC_JDR3_JDATA_Pos)
	0x00000080
#define	ADC_JDR3_JDATA_8   (0x00000100UL << ADC_JDR3_JDATA_Pos)
	0x00000100
#define	ADC_JDR3_JDATA_9   (0x00000200UL << ADC_JDR3_JDATA_Pos)
	0x00000200
#define	ADC_JDR3_JDATA_10   (0x00000400UL << ADC_JDR3_JDATA_Pos)
	0x00000400
#define	ADC_JDR3_JDATA_11   (0x00000800UL << ADC_JDR3_JDATA_Pos)
	0x00000800
#define	ADC_JDR3_JDATA_12   (0x00001000UL << ADC_JDR3_JDATA_Pos)
	0x00001000
#define	ADC_JDR3_JDATA_13   (0x00002000UL << ADC_JDR3_JDATA_Pos)
	0x00002000
#define	ADC_JDR3_JDATA_14   (0x00004000UL << ADC_JDR3_JDATA_Pos)
	0x00004000
#define	ADC_JDR3_JDATA_15   (0x00008000UL << ADC_JDR3_JDATA_Pos)
	0x00008000
#define	ADC_JDR3_JDATA_16   (0x00010000UL << ADC_JDR3_JDATA_Pos)
	0x00010000
#define	ADC_JDR3_JDATA_17   (0x00020000UL << ADC_JDR3_JDATA_Pos)
	0x00020000
#define	ADC_JDR3_JDATA_18   (0x00040000UL << ADC_JDR3_JDATA_Pos)
	0x00040000
#define	ADC_JDR3_JDATA_19   (0x00080000UL << ADC_JDR3_JDATA_Pos)
	0x00080000
#define	ADC_JDR3_JDATA_20   (0x00100000UL << ADC_JDR3_JDATA_Pos)
	0x00100000
#define	ADC_JDR3_JDATA_21   (0x00200000UL << ADC_JDR3_JDATA_Pos)
	0x00200000
#define	ADC_JDR3_JDATA_22   (0x00400000UL << ADC_JDR3_JDATA_Pos)
	0x00400000
#define	ADC_JDR3_JDATA_23   (0x00800000UL << ADC_JDR3_JDATA_Pos)
	0x00800000
#define	ADC_JDR3_JDATA_24   (0x01000000UL << ADC_JDR3_JDATA_Pos)
	0x01000000
#define	ADC_JDR3_JDATA_25   (0x02000000UL << ADC_JDR3_JDATA_Pos)
	0x02000000
#define	ADC_JDR3_JDATA_26   (0x04000000UL << ADC_JDR3_JDATA_Pos)
	0x04000000
#define	ADC_JDR3_JDATA_27   (0x08000000UL << ADC_JDR3_JDATA_Pos)
	0x08000000
#define	ADC_JDR3_JDATA_28   (0x10000000UL << ADC_JDR3_JDATA_Pos)
	0x10000000
#define	ADC_JDR3_JDATA_29   (0x20000000UL << ADC_JDR3_JDATA_Pos)
	0x20000000
#define	ADC_JDR3_JDATA_30   (0x40000000UL << ADC_JDR3_JDATA_Pos)
	0x40000000
#define	ADC_JDR3_JDATA_31   (0x80000000UL << ADC_JDR3_JDATA_Pos)
	0x80000000
#define	ADC_JDR4_JDATA_Pos   (0U)
#define	ADC_JDR4_JDATA_Msk   (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)
	0xFFFFFFFF
#define	ADC_JDR4_JDATA   ADC_JDR4_JDATA_Msk
	ADC Injected DATA.
#define	ADC_JDR4_JDATA_0   (0x00000001UL << ADC_JDR4_JDATA_Pos)
	0x00000001
#define	ADC_JDR4_JDATA_1   (0x00000002UL << ADC_JDR4_JDATA_Pos)
	0x00000002
#define	ADC_JDR4_JDATA_2   (0x00000004UL << ADC_JDR4_JDATA_Pos)
	0x00000004
#define	ADC_JDR4_JDATA_3   (0x00000008UL << ADC_JDR4_JDATA_Pos)
	0x00000008
#define	ADC_JDR4_JDATA_4   (0x00000010UL << ADC_JDR4_JDATA_Pos)
	0x00000010
#define	ADC_JDR4_JDATA_5   (0x00000020UL << ADC_JDR4_JDATA_Pos)
	0x00000020
#define	ADC_JDR4_JDATA_6   (0x00000040UL << ADC_JDR4_JDATA_Pos)
	0x00000040
#define	ADC_JDR4_JDATA_7   (0x00000080UL << ADC_JDR4_JDATA_Pos)
	0x00000080
#define	ADC_JDR4_JDATA_8   (0x00000100UL << ADC_JDR4_JDATA_Pos)
	0x00000100
#define	ADC_JDR4_JDATA_9   (0x00000200UL << ADC_JDR4_JDATA_Pos)
	0x00000200
#define	ADC_JDR4_JDATA_10   (0x00000400UL << ADC_JDR4_JDATA_Pos)
	0x00000400
#define	ADC_JDR4_JDATA_11   (0x00000800UL << ADC_JDR4_JDATA_Pos)
	0x00000800
#define	ADC_JDR4_JDATA_12   (0x00001000UL << ADC_JDR4_JDATA_Pos)
	0x00001000
#define	ADC_JDR4_JDATA_13   (0x00002000UL << ADC_JDR4_JDATA_Pos)
	0x00002000
#define	ADC_JDR4_JDATA_14   (0x00004000UL << ADC_JDR4_JDATA_Pos)
	0x00004000
#define	ADC_JDR4_JDATA_15   (0x00008000UL << ADC_JDR4_JDATA_Pos)
	0x00008000
#define	ADC_JDR4_JDATA_16   (0x00010000UL << ADC_JDR4_JDATA_Pos)
	0x00010000
#define	ADC_JDR4_JDATA_17   (0x00020000UL << ADC_JDR4_JDATA_Pos)
	0x00020000
#define	ADC_JDR4_JDATA_18   (0x00040000UL << ADC_JDR4_JDATA_Pos)
	0x00040000
#define	ADC_JDR4_JDATA_19   (0x00080000UL << ADC_JDR4_JDATA_Pos)
	0x00080000
#define	ADC_JDR4_JDATA_20   (0x00100000UL << ADC_JDR4_JDATA_Pos)
	0x00100000
#define	ADC_JDR4_JDATA_21   (0x00200000UL << ADC_JDR4_JDATA_Pos)
	0x00200000
#define	ADC_JDR4_JDATA_22   (0x00400000UL << ADC_JDR4_JDATA_Pos)
	0x00400000
#define	ADC_JDR4_JDATA_23   (0x00800000UL << ADC_JDR4_JDATA_Pos)
	0x00800000
#define	ADC_JDR4_JDATA_24   (0x01000000UL << ADC_JDR4_JDATA_Pos)
	0x01000000
#define	ADC_JDR4_JDATA_25   (0x02000000UL << ADC_JDR4_JDATA_Pos)
	0x02000000
#define	ADC_JDR4_JDATA_26   (0x04000000UL << ADC_JDR4_JDATA_Pos)
	0x04000000
#define	ADC_JDR4_JDATA_27   (0x08000000UL << ADC_JDR4_JDATA_Pos)
	0x08000000
#define	ADC_JDR4_JDATA_28   (0x10000000UL << ADC_JDR4_JDATA_Pos)
	0x10000000
#define	ADC_JDR4_JDATA_29   (0x20000000UL << ADC_JDR4_JDATA_Pos)
	0x20000000
#define	ADC_JDR4_JDATA_30   (0x40000000UL << ADC_JDR4_JDATA_Pos)
	0x40000000
#define	ADC_JDR4_JDATA_31   (0x80000000UL << ADC_JDR4_JDATA_Pos)
	0x80000000
#define	ADC_AWD2CR_AWD2CH_Pos   (0U)
#define	ADC_AWD2CR_AWD2CH_Msk   (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)
	0x000FFFFF
#define	ADC_AWD2CR_AWD2CH   ADC_AWD2CR_AWD2CH_Msk
	ADC Analog watchdog 2 channel selection.
#define	ADC_AWD2CR_AWD2CH_0   (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)
	0x00000001
#define	ADC_AWD2CR_AWD2CH_1   (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)
	0x00000002
#define	ADC_AWD2CR_AWD2CH_2   (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)
	0x00000004
#define	ADC_AWD2CR_AWD2CH_3   (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)
	0x00000008
#define	ADC_AWD2CR_AWD2CH_4   (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)
	0x00000010
#define	ADC_AWD2CR_AWD2CH_5   (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)
	0x00000020
#define	ADC_AWD2CR_AWD2CH_6   (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)
	0x00000040
#define	ADC_AWD2CR_AWD2CH_7   (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)
	0x00000080
#define	ADC_AWD2CR_AWD2CH_8   (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)
	0x00000100
#define	ADC_AWD2CR_AWD2CH_9   (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)
	0x00000200
#define	ADC_AWD2CR_AWD2CH_10   (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)
	0x00000400
#define	ADC_AWD2CR_AWD2CH_11   (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)
	0x00000800
#define	ADC_AWD2CR_AWD2CH_12   (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)
	0x00001000
#define	ADC_AWD2CR_AWD2CH_13   (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)
	0x00002000
#define	ADC_AWD2CR_AWD2CH_14   (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)
	0x00004000
#define	ADC_AWD2CR_AWD2CH_15   (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)
	0x00008000
#define	ADC_AWD2CR_AWD2CH_16   (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)
	0x00010000
#define	ADC_AWD2CR_AWD2CH_17   (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)
	0x00020000
#define	ADC_AWD2CR_AWD2CH_18   (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)
	0x00040000
#define	ADC_AWD2CR_AWD2CH_19   (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)
	0x00080000
#define	ADC3_AWD2CR_AWD2CH_Pos   (0U)
#define	ADC3_AWD2CR_AWD2CH_Msk   (0x7FFFFUL << ADC3_AWD2CR_AWD2CH_Pos)
	0x0007FFFF
#define	ADC3_AWD2CR_AWD2CH   ADC3_AWD2CR_AWD2CH_Msk
	ADC Analog watchdog 2 channel selection.
#define	ADC_AWD3CR_AWD3CH_Pos   (0U)
#define	ADC_AWD3CR_AWD3CH_Msk   (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)
	0x000FFFFF
#define	ADC_AWD3CR_AWD3CH   ADC_AWD3CR_AWD3CH_Msk
	ADC Analog watchdog 2 channel selection.
#define	ADC_AWD3CR_AWD3CH_0   (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)
	0x00000001
#define	ADC_AWD3CR_AWD3CH_1   (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)
	0x00000002
#define	ADC_AWD3CR_AWD3CH_2   (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)
	0x00000004
#define	ADC_AWD3CR_AWD3CH_3   (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)
	0x00000008
#define	ADC_AWD3CR_AWD3CH_4   (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)
	0x00000010
#define	ADC_AWD3CR_AWD3CH_5   (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)
	0x00000020
#define	ADC_AWD3CR_AWD3CH_6   (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)
	0x00000040
#define	ADC_AWD3CR_AWD3CH_7   (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)
	0x00000080
#define	ADC_AWD3CR_AWD3CH_8   (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)
	0x00000100
#define	ADC_AWD3CR_AWD3CH_9   (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)
	0x00000200
#define	ADC_AWD3CR_AWD3CH_10   (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)
	0x00000400
#define	ADC_AWD3CR_AWD3CH_11   (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)
	0x00000800
#define	ADC_AWD3CR_AWD3CH_12   (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)
	0x00001000
#define	ADC_AWD3CR_AWD3CH_13   (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)
	0x00002000
#define	ADC_AWD3CR_AWD3CH_14   (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)
	0x00004000
#define	ADC_AWD3CR_AWD3CH_15   (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)
	0x00008000
#define	ADC_AWD3CR_AWD3CH_16   (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)
	0x00010000
#define	ADC_AWD3CR_AWD3CH_17   (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)
	0x00020000
#define	ADC_AWD3CR_AWD3CH_18   (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)
	0x00040000
#define	ADC_AWD3CR_AWD3CH_19   (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)
	0x00080000
#define	ADC3_AWD3CR_AWD3CH_Pos   (0U)
#define	ADC3_AWD3CR_AWD3CH_Msk   (0x7FFFFUL << ADC3_AWD3CR_AWD3CH_Pos)
	0x0007FFFF
#define	ADC3_AWD3CR_AWD3CH   ADC3_AWD3CR_AWD3CH_Msk
	ADC Analog watchdog 3 channel selection.
#define	ADC_DIFSEL_DIFSEL_Pos   (0U)
#define	ADC_DIFSEL_DIFSEL_Msk   (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)
	0x000FFFFF
#define	ADC_DIFSEL_DIFSEL   ADC_DIFSEL_DIFSEL_Msk
	ADC differential modes for channels 1 to 18.
#define	ADC_DIFSEL_DIFSEL_0   (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)
	0x00000001
#define	ADC_DIFSEL_DIFSEL_1   (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)
	0x00000002
#define	ADC_DIFSEL_DIFSEL_2   (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)
	0x00000004
#define	ADC_DIFSEL_DIFSEL_3   (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)
	0x00000008
#define	ADC_DIFSEL_DIFSEL_4   (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)
	0x00000010
#define	ADC_DIFSEL_DIFSEL_5   (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)
	0x00000020
#define	ADC_DIFSEL_DIFSEL_6   (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)
	0x00000040
#define	ADC_DIFSEL_DIFSEL_7   (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)
	0x00000080
#define	ADC_DIFSEL_DIFSEL_8   (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)
	0x00000100
#define	ADC_DIFSEL_DIFSEL_9   (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)
	0x00000200
#define	ADC_DIFSEL_DIFSEL_10   (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)
	0x00000400
#define	ADC_DIFSEL_DIFSEL_11   (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)
	0x00000800
#define	ADC_DIFSEL_DIFSEL_12   (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)
	0x00001000
#define	ADC_DIFSEL_DIFSEL_13   (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)
	0x00002000
#define	ADC_DIFSEL_DIFSEL_14   (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)
	0x00004000
#define	ADC_DIFSEL_DIFSEL_15   (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)
	0x00008000
#define	ADC_DIFSEL_DIFSEL_16   (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)
	0x00010000
#define	ADC_DIFSEL_DIFSEL_17   (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)
	0x00020000
#define	ADC_DIFSEL_DIFSEL_18   (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)
	0x00040000
#define	ADC_DIFSEL_DIFSEL_19   (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)
	0x00080000
#define	ADC_CALFACT_CALFACT_S_Pos   (0U)
#define	ADC_CALFACT_CALFACT_S_Msk   (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos)
	0x000007FF
#define	ADC_CALFACT_CALFACT_S   ADC_CALFACT_CALFACT_S_Msk
	ADC calibration factors in single-ended mode.
#define	ADC_CALFACT_CALFACT_S_0   (0x001UL << ADC_CALFACT_CALFACT_S_Pos)
	0x00000001
#define	ADC_CALFACT_CALFACT_S_1   (0x002UL << ADC_CALFACT_CALFACT_S_Pos)
	0x00000002
#define	ADC_CALFACT_CALFACT_S_2   (0x004UL << ADC_CALFACT_CALFACT_S_Pos)
	0x00000004
#define	ADC_CALFACT_CALFACT_S_3   (0x008UL << ADC_CALFACT_CALFACT_S_Pos)
	0x00000008
#define	ADC_CALFACT_CALFACT_S_4   (0x010UL << ADC_CALFACT_CALFACT_S_Pos)
	0x00000010
#define	ADC_CALFACT_CALFACT_S_5   (0x020UL << ADC_CALFACT_CALFACT_S_Pos)
	0x00000020
#define	ADC_CALFACT_CALFACT_S_6   (0x040UL << ADC_CALFACT_CALFACT_S_Pos)
	0x00000040
#define	ADC_CALFACT_CALFACT_S_7   (0x080UL << ADC_CALFACT_CALFACT_S_Pos)
	0x00000080
#define	ADC_CALFACT_CALFACT_S_8   (0x100UL << ADC_CALFACT_CALFACT_S_Pos)
	0x00000100
#define	ADC_CALFACT_CALFACT_S_9   (0x200UL << ADC_CALFACT_CALFACT_S_Pos)
	0x00000200
#define	ADC_CALFACT_CALFACT_S_10   (0x400UL << ADC_CALFACT_CALFACT_S_Pos)
	0x00000400
#define	ADC_CALFACT_CALFACT_D_Pos   (16U)
#define	ADC_CALFACT_CALFACT_D_Msk   (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos)
	0x07FF0000
#define	ADC_CALFACT_CALFACT_D   ADC_CALFACT_CALFACT_D_Msk
	ADC calibration factors in differential mode.
#define	ADC_CALFACT_CALFACT_D_0   (0x001UL << ADC_CALFACT_CALFACT_D_Pos)
	0x00010000
#define	ADC_CALFACT_CALFACT_D_1   (0x002UL << ADC_CALFACT_CALFACT_D_Pos)
	0x00020000
#define	ADC_CALFACT_CALFACT_D_2   (0x004UL << ADC_CALFACT_CALFACT_D_Pos)
	0x00040000
#define	ADC_CALFACT_CALFACT_D_3   (0x008UL << ADC_CALFACT_CALFACT_D_Pos)
	0x00080000
#define	ADC_CALFACT_CALFACT_D_4   (0x010UL << ADC_CALFACT_CALFACT_D_Pos)
	0x00100000
#define	ADC_CALFACT_CALFACT_D_5   (0x020UL << ADC_CALFACT_CALFACT_D_Pos)
	0x00200000
#define	ADC_CALFACT_CALFACT_D_6   (0x040UL << ADC_CALFACT_CALFACT_D_Pos)
	0x00400000
#define	ADC_CALFACT_CALFACT_D_7   (0x080UL << ADC_CALFACT_CALFACT_D_Pos)
	0x00800000
#define	ADC_CALFACT_CALFACT_D_8   (0x100UL << ADC_CALFACT_CALFACT_D_Pos)
	0x01000000
#define	ADC_CALFACT_CALFACT_D_9   (0x200UL << ADC_CALFACT_CALFACT_D_Pos)
	0x02000000
#define	ADC_CALFACT_CALFACT_D_10   (0x400UL << ADC_CALFACT_CALFACT_D_Pos)
	0x04000000
#define	ADC_CALFACT2_LINCALFACT_Pos   (0U)
#define	ADC_CALFACT2_LINCALFACT_Msk   (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos)
	0x3FFFFFFF
#define	ADC_CALFACT2_LINCALFACT   ADC_CALFACT2_LINCALFACT_Msk
	ADC Linearity calibration factors.
#define	ADC_CALFACT2_LINCALFACT_0   (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x00000001
#define	ADC_CALFACT2_LINCALFACT_1   (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x00000002
#define	ADC_CALFACT2_LINCALFACT_2   (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x00000004
#define	ADC_CALFACT2_LINCALFACT_3   (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x00000008
#define	ADC_CALFACT2_LINCALFACT_4   (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x00000010
#define	ADC_CALFACT2_LINCALFACT_5   (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x00000020
#define	ADC_CALFACT2_LINCALFACT_6   (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x00000040
#define	ADC_CALFACT2_LINCALFACT_7   (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x00000080
#define	ADC_CALFACT2_LINCALFACT_8   (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x00000100
#define	ADC_CALFACT2_LINCALFACT_9   (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x00000200
#define	ADC_CALFACT2_LINCALFACT_10   (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x00000400
#define	ADC_CALFACT2_LINCALFACT_11   (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x00000800
#define	ADC_CALFACT2_LINCALFACT_12   (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x00001000
#define	ADC_CALFACT2_LINCALFACT_13   (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x00002000
#define	ADC_CALFACT2_LINCALFACT_14   (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x00004000
#define	ADC_CALFACT2_LINCALFACT_15   (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x00008000
#define	ADC_CALFACT2_LINCALFACT_16   (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x00010000
#define	ADC_CALFACT2_LINCALFACT_17   (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x00020000
#define	ADC_CALFACT2_LINCALFACT_18   (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x00040000
#define	ADC_CALFACT2_LINCALFACT_19   (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x00080000
#define	ADC_CALFACT2_LINCALFACT_20   (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x00100000
#define	ADC_CALFACT2_LINCALFACT_21   (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x00200000
#define	ADC_CALFACT2_LINCALFACT_22   (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x00400000
#define	ADC_CALFACT2_LINCALFACT_23   (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x00800000
#define	ADC_CALFACT2_LINCALFACT_24   (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x01000000
#define	ADC_CALFACT2_LINCALFACT_25   (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x02000000
#define	ADC_CALFACT2_LINCALFACT_26   (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x04000000
#define	ADC_CALFACT2_LINCALFACT_27   (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x08000000
#define	ADC_CALFACT2_LINCALFACT_28   (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x10000000
#define	ADC_CALFACT2_LINCALFACT_29   (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos)
	0x20000000
#define	ADC_CSR_ADRDY_MST_Pos   (0U)
#define	ADC_CSR_ADRDY_MST_Msk   (0x1UL << ADC_CSR_ADRDY_MST_Pos)
	0x00000001
#define	ADC_CSR_ADRDY_MST   ADC_CSR_ADRDY_MST_Msk
	Master ADC ready.
#define	ADC_CSR_EOSMP_MST_Pos   (1U)
#define	ADC_CSR_EOSMP_MST_Msk   (0x1UL << ADC_CSR_EOSMP_MST_Pos)
	0x00000002
#define	ADC_CSR_EOSMP_MST   ADC_CSR_EOSMP_MST_Msk
	End of sampling phase flag of the master ADC.
#define	ADC_CSR_EOC_MST_Pos   (2U)
#define	ADC_CSR_EOC_MST_Msk   (0x1UL << ADC_CSR_EOC_MST_Pos)
	0x00000004
#define	ADC_CSR_EOC_MST   ADC_CSR_EOC_MST_Msk
	End of regular conversion of the master ADC.
#define	ADC_CSR_EOS_MST_Pos   (3U)
#define	ADC_CSR_EOS_MST_Msk   (0x1UL << ADC_CSR_EOS_MST_Pos)
	0x00000008
#define	ADC_CSR_EOS_MST   ADC_CSR_EOS_MST_Msk
	End of regular sequence flag of the master ADC.
#define	ADC_CSR_OVR_MST_Pos   (4U)
#define	ADC_CSR_OVR_MST_Msk   (0x1UL << ADC_CSR_OVR_MST_Pos)
	0x00000010
#define	ADC_CSR_OVR_MST   ADC_CSR_OVR_MST_Msk
	Overrun flag of the master ADC.
#define	ADC_CSR_JEOC_MST_Pos   (5U)
#define	ADC_CSR_JEOC_MST_Msk   (0x1UL << ADC_CSR_JEOC_MST_Pos)
	0x00000020
#define	ADC_CSR_JEOC_MST   ADC_CSR_JEOC_MST_Msk
	End of injected conversion of the master ADC.
#define	ADC_CSR_JEOS_MST_Pos   (6U)
#define	ADC_CSR_JEOS_MST_Msk   (0x1UL << ADC_CSR_JEOS_MST_Pos)
	0x00000040
#define	ADC_CSR_JEOS_MST   ADC_CSR_JEOS_MST_Msk
	End of injected sequence flag of the master ADC.
#define	ADC_CSR_AWD1_MST_Pos   (7U)
#define	ADC_CSR_AWD1_MST_Msk   (0x1UL << ADC_CSR_AWD1_MST_Pos)
	0x00000080
#define	ADC_CSR_AWD1_MST   ADC_CSR_AWD1_MST_Msk
	Analog watchdog 1 flag of the master ADC.
#define	ADC_CSR_AWD2_MST_Pos   (8U)
#define	ADC_CSR_AWD2_MST_Msk   (0x1UL << ADC_CSR_AWD2_MST_Pos)
	0x00000100
#define	ADC_CSR_AWD2_MST   ADC_CSR_AWD2_MST_Msk
	Analog watchdog 2 flag of the master ADC.
#define	ADC_CSR_AWD3_MST_Pos   (9U)
#define	ADC_CSR_AWD3_MST_Msk   (0x1UL << ADC_CSR_AWD3_MST_Pos)
	0x00000200
#define	ADC_CSR_AWD3_MST   ADC_CSR_AWD3_MST_Msk
	Analog watchdog 3 flag of the master ADC.
#define	ADC_CSR_JQOVF_MST_Pos   (10U)
#define	ADC_CSR_JQOVF_MST_Msk   (0x1UL << ADC_CSR_JQOVF_MST_Pos)
	0x00000400
#define	ADC_CSR_JQOVF_MST   ADC_CSR_JQOVF_MST_Msk
	Injected context queue overflow flag of the master ADC.
#define	ADC_CSR_ADRDY_SLV_Pos   (16U)
#define	ADC_CSR_ADRDY_SLV_Msk   (0x1UL << ADC_CSR_ADRDY_SLV_Pos)
	0x00010000
#define	ADC_CSR_ADRDY_SLV   ADC_CSR_ADRDY_SLV_Msk
	Slave ADC ready.
#define	ADC_CSR_EOSMP_SLV_Pos   (17U)
#define	ADC_CSR_EOSMP_SLV_Msk   (0x1UL << ADC_CSR_EOSMP_SLV_Pos)
	0x00020000
#define	ADC_CSR_EOSMP_SLV   ADC_CSR_EOSMP_SLV_Msk
	End of sampling phase flag of the slave ADC.
#define	ADC_CSR_EOC_SLV_Pos   (18U)
#define	ADC_CSR_EOC_SLV_Msk   (0x1UL << ADC_CSR_EOC_SLV_Pos)
	0x00040000
#define	ADC_CSR_EOC_SLV   ADC_CSR_EOC_SLV_Msk
	End of regular conversion of the slave ADC.
#define	ADC_CSR_EOS_SLV_Pos   (19U)
#define	ADC_CSR_EOS_SLV_Msk   (0x1UL << ADC_CSR_EOS_SLV_Pos)
	0x00080000
#define	ADC_CSR_EOS_SLV   ADC_CSR_EOS_SLV_Msk
	End of regular sequence flag of the slave ADC.
#define	ADC_CSR_OVR_SLV_Pos   (20U)
#define	ADC_CSR_OVR_SLV_Msk   (0x1UL << ADC_CSR_OVR_SLV_Pos)
	0x00100000
#define	ADC_CSR_OVR_SLV   ADC_CSR_OVR_SLV_Msk
	Overrun flag of the slave ADC.
#define	ADC_CSR_JEOC_SLV_Pos   (21U)
#define	ADC_CSR_JEOC_SLV_Msk   (0x1UL << ADC_CSR_JEOC_SLV_Pos)
	0x00200000
#define	ADC_CSR_JEOC_SLV   ADC_CSR_JEOC_SLV_Msk
	End of injected conversion of the slave ADC.
#define	ADC_CSR_JEOS_SLV_Pos   (22U)
#define	ADC_CSR_JEOS_SLV_Msk   (0x1UL << ADC_CSR_JEOS_SLV_Pos)
	0x00400000
#define	ADC_CSR_JEOS_SLV   ADC_CSR_JEOS_SLV_Msk
	End of injected sequence flag of the slave ADC.
#define	ADC_CSR_AWD1_SLV_Pos   (23U)
#define	ADC_CSR_AWD1_SLV_Msk   (0x1UL << ADC_CSR_AWD1_SLV_Pos)
	0x00800000
#define	ADC_CSR_AWD1_SLV   ADC_CSR_AWD1_SLV_Msk
	Analog watchdog 1 flag of the slave ADC.
#define	ADC_CSR_AWD2_SLV_Pos   (24U)
#define	ADC_CSR_AWD2_SLV_Msk   (0x1UL << ADC_CSR_AWD2_SLV_Pos)
	0x01000000
#define	ADC_CSR_AWD2_SLV   ADC_CSR_AWD2_SLV_Msk
	Analog watchdog 2 flag of the slave ADC.
#define	ADC_CSR_AWD3_SLV_Pos   (25U)
#define	ADC_CSR_AWD3_SLV_Msk   (0x1UL << ADC_CSR_AWD3_SLV_Pos)
	0x02000000
#define	ADC_CSR_AWD3_SLV   ADC_CSR_AWD3_SLV_Msk
	Analog watchdog 3 flag of the slave ADC.
#define	ADC_CSR_JQOVF_SLV_Pos   (26U)
#define	ADC_CSR_JQOVF_SLV_Msk   (0x1UL << ADC_CSR_JQOVF_SLV_Pos)
	0x04000000
#define	ADC_CSR_JQOVF_SLV   ADC_CSR_JQOVF_SLV_Msk
	Injected context queue overflow flag of the slave ADC.
#define	ADC_CCR_DUAL_Pos   (0U)
#define	ADC_CCR_DUAL_Msk   (0x1FUL << ADC_CCR_DUAL_Pos)
	0x0000001F
#define	ADC_CCR_DUAL   ADC_CCR_DUAL_Msk
	Dual ADC mode selection.
#define	ADC_CCR_DUAL_0   (0x01UL << ADC_CCR_DUAL_Pos)
	0x00000001
#define	ADC_CCR_DUAL_1   (0x02UL << ADC_CCR_DUAL_Pos)
	0x00000002
#define	ADC_CCR_DUAL_2   (0x04UL << ADC_CCR_DUAL_Pos)
	0x00000004
#define	ADC_CCR_DUAL_3   (0x08UL << ADC_CCR_DUAL_Pos)
	0x00000008
#define	ADC_CCR_DUAL_4   (0x10UL << ADC_CCR_DUAL_Pos)
	0x00000010
#define	ADC_CCR_DELAY_Pos   (8U)
#define	ADC_CCR_DELAY_Msk   (0xFUL << ADC_CCR_DELAY_Pos)
	0x00000F00
#define	ADC_CCR_DELAY   ADC_CCR_DELAY_Msk
	Delay between 2 sampling phases.
#define	ADC_CCR_DELAY_0   (0x1UL << ADC_CCR_DELAY_Pos)
	0x00000100
#define	ADC_CCR_DELAY_1   (0x2UL << ADC_CCR_DELAY_Pos)
	0x00000200
#define	ADC_CCR_DELAY_2   (0x4UL << ADC_CCR_DELAY_Pos)
	0x00000400
#define	ADC_CCR_DELAY_3   (0x8UL << ADC_CCR_DELAY_Pos)
	0x00000800
#define	ADC_CCR_DAMDF_Pos   (14U)
#define	ADC_CCR_DAMDF_Msk   (0x3UL << ADC_CCR_DAMDF_Pos)
	0x0000C000
#define	ADC_CCR_DAMDF   ADC_CCR_DAMDF_Msk
	Dual ADC mode Data format.
#define	ADC_CCR_DAMDF_0   (0x1UL << ADC_CCR_DAMDF_Pos)
	0x00004000
#define	ADC_CCR_DAMDF_1   (0x2UL << ADC_CCR_DAMDF_Pos)
	0x00008000
#define	ADC_CCR_CKMODE_Pos   (16U)
#define	ADC_CCR_CKMODE_Msk   (0x3UL << ADC_CCR_CKMODE_Pos)
	0x00030000
#define	ADC_CCR_CKMODE   ADC_CCR_CKMODE_Msk
	ADC clock mode.
#define	ADC_CCR_CKMODE_0   (0x1UL << ADC_CCR_CKMODE_Pos)
	0x00010000
#define	ADC_CCR_CKMODE_1   (0x2UL << ADC_CCR_CKMODE_Pos)
	0x00020000
#define	ADC_CCR_PRESC_Pos   (18U)
#define	ADC_CCR_PRESC_Msk   (0xFUL << ADC_CCR_PRESC_Pos)
	0x003C0000
#define	ADC_CCR_PRESC   ADC_CCR_PRESC_Msk
	ADC prescaler.
#define	ADC_CCR_PRESC_0   (0x1UL << ADC_CCR_PRESC_Pos)
	0x00040000
#define	ADC_CCR_PRESC_1   (0x2UL << ADC_CCR_PRESC_Pos)
	0x00080000
#define	ADC_CCR_PRESC_2   (0x4UL << ADC_CCR_PRESC_Pos)
	0x00100000
#define	ADC_CCR_PRESC_3   (0x8UL << ADC_CCR_PRESC_Pos)
	0x00200000
#define	ADC_CCR_VREFEN_Pos   (22U)
#define	ADC_CCR_VREFEN_Msk   (0x1UL << ADC_CCR_VREFEN_Pos)
	0x00400000
#define	ADC_CCR_VREFEN   ADC_CCR_VREFEN_Msk
	VREFINT enable.
#define	ADC_CCR_TSEN_Pos   (23U)
#define	ADC_CCR_TSEN_Msk   (0x1UL << ADC_CCR_TSEN_Pos)
	0x00800000
#define	ADC_CCR_TSEN   ADC_CCR_TSEN_Msk
	Temperature sensor enable.
#define	ADC_CCR_VBATEN_Pos   (24U)
#define	ADC_CCR_VBATEN_Msk   (0x1UL << ADC_CCR_VBATEN_Pos)
	0x01000000
#define	ADC_CCR_VBATEN   ADC_CCR_VBATEN_Msk
	VBAT enable.
#define	ADC_CDR_RDATA_MST_Pos   (0U)
#define	ADC_CDR_RDATA_MST_Msk   (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)
	0x0000FFFF
#define	ADC_CDR_RDATA_MST   ADC_CDR_RDATA_MST_Msk
	ADC multimode master group regular conversion data.
#define	ADC_CDR_RDATA_SLV_Pos   (16U)
#define	ADC_CDR_RDATA_SLV_Msk   (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)
	0xFFFF0000
#define	ADC_CDR_RDATA_SLV   ADC_CDR_RDATA_SLV_Msk
	ADC multimode slave group regular conversion data.
#define	ADC_CDR2_RDATA_ALT_Pos   (0U)
#define	ADC_CDR2_RDATA_ALT_Msk   (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos)
	0xFFFFFFFF
#define	ADC_CDR2_RDATA_ALT   ADC_CDR2_RDATA_ALT_Msk
	Regular data of the master/slave alternated ADCs.
#define	VREFBUF_CSR_ENVR_Pos   (0U)
#define	VREFBUF_CSR_ENVR_Msk   (0x1UL << VREFBUF_CSR_ENVR_Pos)
	0x00000001
#define	VREFBUF_CSR_ENVR   VREFBUF_CSR_ENVR_Msk
	Voltage reference buffer enable.
#define	VREFBUF_CSR_HIZ_Pos   (1U)
#define	VREFBUF_CSR_HIZ_Msk   (0x1UL << VREFBUF_CSR_HIZ_Pos)
	0x00000002
#define	VREFBUF_CSR_HIZ   VREFBUF_CSR_HIZ_Msk
	High impedance mode.
#define	VREFBUF_CSR_VRR_Pos   (3U)
#define	VREFBUF_CSR_VRR_Msk   (0x1UL << VREFBUF_CSR_VRR_Pos)
	0x00000008
#define	VREFBUF_CSR_VRR   VREFBUF_CSR_VRR_Msk
	Voltage reference buffer ready.
#define	VREFBUF_CSR_VRS_Pos   (4U)
#define	VREFBUF_CSR_VRS_Msk   (0x7UL << VREFBUF_CSR_VRS_Pos)
	0x00000070
#define	VREFBUF_CSR_VRS   VREFBUF_CSR_VRS_Msk
	Voltage reference scale.
#define	VREFBUF_CSR_VRS_OUT1   (0U)
	Voltage reference VREF_OUT1.
#define	VREFBUF_CSR_VRS_OUT2_Pos   (4U)
#define	VREFBUF_CSR_VRS_OUT2_Msk   (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)
	0x00000010
#define	VREFBUF_CSR_VRS_OUT2   VREFBUF_CSR_VRS_OUT2_Msk
	Voltage reference VREF_OUT2.
#define	VREFBUF_CSR_VRS_OUT3_Pos   (5U)
#define	VREFBUF_CSR_VRS_OUT3_Msk   (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)
	0x00000020
#define	VREFBUF_CSR_VRS_OUT3   VREFBUF_CSR_VRS_OUT3_Msk
	Voltage reference VREF_OUT3.
#define	VREFBUF_CSR_VRS_OUT4_Pos   (4U)
#define	VREFBUF_CSR_VRS_OUT4_Msk   (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)
	0x00000030
#define	VREFBUF_CSR_VRS_OUT4   VREFBUF_CSR_VRS_OUT4_Msk
	Voltage reference VREF_OUT4.
#define	VREFBUF_CCR_TRIM_Pos   (0U)
#define	VREFBUF_CCR_TRIM_Msk   (0x3FUL << VREFBUF_CCR_TRIM_Pos)
	0x0000003F
#define	VREFBUF_CCR_TRIM   VREFBUF_CCR_TRIM_Msk
	TRIM[5:0] bits (Trimming code).
#define	FDCAN_CREL_DAY_Pos   (0U)
	<FDCAN control and status registers
#define	FDCAN_CREL_DAY_Msk   (0xFFUL << FDCAN_CREL_DAY_Pos)
	0x000000FF
#define	FDCAN_CREL_DAY   FDCAN_CREL_DAY_Msk
	Timestamp Day.
#define	FDCAN_CREL_MON_Pos   (8U)
#define	FDCAN_CREL_MON_Msk   (0xFFUL << FDCAN_CREL_MON_Pos)
	0x0000FF00
#define	FDCAN_CREL_MON   FDCAN_CREL_MON_Msk
	Timestamp Month.
#define	FDCAN_CREL_YEAR_Pos   (16U)
#define	FDCAN_CREL_YEAR_Msk   (0xFUL << FDCAN_CREL_YEAR_Pos)
	0x000F0000
#define	FDCAN_CREL_YEAR   FDCAN_CREL_YEAR_Msk
	Timestamp Year.
#define	FDCAN_CREL_SUBSTEP_Pos   (20U)
#define	FDCAN_CREL_SUBSTEP_Msk   (0xFUL << FDCAN_CREL_SUBSTEP_Pos)
	0x00F00000
#define	FDCAN_CREL_SUBSTEP   FDCAN_CREL_SUBSTEP_Msk
	Sub-step of Core release.
#define	FDCAN_CREL_STEP_Pos   (24U)
#define	FDCAN_CREL_STEP_Msk   (0xFUL << FDCAN_CREL_STEP_Pos)
	0x0F000000
#define	FDCAN_CREL_STEP   FDCAN_CREL_STEP_Msk
	Step of Core release.
#define	FDCAN_CREL_REL_Pos   (28U)
#define	FDCAN_CREL_REL_Msk   (0xFUL << FDCAN_CREL_REL_Pos)
	0xF0000000
#define	FDCAN_CREL_REL   FDCAN_CREL_REL_Msk
	Core release.
#define	FDCAN_ENDN_ETV_Pos   (0U)
#define	FDCAN_ENDN_ETV_Msk   (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)
	0xFFFFFFFF
#define	FDCAN_ENDN_ETV   FDCAN_ENDN_ETV_Msk
	Endianness Test Value.
#define	FDCAN_DBTP_DSJW_Pos   (0U)
#define	FDCAN_DBTP_DSJW_Msk   (0xFUL << FDCAN_DBTP_DSJW_Pos)
	0x0000000F
#define	FDCAN_DBTP_DSJW   FDCAN_DBTP_DSJW_Msk
	Synchronization Jump Width.
#define	FDCAN_DBTP_DTSEG2_Pos   (4U)
#define	FDCAN_DBTP_DTSEG2_Msk   (0xFUL << FDCAN_DBTP_DTSEG2_Pos)
	0x000000F0
#define	FDCAN_DBTP_DTSEG2   FDCAN_DBTP_DTSEG2_Msk
	Data time segment after sample point.
#define	FDCAN_DBTP_DTSEG1_Pos   (8U)
#define	FDCAN_DBTP_DTSEG1_Msk   (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)
	0x00001F00
#define	FDCAN_DBTP_DTSEG1   FDCAN_DBTP_DTSEG1_Msk
	Data time segment before sample point.
#define	FDCAN_DBTP_DBRP_Pos   (16U)
#define	FDCAN_DBTP_DBRP_Msk   (0x1FUL << FDCAN_DBTP_DBRP_Pos)
	0x001F0000
#define	FDCAN_DBTP_DBRP   FDCAN_DBTP_DBRP_Msk
	Data BIt Rate Prescaler.
#define	FDCAN_DBTP_TDC_Pos   (23U)
#define	FDCAN_DBTP_TDC_Msk   (0x1UL << FDCAN_DBTP_TDC_Pos)
	0x00800000
#define	FDCAN_DBTP_TDC   FDCAN_DBTP_TDC_Msk
	Transceiver Delay Compensation.
#define	FDCAN_TEST_LBCK_Pos   (4U)
#define	FDCAN_TEST_LBCK_Msk   (0x1UL << FDCAN_TEST_LBCK_Pos)
	0x00000010
#define	FDCAN_TEST_LBCK   FDCAN_TEST_LBCK_Msk
	Loop Back mode.
#define	FDCAN_TEST_TX_Pos   (5U)
#define	FDCAN_TEST_TX_Msk   (0x3UL << FDCAN_TEST_TX_Pos)
	0x00000060
#define	FDCAN_TEST_TX   FDCAN_TEST_TX_Msk
	Control of Transmit Pin.
#define	FDCAN_TEST_RX_Pos   (7U)
#define	FDCAN_TEST_RX_Msk   (0x1UL << FDCAN_TEST_RX_Pos)
	0x00000080
#define	FDCAN_TEST_RX   FDCAN_TEST_RX_Msk
	Receive Pin.
#define	FDCAN_RWD_WDC_Pos   (0U)
#define	FDCAN_RWD_WDC_Msk   (0xFFUL << FDCAN_RWD_WDC_Pos)
	0x000000FF
#define	FDCAN_RWD_WDC   FDCAN_RWD_WDC_Msk
	Watchdog configuration.
#define	FDCAN_RWD_WDV_Pos   (8U)
#define	FDCAN_RWD_WDV_Msk   (0xFFUL << FDCAN_RWD_WDV_Pos)
	0x0000FF00
#define	FDCAN_RWD_WDV   FDCAN_RWD_WDV_Msk
	Watchdog value.
#define	FDCAN_CCCR_INIT_Pos   (0U)
#define	FDCAN_CCCR_INIT_Msk   (0x1UL << FDCAN_CCCR_INIT_Pos)
	0x00000001
#define	FDCAN_CCCR_INIT   FDCAN_CCCR_INIT_Msk
	Initialization.
#define	FDCAN_CCCR_CCE_Pos   (1U)
#define	FDCAN_CCCR_CCE_Msk   (0x1UL << FDCAN_CCCR_CCE_Pos)
	0x00000002
#define	FDCAN_CCCR_CCE   FDCAN_CCCR_CCE_Msk
	Configuration Change Enable.
#define	FDCAN_CCCR_ASM_Pos   (2U)
#define	FDCAN_CCCR_ASM_Msk   (0x1UL << FDCAN_CCCR_ASM_Pos)
	0x00000004
#define	FDCAN_CCCR_ASM   FDCAN_CCCR_ASM_Msk
	ASM Restricted Operation Mode.
#define	FDCAN_CCCR_CSA_Pos   (3U)
#define	FDCAN_CCCR_CSA_Msk   (0x1UL << FDCAN_CCCR_CSA_Pos)
	0x00000008
#define	FDCAN_CCCR_CSA   FDCAN_CCCR_CSA_Msk
	Clock Stop Acknowledge.
#define	FDCAN_CCCR_CSR_Pos   (4U)
#define	FDCAN_CCCR_CSR_Msk   (0x1UL << FDCAN_CCCR_CSR_Pos)
	0x00000010
#define	FDCAN_CCCR_CSR   FDCAN_CCCR_CSR_Msk
	Clock Stop Request.
#define	FDCAN_CCCR_MON_Pos   (5U)
#define	FDCAN_CCCR_MON_Msk   (0x1UL << FDCAN_CCCR_MON_Pos)
	0x00000020
#define	FDCAN_CCCR_MON   FDCAN_CCCR_MON_Msk
	Bus Monitoring Mode.
#define	FDCAN_CCCR_DAR_Pos   (6U)
#define	FDCAN_CCCR_DAR_Msk   (0x1UL << FDCAN_CCCR_DAR_Pos)
	0x00000040
#define	FDCAN_CCCR_DAR   FDCAN_CCCR_DAR_Msk
	Disable Automatic Retransmission.
#define	FDCAN_CCCR_TEST_Pos   (7U)
#define	FDCAN_CCCR_TEST_Msk   (0x1UL << FDCAN_CCCR_TEST_Pos)
	0x00000080
#define	FDCAN_CCCR_TEST   FDCAN_CCCR_TEST_Msk
	Test Mode Enable.
#define	FDCAN_CCCR_FDOE_Pos   (8U)
#define	FDCAN_CCCR_FDOE_Msk   (0x1UL << FDCAN_CCCR_FDOE_Pos)
	0x00000100
#define	FDCAN_CCCR_FDOE   FDCAN_CCCR_FDOE_Msk
	FD Operation Enable.
#define	FDCAN_CCCR_BRSE_Pos   (9U)
#define	FDCAN_CCCR_BRSE_Msk   (0x1UL << FDCAN_CCCR_BRSE_Pos)
	0x00000200
#define	FDCAN_CCCR_BRSE   FDCAN_CCCR_BRSE_Msk
	FDCAN Bit Rate Switching.
#define	FDCAN_CCCR_PXHD_Pos   (12U)
#define	FDCAN_CCCR_PXHD_Msk   (0x1UL << FDCAN_CCCR_PXHD_Pos)
	0x00001000
#define	FDCAN_CCCR_PXHD   FDCAN_CCCR_PXHD_Msk
	Protocol Exception Handling Disable.
#define	FDCAN_CCCR_EFBI_Pos   (13U)
#define	FDCAN_CCCR_EFBI_Msk   (0x1UL << FDCAN_CCCR_EFBI_Pos)
	0x00002000
#define	FDCAN_CCCR_EFBI   FDCAN_CCCR_EFBI_Msk
	Edge Filtering during Bus Integration.
#define	FDCAN_CCCR_TXP_Pos   (14U)
#define	FDCAN_CCCR_TXP_Msk   (0x1UL << FDCAN_CCCR_TXP_Pos)
	0x00004000
#define	FDCAN_CCCR_TXP   FDCAN_CCCR_TXP_Msk
	Two CAN bit times Pause.
#define	FDCAN_CCCR_NISO_Pos   (15U)
#define	FDCAN_CCCR_NISO_Msk   (0x1UL << FDCAN_CCCR_NISO_Pos)
	0x00008000
#define	FDCAN_CCCR_NISO   FDCAN_CCCR_NISO_Msk
	Non ISO Operation.
#define	FDCAN_NBTP_NTSEG2_Pos   (0U)
#define	FDCAN_NBTP_NTSEG2_Msk   (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)
	0x0000007F
#define	FDCAN_NBTP_NTSEG2   FDCAN_NBTP_NTSEG2_Msk
	Nominal Time segment after sample point.
#define	FDCAN_NBTP_NTSEG1_Pos   (8U)
#define	FDCAN_NBTP_NTSEG1_Msk   (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)
	0x0000FF00
#define	FDCAN_NBTP_NTSEG1   FDCAN_NBTP_NTSEG1_Msk
	Nominal Time segment before sample point.
#define	FDCAN_NBTP_NBRP_Pos   (16U)
#define	FDCAN_NBTP_NBRP_Msk   (0x1FFUL << FDCAN_NBTP_NBRP_Pos)
	0x01FF0000
#define	FDCAN_NBTP_NBRP   FDCAN_NBTP_NBRP_Msk
	Bit Rate Prescaler.
#define	FDCAN_NBTP_NSJW_Pos   (25U)
#define	FDCAN_NBTP_NSJW_Msk   (0x7FUL << FDCAN_NBTP_NSJW_Pos)
	0xFE000000
#define	FDCAN_NBTP_NSJW   FDCAN_NBTP_NSJW_Msk
	Nominal (Re)Synchronization Jump Width.
#define	FDCAN_TSCC_TSS_Pos   (0U)
#define	FDCAN_TSCC_TSS_Msk   (0x3UL << FDCAN_TSCC_TSS_Pos)
	0x00000003
#define	FDCAN_TSCC_TSS   FDCAN_TSCC_TSS_Msk
	Timestamp Select.
#define	FDCAN_TSCC_TCP_Pos   (16U)
#define	FDCAN_TSCC_TCP_Msk   (0xFUL << FDCAN_TSCC_TCP_Pos)
	0x000F0000
#define	FDCAN_TSCC_TCP   FDCAN_TSCC_TCP_Msk
	Timestamp Counter Prescaler.
#define	FDCAN_TSCV_TSC_Pos   (0U)
#define	FDCAN_TSCV_TSC_Msk   (0xFFFFUL << FDCAN_TSCV_TSC_Pos)
	0x0000FFFF
#define	FDCAN_TSCV_TSC   FDCAN_TSCV_TSC_Msk
	Timestamp Counter.
#define	FDCAN_TOCC_ETOC_Pos   (0U)
#define	FDCAN_TOCC_ETOC_Msk   (0x1UL << FDCAN_TOCC_ETOC_Pos)
	0x00000001
#define	FDCAN_TOCC_ETOC   FDCAN_TOCC_ETOC_Msk
	Enable Timeout Counter.
#define	FDCAN_TOCC_TOS_Pos   (1U)
#define	FDCAN_TOCC_TOS_Msk   (0x3UL << FDCAN_TOCC_TOS_Pos)
	0x00000006
#define	FDCAN_TOCC_TOS   FDCAN_TOCC_TOS_Msk
	Timeout Select.
#define	FDCAN_TOCC_TOP_Pos   (16U)
#define	FDCAN_TOCC_TOP_Msk   (0xFFFFUL << FDCAN_TOCC_TOP_Pos)
	0xFFFF0000
#define	FDCAN_TOCC_TOP   FDCAN_TOCC_TOP_Msk
	Timeout Period.
#define	FDCAN_TOCV_TOC_Pos   (0U)
#define	FDCAN_TOCV_TOC_Msk   (0xFFFFUL << FDCAN_TOCV_TOC_Pos)
	0x0000FFFF
#define	FDCAN_TOCV_TOC   FDCAN_TOCV_TOC_Msk
	Timeout Counter.
#define	FDCAN_ECR_TEC_Pos   (0U)
#define	FDCAN_ECR_TEC_Msk   (0xFFUL << FDCAN_ECR_TEC_Pos)
	0x000000FF
#define	FDCAN_ECR_TEC   FDCAN_ECR_TEC_Msk
	Transmit Error Counter.
#define	FDCAN_ECR_REC_Pos   (8U)
#define	FDCAN_ECR_REC_Msk   (0x7FUL << FDCAN_ECR_REC_Pos)
	0x00007F00
#define	FDCAN_ECR_REC   FDCAN_ECR_REC_Msk
	Receive Error Counter.
#define	FDCAN_ECR_RP_Pos   (15U)
#define	FDCAN_ECR_RP_Msk   (0x1UL << FDCAN_ECR_RP_Pos)
	0x00008000
#define	FDCAN_ECR_RP   FDCAN_ECR_RP_Msk
	Receive Error Passive.
#define	FDCAN_ECR_CEL_Pos   (16U)
#define	FDCAN_ECR_CEL_Msk   (0xFFUL << FDCAN_ECR_CEL_Pos)
	0x00FF0000
#define	FDCAN_ECR_CEL   FDCAN_ECR_CEL_Msk
	CAN Error Logging.
#define	FDCAN_PSR_LEC_Pos   (0U)
#define	FDCAN_PSR_LEC_Msk   (0x7UL << FDCAN_PSR_LEC_Pos)
	0x00000007
#define	FDCAN_PSR_LEC   FDCAN_PSR_LEC_Msk
	Last Error Code.
#define	FDCAN_PSR_ACT_Pos   (3U)
#define	FDCAN_PSR_ACT_Msk   (0x3UL << FDCAN_PSR_ACT_Pos)
	0x00000018
#define	FDCAN_PSR_ACT   FDCAN_PSR_ACT_Msk
	Activity.
#define	FDCAN_PSR_EP_Pos   (5U)
#define	FDCAN_PSR_EP_Msk   (0x1UL << FDCAN_PSR_EP_Pos)
	0x00000020
#define	FDCAN_PSR_EP   FDCAN_PSR_EP_Msk
	Error Passive.
#define	FDCAN_PSR_EW_Pos   (6U)
#define	FDCAN_PSR_EW_Msk   (0x1UL << FDCAN_PSR_EW_Pos)
	0x00000040
#define	FDCAN_PSR_EW   FDCAN_PSR_EW_Msk
	Warning Status.
#define	FDCAN_PSR_BO_Pos   (7U)
#define	FDCAN_PSR_BO_Msk   (0x1UL << FDCAN_PSR_BO_Pos)
	0x00000080
#define	FDCAN_PSR_BO   FDCAN_PSR_BO_Msk
	Bus_Off Status.
#define	FDCAN_PSR_DLEC_Pos   (8U)
#define	FDCAN_PSR_DLEC_Msk   (0x7UL << FDCAN_PSR_DLEC_Pos)
	0x00000700
#define	FDCAN_PSR_DLEC   FDCAN_PSR_DLEC_Msk
	Data Last Error Code.
#define	FDCAN_PSR_RESI_Pos   (11U)
#define	FDCAN_PSR_RESI_Msk   (0x1UL << FDCAN_PSR_RESI_Pos)
	0x00000800
#define	FDCAN_PSR_RESI   FDCAN_PSR_RESI_Msk
	ESI flag of last received FDCAN Message.
#define	FDCAN_PSR_RBRS_Pos   (12U)
#define	FDCAN_PSR_RBRS_Msk   (0x1UL << FDCAN_PSR_RBRS_Pos)
	0x00001000
#define	FDCAN_PSR_RBRS   FDCAN_PSR_RBRS_Msk
	BRS flag of last received FDCAN Message.
#define	FDCAN_PSR_REDL_Pos   (13U)
#define	FDCAN_PSR_REDL_Msk   (0x1UL << FDCAN_PSR_REDL_Pos)
	0x00002000
#define	FDCAN_PSR_REDL   FDCAN_PSR_REDL_Msk
	Received FDCAN Message.
#define	FDCAN_PSR_PXE_Pos   (14U)
#define	FDCAN_PSR_PXE_Msk   (0x1UL << FDCAN_PSR_PXE_Pos)
	0x00004000
#define	FDCAN_PSR_PXE   FDCAN_PSR_PXE_Msk
	Protocol Exception Event.
#define	FDCAN_PSR_TDCV_Pos   (16U)
#define	FDCAN_PSR_TDCV_Msk   (0x7FUL << FDCAN_PSR_TDCV_Pos)
	0x007F0000
#define	FDCAN_PSR_TDCV   FDCAN_PSR_TDCV_Msk
	Transmitter Delay Compensation Value.
#define	FDCAN_TDCR_TDCF_Pos   (0U)
#define	FDCAN_TDCR_TDCF_Msk   (0x7FUL << FDCAN_TDCR_TDCF_Pos)
	0x0000007F
#define	FDCAN_TDCR_TDCF   FDCAN_TDCR_TDCF_Msk
	Transmitter Delay Compensation Filter.
#define	FDCAN_TDCR_TDCO_Pos   (8U)
#define	FDCAN_TDCR_TDCO_Msk   (0x7FUL << FDCAN_TDCR_TDCO_Pos)
	0x00007F00
#define	FDCAN_TDCR_TDCO   FDCAN_TDCR_TDCO_Msk
	Transmitter Delay Compensation Offset.
#define	FDCAN_IR_RF0N_Pos   (0U)
#define	FDCAN_IR_RF0N_Msk   (0x1UL << FDCAN_IR_RF0N_Pos)
	0x00000001
#define	FDCAN_IR_RF0N   FDCAN_IR_RF0N_Msk
	Rx FIFO 0 New Message.
#define	FDCAN_IR_RF0W_Pos   (1U)
#define	FDCAN_IR_RF0W_Msk   (0x1UL << FDCAN_IR_RF0W_Pos)
	0x00000002
#define	FDCAN_IR_RF0W   FDCAN_IR_RF0W_Msk
	Rx FIFO 0 Watermark Reached.
#define	FDCAN_IR_RF0F_Pos   (2U)
#define	FDCAN_IR_RF0F_Msk   (0x1UL << FDCAN_IR_RF0F_Pos)
	0x00000004
#define	FDCAN_IR_RF0F   FDCAN_IR_RF0F_Msk
	Rx FIFO 0 Full.
#define	FDCAN_IR_RF0L_Pos   (3U)
#define	FDCAN_IR_RF0L_Msk   (0x1UL << FDCAN_IR_RF0L_Pos)
	0x00000008
#define	FDCAN_IR_RF0L   FDCAN_IR_RF0L_Msk
	Rx FIFO 0 Message Lost.
#define	FDCAN_IR_RF1N_Pos   (4U)
#define	FDCAN_IR_RF1N_Msk   (0x1UL << FDCAN_IR_RF1N_Pos)
	0x00000010
#define	FDCAN_IR_RF1N   FDCAN_IR_RF1N_Msk
	Rx FIFO 1 New Message.
#define	FDCAN_IR_RF1W_Pos   (5U)
#define	FDCAN_IR_RF1W_Msk   (0x1UL << FDCAN_IR_RF1W_Pos)
	0x00000020
#define	FDCAN_IR_RF1W   FDCAN_IR_RF1W_Msk
	Rx FIFO 1 Watermark Reached.
#define	FDCAN_IR_RF1F_Pos   (6U)
#define	FDCAN_IR_RF1F_Msk   (0x1UL << FDCAN_IR_RF1F_Pos)
	0x00000040
#define	FDCAN_IR_RF1F   FDCAN_IR_RF1F_Msk
	Rx FIFO 1 Full.
#define	FDCAN_IR_RF1L_Pos   (7U)
#define	FDCAN_IR_RF1L_Msk   (0x1UL << FDCAN_IR_RF1L_Pos)
	0x00000080
#define	FDCAN_IR_RF1L   FDCAN_IR_RF1L_Msk
	Rx FIFO 1 Message Lost.
#define	FDCAN_IR_HPM_Pos   (8U)
#define	FDCAN_IR_HPM_Msk   (0x1UL << FDCAN_IR_HPM_Pos)
	0x00000100
#define	FDCAN_IR_HPM   FDCAN_IR_HPM_Msk
	High Priority Message.
#define	FDCAN_IR_TC_Pos   (9U)
#define	FDCAN_IR_TC_Msk   (0x1UL << FDCAN_IR_TC_Pos)
	0x00000200
#define	FDCAN_IR_TC   FDCAN_IR_TC_Msk
	Transmission Completed.
#define	FDCAN_IR_TCF_Pos   (10U)
#define	FDCAN_IR_TCF_Msk   (0x1UL << FDCAN_IR_TCF_Pos)
	0x00000400
#define	FDCAN_IR_TCF   FDCAN_IR_TCF_Msk
	Transmission Cancellation Finished.
#define	FDCAN_IR_TFE_Pos   (11U)
#define	FDCAN_IR_TFE_Msk   (0x1UL << FDCAN_IR_TFE_Pos)
	0x00000800
#define	FDCAN_IR_TFE   FDCAN_IR_TFE_Msk
	Tx FIFO Empty.
#define	FDCAN_IR_TEFN_Pos   (12U)
#define	FDCAN_IR_TEFN_Msk   (0x1UL << FDCAN_IR_TEFN_Pos)
	0x00001000
#define	FDCAN_IR_TEFN   FDCAN_IR_TEFN_Msk
	Tx Event FIFO New Entry.
#define	FDCAN_IR_TEFW_Pos   (13U)
#define	FDCAN_IR_TEFW_Msk   (0x1UL << FDCAN_IR_TEFW_Pos)
	0x00002000
#define	FDCAN_IR_TEFW   FDCAN_IR_TEFW_Msk
	Tx Event FIFO Watermark Reached.
#define	FDCAN_IR_TEFF_Pos   (14U)
#define	FDCAN_IR_TEFF_Msk   (0x1UL << FDCAN_IR_TEFF_Pos)
	0x00004000
#define	FDCAN_IR_TEFF   FDCAN_IR_TEFF_Msk
	Tx Event FIFO Full.
#define	FDCAN_IR_TEFL_Pos   (15U)
#define	FDCAN_IR_TEFL_Msk   (0x1UL << FDCAN_IR_TEFL_Pos)
	0x00008000
#define	FDCAN_IR_TEFL   FDCAN_IR_TEFL_Msk
	Tx Event FIFO Element Lost.
#define	FDCAN_IR_TSW_Pos   (16U)
#define	FDCAN_IR_TSW_Msk   (0x1UL << FDCAN_IR_TSW_Pos)
	0x00010000
#define	FDCAN_IR_TSW   FDCAN_IR_TSW_Msk
	Timestamp Wraparound.
#define	FDCAN_IR_MRAF_Pos   (17U)
#define	FDCAN_IR_MRAF_Msk   (0x1UL << FDCAN_IR_MRAF_Pos)
	0x00020000
#define	FDCAN_IR_MRAF   FDCAN_IR_MRAF_Msk
	Message RAM Access Failure.
#define	FDCAN_IR_TOO_Pos   (18U)
#define	FDCAN_IR_TOO_Msk   (0x1UL << FDCAN_IR_TOO_Pos)
	0x00040000
#define	FDCAN_IR_TOO   FDCAN_IR_TOO_Msk
	Timeout Occurred.
#define	FDCAN_IR_DRX_Pos   (19U)
#define	FDCAN_IR_DRX_Msk   (0x1UL << FDCAN_IR_DRX_Pos)
	0x00080000
#define	FDCAN_IR_DRX   FDCAN_IR_DRX_Msk
	Message stored to Dedicated Rx Buffer.
#define	FDCAN_IR_ELO_Pos   (22U)
#define	FDCAN_IR_ELO_Msk   (0x1UL << FDCAN_IR_ELO_Pos)
	0x00400000
#define	FDCAN_IR_ELO   FDCAN_IR_ELO_Msk
	Error Logging Overflow.
#define	FDCAN_IR_EP_Pos   (23U)
#define	FDCAN_IR_EP_Msk   (0x1UL << FDCAN_IR_EP_Pos)
	0x00800000
#define	FDCAN_IR_EP   FDCAN_IR_EP_Msk
	Error Passive.
#define	FDCAN_IR_EW_Pos   (24U)
#define	FDCAN_IR_EW_Msk   (0x1UL << FDCAN_IR_EW_Pos)
	0x01000000
#define	FDCAN_IR_EW   FDCAN_IR_EW_Msk
	Warning Status.
#define	FDCAN_IR_BO_Pos   (25U)
#define	FDCAN_IR_BO_Msk   (0x1UL << FDCAN_IR_BO_Pos)
	0x02000000
#define	FDCAN_IR_BO   FDCAN_IR_BO_Msk
	Bus_Off Status.
#define	FDCAN_IR_WDI_Pos   (26U)
#define	FDCAN_IR_WDI_Msk   (0x1UL << FDCAN_IR_WDI_Pos)
	0x04000000
#define	FDCAN_IR_WDI   FDCAN_IR_WDI_Msk
	Watchdog Interrupt.
#define	FDCAN_IR_PEA_Pos   (27U)
#define	FDCAN_IR_PEA_Msk   (0x1UL << FDCAN_IR_PEA_Pos)
	0x08000000
#define	FDCAN_IR_PEA   FDCAN_IR_PEA_Msk
	Protocol Error in Arbitration Phase.
#define	FDCAN_IR_PED_Pos   (28U)
#define	FDCAN_IR_PED_Msk   (0x1UL << FDCAN_IR_PED_Pos)
	0x10000000
#define	FDCAN_IR_PED   FDCAN_IR_PED_Msk
	Protocol Error in Data Phase.
#define	FDCAN_IR_ARA_Pos   (29U)
#define	FDCAN_IR_ARA_Msk   (0x1UL << FDCAN_IR_ARA_Pos)
	0x20000000
#define	FDCAN_IR_ARA   FDCAN_IR_ARA_Msk
	Access to Reserved Address.
#define	FDCAN_IE_RF0NE_Pos   (0U)
#define	FDCAN_IE_RF0NE_Msk   (0x1UL << FDCAN_IE_RF0NE_Pos)
	0x00000001
#define	FDCAN_IE_RF0NE   FDCAN_IE_RF0NE_Msk
	Rx FIFO 0 New Message Enable.
#define	FDCAN_IE_RF0WE_Pos   (1U)
#define	FDCAN_IE_RF0WE_Msk   (0x1UL << FDCAN_IE_RF0WE_Pos)
	0x00000002
#define	FDCAN_IE_RF0WE   FDCAN_IE_RF0WE_Msk
	Rx FIFO 0 Watermark Reached Enable.
#define	FDCAN_IE_RF0FE_Pos   (2U)
#define	FDCAN_IE_RF0FE_Msk   (0x1UL << FDCAN_IE_RF0FE_Pos)
	0x00000004
#define	FDCAN_IE_RF0FE   FDCAN_IE_RF0FE_Msk
	Rx FIFO 0 Full Enable.
#define	FDCAN_IE_RF0LE_Pos   (3U)
#define	FDCAN_IE_RF0LE_Msk   (0x1UL << FDCAN_IE_RF0LE_Pos)
	0x00000008
#define	FDCAN_IE_RF0LE   FDCAN_IE_RF0LE_Msk
	Rx FIFO 0 Message Lost Enable.
#define	FDCAN_IE_RF1NE_Pos   (4U)
#define	FDCAN_IE_RF1NE_Msk   (0x1UL << FDCAN_IE_RF1NE_Pos)
	0x00000010
#define	FDCAN_IE_RF1NE   FDCAN_IE_RF1NE_Msk
	Rx FIFO 1 New Message Enable.
#define	FDCAN_IE_RF1WE_Pos   (5U)
#define	FDCAN_IE_RF1WE_Msk   (0x1UL << FDCAN_IE_RF1WE_Pos)
	0x00000020
#define	FDCAN_IE_RF1WE   FDCAN_IE_RF1WE_Msk
	Rx FIFO 1 Watermark Reached Enable.
#define	FDCAN_IE_RF1FE_Pos   (6U)
#define	FDCAN_IE_RF1FE_Msk   (0x1UL << FDCAN_IE_RF1FE_Pos)
	0x00000040
#define	FDCAN_IE_RF1FE   FDCAN_IE_RF1FE_Msk
	Rx FIFO 1 Full Enable.
#define	FDCAN_IE_RF1LE_Pos   (7U)
#define	FDCAN_IE_RF1LE_Msk   (0x1UL << FDCAN_IE_RF1LE_Pos)
	0x00000080
#define	FDCAN_IE_RF1LE   FDCAN_IE_RF1LE_Msk
	Rx FIFO 1 Message Lost Enable.
#define	FDCAN_IE_HPME_Pos   (8U)
#define	FDCAN_IE_HPME_Msk   (0x1UL << FDCAN_IE_HPME_Pos)
	0x00000100
#define	FDCAN_IE_HPME   FDCAN_IE_HPME_Msk
	High Priority Message Enable.
#define	FDCAN_IE_TCE_Pos   (9U)
#define	FDCAN_IE_TCE_Msk   (0x1UL << FDCAN_IE_TCE_Pos)
	0x00000200
#define	FDCAN_IE_TCE   FDCAN_IE_TCE_Msk
	Transmission Completed Enable.
#define	FDCAN_IE_TCFE_Pos   (10U)
#define	FDCAN_IE_TCFE_Msk   (0x1UL << FDCAN_IE_TCFE_Pos)
	0x00000400
#define	FDCAN_IE_TCFE   FDCAN_IE_TCFE_Msk
	Transmission Cancellation Finished Enable.
#define	FDCAN_IE_TFEE_Pos   (11U)
#define	FDCAN_IE_TFEE_Msk   (0x1UL << FDCAN_IE_TFEE_Pos)
	0x00000800
#define	FDCAN_IE_TFEE   FDCAN_IE_TFEE_Msk
	Tx FIFO Empty Enable.
#define	FDCAN_IE_TEFNE_Pos   (12U)
#define	FDCAN_IE_TEFNE_Msk   (0x1UL << FDCAN_IE_TEFNE_Pos)
	0x00001000
#define	FDCAN_IE_TEFNE   FDCAN_IE_TEFNE_Msk
	Tx Event FIFO New Entry Enable.
#define	FDCAN_IE_TEFWE_Pos   (13U)
#define	FDCAN_IE_TEFWE_Msk   (0x1UL << FDCAN_IE_TEFWE_Pos)
	0x00002000
#define	FDCAN_IE_TEFWE   FDCAN_IE_TEFWE_Msk
	Tx Event FIFO Watermark Reached Enable.
#define	FDCAN_IE_TEFFE_Pos   (14U)
#define	FDCAN_IE_TEFFE_Msk   (0x1UL << FDCAN_IE_TEFFE_Pos)
	0x00004000
#define	FDCAN_IE_TEFFE   FDCAN_IE_TEFFE_Msk
	Tx Event FIFO Full Enable.
#define	FDCAN_IE_TEFLE_Pos   (15U)
#define	FDCAN_IE_TEFLE_Msk   (0x1UL << FDCAN_IE_TEFLE_Pos)
	0x00008000
#define	FDCAN_IE_TEFLE   FDCAN_IE_TEFLE_Msk
	Tx Event FIFO Element Lost Enable.
#define	FDCAN_IE_TSWE_Pos   (16U)
#define	FDCAN_IE_TSWE_Msk   (0x1UL << FDCAN_IE_TSWE_Pos)
	0x00010000
#define	FDCAN_IE_TSWE   FDCAN_IE_TSWE_Msk
	Timestamp Wraparound Enable.
#define	FDCAN_IE_MRAFE_Pos   (17U)
#define	FDCAN_IE_MRAFE_Msk   (0x1UL << FDCAN_IE_MRAFE_Pos)
	0x00020000
#define	FDCAN_IE_MRAFE   FDCAN_IE_MRAFE_Msk
	Message RAM Access Failure Enable.
#define	FDCAN_IE_TOOE_Pos   (18U)
#define	FDCAN_IE_TOOE_Msk   (0x1UL << FDCAN_IE_TOOE_Pos)
	0x00040000
#define	FDCAN_IE_TOOE   FDCAN_IE_TOOE_Msk
	Timeout Occurred Enable.
#define	FDCAN_IE_DRXE_Pos   (19U)
#define	FDCAN_IE_DRXE_Msk   (0x1UL << FDCAN_IE_DRXE_Pos)
	0x00080000
#define	FDCAN_IE_DRXE   FDCAN_IE_DRXE_Msk
	Message stored to Dedicated Rx Buffer Enable.
#define	FDCAN_IE_BECE_Pos   (20U)
#define	FDCAN_IE_BECE_Msk   (0x1UL << FDCAN_IE_BECE_Pos)
	0x00100000
#define	FDCAN_IE_BECE   FDCAN_IE_BECE_Msk
	Bit Error Corrected Interrupt Enable.
#define	FDCAN_IE_BEUE_Pos   (21U)
#define	FDCAN_IE_BEUE_Msk   (0x1UL << FDCAN_IE_BEUE_Pos)
	0x00200000
#define	FDCAN_IE_BEUE   FDCAN_IE_BEUE_Msk
	Bit Error Uncorrected Interrupt Enable.
#define	FDCAN_IE_ELOE_Pos   (22U)
#define	FDCAN_IE_ELOE_Msk   (0x1UL << FDCAN_IE_ELOE_Pos)
	0x00400000
#define	FDCAN_IE_ELOE   FDCAN_IE_ELOE_Msk
	Error Logging Overflow Enable.
#define	FDCAN_IE_EPE_Pos   (23U)
#define	FDCAN_IE_EPE_Msk   (0x1UL << FDCAN_IE_EPE_Pos)
	0x00800000
#define	FDCAN_IE_EPE   FDCAN_IE_EPE_Msk
	Error Passive Enable.
#define	FDCAN_IE_EWE_Pos   (24U)
#define	FDCAN_IE_EWE_Msk   (0x1UL << FDCAN_IE_EWE_Pos)
	0x01000000
#define	FDCAN_IE_EWE   FDCAN_IE_EWE_Msk
	Warning Status Enable.
#define	FDCAN_IE_BOE_Pos   (25U)
#define	FDCAN_IE_BOE_Msk   (0x1UL << FDCAN_IE_BOE_Pos)
	0x02000000
#define	FDCAN_IE_BOE   FDCAN_IE_BOE_Msk
	Bus_Off Status Enable.
#define	FDCAN_IE_WDIE_Pos   (26U)
#define	FDCAN_IE_WDIE_Msk   (0x1UL << FDCAN_IE_WDIE_Pos)
	0x04000000
#define	FDCAN_IE_WDIE   FDCAN_IE_WDIE_Msk
	Watchdog Interrupt Enable.
#define	FDCAN_IE_PEAE_Pos   (27U)
#define	FDCAN_IE_PEAE_Msk   (0x1UL << FDCAN_IE_PEAE_Pos)
	0x08000000
#define	FDCAN_IE_PEAE   FDCAN_IE_PEAE_Msk
	Protocol Error in Arbitration Phase Enable.
#define	FDCAN_IE_PEDE_Pos   (28U)
#define	FDCAN_IE_PEDE_Msk   (0x1UL << FDCAN_IE_PEDE_Pos)
	0x10000000
#define	FDCAN_IE_PEDE   FDCAN_IE_PEDE_Msk
	Protocol Error in Data Phase Enable.
#define	FDCAN_IE_ARAE_Pos   (29U)
#define	FDCAN_IE_ARAE_Msk   (0x1UL << FDCAN_IE_ARAE_Pos)
	0x20000000
#define	FDCAN_IE_ARAE   FDCAN_IE_ARAE_Msk
	Access to Reserved Address Enable.
#define	FDCAN_ILS_RF0NL_Pos   (0U)
#define	FDCAN_ILS_RF0NL_Msk   (0x1UL << FDCAN_ILS_RF0NL_Pos)
	0x00000001
#define	FDCAN_ILS_RF0NL   FDCAN_ILS_RF0NL_Msk
	Rx FIFO 0 New Message Line.
#define	FDCAN_ILS_RF0WL_Pos   (1U)
#define	FDCAN_ILS_RF0WL_Msk   (0x1UL << FDCAN_ILS_RF0WL_Pos)
	0x00000002
#define	FDCAN_ILS_RF0WL   FDCAN_ILS_RF0WL_Msk
	Rx FIFO 0 Watermark Reached Line.
#define	FDCAN_ILS_RF0FL_Pos   (2U)
#define	FDCAN_ILS_RF0FL_Msk   (0x1UL << FDCAN_ILS_RF0FL_Pos)
	0x00000004
#define	FDCAN_ILS_RF0FL   FDCAN_ILS_RF0FL_Msk
	Rx FIFO 0 Full Line.
#define	FDCAN_ILS_RF0LL_Pos   (3U)
#define	FDCAN_ILS_RF0LL_Msk   (0x1UL << FDCAN_ILS_RF0LL_Pos)
	0x00000008
#define	FDCAN_ILS_RF0LL   FDCAN_ILS_RF0LL_Msk
	Rx FIFO 0 Message Lost Line.
#define	FDCAN_ILS_RF1NL_Pos   (4U)
#define	FDCAN_ILS_RF1NL_Msk   (0x1UL << FDCAN_ILS_RF1NL_Pos)
	0x00000010
#define	FDCAN_ILS_RF1NL   FDCAN_ILS_RF1NL_Msk
	Rx FIFO 1 New Message Line.
#define	FDCAN_ILS_RF1WL_Pos   (5U)
#define	FDCAN_ILS_RF1WL_Msk   (0x1UL << FDCAN_ILS_RF1WL_Pos)
	0x00000020
#define	FDCAN_ILS_RF1WL   FDCAN_ILS_RF1WL_Msk
	Rx FIFO 1 Watermark Reached Line.
#define	FDCAN_ILS_RF1FL_Pos   (6U)
#define	FDCAN_ILS_RF1FL_Msk   (0x1UL << FDCAN_ILS_RF1FL_Pos)
	0x00000040
#define	FDCAN_ILS_RF1FL   FDCAN_ILS_RF1FL_Msk
	Rx FIFO 1 Full Line.
#define	FDCAN_ILS_RF1LL_Pos   (7U)
#define	FDCAN_ILS_RF1LL_Msk   (0x1UL << FDCAN_ILS_RF1LL_Pos)
	0x00000080
#define	FDCAN_ILS_RF1LL   FDCAN_ILS_RF1LL_Msk
	Rx FIFO 1 Message Lost Line.
#define	FDCAN_ILS_HPML_Pos   (8U)
#define	FDCAN_ILS_HPML_Msk   (0x1UL << FDCAN_ILS_HPML_Pos)
	0x00000100
#define	FDCAN_ILS_HPML   FDCAN_ILS_HPML_Msk
	High Priority Message Line.
#define	FDCAN_ILS_TCL_Pos   (9U)
#define	FDCAN_ILS_TCL_Msk   (0x1UL << FDCAN_ILS_TCL_Pos)
	0x00000200
#define	FDCAN_ILS_TCL   FDCAN_ILS_TCL_Msk
	Transmission Completed Line.
#define	FDCAN_ILS_TCFL_Pos   (10U)
#define	FDCAN_ILS_TCFL_Msk   (0x1UL << FDCAN_ILS_TCFL_Pos)
	0x00000400
#define	FDCAN_ILS_TCFL   FDCAN_ILS_TCFL_Msk
	Transmission Cancellation Finished Line.
#define	FDCAN_ILS_TFEL_Pos   (11U)
#define	FDCAN_ILS_TFEL_Msk   (0x1UL << FDCAN_ILS_TFEL_Pos)
	0x00000800
#define	FDCAN_ILS_TFEL   FDCAN_ILS_TFEL_Msk
	Tx FIFO Empty Line.
#define	FDCAN_ILS_TEFNL_Pos   (12U)
#define	FDCAN_ILS_TEFNL_Msk   (0x1UL << FDCAN_ILS_TEFNL_Pos)
	0x00001000
#define	FDCAN_ILS_TEFNL   FDCAN_ILS_TEFNL_Msk
	Tx Event FIFO New Entry Line.
#define	FDCAN_ILS_TEFWL_Pos   (13U)
#define	FDCAN_ILS_TEFWL_Msk   (0x1UL << FDCAN_ILS_TEFWL_Pos)
	0x00002000
#define	FDCAN_ILS_TEFWL   FDCAN_ILS_TEFWL_Msk
	Tx Event FIFO Watermark Reached Line.
#define	FDCAN_ILS_TEFFL_Pos   (14U)
#define	FDCAN_ILS_TEFFL_Msk   (0x1UL << FDCAN_ILS_TEFFL_Pos)
	0x00004000
#define	FDCAN_ILS_TEFFL   FDCAN_ILS_TEFFL_Msk
	Tx Event FIFO Full Line.
#define	FDCAN_ILS_TEFLL_Pos   (15U)
#define	FDCAN_ILS_TEFLL_Msk   (0x1UL << FDCAN_ILS_TEFLL_Pos)
	0x00008000
#define	FDCAN_ILS_TEFLL   FDCAN_ILS_TEFLL_Msk
	Tx Event FIFO Element Lost Line.
#define	FDCAN_ILS_TSWL_Pos   (16U)
#define	FDCAN_ILS_TSWL_Msk   (0x1UL << FDCAN_ILS_TSWL_Pos)
	0x00010000
#define	FDCAN_ILS_TSWL   FDCAN_ILS_TSWL_Msk
	Timestamp Wraparound Line.
#define	FDCAN_ILS_MRAFE_Pos   (17U)
#define	FDCAN_ILS_MRAFE_Msk   (0x1UL << FDCAN_ILS_MRAFE_Pos)
	0x00020000
#define	FDCAN_ILS_MRAFE   FDCAN_ILS_MRAFE_Msk
	Message RAM Access Failure Line.
#define	FDCAN_ILS_TOOE_Pos   (18U)
#define	FDCAN_ILS_TOOE_Msk   (0x1UL << FDCAN_ILS_TOOE_Pos)
	0x00040000
#define	FDCAN_ILS_TOOE   FDCAN_ILS_TOOE_Msk
	Timeout Occurred Line.
#define	FDCAN_ILS_DRXE_Pos   (19U)
#define	FDCAN_ILS_DRXE_Msk   (0x1UL << FDCAN_ILS_DRXE_Pos)
	0x00080000
#define	FDCAN_ILS_DRXE   FDCAN_ILS_DRXE_Msk
	Message stored to Dedicated Rx Buffer Line.
#define	FDCAN_ILS_BECE_Pos   (20U)
#define	FDCAN_ILS_BECE_Msk   (0x1UL << FDCAN_ILS_BECE_Pos)
	0x00100000
#define	FDCAN_ILS_BECE   FDCAN_ILS_BECE_Msk
	Bit Error Corrected Interrupt Line.
#define	FDCAN_ILS_BEUE_Pos   (21U)
#define	FDCAN_ILS_BEUE_Msk   (0x1UL << FDCAN_ILS_BEUE_Pos)
	0x00200000
#define	FDCAN_ILS_BEUE   FDCAN_ILS_BEUE_Msk
	Bit Error Uncorrected Interrupt Line.
#define	FDCAN_ILS_ELOE_Pos   (22U)
#define	FDCAN_ILS_ELOE_Msk   (0x1UL << FDCAN_ILS_ELOE_Pos)
	0x00400000
#define	FDCAN_ILS_ELOE   FDCAN_ILS_ELOE_Msk
	Error Logging Overflow Line.
#define	FDCAN_ILS_EPE_Pos   (23U)
#define	FDCAN_ILS_EPE_Msk   (0x1UL << FDCAN_ILS_EPE_Pos)
	0x00800000
#define	FDCAN_ILS_EPE   FDCAN_ILS_EPE_Msk
	Error Passive Line.
#define	FDCAN_ILS_EWE_Pos   (24U)
#define	FDCAN_ILS_EWE_Msk   (0x1UL << FDCAN_ILS_EWE_Pos)
	0x01000000
#define	FDCAN_ILS_EWE   FDCAN_ILS_EWE_Msk
	Warning Status Line.
#define	FDCAN_ILS_BOE_Pos   (25U)
#define	FDCAN_ILS_BOE_Msk   (0x1UL << FDCAN_ILS_BOE_Pos)
	0x02000000
#define	FDCAN_ILS_BOE   FDCAN_ILS_BOE_Msk
	Bus_Off Status Line.
#define	FDCAN_ILS_WDIE_Pos   (26U)
#define	FDCAN_ILS_WDIE_Msk   (0x1UL << FDCAN_ILS_WDIE_Pos)
	0x04000000
#define	FDCAN_ILS_WDIE   FDCAN_ILS_WDIE_Msk
	Watchdog Interrupt Line.
#define	FDCAN_ILS_PEAE_Pos   (27U)
#define	FDCAN_ILS_PEAE_Msk   (0x1UL << FDCAN_ILS_PEAE_Pos)
	0x08000000
#define	FDCAN_ILS_PEAE   FDCAN_ILS_PEAE_Msk
	Protocol Error in Arbitration Phase Line.
#define	FDCAN_ILS_PEDE_Pos   (28U)
#define	FDCAN_ILS_PEDE_Msk   (0x1UL << FDCAN_ILS_PEDE_Pos)
	0x10000000
#define	FDCAN_ILS_PEDE   FDCAN_ILS_PEDE_Msk
	Protocol Error in Data Phase Line.
#define	FDCAN_ILS_ARAE_Pos   (29U)
#define	FDCAN_ILS_ARAE_Msk   (0x1UL << FDCAN_ILS_ARAE_Pos)
	0x20000000
#define	FDCAN_ILS_ARAE   FDCAN_ILS_ARAE_Msk
	Access to Reserved Address Line.
#define	FDCAN_ILE_EINT0_Pos   (0U)
#define	FDCAN_ILE_EINT0_Msk   (0x1UL << FDCAN_ILE_EINT0_Pos)
	0x00000001
#define	FDCAN_ILE_EINT0   FDCAN_ILE_EINT0_Msk
	Enable Interrupt Line 0.
#define	FDCAN_ILE_EINT1_Pos   (1U)
#define	FDCAN_ILE_EINT1_Msk   (0x1UL << FDCAN_ILE_EINT1_Pos)
	0x00000002
#define	FDCAN_ILE_EINT1   FDCAN_ILE_EINT1_Msk
	Enable Interrupt Line 1.
#define	FDCAN_GFC_RRFE_Pos   (0U)
#define	FDCAN_GFC_RRFE_Msk   (0x1UL << FDCAN_GFC_RRFE_Pos)
	0x00000001
#define	FDCAN_GFC_RRFE   FDCAN_GFC_RRFE_Msk
	Reject Remote Frames Extended.
#define	FDCAN_GFC_RRFS_Pos   (1U)
#define	FDCAN_GFC_RRFS_Msk   (0x1UL << FDCAN_GFC_RRFS_Pos)
	0x00000002
#define	FDCAN_GFC_RRFS   FDCAN_GFC_RRFS_Msk
	Reject Remote Frames Standard.
#define	FDCAN_GFC_ANFE_Pos   (2U)
#define	FDCAN_GFC_ANFE_Msk   (0x3UL << FDCAN_GFC_ANFE_Pos)
	0x0000000C
#define	FDCAN_GFC_ANFE   FDCAN_GFC_ANFE_Msk
	Accept Non-matching Frames Extended.
#define	FDCAN_GFC_ANFS_Pos   (4U)
#define	FDCAN_GFC_ANFS_Msk   (0x3UL << FDCAN_GFC_ANFS_Pos)
	0x00000030
#define	FDCAN_GFC_ANFS   FDCAN_GFC_ANFS_Msk
	Accept Non-matching Frames Standard.
#define	FDCAN_SIDFC_FLSSA_Pos   (2U)
#define	FDCAN_SIDFC_FLSSA_Msk   (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)
	0x0000FFFC
#define	FDCAN_SIDFC_FLSSA   FDCAN_SIDFC_FLSSA_Msk
	Filter List Standard Start Address.
#define	FDCAN_SIDFC_LSS_Pos   (16U)
#define	FDCAN_SIDFC_LSS_Msk   (0xFFUL << FDCAN_SIDFC_LSS_Pos)
	0x00FF0000
#define	FDCAN_SIDFC_LSS   FDCAN_SIDFC_LSS_Msk
	List Size Standard.
#define	FDCAN_XIDFC_FLESA_Pos   (2U)
#define	FDCAN_XIDFC_FLESA_Msk   (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)
	0x0000FFFC
#define	FDCAN_XIDFC_FLESA   FDCAN_XIDFC_FLESA_Msk
	Filter List Standard Start Address.
#define	FDCAN_XIDFC_LSE_Pos   (16U)
#define	FDCAN_XIDFC_LSE_Msk   (0x7FUL << FDCAN_XIDFC_LSE_Pos)
	0x007F0000
#define	FDCAN_XIDFC_LSE   FDCAN_XIDFC_LSE_Msk
	List Size Extended.
#define	FDCAN_XIDAM_EIDM_Pos   (0U)
#define	FDCAN_XIDAM_EIDM_Msk   (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)
	0x1FFFFFFF
#define	FDCAN_XIDAM_EIDM   FDCAN_XIDAM_EIDM_Msk
	Extended ID Mask.
#define	FDCAN_HPMS_BIDX_Pos   (0U)
#define	FDCAN_HPMS_BIDX_Msk   (0x3FUL << FDCAN_HPMS_BIDX_Pos)
	0x0000003F
#define	FDCAN_HPMS_BIDX   FDCAN_HPMS_BIDX_Msk
	Buffer Index.
#define	FDCAN_HPMS_MSI_Pos   (6U)
#define	FDCAN_HPMS_MSI_Msk   (0x3UL << FDCAN_HPMS_MSI_Pos)
	0x000000C0
#define	FDCAN_HPMS_MSI   FDCAN_HPMS_MSI_Msk
	Message Storage Indicator.
#define	FDCAN_HPMS_FIDX_Pos   (8U)
#define	FDCAN_HPMS_FIDX_Msk   (0x7FUL << FDCAN_HPMS_FIDX_Pos)
	0x00007F00
#define	FDCAN_HPMS_FIDX   FDCAN_HPMS_FIDX_Msk
	Filter Index.
#define	FDCAN_HPMS_FLST_Pos   (15U)
#define	FDCAN_HPMS_FLST_Msk   (0x1UL << FDCAN_HPMS_FLST_Pos)
	0x00008000
#define	FDCAN_HPMS_FLST   FDCAN_HPMS_FLST_Msk
	Filter List.
#define	FDCAN_NDAT1_ND0_Pos   (0U)
#define	FDCAN_NDAT1_ND0_Msk   (0x1UL << FDCAN_NDAT1_ND0_Pos)
	0x00000001
#define	FDCAN_NDAT1_ND0   FDCAN_NDAT1_ND0_Msk
	New Data flag of Rx Buffer 0.
#define	FDCAN_NDAT1_ND1_Pos   (1U)
#define	FDCAN_NDAT1_ND1_Msk   (0x1UL << FDCAN_NDAT1_ND1_Pos)
	0x00000002
#define	FDCAN_NDAT1_ND1   FDCAN_NDAT1_ND1_Msk
	New Data flag of Rx Buffer 1.
#define	FDCAN_NDAT1_ND2_Pos   (2U)
#define	FDCAN_NDAT1_ND2_Msk   (0x1UL << FDCAN_NDAT1_ND2_Pos)
	0x00000004
#define	FDCAN_NDAT1_ND2   FDCAN_NDAT1_ND2_Msk
	New Data flag of Rx Buffer 2.
#define	FDCAN_NDAT1_ND3_Pos   (3U)
#define	FDCAN_NDAT1_ND3_Msk   (0x1UL << FDCAN_NDAT1_ND3_Pos)
	0x00000008
#define	FDCAN_NDAT1_ND3   FDCAN_NDAT1_ND3_Msk
	New Data flag of Rx Buffer 3.
#define	FDCAN_NDAT1_ND4_Pos   (4U)
#define	FDCAN_NDAT1_ND4_Msk   (0x1UL << FDCAN_NDAT1_ND4_Pos)
	0x00000010
#define	FDCAN_NDAT1_ND4   FDCAN_NDAT1_ND4_Msk
	New Data flag of Rx Buffer 4.
#define	FDCAN_NDAT1_ND5_Pos   (5U)
#define	FDCAN_NDAT1_ND5_Msk   (0x1UL << FDCAN_NDAT1_ND5_Pos)
	0x00000020
#define	FDCAN_NDAT1_ND5   FDCAN_NDAT1_ND5_Msk
	New Data flag of Rx Buffer 5.
#define	FDCAN_NDAT1_ND6_Pos   (6U)
#define	FDCAN_NDAT1_ND6_Msk   (0x1UL << FDCAN_NDAT1_ND6_Pos)
	0x00000040
#define	FDCAN_NDAT1_ND6   FDCAN_NDAT1_ND6_Msk
	New Data flag of Rx Buffer 6.
#define	FDCAN_NDAT1_ND7_Pos   (7U)
#define	FDCAN_NDAT1_ND7_Msk   (0x1UL << FDCAN_NDAT1_ND7_Pos)
	0x00000080
#define	FDCAN_NDAT1_ND7   FDCAN_NDAT1_ND7_Msk
	New Data flag of Rx Buffer 7.
#define	FDCAN_NDAT1_ND8_Pos   (8U)
#define	FDCAN_NDAT1_ND8_Msk   (0x1UL << FDCAN_NDAT1_ND8_Pos)
	0x00000100
#define	FDCAN_NDAT1_ND8   FDCAN_NDAT1_ND8_Msk
	New Data flag of Rx Buffer 8.
#define	FDCAN_NDAT1_ND9_Pos   (9U)
#define	FDCAN_NDAT1_ND9_Msk   (0x1UL << FDCAN_NDAT1_ND9_Pos)
	0x00000200
#define	FDCAN_NDAT1_ND9   FDCAN_NDAT1_ND9_Msk
	New Data flag of Rx Buffer 9.
#define	FDCAN_NDAT1_ND10_Pos   (10U)
#define	FDCAN_NDAT1_ND10_Msk   (0x1UL << FDCAN_NDAT1_ND10_Pos)
	0x00000400
#define	FDCAN_NDAT1_ND10   FDCAN_NDAT1_ND10_Msk
	New Data flag of Rx Buffer 10.
#define	FDCAN_NDAT1_ND11_Pos   (11U)
#define	FDCAN_NDAT1_ND11_Msk   (0x1UL << FDCAN_NDAT1_ND11_Pos)
	0x00000800
#define	FDCAN_NDAT1_ND11   FDCAN_NDAT1_ND11_Msk
	New Data flag of Rx Buffer 11.
#define	FDCAN_NDAT1_ND12_Pos   (12U)
#define	FDCAN_NDAT1_ND12_Msk   (0x1UL << FDCAN_NDAT1_ND12_Pos)
	0x00001000
#define	FDCAN_NDAT1_ND12   FDCAN_NDAT1_ND12_Msk
	New Data flag of Rx Buffer 12.
#define	FDCAN_NDAT1_ND13_Pos   (13U)
#define	FDCAN_NDAT1_ND13_Msk   (0x1UL << FDCAN_NDAT1_ND13_Pos)
	0x00002000
#define	FDCAN_NDAT1_ND13   FDCAN_NDAT1_ND13_Msk
	New Data flag of Rx Buffer 13.
#define	FDCAN_NDAT1_ND14_Pos   (14U)
#define	FDCAN_NDAT1_ND14_Msk   (0x1UL << FDCAN_NDAT1_ND14_Pos)
	0x00004000
#define	FDCAN_NDAT1_ND14   FDCAN_NDAT1_ND14_Msk
	New Data flag of Rx Buffer 14.
#define	FDCAN_NDAT1_ND15_Pos   (15U)
#define	FDCAN_NDAT1_ND15_Msk   (0x1UL << FDCAN_NDAT1_ND15_Pos)
	0x00008000
#define	FDCAN_NDAT1_ND15   FDCAN_NDAT1_ND15_Msk
	New Data flag of Rx Buffer 15.
#define	FDCAN_NDAT1_ND16_Pos   (16U)
#define	FDCAN_NDAT1_ND16_Msk   (0x1UL << FDCAN_NDAT1_ND16_Pos)
	0x00010000
#define	FDCAN_NDAT1_ND16   FDCAN_NDAT1_ND16_Msk
	New Data flag of Rx Buffer 16.
#define	FDCAN_NDAT1_ND17_Pos   (17U)
#define	FDCAN_NDAT1_ND17_Msk   (0x1UL << FDCAN_NDAT1_ND17_Pos)
	0x00020000
#define	FDCAN_NDAT1_ND17   FDCAN_NDAT1_ND17_Msk
	New Data flag of Rx Buffer 17.
#define	FDCAN_NDAT1_ND18_Pos   (18U)
#define	FDCAN_NDAT1_ND18_Msk   (0x1UL << FDCAN_NDAT1_ND18_Pos)
	0x00040000
#define	FDCAN_NDAT1_ND18   FDCAN_NDAT1_ND18_Msk
	New Data flag of Rx Buffer 18.
#define	FDCAN_NDAT1_ND19_Pos   (19U)
#define	FDCAN_NDAT1_ND19_Msk   (0x1UL << FDCAN_NDAT1_ND19_Pos)
	0x00080000
#define	FDCAN_NDAT1_ND19   FDCAN_NDAT1_ND19_Msk
	New Data flag of Rx Buffer 19.
#define	FDCAN_NDAT1_ND20_Pos   (20U)
#define	FDCAN_NDAT1_ND20_Msk   (0x1UL << FDCAN_NDAT1_ND20_Pos)
	0x00100000
#define	FDCAN_NDAT1_ND20   FDCAN_NDAT1_ND20_Msk
	New Data flag of Rx Buffer 20.
#define	FDCAN_NDAT1_ND21_Pos   (21U)
#define	FDCAN_NDAT1_ND21_Msk   (0x1UL << FDCAN_NDAT1_ND21_Pos)
	0x00200000
#define	FDCAN_NDAT1_ND21   FDCAN_NDAT1_ND21_Msk
	New Data flag of Rx Buffer 21.
#define	FDCAN_NDAT1_ND22_Pos   (22U)
#define	FDCAN_NDAT1_ND22_Msk   (0x1UL << FDCAN_NDAT1_ND22_Pos)
	0x00400000
#define	FDCAN_NDAT1_ND22   FDCAN_NDAT1_ND22_Msk
	New Data flag of Rx Buffer 22.
#define	FDCAN_NDAT1_ND23_Pos   (23U)
#define	FDCAN_NDAT1_ND23_Msk   (0x1UL << FDCAN_NDAT1_ND23_Pos)
	0x00800000
#define	FDCAN_NDAT1_ND23   FDCAN_NDAT1_ND23_Msk
	New Data flag of Rx Buffer 23.
#define	FDCAN_NDAT1_ND24_Pos   (24U)
#define	FDCAN_NDAT1_ND24_Msk   (0x1UL << FDCAN_NDAT1_ND24_Pos)
	0x01000000
#define	FDCAN_NDAT1_ND24   FDCAN_NDAT1_ND24_Msk
	New Data flag of Rx Buffer 24.
#define	FDCAN_NDAT1_ND25_Pos   (25U)
#define	FDCAN_NDAT1_ND25_Msk   (0x1UL << FDCAN_NDAT1_ND25_Pos)
	0x02000000
#define	FDCAN_NDAT1_ND25   FDCAN_NDAT1_ND25_Msk
	New Data flag of Rx Buffer 25.
#define	FDCAN_NDAT1_ND26_Pos   (26U)
#define	FDCAN_NDAT1_ND26_Msk   (0x1UL << FDCAN_NDAT1_ND26_Pos)
	0x04000000
#define	FDCAN_NDAT1_ND26   FDCAN_NDAT1_ND26_Msk
	New Data flag of Rx Buffer 26.
#define	FDCAN_NDAT1_ND27_Pos   (27U)
#define	FDCAN_NDAT1_ND27_Msk   (0x1UL << FDCAN_NDAT1_ND27_Pos)
	0x08000000
#define	FDCAN_NDAT1_ND27   FDCAN_NDAT1_ND27_Msk
	New Data flag of Rx Buffer 27.
#define	FDCAN_NDAT1_ND28_Pos   (28U)
#define	FDCAN_NDAT1_ND28_Msk   (0x1UL << FDCAN_NDAT1_ND28_Pos)
	0x10000000
#define	FDCAN_NDAT1_ND28   FDCAN_NDAT1_ND28_Msk
	New Data flag of Rx Buffer 28.
#define	FDCAN_NDAT1_ND29_Pos   (29U)
#define	FDCAN_NDAT1_ND29_Msk   (0x1UL << FDCAN_NDAT1_ND29_Pos)
	0x20000000
#define	FDCAN_NDAT1_ND29   FDCAN_NDAT1_ND29_Msk
	New Data flag of Rx Buffer 29.
#define	FDCAN_NDAT1_ND30_Pos   (30U)
#define	FDCAN_NDAT1_ND30_Msk   (0x1UL << FDCAN_NDAT1_ND30_Pos)
	0x40000000
#define	FDCAN_NDAT1_ND30   FDCAN_NDAT1_ND30_Msk
	New Data flag of Rx Buffer 30.
#define	FDCAN_NDAT1_ND31_Pos   (31U)
#define	FDCAN_NDAT1_ND31_Msk   (0x1UL << FDCAN_NDAT1_ND31_Pos)
	0x80000000
#define	FDCAN_NDAT1_ND31   FDCAN_NDAT1_ND31_Msk
	New Data flag of Rx Buffer 31.
#define	FDCAN_NDAT2_ND32_Pos   (0U)
#define	FDCAN_NDAT2_ND32_Msk   (0x1UL << FDCAN_NDAT2_ND32_Pos)
	0x00000001
#define	FDCAN_NDAT2_ND32   FDCAN_NDAT2_ND32_Msk
	New Data flag of Rx Buffer 32.
#define	FDCAN_NDAT2_ND33_Pos   (1U)
#define	FDCAN_NDAT2_ND33_Msk   (0x1UL << FDCAN_NDAT2_ND33_Pos)
	0x00000002
#define	FDCAN_NDAT2_ND33   FDCAN_NDAT2_ND33_Msk
	New Data flag of Rx Buffer 33.
#define	FDCAN_NDAT2_ND34_Pos   (2U)
#define	FDCAN_NDAT2_ND34_Msk   (0x1UL << FDCAN_NDAT2_ND34_Pos)
	0x00000004
#define	FDCAN_NDAT2_ND34   FDCAN_NDAT2_ND34_Msk
	New Data flag of Rx Buffer 34.
#define	FDCAN_NDAT2_ND35_Pos   (3U)
#define	FDCAN_NDAT2_ND35_Msk   (0x1UL << FDCAN_NDAT2_ND35_Pos)
	0x00000008
#define	FDCAN_NDAT2_ND35   FDCAN_NDAT2_ND35_Msk
	New Data flag of Rx Buffer 35.
#define	FDCAN_NDAT2_ND36_Pos   (4U)
#define	FDCAN_NDAT2_ND36_Msk   (0x1UL << FDCAN_NDAT2_ND36_Pos)
	0x00000010
#define	FDCAN_NDAT2_ND36   FDCAN_NDAT2_ND36_Msk
	New Data flag of Rx Buffer 36.
#define	FDCAN_NDAT2_ND37_Pos   (5U)
#define	FDCAN_NDAT2_ND37_Msk   (0x1UL << FDCAN_NDAT2_ND37_Pos)
	0x00000020
#define	FDCAN_NDAT2_ND37   FDCAN_NDAT2_ND37_Msk
	New Data flag of Rx Buffer 37.
#define	FDCAN_NDAT2_ND38_Pos   (6U)
#define	FDCAN_NDAT2_ND38_Msk   (0x1UL << FDCAN_NDAT2_ND38_Pos)
	0x00000040
#define	FDCAN_NDAT2_ND38   FDCAN_NDAT2_ND38_Msk
	New Data flag of Rx Buffer 38.
#define	FDCAN_NDAT2_ND39_Pos   (7U)
#define	FDCAN_NDAT2_ND39_Msk   (0x1UL << FDCAN_NDAT2_ND39_Pos)
	0x00000080
#define	FDCAN_NDAT2_ND39   FDCAN_NDAT2_ND39_Msk
	New Data flag of Rx Buffer 39.
#define	FDCAN_NDAT2_ND40_Pos   (8U)
#define	FDCAN_NDAT2_ND40_Msk   (0x1UL << FDCAN_NDAT2_ND40_Pos)
	0x00000100
#define	FDCAN_NDAT2_ND40   FDCAN_NDAT2_ND40_Msk
	New Data flag of Rx Buffer 40.
#define	FDCAN_NDAT2_ND41_Pos   (9U)
#define	FDCAN_NDAT2_ND41_Msk   (0x1UL << FDCAN_NDAT2_ND41_Pos)
	0x00000200
#define	FDCAN_NDAT2_ND41   FDCAN_NDAT2_ND41_Msk
	New Data flag of Rx Buffer 41.
#define	FDCAN_NDAT2_ND42_Pos   (10U)
#define	FDCAN_NDAT2_ND42_Msk   (0x1UL << FDCAN_NDAT2_ND42_Pos)
	0x00000400
#define	FDCAN_NDAT2_ND42   FDCAN_NDAT2_ND42_Msk
	New Data flag of Rx Buffer 42.
#define	FDCAN_NDAT2_ND43_Pos   (11U)
#define	FDCAN_NDAT2_ND43_Msk   (0x1UL << FDCAN_NDAT2_ND43_Pos)
	0x00000800
#define	FDCAN_NDAT2_ND43   FDCAN_NDAT2_ND43_Msk
	New Data flag of Rx Buffer 43.
#define	FDCAN_NDAT2_ND44_Pos   (12U)
#define	FDCAN_NDAT2_ND44_Msk   (0x1UL << FDCAN_NDAT2_ND44_Pos)
	0x00001000
#define	FDCAN_NDAT2_ND44   FDCAN_NDAT2_ND44_Msk
	New Data flag of Rx Buffer 44.
#define	FDCAN_NDAT2_ND45_Pos   (13U)
#define	FDCAN_NDAT2_ND45_Msk   (0x1UL << FDCAN_NDAT2_ND45_Pos)
	0x00002000
#define	FDCAN_NDAT2_ND45   FDCAN_NDAT2_ND45_Msk
	New Data flag of Rx Buffer 45.
#define	FDCAN_NDAT2_ND46_Pos   (14U)
#define	FDCAN_NDAT2_ND46_Msk   (0x1UL << FDCAN_NDAT2_ND46_Pos)
	0x00004000
#define	FDCAN_NDAT2_ND46   FDCAN_NDAT2_ND46_Msk
	New Data flag of Rx Buffer 46.
#define	FDCAN_NDAT2_ND47_Pos   (15U)
#define	FDCAN_NDAT2_ND47_Msk   (0x1UL << FDCAN_NDAT2_ND47_Pos)
	0x00008000
#define	FDCAN_NDAT2_ND47   FDCAN_NDAT2_ND47_Msk
	New Data flag of Rx Buffer 47.
#define	FDCAN_NDAT2_ND48_Pos   (16U)
#define	FDCAN_NDAT2_ND48_Msk   (0x1UL << FDCAN_NDAT2_ND48_Pos)
	0x00010000
#define	FDCAN_NDAT2_ND48   FDCAN_NDAT2_ND48_Msk
	New Data flag of Rx Buffer 48.
#define	FDCAN_NDAT2_ND49_Pos   (17U)
#define	FDCAN_NDAT2_ND49_Msk   (0x1UL << FDCAN_NDAT2_ND49_Pos)
	0x00020000
#define	FDCAN_NDAT2_ND49   FDCAN_NDAT2_ND49_Msk
	New Data flag of Rx Buffer 49.
#define	FDCAN_NDAT2_ND50_Pos   (18U)
#define	FDCAN_NDAT2_ND50_Msk   (0x1UL << FDCAN_NDAT2_ND50_Pos)
	0x00040000
#define	FDCAN_NDAT2_ND50   FDCAN_NDAT2_ND50_Msk
	New Data flag of Rx Buffer 50.
#define	FDCAN_NDAT2_ND51_Pos   (19U)
#define	FDCAN_NDAT2_ND51_Msk   (0x1UL << FDCAN_NDAT2_ND51_Pos)
	0x00080000
#define	FDCAN_NDAT2_ND51   FDCAN_NDAT2_ND51_Msk
	New Data flag of Rx Buffer 51.
#define	FDCAN_NDAT2_ND52_Pos   (20U)
#define	FDCAN_NDAT2_ND52_Msk   (0x1UL << FDCAN_NDAT2_ND52_Pos)
	0x00100000
#define	FDCAN_NDAT2_ND52   FDCAN_NDAT2_ND52_Msk
	New Data flag of Rx Buffer 52.
#define	FDCAN_NDAT2_ND53_Pos   (21U)
#define	FDCAN_NDAT2_ND53_Msk   (0x1UL << FDCAN_NDAT2_ND53_Pos)
	0x00200000
#define	FDCAN_NDAT2_ND53   FDCAN_NDAT2_ND53_Msk
	New Data flag of Rx Buffer 53.
#define	FDCAN_NDAT2_ND54_Pos   (22U)
#define	FDCAN_NDAT2_ND54_Msk   (0x1UL << FDCAN_NDAT2_ND54_Pos)
	0x00400000
#define	FDCAN_NDAT2_ND54   FDCAN_NDAT2_ND54_Msk
	New Data flag of Rx Buffer 54.
#define	FDCAN_NDAT2_ND55_Pos   (23U)
#define	FDCAN_NDAT2_ND55_Msk   (0x1UL << FDCAN_NDAT2_ND55_Pos)
	0x00800000
#define	FDCAN_NDAT2_ND55   FDCAN_NDAT2_ND55_Msk
	New Data flag of Rx Buffer 55.
#define	FDCAN_NDAT2_ND56_Pos   (24U)
#define	FDCAN_NDAT2_ND56_Msk   (0x1UL << FDCAN_NDAT2_ND56_Pos)
	0x01000000
#define	FDCAN_NDAT2_ND56   FDCAN_NDAT2_ND56_Msk
	New Data flag of Rx Buffer 56.
#define	FDCAN_NDAT2_ND57_Pos   (25U)
#define	FDCAN_NDAT2_ND57_Msk   (0x1UL << FDCAN_NDAT2_ND57_Pos)
	0x02000000
#define	FDCAN_NDAT2_ND57   FDCAN_NDAT2_ND57_Msk
	New Data flag of Rx Buffer 57.
#define	FDCAN_NDAT2_ND58_Pos   (26U)
#define	FDCAN_NDAT2_ND58_Msk   (0x1UL << FDCAN_NDAT2_ND58_Pos)
	0x04000000
#define	FDCAN_NDAT2_ND58   FDCAN_NDAT2_ND58_Msk
	New Data flag of Rx Buffer 58.
#define	FDCAN_NDAT2_ND59_Pos   (27U)
#define	FDCAN_NDAT2_ND59_Msk   (0x1UL << FDCAN_NDAT2_ND59_Pos)
	0x08000000
#define	FDCAN_NDAT2_ND59   FDCAN_NDAT2_ND59_Msk
	New Data flag of Rx Buffer 59.
#define	FDCAN_NDAT2_ND60_Pos   (28U)
#define	FDCAN_NDAT2_ND60_Msk   (0x1UL << FDCAN_NDAT2_ND60_Pos)
	0x10000000
#define	FDCAN_NDAT2_ND60   FDCAN_NDAT2_ND60_Msk
	New Data flag of Rx Buffer 60.
#define	FDCAN_NDAT2_ND61_Pos   (29U)
#define	FDCAN_NDAT2_ND61_Msk   (0x1UL << FDCAN_NDAT2_ND61_Pos)
	0x20000000
#define	FDCAN_NDAT2_ND61   FDCAN_NDAT2_ND61_Msk
	New Data flag of Rx Buffer 61.
#define	FDCAN_NDAT2_ND62_Pos   (30U)
#define	FDCAN_NDAT2_ND62_Msk   (0x1UL << FDCAN_NDAT2_ND62_Pos)
	0x40000000
#define	FDCAN_NDAT2_ND62   FDCAN_NDAT2_ND62_Msk
	New Data flag of Rx Buffer 62.
#define	FDCAN_NDAT2_ND63_Pos   (31U)
#define	FDCAN_NDAT2_ND63_Msk   (0x1UL << FDCAN_NDAT2_ND63_Pos)
	0x80000000
#define	FDCAN_NDAT2_ND63   FDCAN_NDAT2_ND63_Msk
	New Data flag of Rx Buffer 63.
#define	FDCAN_RXF0C_F0SA_Pos   (2U)
#define	FDCAN_RXF0C_F0SA_Msk   (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)
	0x0000FFFC
#define	FDCAN_RXF0C_F0SA   FDCAN_RXF0C_F0SA_Msk
	Rx FIFO 0 Start Address.
#define	FDCAN_RXF0C_F0S_Pos   (16U)
#define	FDCAN_RXF0C_F0S_Msk   (0x7FUL << FDCAN_RXF0C_F0S_Pos)
	0x007F0000
#define	FDCAN_RXF0C_F0S   FDCAN_RXF0C_F0S_Msk
	Number of Rx FIFO 0 elements.
#define	FDCAN_RXF0C_F0WM_Pos   (24U)
#define	FDCAN_RXF0C_F0WM_Msk   (0x7FUL << FDCAN_RXF0C_F0WM_Pos)
	0x7F000000
#define	FDCAN_RXF0C_F0WM   FDCAN_RXF0C_F0WM_Msk
	FIFO 0 Watermark.
#define	FDCAN_RXF0C_F0OM_Pos   (31U)
#define	FDCAN_RXF0C_F0OM_Msk   (0x1UL << FDCAN_RXF0C_F0OM_Pos)
	0x80000000
#define	FDCAN_RXF0C_F0OM   FDCAN_RXF0C_F0OM_Msk
	FIFO 0 Operation Mode.
#define	FDCAN_RXF0S_F0FL_Pos   (0U)
#define	FDCAN_RXF0S_F0FL_Msk   (0x7FUL << FDCAN_RXF0S_F0FL_Pos)
	0x0000007F
#define	FDCAN_RXF0S_F0FL   FDCAN_RXF0S_F0FL_Msk
	Rx FIFO 0 Fill Level.
#define	FDCAN_RXF0S_F0GI_Pos   (8U)
#define	FDCAN_RXF0S_F0GI_Msk   (0x3FUL << FDCAN_RXF0S_F0GI_Pos)
	0x00003F00
#define	FDCAN_RXF0S_F0GI   FDCAN_RXF0S_F0GI_Msk
	Rx FIFO 0 Get Index.
#define	FDCAN_RXF0S_F0PI_Pos   (16U)
#define	FDCAN_RXF0S_F0PI_Msk   (0x3FUL << FDCAN_RXF0S_F0PI_Pos)
	0x003F0000
#define	FDCAN_RXF0S_F0PI   FDCAN_RXF0S_F0PI_Msk
	Rx FIFO 0 Put Index.
#define	FDCAN_RXF0S_F0F_Pos   (24U)
#define	FDCAN_RXF0S_F0F_Msk   (0x1UL << FDCAN_RXF0S_F0F_Pos)
	0x01000000
#define	FDCAN_RXF0S_F0F   FDCAN_RXF0S_F0F_Msk
	Rx FIFO 0 Full.
#define	FDCAN_RXF0S_RF0L_Pos   (25U)
#define	FDCAN_RXF0S_RF0L_Msk   (0x1UL << FDCAN_RXF0S_RF0L_Pos)
	0x02000000
#define	FDCAN_RXF0S_RF0L   FDCAN_RXF0S_RF0L_Msk
	Rx FIFO 0 Message Lost.
#define	FDCAN_RXF0A_F0AI_Pos   (0U)
#define	FDCAN_RXF0A_F0AI_Msk   (0x3FUL << FDCAN_RXF0A_F0AI_Pos)
	0x0000003F
#define	FDCAN_RXF0A_F0AI   FDCAN_RXF0A_F0AI_Msk
	Rx FIFO 0 Acknowledge Index.
#define	FDCAN_RXBC_RBSA_Pos   (2U)
#define	FDCAN_RXBC_RBSA_Msk   (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)
	0x0000FFFC
#define	FDCAN_RXBC_RBSA   FDCAN_RXBC_RBSA_Msk
	Rx Buffer Start Address.
#define	FDCAN_RXF1C_F1SA_Pos   (2U)
#define	FDCAN_RXF1C_F1SA_Msk   (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)
	0x0000FFFC
#define	FDCAN_RXF1C_F1SA   FDCAN_RXF1C_F1SA_Msk
	Rx FIFO 1 Start Address.
#define	FDCAN_RXF1C_F1S_Pos   (16U)
#define	FDCAN_RXF1C_F1S_Msk   (0x7FUL << FDCAN_RXF1C_F1S_Pos)
	0x007F0000
#define	FDCAN_RXF1C_F1S   FDCAN_RXF1C_F1S_Msk
	Number of Rx FIFO 1 elements.
#define	FDCAN_RXF1C_F1WM_Pos   (24U)
#define	FDCAN_RXF1C_F1WM_Msk   (0x7FUL << FDCAN_RXF1C_F1WM_Pos)
	0x7F000000
#define	FDCAN_RXF1C_F1WM   FDCAN_RXF1C_F1WM_Msk
	Rx FIFO 1 Watermark.
#define	FDCAN_RXF1C_F1OM_Pos   (31U)
#define	FDCAN_RXF1C_F1OM_Msk   (0x1UL << FDCAN_RXF1C_F1OM_Pos)
	0x80000000
#define	FDCAN_RXF1C_F1OM   FDCAN_RXF1C_F1OM_Msk
	FIFO 1 Operation Mode.
#define	FDCAN_RXF1S_F1FL_Pos   (0U)
#define	FDCAN_RXF1S_F1FL_Msk   (0x7FUL << FDCAN_RXF1S_F1FL_Pos)
	0x0000007F
#define	FDCAN_RXF1S_F1FL   FDCAN_RXF1S_F1FL_Msk
	Rx FIFO 1 Fill Level.
#define	FDCAN_RXF1S_F1GI_Pos   (8U)
#define	FDCAN_RXF1S_F1GI_Msk   (0x3FUL << FDCAN_RXF1S_F1GI_Pos)
	0x00003F00
#define	FDCAN_RXF1S_F1GI   FDCAN_RXF1S_F1GI_Msk
	Rx FIFO 1 Get Index.
#define	FDCAN_RXF1S_F1PI_Pos   (16U)
#define	FDCAN_RXF1S_F1PI_Msk   (0x3FUL << FDCAN_RXF1S_F1PI_Pos)
	0x003F0000
#define	FDCAN_RXF1S_F1PI   FDCAN_RXF1S_F1PI_Msk
	Rx FIFO 1 Put Index.
#define	FDCAN_RXF1S_F1F_Pos   (24U)
#define	FDCAN_RXF1S_F1F_Msk   (0x1UL << FDCAN_RXF1S_F1F_Pos)
	0x01000000
#define	FDCAN_RXF1S_F1F   FDCAN_RXF1S_F1F_Msk
	Rx FIFO 1 Full.
#define	FDCAN_RXF1S_RF1L_Pos   (25U)
#define	FDCAN_RXF1S_RF1L_Msk   (0x1UL << FDCAN_RXF1S_RF1L_Pos)
	0x02000000
#define	FDCAN_RXF1S_RF1L   FDCAN_RXF1S_RF1L_Msk
	Rx FIFO 1 Message Lost.
#define	FDCAN_RXF1A_F1AI_Pos   (0U)
#define	FDCAN_RXF1A_F1AI_Msk   (0x3FUL << FDCAN_RXF1A_F1AI_Pos)
	0x0000003F
#define	FDCAN_RXF1A_F1AI   FDCAN_RXF1A_F1AI_Msk
	Rx FIFO 1 Acknowledge Index.
#define	FDCAN_RXESC_F0DS_Pos   (0U)
#define	FDCAN_RXESC_F0DS_Msk   (0x7UL << FDCAN_RXESC_F0DS_Pos)
	0x00000007
#define	FDCAN_RXESC_F0DS   FDCAN_RXESC_F0DS_Msk
	Rx FIFO 1 Data Field Size.
#define	FDCAN_RXESC_F1DS_Pos   (4U)
#define	FDCAN_RXESC_F1DS_Msk   (0x7UL << FDCAN_RXESC_F1DS_Pos)
	0x00000070
#define	FDCAN_RXESC_F1DS   FDCAN_RXESC_F1DS_Msk
	Rx FIFO 0 Data Field Size.
#define	FDCAN_RXESC_RBDS_Pos   (8U)
#define	FDCAN_RXESC_RBDS_Msk   (0x7UL << FDCAN_RXESC_RBDS_Pos)
	0x00000700
#define	FDCAN_RXESC_RBDS   FDCAN_RXESC_RBDS_Msk
	Rx Buffer Data Field Size.
#define	FDCAN_TXBC_TBSA_Pos   (2U)
#define	FDCAN_TXBC_TBSA_Msk   (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)
	0x0000FFFC
#define	FDCAN_TXBC_TBSA   FDCAN_TXBC_TBSA_Msk
	Tx Buffers Start Address.
#define	FDCAN_TXBC_NDTB_Pos   (16U)
#define	FDCAN_TXBC_NDTB_Msk   (0x3FUL << FDCAN_TXBC_NDTB_Pos)
	0x003F0000
#define	FDCAN_TXBC_NDTB   FDCAN_TXBC_NDTB_Msk
	Number of Dedicated Transmit Buffers.
#define	FDCAN_TXBC_TFQS_Pos   (24U)
#define	FDCAN_TXBC_TFQS_Msk   (0x3FUL << FDCAN_TXBC_TFQS_Pos)
	0x3F000000
#define	FDCAN_TXBC_TFQS   FDCAN_TXBC_TFQS_Msk
	Transmit FIFO/Queue Size.
#define	FDCAN_TXBC_TFQM_Pos   (30U)
#define	FDCAN_TXBC_TFQM_Msk   (0x1UL << FDCAN_TXBC_TFQM_Pos)
	0x40000000
#define	FDCAN_TXBC_TFQM   FDCAN_TXBC_TFQM_Msk
	Tx FIFO/Queue Mode.
#define	FDCAN_TXFQS_TFFL_Pos   (0U)
#define	FDCAN_TXFQS_TFFL_Msk   (0x3FUL << FDCAN_TXFQS_TFFL_Pos)
	0x0000003F
#define	FDCAN_TXFQS_TFFL   FDCAN_TXFQS_TFFL_Msk
	Tx FIFO Free Level.
#define	FDCAN_TXFQS_TFGI_Pos   (8U)
#define	FDCAN_TXFQS_TFGI_Msk   (0x1FUL << FDCAN_TXFQS_TFGI_Pos)
	0x00001F00
#define	FDCAN_TXFQS_TFGI   FDCAN_TXFQS_TFGI_Msk
	Tx FIFO Get Index.
#define	FDCAN_TXFQS_TFQPI_Pos   (16U)
#define	FDCAN_TXFQS_TFQPI_Msk   (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)
	0x001F0000
#define	FDCAN_TXFQS_TFQPI   FDCAN_TXFQS_TFQPI_Msk
	Tx FIFO/Queue Put Index.
#define	FDCAN_TXFQS_TFQF_Pos   (21U)
#define	FDCAN_TXFQS_TFQF_Msk   (0x1UL << FDCAN_TXFQS_TFQF_Pos)
	0x00200000
#define	FDCAN_TXFQS_TFQF   FDCAN_TXFQS_TFQF_Msk
	Tx FIFO/Queue Full.
#define	FDCAN_TXESC_TBDS_Pos   (0U)
#define	FDCAN_TXESC_TBDS_Msk   (0x7UL << FDCAN_TXESC_TBDS_Pos)
	0x00000007
#define	FDCAN_TXESC_TBDS   FDCAN_TXESC_TBDS_Msk
	Tx Buffer Data Field Size.
#define	FDCAN_TXBRP_TRP_Pos   (0U)
#define	FDCAN_TXBRP_TRP_Msk   (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)
	0xFFFFFFFF
#define	FDCAN_TXBRP_TRP   FDCAN_TXBRP_TRP_Msk
	Transmission Request Pending.
#define	FDCAN_TXBAR_AR_Pos   (0U)
#define	FDCAN_TXBAR_AR_Msk   (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)
	0xFFFFFFFF
#define	FDCAN_TXBAR_AR   FDCAN_TXBAR_AR_Msk
	Add Request.
#define	FDCAN_TXBCR_CR_Pos   (0U)
#define	FDCAN_TXBCR_CR_Msk   (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)
	0xFFFFFFFF
#define	FDCAN_TXBCR_CR   FDCAN_TXBCR_CR_Msk
	Cancellation Request.
#define	FDCAN_TXBTO_TO_Pos   (0U)
#define	FDCAN_TXBTO_TO_Msk   (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)
	0xFFFFFFFF
#define	FDCAN_TXBTO_TO   FDCAN_TXBTO_TO_Msk
	Transmission Occurred.
#define	FDCAN_TXBCF_CF_Pos   (0U)
#define	FDCAN_TXBCF_CF_Msk   (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)
	0xFFFFFFFF
#define	FDCAN_TXBCF_CF   FDCAN_TXBCF_CF_Msk
	Cancellation Finished.
#define	FDCAN_TXBTIE_TIE_Pos   (0U)
#define	FDCAN_TXBTIE_TIE_Msk   (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)
	0xFFFFFFFF
#define	FDCAN_TXBTIE_TIE   FDCAN_TXBTIE_TIE_Msk
	Transmission Interrupt Enable.
#define	FDCAN_TXBCIE_CFIE_Pos   (0U)
#define	FDCAN_TXBCIE_CFIE_Msk   (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)
	0xFFFFFFFF
#define	FDCAN_TXBCIE_CFIE   FDCAN_TXBCIE_CFIE_Msk
	Cancellation Finished Interrupt Enable.
#define	FDCAN_TXEFC_EFSA_Pos   (2U)
#define	FDCAN_TXEFC_EFSA_Msk   (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)
	0x0000FFFC
#define	FDCAN_TXEFC_EFSA   FDCAN_TXEFC_EFSA_Msk
	Event FIFO Start Address.
#define	FDCAN_TXEFC_EFS_Pos   (16U)
#define	FDCAN_TXEFC_EFS_Msk   (0x3FUL << FDCAN_TXEFC_EFS_Pos)
	0x003F0000
#define	FDCAN_TXEFC_EFS   FDCAN_TXEFC_EFS_Msk
	Event FIFO Size.
#define	FDCAN_TXEFC_EFWM_Pos   (24U)
#define	FDCAN_TXEFC_EFWM_Msk   (0x3FUL << FDCAN_TXEFC_EFWM_Pos)
	0x3F000000
#define	FDCAN_TXEFC_EFWM   FDCAN_TXEFC_EFWM_Msk
	Event FIFO Watermark.
#define	FDCAN_TXEFS_EFFL_Pos   (0U)
#define	FDCAN_TXEFS_EFFL_Msk   (0x3FUL << FDCAN_TXEFS_EFFL_Pos)
	0x0000003F
#define	FDCAN_TXEFS_EFFL   FDCAN_TXEFS_EFFL_Msk
	Event FIFO Fill Level.
#define	FDCAN_TXEFS_EFGI_Pos   (8U)
#define	FDCAN_TXEFS_EFGI_Msk   (0x1FUL << FDCAN_TXEFS_EFGI_Pos)
	0x00001F00
#define	FDCAN_TXEFS_EFGI   FDCAN_TXEFS_EFGI_Msk
	Event FIFO Get Index.
#define	FDCAN_TXEFS_EFPI_Pos   (16U)
#define	FDCAN_TXEFS_EFPI_Msk   (0x1FUL << FDCAN_TXEFS_EFPI_Pos)
	0x001F0000
#define	FDCAN_TXEFS_EFPI   FDCAN_TXEFS_EFPI_Msk
	Event FIFO Put Index.
#define	FDCAN_TXEFS_EFF_Pos   (24U)
#define	FDCAN_TXEFS_EFF_Msk   (0x1UL << FDCAN_TXEFS_EFF_Pos)
	0x01000000
#define	FDCAN_TXEFS_EFF   FDCAN_TXEFS_EFF_Msk
	Event FIFO Full.
#define	FDCAN_TXEFS_TEFL_Pos   (25U)
#define	FDCAN_TXEFS_TEFL_Msk   (0x1UL << FDCAN_TXEFS_TEFL_Pos)
	0x02000000
#define	FDCAN_TXEFS_TEFL   FDCAN_TXEFS_TEFL_Msk
	Tx Event FIFO Element Lost.
#define	FDCAN_TXEFA_EFAI_Pos   (0U)
#define	FDCAN_TXEFA_EFAI_Msk   (0x1FUL << FDCAN_TXEFA_EFAI_Pos)
	0x0000001F
#define	FDCAN_TXEFA_EFAI   FDCAN_TXEFA_EFAI_Msk
	Event FIFO Acknowledge Index.
#define	FDCAN_TTTMC_TMSA_Pos   (2U)
#define	FDCAN_TTTMC_TMSA_Msk   (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)
	0x0000FFFC
#define	FDCAN_TTTMC_TMSA   FDCAN_TTTMC_TMSA_Msk
	Trigger Memory Start Address.
#define	FDCAN_TTTMC_TME_Pos   (16U)
#define	FDCAN_TTTMC_TME_Msk   (0x7FUL << FDCAN_TTTMC_TME_Pos)
	0x007F0000
#define	FDCAN_TTTMC_TME   FDCAN_TTTMC_TME_Msk
	Trigger Memory Elements.
#define	FDCAN_TTRMC_RID_Pos   (0U)
#define	FDCAN_TTRMC_RID_Msk   (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)
	0x1FFFFFFF
#define	FDCAN_TTRMC_RID   FDCAN_TTRMC_RID_Msk
	Reference Identifier.
#define	FDCAN_TTRMC_XTD_Pos   (30U)
#define	FDCAN_TTRMC_XTD_Msk   (0x1UL << FDCAN_TTRMC_XTD_Pos)
	0x40000000
#define	FDCAN_TTRMC_XTD   FDCAN_TTRMC_XTD_Msk
	Extended Identifier.
#define	FDCAN_TTRMC_RMPS_Pos   (31U)
#define	FDCAN_TTRMC_RMPS_Msk   (0x1UL << FDCAN_TTRMC_RMPS_Pos)
	0x80000000
#define	FDCAN_TTRMC_RMPS   FDCAN_TTRMC_RMPS_Msk
	Reference Message Payload Select.
#define	FDCAN_TTOCF_OM_Pos   (0U)
#define	FDCAN_TTOCF_OM_Msk   (0x3UL << FDCAN_TTOCF_OM_Pos)
	0x00000003
#define	FDCAN_TTOCF_OM   FDCAN_TTOCF_OM_Msk
	Operation Mode.
#define	FDCAN_TTOCF_GEN_Pos   (3U)
#define	FDCAN_TTOCF_GEN_Msk   (0x1UL << FDCAN_TTOCF_GEN_Pos)
	0x00000008
#define	FDCAN_TTOCF_GEN   FDCAN_TTOCF_GEN_Msk
	Gap Enable.
#define	FDCAN_TTOCF_TM_Pos   (4U)
#define	FDCAN_TTOCF_TM_Msk   (0x1UL << FDCAN_TTOCF_TM_Pos)
	0x00000010
#define	FDCAN_TTOCF_TM   FDCAN_TTOCF_TM_Msk
	Time Master.
#define	FDCAN_TTOCF_LDSDL_Pos   (5U)
#define	FDCAN_TTOCF_LDSDL_Msk   (0x7UL << FDCAN_TTOCF_LDSDL_Pos)
	0x000000E0
#define	FDCAN_TTOCF_LDSDL   FDCAN_TTOCF_LDSDL_Msk
	LD of Synchronization Deviation Limit.
#define	FDCAN_TTOCF_IRTO_Pos   (8U)
#define	FDCAN_TTOCF_IRTO_Msk   (0x7FUL << FDCAN_TTOCF_IRTO_Pos)
	0x00007F00
#define	FDCAN_TTOCF_IRTO   FDCAN_TTOCF_IRTO_Msk
	Initial Reference Trigger Offset.
#define	FDCAN_TTOCF_EECS_Pos   (15U)
#define	FDCAN_TTOCF_EECS_Msk   (0x1UL << FDCAN_TTOCF_EECS_Pos)
	0x00008000
#define	FDCAN_TTOCF_EECS   FDCAN_TTOCF_EECS_Msk
	Enable External Clock Synchronization.
#define	FDCAN_TTOCF_AWL_Pos   (16U)
#define	FDCAN_TTOCF_AWL_Msk   (0xFFUL << FDCAN_TTOCF_AWL_Pos)
	0x00FF0000
#define	FDCAN_TTOCF_AWL   FDCAN_TTOCF_AWL_Msk
	Application Watchdog Limit.
#define	FDCAN_TTOCF_EGTF_Pos   (24U)
#define	FDCAN_TTOCF_EGTF_Msk   (0x1UL << FDCAN_TTOCF_EGTF_Pos)
	0x01000000
#define	FDCAN_TTOCF_EGTF   FDCAN_TTOCF_EGTF_Msk
	Enable Global Time Filtering.
#define	FDCAN_TTOCF_ECC_Pos   (25U)
#define	FDCAN_TTOCF_ECC_Msk   (0x1UL << FDCAN_TTOCF_ECC_Pos)
	0x02000000
#define	FDCAN_TTOCF_ECC   FDCAN_TTOCF_ECC_Msk
	Enable Clock Calibration.
#define	FDCAN_TTOCF_EVTP_Pos   (26U)
#define	FDCAN_TTOCF_EVTP_Msk   (0x1UL << FDCAN_TTOCF_EVTP_Pos)
	0x04000000
#define	FDCAN_TTOCF_EVTP   FDCAN_TTOCF_EVTP_Msk
	Event Trigger Polarity.
#define	FDCAN_TTMLM_CCM_Pos   (0U)
#define	FDCAN_TTMLM_CCM_Msk   (0x3FUL << FDCAN_TTMLM_CCM_Pos)
	0x0000003F
#define	FDCAN_TTMLM_CCM   FDCAN_TTMLM_CCM_Msk
	Cycle Count Max.
#define	FDCAN_TTMLM_CSS_Pos   (6U)
#define	FDCAN_TTMLM_CSS_Msk   (0x3UL << FDCAN_TTMLM_CSS_Pos)
	0x000000C0
#define	FDCAN_TTMLM_CSS   FDCAN_TTMLM_CSS_Msk
	Cycle Start Synchronization.
#define	FDCAN_TTMLM_TXEW_Pos   (8U)
#define	FDCAN_TTMLM_TXEW_Msk   (0xFUL << FDCAN_TTMLM_TXEW_Pos)
	0x00000F00
#define	FDCAN_TTMLM_TXEW   FDCAN_TTMLM_TXEW_Msk
	Tx Enable Window.
#define	FDCAN_TTMLM_ENTT_Pos   (16U)
#define	FDCAN_TTMLM_ENTT_Msk   (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)
	0x0FFF0000
#define	FDCAN_TTMLM_ENTT   FDCAN_TTMLM_ENTT_Msk
	Expected Number of Tx Triggers.
#define	FDCAN_TURCF_NCL_Pos   (0U)
#define	FDCAN_TURCF_NCL_Msk   (0xFFFFUL << FDCAN_TURCF_NCL_Pos)
	0x0000FFFF
#define	FDCAN_TURCF_NCL   FDCAN_TURCF_NCL_Msk
	Numerator Configuration Low.
#define	FDCAN_TURCF_DC_Pos   (16U)
#define	FDCAN_TURCF_DC_Msk   (0x3FFFUL << FDCAN_TURCF_DC_Pos)
	0x3FFF0000
#define	FDCAN_TURCF_DC   FDCAN_TURCF_DC_Msk
	Denominator Configuration.
#define	FDCAN_TURCF_ELT_Pos   (31U)
#define	FDCAN_TURCF_ELT_Msk   (0x1UL << FDCAN_TURCF_ELT_Pos)
	0x80000000
#define	FDCAN_TURCF_ELT   FDCAN_TURCF_ELT_Msk
	Enable Local Time.
#define	FDCAN_TTOCN_SGT_Pos   (0U)
#define	FDCAN_TTOCN_SGT_Msk   (0x1UL << FDCAN_TTOCN_SGT_Pos)
	0x00000001
#define	FDCAN_TTOCN_SGT   FDCAN_TTOCN_SGT_Msk
	Set Global time.
#define	FDCAN_TTOCN_ECS_Pos   (1U)
#define	FDCAN_TTOCN_ECS_Msk   (0x1UL << FDCAN_TTOCN_ECS_Pos)
	0x00000002
#define	FDCAN_TTOCN_ECS   FDCAN_TTOCN_ECS_Msk
	External Clock Synchronization.
#define	FDCAN_TTOCN_SWP_Pos   (2U)
#define	FDCAN_TTOCN_SWP_Msk   (0x1UL << FDCAN_TTOCN_SWP_Pos)
	0x00000004
#define	FDCAN_TTOCN_SWP   FDCAN_TTOCN_SWP_Msk
	Stop Watch Polarity.
#define	FDCAN_TTOCN_SWS_Pos   (3U)
#define	FDCAN_TTOCN_SWS_Msk   (0x3UL << FDCAN_TTOCN_SWS_Pos)
	0x00000018
#define	FDCAN_TTOCN_SWS   FDCAN_TTOCN_SWS_Msk
	Stop Watch Source.
#define	FDCAN_TTOCN_RTIE_Pos   (5U)
#define	FDCAN_TTOCN_RTIE_Msk   (0x1UL << FDCAN_TTOCN_RTIE_Pos)
	0x00000020
#define	FDCAN_TTOCN_RTIE   FDCAN_TTOCN_RTIE_Msk
	Register Time Mark Interrupt Pulse Enable.
#define	FDCAN_TTOCN_TMC_Pos   (6U)
#define	FDCAN_TTOCN_TMC_Msk   (0x3UL << FDCAN_TTOCN_TMC_Pos)
	0x000000C0
#define	FDCAN_TTOCN_TMC   FDCAN_TTOCN_TMC_Msk
	Register Time Mark Compare.
#define	FDCAN_TTOCN_TTIE_Pos   (8U)
#define	FDCAN_TTOCN_TTIE_Msk   (0x1UL << FDCAN_TTOCN_TTIE_Pos)
	0x00000100
#define	FDCAN_TTOCN_TTIE   FDCAN_TTOCN_TTIE_Msk
	Trigger Time Mark Interrupt Pulse Enable.
#define	FDCAN_TTOCN_GCS_Pos   (9U)
#define	FDCAN_TTOCN_GCS_Msk   (0x1UL << FDCAN_TTOCN_GCS_Pos)
	0x00000200
#define	FDCAN_TTOCN_GCS   FDCAN_TTOCN_GCS_Msk
	Gap Control Select.
#define	FDCAN_TTOCN_FGP_Pos   (10U)
#define	FDCAN_TTOCN_FGP_Msk   (0x1UL << FDCAN_TTOCN_FGP_Pos)
	0x00000400
#define	FDCAN_TTOCN_FGP   FDCAN_TTOCN_FGP_Msk
	Finish Gap.
#define	FDCAN_TTOCN_TMG_Pos   (11U)
#define	FDCAN_TTOCN_TMG_Msk   (0x1UL << FDCAN_TTOCN_TMG_Pos)
	0x00000800
#define	FDCAN_TTOCN_TMG   FDCAN_TTOCN_TMG_Msk
	Time Mark Gap.
#define	FDCAN_TTOCN_NIG_Pos   (12U)
#define	FDCAN_TTOCN_NIG_Msk   (0x1UL << FDCAN_TTOCN_NIG_Pos)
	0x00001000
#define	FDCAN_TTOCN_NIG   FDCAN_TTOCN_NIG_Msk
	Next is Gap.
#define	FDCAN_TTOCN_ESCN_Pos   (13U)
#define	FDCAN_TTOCN_ESCN_Msk   (0x1UL << FDCAN_TTOCN_ESCN_Pos)
	0x00002000
#define	FDCAN_TTOCN_ESCN   FDCAN_TTOCN_ESCN_Msk
	External Synchronization Control.
#define	FDCAN_TTOCN_LCKC_Pos   (15U)
#define	FDCAN_TTOCN_LCKC_Msk   (0x1UL << FDCAN_TTOCN_LCKC_Pos)
	0x00008000
#define	FDCAN_TTOCN_LCKC   FDCAN_TTOCN_LCKC_Msk
	TT Operation Control Register Locked.
#define	FDCAN_TTGTP_TP_Pos   (0U)
#define	FDCAN_TTGTP_TP_Msk   (0xFFFFUL << FDCAN_TTGTP_TP_Pos)
	0x0000FFFF
#define	FDCAN_TTGTP_TP   FDCAN_TTGTP_TP_Msk
	Time Preset.
#define	FDCAN_TTGTP_CTP_Pos   (16U)
#define	FDCAN_TTGTP_CTP_Msk   (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)
	0xFFFF0000
#define	FDCAN_TTGTP_CTP   FDCAN_TTGTP_CTP_Msk
	Cycle Time Target Phase.
#define	FDCAN_TTTMK_TM_Pos   (0U)
#define	FDCAN_TTTMK_TM_Msk   (0xFFFFUL << FDCAN_TTTMK_TM_Pos)
	0x0000FFFF
#define	FDCAN_TTTMK_TM   FDCAN_TTTMK_TM_Msk
	Time Mark.
#define	FDCAN_TTTMK_TICC_Pos   (16U)
#define	FDCAN_TTTMK_TICC_Msk   (0x7FUL << FDCAN_TTTMK_TICC_Pos)
	0x007F0000
#define	FDCAN_TTTMK_TICC   FDCAN_TTTMK_TICC_Msk
	Time Mark Cycle Code.
#define	FDCAN_TTTMK_LCKM_Pos   (31U)
#define	FDCAN_TTTMK_LCKM_Msk   (0x1UL << FDCAN_TTTMK_LCKM_Pos)
	0x80000000
#define	FDCAN_TTTMK_LCKM   FDCAN_TTTMK_LCKM_Msk
	TT Time Mark Register Locked.
#define	FDCAN_TTIR_SBC_Pos   (0U)
#define	FDCAN_TTIR_SBC_Msk   (0x1UL << FDCAN_TTIR_SBC_Pos)
	0x00000001
#define	FDCAN_TTIR_SBC   FDCAN_TTIR_SBC_Msk
	Start of Basic Cycle.
#define	FDCAN_TTIR_SMC_Pos   (1U)
#define	FDCAN_TTIR_SMC_Msk   (0x1UL << FDCAN_TTIR_SMC_Pos)
	0x00000002
#define	FDCAN_TTIR_SMC   FDCAN_TTIR_SMC_Msk
	Start of Matrix Cycle.
#define	FDCAN_TTIR_CSM_Pos   (2U)
#define	FDCAN_TTIR_CSM_Msk   (0x1UL << FDCAN_TTIR_CSM_Pos)
	0x00000004
#define	FDCAN_TTIR_CSM   FDCAN_TTIR_CSM_Msk
	Change of Synchronization Mode.
#define	FDCAN_TTIR_SOG_Pos   (3U)
#define	FDCAN_TTIR_SOG_Msk   (0x1UL << FDCAN_TTIR_SOG_Pos)
	0x00000008
#define	FDCAN_TTIR_SOG   FDCAN_TTIR_SOG_Msk
	Start of Gap.
#define	FDCAN_TTIR_RTMI_Pos   (4U)
#define	FDCAN_TTIR_RTMI_Msk   (0x1UL << FDCAN_TTIR_RTMI_Pos)
	0x00000010
#define	FDCAN_TTIR_RTMI   FDCAN_TTIR_RTMI_Msk
	Register Time Mark Interrupt.
#define	FDCAN_TTIR_TTMI_Pos   (5U)
#define	FDCAN_TTIR_TTMI_Msk   (0x1UL << FDCAN_TTIR_TTMI_Pos)
	0x00000020
#define	FDCAN_TTIR_TTMI   FDCAN_TTIR_TTMI_Msk
	Trigger Time Mark Event Internal.
#define	FDCAN_TTIR_SWE_Pos   (6U)
#define	FDCAN_TTIR_SWE_Msk   (0x1UL << FDCAN_TTIR_SWE_Pos)
	0x00000040
#define	FDCAN_TTIR_SWE   FDCAN_TTIR_SWE_Msk
	Stop Watch Event.
#define	FDCAN_TTIR_GTW_Pos   (7U)
#define	FDCAN_TTIR_GTW_Msk   (0x1UL << FDCAN_TTIR_GTW_Pos)
	0x00000080
#define	FDCAN_TTIR_GTW   FDCAN_TTIR_GTW_Msk
	Global Time Wrap.
#define	FDCAN_TTIR_GTD_Pos   (8U)
#define	FDCAN_TTIR_GTD_Msk   (0x1UL << FDCAN_TTIR_GTD_Pos)
	0x00000100
#define	FDCAN_TTIR_GTD   FDCAN_TTIR_GTD_Msk
	Global Time Discontinuity.
#define	FDCAN_TTIR_GTE_Pos   (9U)
#define	FDCAN_TTIR_GTE_Msk   (0x1UL << FDCAN_TTIR_GTE_Pos)
	0x00000200
#define	FDCAN_TTIR_GTE   FDCAN_TTIR_GTE_Msk
	Global Time Error.
#define	FDCAN_TTIR_TXU_Pos   (10U)
#define	FDCAN_TTIR_TXU_Msk   (0x1UL << FDCAN_TTIR_TXU_Pos)
	0x00000400
#define	FDCAN_TTIR_TXU   FDCAN_TTIR_TXU_Msk
	Tx Count Underflow.
#define	FDCAN_TTIR_TXO_Pos   (11U)
#define	FDCAN_TTIR_TXO_Msk   (0x1UL << FDCAN_TTIR_TXO_Pos)
	0x00000800
#define	FDCAN_TTIR_TXO   FDCAN_TTIR_TXO_Msk
	Tx Count Overflow.
#define	FDCAN_TTIR_SE1_Pos   (12U)
#define	FDCAN_TTIR_SE1_Msk   (0x1UL << FDCAN_TTIR_SE1_Pos)
	0x00001000
#define	FDCAN_TTIR_SE1   FDCAN_TTIR_SE1_Msk
	Scheduling Error 1.
#define	FDCAN_TTIR_SE2_Pos   (13U)
#define	FDCAN_TTIR_SE2_Msk   (0x1UL << FDCAN_TTIR_SE2_Pos)
	0x00002000
#define	FDCAN_TTIR_SE2   FDCAN_TTIR_SE2_Msk
	Scheduling Error 2.
#define	FDCAN_TTIR_ELC_Pos   (14U)
#define	FDCAN_TTIR_ELC_Msk   (0x1UL << FDCAN_TTIR_ELC_Pos)
	0x00004000
#define	FDCAN_TTIR_ELC   FDCAN_TTIR_ELC_Msk
	Error Level Changed.
#define	FDCAN_TTIR_IWT_Pos   (15U)
#define	FDCAN_TTIR_IWT_Msk   (0x1UL << FDCAN_TTIR_IWT_Pos)
	0x00008000
#define	FDCAN_TTIR_IWT   FDCAN_TTIR_IWT_Msk
	Initialization Watch Trigger.
#define	FDCAN_TTIR_WT_Pos   (16U)
#define	FDCAN_TTIR_WT_Msk   (0x1UL << FDCAN_TTIR_WT_Pos)
	0x00010000
#define	FDCAN_TTIR_WT   FDCAN_TTIR_WT_Msk
	Watch Trigger.
#define	FDCAN_TTIR_AW_Pos   (17U)
#define	FDCAN_TTIR_AW_Msk   (0x1UL << FDCAN_TTIR_AW_Pos)
	0x00020000
#define	FDCAN_TTIR_AW   FDCAN_TTIR_AW_Msk
	Application Watchdog.
#define	FDCAN_TTIR_CER_Pos   (18U)
#define	FDCAN_TTIR_CER_Msk   (0x1UL << FDCAN_TTIR_CER_Pos)
	0x00040000
#define	FDCAN_TTIR_CER   FDCAN_TTIR_CER_Msk
	Configuration Error.
#define	FDCAN_TTIE_SBCE_Pos   (0U)
#define	FDCAN_TTIE_SBCE_Msk   (0x1UL << FDCAN_TTIE_SBCE_Pos)
	0x00000001
#define	FDCAN_TTIE_SBCE   FDCAN_TTIE_SBCE_Msk
	Start of Basic Cycle Interrupt Enable.
#define	FDCAN_TTIE_SMCE_Pos   (1U)
#define	FDCAN_TTIE_SMCE_Msk   (0x1UL << FDCAN_TTIE_SMCE_Pos)
	0x00000002
#define	FDCAN_TTIE_SMCE   FDCAN_TTIE_SMCE_Msk
	Start of Matrix Cycle Interrupt Enable.
#define	FDCAN_TTIE_CSME_Pos   (2U)
#define	FDCAN_TTIE_CSME_Msk   (0x1UL << FDCAN_TTIE_CSME_Pos)
	0x00000004
#define	FDCAN_TTIE_CSME   FDCAN_TTIE_CSME_Msk
	Change of Synchronization Mode Interrupt Enable.
#define	FDCAN_TTIE_SOGE_Pos   (3U)
#define	FDCAN_TTIE_SOGE_Msk   (0x1UL << FDCAN_TTIE_SOGE_Pos)
	0x00000008
#define	FDCAN_TTIE_SOGE   FDCAN_TTIE_SOGE_Msk
	Start of Gap Interrupt Enable.
#define	FDCAN_TTIE_RTMIE_Pos   (4U)
#define	FDCAN_TTIE_RTMIE_Msk   (0x1UL << FDCAN_TTIE_RTMIE_Pos)
	0x00000010
#define	FDCAN_TTIE_RTMIE   FDCAN_TTIE_RTMIE_Msk
	Register Time Mark Interrupt Interrupt Enable.
#define	FDCAN_TTIE_TTMIE_Pos   (5U)
#define	FDCAN_TTIE_TTMIE_Msk   (0x1UL << FDCAN_TTIE_TTMIE_Pos)
	0x00000020
#define	FDCAN_TTIE_TTMIE   FDCAN_TTIE_TTMIE_Msk
	Trigger Time Mark Event Internal Interrupt Enable.
#define	FDCAN_TTIE_SWEE_Pos   (6U)
#define	FDCAN_TTIE_SWEE_Msk   (0x1UL << FDCAN_TTIE_SWEE_Pos)
	0x00000040
#define	FDCAN_TTIE_SWEE   FDCAN_TTIE_SWEE_Msk
	Stop Watch Event Interrupt Enable.
#define	FDCAN_TTIE_GTWE_Pos   (7U)
#define	FDCAN_TTIE_GTWE_Msk   (0x1UL << FDCAN_TTIE_GTWE_Pos)
	0x00000080
#define	FDCAN_TTIE_GTWE   FDCAN_TTIE_GTWE_Msk
	Global Time Wrap Interrupt Enable.
#define	FDCAN_TTIE_GTDE_Pos   (8U)
#define	FDCAN_TTIE_GTDE_Msk   (0x1UL << FDCAN_TTIE_GTDE_Pos)
	0x00000100
#define	FDCAN_TTIE_GTDE   FDCAN_TTIE_GTDE_Msk
	Global Time Discontinuity Interrupt Enable.
#define	FDCAN_TTIE_GTEE_Pos   (9U)
#define	FDCAN_TTIE_GTEE_Msk   (0x1UL << FDCAN_TTIE_GTEE_Pos)
	0x00000200
#define	FDCAN_TTIE_GTEE   FDCAN_TTIE_GTEE_Msk
	Global Time Error Interrupt Enable.
#define	FDCAN_TTIE_TXUE_Pos   (10U)
#define	FDCAN_TTIE_TXUE_Msk   (0x1UL << FDCAN_TTIE_TXUE_Pos)
	0x00000400
#define	FDCAN_TTIE_TXUE   FDCAN_TTIE_TXUE_Msk
	Tx Count Underflow Interrupt Enable.
#define	FDCAN_TTIE_TXOE_Pos   (11U)
#define	FDCAN_TTIE_TXOE_Msk   (0x1UL << FDCAN_TTIE_TXOE_Pos)
	0x00000800
#define	FDCAN_TTIE_TXOE   FDCAN_TTIE_TXOE_Msk
	Tx Count Overflow Interrupt Enable.
#define	FDCAN_TTIE_SE1E_Pos   (12U)
#define	FDCAN_TTIE_SE1E_Msk   (0x1UL << FDCAN_TTIE_SE1E_Pos)
	0x00001000
#define	FDCAN_TTIE_SE1E   FDCAN_TTIE_SE1E_Msk
	Scheduling Error 1 Interrupt Enable.
#define	FDCAN_TTIE_SE2E_Pos   (13U)
#define	FDCAN_TTIE_SE2E_Msk   (0x1UL << FDCAN_TTIE_SE2E_Pos)
	0x00002000
#define	FDCAN_TTIE_SE2E   FDCAN_TTIE_SE2E_Msk
	Scheduling Error 2 Interrupt Enable.
#define	FDCAN_TTIE_ELCE_Pos   (14U)
#define	FDCAN_TTIE_ELCE_Msk   (0x1UL << FDCAN_TTIE_ELCE_Pos)
	0x00004000
#define	FDCAN_TTIE_ELCE   FDCAN_TTIE_ELCE_Msk
	Error Level Changed Interrupt Enable.
#define	FDCAN_TTIE_IWTE_Pos   (15U)
#define	FDCAN_TTIE_IWTE_Msk   (0x1UL << FDCAN_TTIE_IWTE_Pos)
	0x00008000
#define	FDCAN_TTIE_IWTE   FDCAN_TTIE_IWTE_Msk
	Initialization Watch Trigger Interrupt Enable.
#define	FDCAN_TTIE_WTE_Pos   (16U)
#define	FDCAN_TTIE_WTE_Msk   (0x1UL << FDCAN_TTIE_WTE_Pos)
	0x00010000
#define	FDCAN_TTIE_WTE   FDCAN_TTIE_WTE_Msk
	Watch Trigger Interrupt Enable.
#define	FDCAN_TTIE_AWE_Pos   (17U)
#define	FDCAN_TTIE_AWE_Msk   (0x1UL << FDCAN_TTIE_AWE_Pos)
	0x00020000
#define	FDCAN_TTIE_AWE   FDCAN_TTIE_AWE_Msk
	Application Watchdog Interrupt Enable.
#define	FDCAN_TTIE_CERE_Pos   (18U)
#define	FDCAN_TTIE_CERE_Msk   (0x1UL << FDCAN_TTIE_CERE_Pos)
	0x00040000
#define	FDCAN_TTIE_CERE   FDCAN_TTIE_CERE_Msk
	Configuration Error Interrupt Enable.
#define	FDCAN_TTILS_SBCS_Pos   (0U)
#define	FDCAN_TTILS_SBCS_Msk   (0x1UL << FDCAN_TTILS_SBCS_Pos)
	0x00000001
#define	FDCAN_TTILS_SBCS   FDCAN_TTILS_SBCS_Msk
	Start of Basic Cycle Interrupt Line.
#define	FDCAN_TTILS_SMCS_Pos   (1U)
#define	FDCAN_TTILS_SMCS_Msk   (0x1UL << FDCAN_TTILS_SMCS_Pos)
	0x00000002
#define	FDCAN_TTILS_SMCS   FDCAN_TTILS_SMCS_Msk
	Start of Matrix Cycle Interrupt Line.
#define	FDCAN_TTILS_CSMS_Pos   (2U)
#define	FDCAN_TTILS_CSMS_Msk   (0x1UL << FDCAN_TTILS_CSMS_Pos)
	0x00000004
#define	FDCAN_TTILS_CSMS   FDCAN_TTILS_CSMS_Msk
	Change of Synchronization Mode Interrupt Line.
#define	FDCAN_TTILS_SOGS_Pos   (3U)
#define	FDCAN_TTILS_SOGS_Msk   (0x1UL << FDCAN_TTILS_SOGS_Pos)
	0x00000008
#define	FDCAN_TTILS_SOGS   FDCAN_TTILS_SOGS_Msk
	Start of Gap Interrupt Line.
#define	FDCAN_TTILS_RTMIS_Pos   (4U)
#define	FDCAN_TTILS_RTMIS_Msk   (0x1UL << FDCAN_TTILS_RTMIS_Pos)
	0x00000010
#define	FDCAN_TTILS_RTMIS   FDCAN_TTILS_RTMIS_Msk
	Register Time Mark Interrupt Interrupt Line.
#define	FDCAN_TTILS_TTMIS_Pos   (5U)
#define	FDCAN_TTILS_TTMIS_Msk   (0x1UL << FDCAN_TTILS_TTMIS_Pos)
	0x00000020
#define	FDCAN_TTILS_TTMIS   FDCAN_TTILS_TTMIS_Msk
	Trigger Time Mark Event Internal Interrupt Line.
#define	FDCAN_TTILS_SWES_Pos   (6U)
#define	FDCAN_TTILS_SWES_Msk   (0x1UL << FDCAN_TTILS_SWES_Pos)
	0x00000040
#define	FDCAN_TTILS_SWES   FDCAN_TTILS_SWES_Msk
	Stop Watch Event Interrupt Line.
#define	FDCAN_TTILS_GTWS_Pos   (7U)
#define	FDCAN_TTILS_GTWS_Msk   (0x1UL << FDCAN_TTILS_GTWS_Pos)
	0x00000080
#define	FDCAN_TTILS_GTWS   FDCAN_TTILS_GTWS_Msk
	Global Time Wrap Interrupt Line.
#define	FDCAN_TTILS_GTDS_Pos   (8U)
#define	FDCAN_TTILS_GTDS_Msk   (0x1UL << FDCAN_TTILS_GTDS_Pos)
	0x00000100
#define	FDCAN_TTILS_GTDS   FDCAN_TTILS_GTDS_Msk
	Global Time Discontinuity Interrupt Line.
#define	FDCAN_TTILS_GTES_Pos   (9U)
#define	FDCAN_TTILS_GTES_Msk   (0x1UL << FDCAN_TTILS_GTES_Pos)
	0x00000200
#define	FDCAN_TTILS_GTES   FDCAN_TTILS_GTES_Msk
	Global Time Error Interrupt Line.
#define	FDCAN_TTILS_TXUS_Pos   (10U)
#define	FDCAN_TTILS_TXUS_Msk   (0x1UL << FDCAN_TTILS_TXUS_Pos)
	0x00000400
#define	FDCAN_TTILS_TXUS   FDCAN_TTILS_TXUS_Msk
	Tx Count Underflow Interrupt Line.
#define	FDCAN_TTILS_TXOS_Pos   (11U)
#define	FDCAN_TTILS_TXOS_Msk   (0x1UL << FDCAN_TTILS_TXOS_Pos)
	0x00000800
#define	FDCAN_TTILS_TXOS   FDCAN_TTILS_TXOS_Msk
	Tx Count Overflow Interrupt Line.
#define	FDCAN_TTILS_SE1S_Pos   (12U)
#define	FDCAN_TTILS_SE1S_Msk   (0x1UL << FDCAN_TTILS_SE1S_Pos)
	0x00001000
#define	FDCAN_TTILS_SE1S   FDCAN_TTILS_SE1S_Msk
	Scheduling Error 1 Interrupt Line.
#define	FDCAN_TTILS_SE2S_Pos   (13U)
#define	FDCAN_TTILS_SE2S_Msk   (0x1UL << FDCAN_TTILS_SE2S_Pos)
	0x00002000
#define	FDCAN_TTILS_SE2S   FDCAN_TTILS_SE2S_Msk
	Scheduling Error 2 Interrupt Line.
#define	FDCAN_TTILS_ELCS_Pos   (14U)
#define	FDCAN_TTILS_ELCS_Msk   (0x1UL << FDCAN_TTILS_ELCS_Pos)
	0x00004000
#define	FDCAN_TTILS_ELCS   FDCAN_TTILS_ELCS_Msk
	Error Level Changed Interrupt Line.
#define	FDCAN_TTILS_IWTS_Pos   (15U)
#define	FDCAN_TTILS_IWTS_Msk   (0x1UL << FDCAN_TTILS_IWTS_Pos)
	0x00008000
#define	FDCAN_TTILS_IWTS   FDCAN_TTILS_IWTS_Msk
	Initialization Watch Trigger Interrupt Line.
#define	FDCAN_TTILS_WTS_Pos   (16U)
#define	FDCAN_TTILS_WTS_Msk   (0x1UL << FDCAN_TTILS_WTS_Pos)
	0x00010000
#define	FDCAN_TTILS_WTS   FDCAN_TTILS_WTS_Msk
	Watch Trigger Interrupt Line.
#define	FDCAN_TTILS_AWS_Pos   (17U)
#define	FDCAN_TTILS_AWS_Msk   (0x1UL << FDCAN_TTILS_AWS_Pos)
	0x00020000
#define	FDCAN_TTILS_AWS   FDCAN_TTILS_AWS_Msk
	Application Watchdog Interrupt Line.
#define	FDCAN_TTILS_CERS_Pos   (18U)
#define	FDCAN_TTILS_CERS_Msk   (0x1UL << FDCAN_TTILS_CERS_Pos)
	0x00040000
#define	FDCAN_TTILS_CERS   FDCAN_TTILS_CERS_Msk
	Configuration Error Interrupt Line.
#define	FDCAN_TTOST_EL_Pos   (0U)
#define	FDCAN_TTOST_EL_Msk   (0x3UL << FDCAN_TTOST_EL_Pos)
	0x00000003
#define	FDCAN_TTOST_EL   FDCAN_TTOST_EL_Msk
	Error Level.
#define	FDCAN_TTOST_MS_Pos   (2U)
#define	FDCAN_TTOST_MS_Msk   (0x3UL << FDCAN_TTOST_MS_Pos)
	0x0000000C
#define	FDCAN_TTOST_MS   FDCAN_TTOST_MS_Msk
	Master State.
#define	FDCAN_TTOST_SYS_Pos   (4U)
#define	FDCAN_TTOST_SYS_Msk   (0x3UL << FDCAN_TTOST_SYS_Pos)
	0x00000030
#define	FDCAN_TTOST_SYS   FDCAN_TTOST_SYS_Msk
	Synchronization State.
#define	FDCAN_TTOST_QGTP_Pos   (6U)
#define	FDCAN_TTOST_QGTP_Msk   (0x1UL << FDCAN_TTOST_QGTP_Pos)
	0x00000040
#define	FDCAN_TTOST_QGTP   FDCAN_TTOST_QGTP_Msk
	Quality of Global Time Phase.
#define	FDCAN_TTOST_QCS_Pos   (7U)
#define	FDCAN_TTOST_QCS_Msk   (0x1UL << FDCAN_TTOST_QCS_Pos)
	0x00000080
#define	FDCAN_TTOST_QCS   FDCAN_TTOST_QCS_Msk
	Quality of Clock Speed.
#define	FDCAN_TTOST_RTO_Pos   (8U)
#define	FDCAN_TTOST_RTO_Msk   (0xFFUL << FDCAN_TTOST_RTO_Pos)
	0x0000FF00
#define	FDCAN_TTOST_RTO   FDCAN_TTOST_RTO_Msk
	Reference Trigger Offset.
#define	FDCAN_TTOST_WGTD_Pos   (22U)
#define	FDCAN_TTOST_WGTD_Msk   (0x1UL << FDCAN_TTOST_WGTD_Pos)
	0x00400000
#define	FDCAN_TTOST_WGTD   FDCAN_TTOST_WGTD_Msk
	Wait for Global Time Discontinuity.
#define	FDCAN_TTOST_GFI_Pos   (23U)
#define	FDCAN_TTOST_GFI_Msk   (0x1UL << FDCAN_TTOST_GFI_Pos)
	0x00800000
#define	FDCAN_TTOST_GFI   FDCAN_TTOST_GFI_Msk
	Gap Finished Indicator.
#define	FDCAN_TTOST_TMP_Pos   (24U)
#define	FDCAN_TTOST_TMP_Msk   (0x7UL << FDCAN_TTOST_TMP_Pos)
	0x07000000
#define	FDCAN_TTOST_TMP   FDCAN_TTOST_TMP_Msk
	Time Master Priority.
#define	FDCAN_TTOST_GSI_Pos   (27U)
#define	FDCAN_TTOST_GSI_Msk   (0x1UL << FDCAN_TTOST_GSI_Pos)
	0x08000000
#define	FDCAN_TTOST_GSI   FDCAN_TTOST_GSI_Msk
	Gap Started Indicator.
#define	FDCAN_TTOST_WFE_Pos   (28U)
#define	FDCAN_TTOST_WFE_Msk   (0x1UL << FDCAN_TTOST_WFE_Pos)
	0x10000000
#define	FDCAN_TTOST_WFE   FDCAN_TTOST_WFE_Msk
	Wait for Event.
#define	FDCAN_TTOST_AWE_Pos   (29U)
#define	FDCAN_TTOST_AWE_Msk   (0x1UL << FDCAN_TTOST_AWE_Pos)
	0x20000000
#define	FDCAN_TTOST_AWE   FDCAN_TTOST_AWE_Msk
	Application Watchdog Event.
#define	FDCAN_TTOST_WECS_Pos   (30U)
#define	FDCAN_TTOST_WECS_Msk   (0x1UL << FDCAN_TTOST_WECS_Pos)
	0x40000000
#define	FDCAN_TTOST_WECS   FDCAN_TTOST_WECS_Msk
	Wait for External Clock Synchronization.
#define	FDCAN_TTOST_SPL_Pos   (31U)
#define	FDCAN_TTOST_SPL_Msk   (0x1UL << FDCAN_TTOST_SPL_Pos)
	0x80000000
#define	FDCAN_TTOST_SPL   FDCAN_TTOST_SPL_Msk
	Schedule Phase Lock.
#define	FDCAN_TURNA_NAV_Pos   (0U)
#define	FDCAN_TURNA_NAV_Msk   (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)
	0x0003FFFF
#define	FDCAN_TURNA_NAV   FDCAN_TURNA_NAV_Msk
	Numerator Actual Value.
#define	FDCAN_TTLGT_LT_Pos   (0U)
#define	FDCAN_TTLGT_LT_Msk   (0xFFFFUL << FDCAN_TTLGT_LT_Pos)
	0x0000FFFF
#define	FDCAN_TTLGT_LT   FDCAN_TTLGT_LT_Msk
	Local Time.
#define	FDCAN_TTLGT_GT_Pos   (16U)
#define	FDCAN_TTLGT_GT_Msk   (0xFFFFUL << FDCAN_TTLGT_GT_Pos)
	0xFFFF0000
#define	FDCAN_TTLGT_GT   FDCAN_TTLGT_GT_Msk
	Global Time.
#define	FDCAN_TTCTC_CT_Pos   (0U)
#define	FDCAN_TTCTC_CT_Msk   (0xFFFFUL << FDCAN_TTCTC_CT_Pos)
	0x0000FFFF
#define	FDCAN_TTCTC_CT   FDCAN_TTCTC_CT_Msk
	Cycle Time.
#define	FDCAN_TTCTC_CC_Pos   (16U)
#define	FDCAN_TTCTC_CC_Msk   (0x3FUL << FDCAN_TTCTC_CC_Pos)
	0x003F0000
#define	FDCAN_TTCTC_CC   FDCAN_TTCTC_CC_Msk
	Cycle Count.
#define	FDCAN_TTCPT_CCV_Pos   (0U)
#define	FDCAN_TTCPT_CCV_Msk   (0x3FUL << FDCAN_TTCPT_CCV_Pos)
	0x0000003F
#define	FDCAN_TTCPT_CCV   FDCAN_TTCPT_CCV_Msk
	Cycle Count Value.
#define	FDCAN_TTCPT_SWV_Pos   (16U)
#define	FDCAN_TTCPT_SWV_Msk   (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)
	0xFFFF0000
#define	FDCAN_TTCPT_SWV   FDCAN_TTCPT_SWV_Msk
	Stop Watch Value.
#define	FDCAN_TTCSM_CSM_Pos   (0U)
#define	FDCAN_TTCSM_CSM_Msk   (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)
	0x0000FFFF
#define	FDCAN_TTCSM_CSM   FDCAN_TTCSM_CSM_Msk
	Cycle Sync Mark.
#define	FDCAN_TTTS_SWTSEL_Pos   (0U)
#define	FDCAN_TTTS_SWTSEL_Msk   (0x3UL << FDCAN_TTTS_SWTSEL_Pos)
	0x00000003
#define	FDCAN_TTTS_SWTSEL   FDCAN_TTTS_SWTSEL_Msk
	Stop watch trigger input selection.
#define	FDCAN_TTTS_EVTSEL_Pos   (4U)
#define	FDCAN_TTTS_EVTSEL_Msk   (0x3UL << FDCAN_TTTS_EVTSEL_Pos)
	0x00000030
#define	FDCAN_TTTS_EVTSEL   FDCAN_TTTS_EVTSEL_Msk
	Event trigger input selection.
#define	FDCANCCU_CREL_DAY_Pos   (0U)
#define	FDCANCCU_CREL_DAY_Msk   (0xFFUL << FDCANCCU_CREL_DAY_Pos)
	0x000000FF
#define	FDCANCCU_CREL_DAY   FDCANCCU_CREL_DAY_Msk
	Timestamp Day.
#define	FDCANCCU_CREL_MON_Pos   (8U)
#define	FDCANCCU_CREL_MON_Msk   (0xFFUL << FDCANCCU_CREL_MON_Pos)
	0x0000FF00
#define	FDCANCCU_CREL_MON   FDCANCCU_CREL_MON_Msk
	Timestamp Month.
#define	FDCANCCU_CREL_YEAR_Pos   (16U)
#define	FDCANCCU_CREL_YEAR_Msk   (0xFUL << FDCANCCU_CREL_YEAR_Pos)
	0x000F0000
#define	FDCANCCU_CREL_YEAR   FDCANCCU_CREL_YEAR_Msk
	Timestamp Year.
#define	FDCANCCU_CREL_SUBSTEP_Pos   (20U)
#define	FDCANCCU_CREL_SUBSTEP_Msk   (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)
	0x00F00000
#define	FDCANCCU_CREL_SUBSTEP   FDCANCCU_CREL_SUBSTEP_Msk
	Sub-step of Core release.
#define	FDCANCCU_CREL_STEP_Pos   (24U)
#define	FDCANCCU_CREL_STEP_Msk   (0xFUL << FDCANCCU_CREL_STEP_Pos)
	0x0F000000
#define	FDCANCCU_CREL_STEP   FDCANCCU_CREL_STEP_Msk
	Step of Core release.
#define	FDCANCCU_CREL_REL_Pos   (28U)
#define	FDCANCCU_CREL_REL_Msk   (0xFUL << FDCANCCU_CREL_REL_Pos)
	0xF0000000
#define	FDCANCCU_CREL_REL   FDCANCCU_CREL_REL_Msk
	Core release.
#define	FDCANCCU_CCFG_TQBT_Pos   (0U)
#define	FDCANCCU_CCFG_TQBT_Msk   (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)
	0x0000001F
#define	FDCANCCU_CCFG_TQBT   FDCANCCU_CCFG_TQBT_Msk
	Time Quanta per Bit Time.
#define	FDCANCCU_CCFG_BCC_Pos   (6U)
#define	FDCANCCU_CCFG_BCC_Msk   (0x1UL << FDCANCCU_CCFG_BCC_Pos)
	0x00000040
#define	FDCANCCU_CCFG_BCC   FDCANCCU_CCFG_BCC_Msk
	Bypass Clock Calibration.
#define	FDCANCCU_CCFG_CFL_Pos   (7U)
#define	FDCANCCU_CCFG_CFL_Msk   (0x1UL << FDCANCCU_CCFG_CFL_Pos)
	0x00000080
#define	FDCANCCU_CCFG_CFL   FDCANCCU_CCFG_CFL_Msk
	Calibration Field Length.
#define	FDCANCCU_CCFG_OCPM_Pos   (8U)
#define	FDCANCCU_CCFG_OCPM_Msk   (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)
	0x0000FF00
#define	FDCANCCU_CCFG_OCPM   FDCANCCU_CCFG_OCPM_Msk
	Oscillator Clock Periods Minimum.
#define	FDCANCCU_CCFG_CDIV_Pos   (16U)
#define	FDCANCCU_CCFG_CDIV_Msk   (0xFUL << FDCANCCU_CCFG_CDIV_Pos)
	0x000F0000
#define	FDCANCCU_CCFG_CDIV   FDCANCCU_CCFG_CDIV_Msk
	Clock Divider.
#define	FDCANCCU_CCFG_SWR_Pos   (31U)
#define	FDCANCCU_CCFG_SWR_Msk   (0x1UL << FDCANCCU_CCFG_SWR_Pos)
	0x80000000
#define	FDCANCCU_CCFG_SWR   FDCANCCU_CCFG_SWR_Msk
	Software Reset.
#define	FDCANCCU_CSTAT_OCPC_Pos   (0U)
#define	FDCANCCU_CSTAT_OCPC_Msk   (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)
	0x0003FFFF
#define	FDCANCCU_CSTAT_OCPC   FDCANCCU_CSTAT_OCPC_Msk
	Oscillator Clock Period Counter.
#define	FDCANCCU_CSTAT_TQC_Pos   (18U)
#define	FDCANCCU_CSTAT_TQC_Msk   (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)
	0x1FFC0000
#define	FDCANCCU_CSTAT_TQC   FDCANCCU_CSTAT_TQC_Msk
	Time Quanta Counter.
#define	FDCANCCU_CSTAT_CALS_Pos   (30U)
#define	FDCANCCU_CSTAT_CALS_Msk   (0x3UL << FDCANCCU_CSTAT_CALS_Pos)
	0xC0000000
#define	FDCANCCU_CSTAT_CALS   FDCANCCU_CSTAT_CALS_Msk
	Calibration State.
#define	FDCANCCU_CWD_WDC_Pos   (0U)
#define	FDCANCCU_CWD_WDC_Msk   (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)
	0x0000FFFF
#define	FDCANCCU_CWD_WDC   FDCANCCU_CWD_WDC_Msk
	Watchdog Configuration.
#define	FDCANCCU_CWD_WDV_Pos   (16U)
#define	FDCANCCU_CWD_WDV_Msk   (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)
	0xFFFF0000
#define	FDCANCCU_CWD_WDV   FDCANCCU_CWD_WDV_Msk
	Watchdog Value.
#define	FDCANCCU_IR_CWE_Pos   (0U)
#define	FDCANCCU_IR_CWE_Msk   (0x1UL << FDCANCCU_IR_CWE_Pos)
	0x00000001
#define	FDCANCCU_IR_CWE   FDCANCCU_IR_CWE_Msk
	Calibration Watchdog Event.
#define	FDCANCCU_IR_CSC_Pos   (1U)
#define	FDCANCCU_IR_CSC_Msk   (0x1UL << FDCANCCU_IR_CSC_Pos)
	0x00000002
#define	FDCANCCU_IR_CSC   FDCANCCU_IR_CSC_Msk
	Calibration State Changed.
#define	FDCANCCU_IE_CWEE_Pos   (0U)
#define	FDCANCCU_IE_CWEE_Msk   (0x1UL << FDCANCCU_IE_CWEE_Pos)
	0x00000001
#define	FDCANCCU_IE_CWEE   FDCANCCU_IE_CWEE_Msk
	Calibration Watchdog Event Enable.
#define	FDCANCCU_IE_CSCE_Pos   (1U)
#define	FDCANCCU_IE_CSCE_Msk   (0x1UL << FDCANCCU_IE_CSCE_Pos)
	0x00000002
#define	FDCANCCU_IE_CSCE   FDCANCCU_IE_CSCE_Msk
	Calibration State Changed Enable.
#define	CEC_CR_CECEN_Pos   (0U)
#define	CEC_CR_CECEN_Msk   (0x1UL << CEC_CR_CECEN_Pos)
	0x00000001
#define	CEC_CR_CECEN   CEC_CR_CECEN_Msk
	CEC Enable.
#define	CEC_CR_TXSOM_Pos   (1U)
#define	CEC_CR_TXSOM_Msk   (0x1UL << CEC_CR_TXSOM_Pos)
	0x00000002
#define	CEC_CR_TXSOM   CEC_CR_TXSOM_Msk
	CEC Tx Start Of Message.
#define	CEC_CR_TXEOM_Pos   (2U)
#define	CEC_CR_TXEOM_Msk   (0x1UL << CEC_CR_TXEOM_Pos)
	0x00000004
#define	CEC_CR_TXEOM   CEC_CR_TXEOM_Msk
	CEC Tx End Of Message.
#define	CEC_CFGR_SFT_Pos   (0U)
#define	CEC_CFGR_SFT_Msk   (0x7UL << CEC_CFGR_SFT_Pos)
	0x00000007
#define	CEC_CFGR_SFT   CEC_CFGR_SFT_Msk
	CEC Signal Free Time.
#define	CEC_CFGR_RXTOL_Pos   (3U)
#define	CEC_CFGR_RXTOL_Msk   (0x1UL << CEC_CFGR_RXTOL_Pos)
	0x00000008
#define	CEC_CFGR_RXTOL   CEC_CFGR_RXTOL_Msk
	CEC Tolerance.
#define	CEC_CFGR_BRESTP_Pos   (4U)
#define	CEC_CFGR_BRESTP_Msk   (0x1UL << CEC_CFGR_BRESTP_Pos)
	0x00000010
#define	CEC_CFGR_BRESTP   CEC_CFGR_BRESTP_Msk
	CEC Rx Stop.
#define	CEC_CFGR_BREGEN_Pos   (5U)
#define	CEC_CFGR_BREGEN_Msk   (0x1UL << CEC_CFGR_BREGEN_Pos)
	0x00000020
#define	CEC_CFGR_BREGEN   CEC_CFGR_BREGEN_Msk
	CEC Bit Rising Error generation.
#define	CEC_CFGR_LBPEGEN_Pos   (6U)
#define	CEC_CFGR_LBPEGEN_Msk   (0x1UL << CEC_CFGR_LBPEGEN_Pos)
	0x00000040
#define	CEC_CFGR_LBPEGEN   CEC_CFGR_LBPEGEN_Msk
	CEC Long Bit Period Error generation.
#define	CEC_CFGR_SFTOPT_Pos   (8U)
#define	CEC_CFGR_SFTOPT_Msk   (0x1UL << CEC_CFGR_SFTOPT_Pos)
	0x00000100
#define	CEC_CFGR_SFTOPT   CEC_CFGR_SFTOPT_Msk
	CEC Signal Free Time optional.
#define	CEC_CFGR_BRDNOGEN_Pos   (7U)
#define	CEC_CFGR_BRDNOGEN_Msk   (0x1UL << CEC_CFGR_BRDNOGEN_Pos)
	0x00000080
#define	CEC_CFGR_BRDNOGEN   CEC_CFGR_BRDNOGEN_Msk
	CEC Broadcast No error generation.
#define	CEC_CFGR_OAR_Pos   (16U)
#define	CEC_CFGR_OAR_Msk   (0x7FFFUL << CEC_CFGR_OAR_Pos)
	0x7FFF0000
#define	CEC_CFGR_OAR   CEC_CFGR_OAR_Msk
	CEC Own Address.
#define	CEC_CFGR_LSTN_Pos   (31U)
#define	CEC_CFGR_LSTN_Msk   (0x1UL << CEC_CFGR_LSTN_Pos)
	0x80000000
#define	CEC_CFGR_LSTN   CEC_CFGR_LSTN_Msk
	CEC Listen mode.
#define	CEC_TXDR_TXD_Pos   (0U)
#define	CEC_TXDR_TXD_Msk   (0xFFUL << CEC_TXDR_TXD_Pos)
	0x000000FF
#define	CEC_TXDR_TXD   CEC_TXDR_TXD_Msk
	CEC Tx Data.
#define	CEC_RXDR_RXD_Pos   (0U)
#define	CEC_RXDR_RXD_Msk   (0xFFUL << CEC_RXDR_RXD_Pos)
	0x000000FF
#define	CEC_RXDR_RXD   CEC_RXDR_RXD_Msk
	CEC Rx Data.
#define	CEC_ISR_RXBR_Pos   (0U)
#define	CEC_ISR_RXBR_Msk   (0x1UL << CEC_ISR_RXBR_Pos)
	0x00000001
#define	CEC_ISR_RXBR   CEC_ISR_RXBR_Msk
	CEC Rx-Byte Received.
#define	CEC_ISR_RXEND_Pos   (1U)
#define	CEC_ISR_RXEND_Msk   (0x1UL << CEC_ISR_RXEND_Pos)
	0x00000002
#define	CEC_ISR_RXEND   CEC_ISR_RXEND_Msk
	CEC End Of Reception.
#define	CEC_ISR_RXOVR_Pos   (2U)
#define	CEC_ISR_RXOVR_Msk   (0x1UL << CEC_ISR_RXOVR_Pos)
	0x00000004
#define	CEC_ISR_RXOVR   CEC_ISR_RXOVR_Msk
	CEC Rx-Overrun.
#define	CEC_ISR_BRE_Pos   (3U)
#define	CEC_ISR_BRE_Msk   (0x1UL << CEC_ISR_BRE_Pos)
	0x00000008
#define	CEC_ISR_BRE   CEC_ISR_BRE_Msk
	CEC Rx Bit Rising Error.
#define	CEC_ISR_SBPE_Pos   (4U)
#define	CEC_ISR_SBPE_Msk   (0x1UL << CEC_ISR_SBPE_Pos)
	0x00000010
#define	CEC_ISR_SBPE   CEC_ISR_SBPE_Msk
	CEC Rx Short Bit period Error.
#define	CEC_ISR_LBPE_Pos   (5U)
#define	CEC_ISR_LBPE_Msk   (0x1UL << CEC_ISR_LBPE_Pos)
	0x00000020
#define	CEC_ISR_LBPE   CEC_ISR_LBPE_Msk
	CEC Rx Long Bit period Error.
#define	CEC_ISR_RXACKE_Pos   (6U)
#define	CEC_ISR_RXACKE_Msk   (0x1UL << CEC_ISR_RXACKE_Pos)
	0x00000040
#define	CEC_ISR_RXACKE   CEC_ISR_RXACKE_Msk
	CEC Rx Missing Acknowledge.
#define	CEC_ISR_ARBLST_Pos   (7U)
#define	CEC_ISR_ARBLST_Msk   (0x1UL << CEC_ISR_ARBLST_Pos)
	0x00000080
#define	CEC_ISR_ARBLST   CEC_ISR_ARBLST_Msk
	CEC Arbitration Lost.
#define	CEC_ISR_TXBR_Pos   (8U)
#define	CEC_ISR_TXBR_Msk   (0x1UL << CEC_ISR_TXBR_Pos)
	0x00000100
#define	CEC_ISR_TXBR   CEC_ISR_TXBR_Msk
	CEC Tx Byte Request.
#define	CEC_ISR_TXEND_Pos   (9U)
#define	CEC_ISR_TXEND_Msk   (0x1UL << CEC_ISR_TXEND_Pos)
	0x00000200
#define	CEC_ISR_TXEND   CEC_ISR_TXEND_Msk
	CEC End of Transmission.
#define	CEC_ISR_TXUDR_Pos   (10U)
#define	CEC_ISR_TXUDR_Msk   (0x1UL << CEC_ISR_TXUDR_Pos)
	0x00000400
#define	CEC_ISR_TXUDR   CEC_ISR_TXUDR_Msk
	CEC Tx-Buffer Underrun.
#define	CEC_ISR_TXERR_Pos   (11U)
#define	CEC_ISR_TXERR_Msk   (0x1UL << CEC_ISR_TXERR_Pos)
	0x00000800
#define	CEC_ISR_TXERR   CEC_ISR_TXERR_Msk
	CEC Tx-Error.
#define	CEC_ISR_TXACKE_Pos   (12U)
#define	CEC_ISR_TXACKE_Msk   (0x1UL << CEC_ISR_TXACKE_Pos)
	0x00001000
#define	CEC_ISR_TXACKE   CEC_ISR_TXACKE_Msk
	CEC Tx Missing Acknowledge.
#define	CEC_IER_RXBRIE_Pos   (0U)
#define	CEC_IER_RXBRIE_Msk   (0x1UL << CEC_IER_RXBRIE_Pos)
	0x00000001
#define	CEC_IER_RXBRIE   CEC_IER_RXBRIE_Msk
	CEC Rx-Byte Received IT Enable.
#define	CEC_IER_RXENDIE_Pos   (1U)
#define	CEC_IER_RXENDIE_Msk   (0x1UL << CEC_IER_RXENDIE_Pos)
	0x00000002
#define	CEC_IER_RXENDIE   CEC_IER_RXENDIE_Msk
	CEC End Of Reception IT Enable.
#define	CEC_IER_RXOVRIE_Pos   (2U)
#define	CEC_IER_RXOVRIE_Msk   (0x1UL << CEC_IER_RXOVRIE_Pos)
	0x00000004
#define	CEC_IER_RXOVRIE   CEC_IER_RXOVRIE_Msk
	CEC Rx-Overrun IT Enable.
#define	CEC_IER_BREIE_Pos   (3U)
#define	CEC_IER_BREIE_Msk   (0x1UL << CEC_IER_BREIE_Pos)
	0x00000008
#define	CEC_IER_BREIE   CEC_IER_BREIE_Msk
	CEC Rx Bit Rising Error IT Enable.
#define	CEC_IER_SBPEIE_Pos   (4U)
#define	CEC_IER_SBPEIE_Msk   (0x1UL << CEC_IER_SBPEIE_Pos)
	0x00000010
#define	CEC_IER_SBPEIE   CEC_IER_SBPEIE_Msk
	CEC Rx Short Bit period Error IT Enable.
#define	CEC_IER_LBPEIE_Pos   (5U)
#define	CEC_IER_LBPEIE_Msk   (0x1UL << CEC_IER_LBPEIE_Pos)
	0x00000020
#define	CEC_IER_LBPEIE   CEC_IER_LBPEIE_Msk
	CEC Rx Long Bit period Error IT Enable.
#define	CEC_IER_RXACKEIE_Pos   (6U)
#define	CEC_IER_RXACKEIE_Msk   (0x1UL << CEC_IER_RXACKEIE_Pos)
	0x00000040
#define	CEC_IER_RXACKEIE   CEC_IER_RXACKEIE_Msk
	CEC Rx Missing Acknowledge IT Enable.
#define	CEC_IER_ARBLSTIE_Pos   (7U)
#define	CEC_IER_ARBLSTIE_Msk   (0x1UL << CEC_IER_ARBLSTIE_Pos)
	0x00000080
#define	CEC_IER_ARBLSTIE   CEC_IER_ARBLSTIE_Msk
	CEC Arbitration Lost IT Enable.
#define	CEC_IER_TXBRIE_Pos   (8U)
#define	CEC_IER_TXBRIE_Msk   (0x1UL << CEC_IER_TXBRIE_Pos)
	0x00000100
#define	CEC_IER_TXBRIE   CEC_IER_TXBRIE_Msk
	CEC Tx Byte Request IT Enable.
#define	CEC_IER_TXENDIE_Pos   (9U)
#define	CEC_IER_TXENDIE_Msk   (0x1UL << CEC_IER_TXENDIE_Pos)
	0x00000200
#define	CEC_IER_TXENDIE   CEC_IER_TXENDIE_Msk
	CEC End of Transmission IT Enable.
#define	CEC_IER_TXUDRIE_Pos   (10U)
#define	CEC_IER_TXUDRIE_Msk   (0x1UL << CEC_IER_TXUDRIE_Pos)
	0x00000400
#define	CEC_IER_TXUDRIE   CEC_IER_TXUDRIE_Msk
	CEC Tx-Buffer Underrun IT Enable.
#define	CEC_IER_TXERRIE_Pos   (11U)
#define	CEC_IER_TXERRIE_Msk   (0x1UL << CEC_IER_TXERRIE_Pos)
	0x00000800
#define	CEC_IER_TXERRIE   CEC_IER_TXERRIE_Msk
	CEC Tx-Error IT Enable.
#define	CEC_IER_TXACKEIE_Pos   (12U)
#define	CEC_IER_TXACKEIE_Msk   (0x1UL << CEC_IER_TXACKEIE_Pos)
	0x00001000
#define	CEC_IER_TXACKEIE   CEC_IER_TXACKEIE_Msk
	CEC Tx Missing Acknowledge IT Enable.
#define	CORDIC_CSR_FUNC_Pos   (0U)
#define	CORDIC_CSR_FUNC_Msk   (0xFUL << CORDIC_CSR_FUNC_Pos)
	0x0000000F
#define	CORDIC_CSR_FUNC   CORDIC_CSR_FUNC_Msk
	Function.
#define	CORDIC_CSR_FUNC_0   (0x1UL << CORDIC_CSR_FUNC_Pos)
	0x00000001
#define	CORDIC_CSR_FUNC_1   (0x2UL << CORDIC_CSR_FUNC_Pos)
	0x00000002
#define	CORDIC_CSR_FUNC_2   (0x4UL << CORDIC_CSR_FUNC_Pos)
	0x00000004
#define	CORDIC_CSR_FUNC_3   (0x8UL << CORDIC_CSR_FUNC_Pos)
	0x00000008
#define	CORDIC_CSR_PRECISION_Pos   (4U)
#define	CORDIC_CSR_PRECISION_Msk   (0xFUL << CORDIC_CSR_PRECISION_Pos)
	0x000000F0
#define	CORDIC_CSR_PRECISION   CORDIC_CSR_PRECISION_Msk
	Precision.
#define	CORDIC_CSR_PRECISION_0   (0x1UL << CORDIC_CSR_PRECISION_Pos)
	0x00000010
#define	CORDIC_CSR_PRECISION_1   (0x2UL << CORDIC_CSR_PRECISION_Pos)
	0x00000020
#define	CORDIC_CSR_PRECISION_2   (0x4UL << CORDIC_CSR_PRECISION_Pos)
	0x00000040
#define	CORDIC_CSR_PRECISION_3   (0x8UL << CORDIC_CSR_PRECISION_Pos)
	0x00000080
#define	CORDIC_CSR_SCALE_Pos   (8U)
#define	CORDIC_CSR_SCALE_Msk   (0x7UL << CORDIC_CSR_SCALE_Pos)
	0x00000700
#define	CORDIC_CSR_SCALE   CORDIC_CSR_SCALE_Msk
	Scaling factor.
#define	CORDIC_CSR_SCALE_0   (0x1UL << CORDIC_CSR_SCALE_Pos)
	0x00000100
#define	CORDIC_CSR_SCALE_1   (0x2UL << CORDIC_CSR_SCALE_Pos)
	0x00000200
#define	CORDIC_CSR_SCALE_2   (0x4UL << CORDIC_CSR_SCALE_Pos)
	0x00000400
#define	CORDIC_CSR_IEN_Pos   (16U)
#define	CORDIC_CSR_IEN_Msk   (0x1UL << CORDIC_CSR_IEN_Pos)
	0x00010000
#define	CORDIC_CSR_IEN   CORDIC_CSR_IEN_Msk
	Interrupt Enable.
#define	CORDIC_CSR_DMAREN_Pos   (17U)
#define	CORDIC_CSR_DMAREN_Msk   (0x1UL << CORDIC_CSR_DMAREN_Pos)
	0x00020000
#define	CORDIC_CSR_DMAREN   CORDIC_CSR_DMAREN_Msk
	DMA Read channel Enable.
#define	CORDIC_CSR_DMAWEN_Pos   (18U)
#define	CORDIC_CSR_DMAWEN_Msk   (0x1UL << CORDIC_CSR_DMAWEN_Pos)
	0x00040000
#define	CORDIC_CSR_DMAWEN   CORDIC_CSR_DMAWEN_Msk
	DMA Write channel Enable.
#define	CORDIC_CSR_NRES_Pos   (19U)
#define	CORDIC_CSR_NRES_Msk   (0x1UL << CORDIC_CSR_NRES_Pos)
	0x00080000
#define	CORDIC_CSR_NRES   CORDIC_CSR_NRES_Msk
	Number of results in WDATA register.
#define	CORDIC_CSR_NARGS_Pos   (20U)
#define	CORDIC_CSR_NARGS_Msk   (0x1UL << CORDIC_CSR_NARGS_Pos)
	0x00100000
#define	CORDIC_CSR_NARGS   CORDIC_CSR_NARGS_Msk
	Number of arguments in RDATA register.
#define	CORDIC_CSR_RESSIZE_Pos   (21U)
#define	CORDIC_CSR_RESSIZE_Msk   (0x1UL << CORDIC_CSR_RESSIZE_Pos)
	0x00200000
#define	CORDIC_CSR_RESSIZE   CORDIC_CSR_RESSIZE_Msk
	Width of output data.
#define	CORDIC_CSR_ARGSIZE_Pos   (22U)
#define	CORDIC_CSR_ARGSIZE_Msk   (0x1UL << CORDIC_CSR_ARGSIZE_Pos)
	0x00400000
#define	CORDIC_CSR_ARGSIZE   CORDIC_CSR_ARGSIZE_Msk
	Width of input data.
#define	CORDIC_CSR_RRDY_Pos   (31U)
#define	CORDIC_CSR_RRDY_Msk   (0x1UL << CORDIC_CSR_RRDY_Pos)
	0x80000000
#define	CORDIC_CSR_RRDY   CORDIC_CSR_RRDY_Msk
	Result Ready Flag.
#define	CORDIC_WDATA_ARG_Pos   (0U)
#define	CORDIC_WDATA_ARG_Msk   (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos)
	0xFFFFFFFF
#define	CORDIC_WDATA_ARG   CORDIC_WDATA_ARG_Msk
	Input Argument.
#define	CORDIC_RDATA_RES_Pos   (0U)
#define	CORDIC_RDATA_RES_Msk   (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos)
	0xFFFFFFFF
#define	CORDIC_RDATA_RES   CORDIC_RDATA_RES_Msk
	Output Result.
#define	CRC_DR_DR_Pos   (0U)
#define	CRC_DR_DR_Msk   (0xFFFFFFFFUL << CRC_DR_DR_Pos)
	0xFFFFFFFF
#define	CRC_DR_DR   CRC_DR_DR_Msk
	Data register bits.
#define	CRC_IDR_IDR_Pos   (0U)
#define	CRC_IDR_IDR_Msk   (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)
	0xFFFFFFFF
#define	CRC_IDR_IDR   CRC_IDR_IDR_Msk
	General-purpose 32-bit data register bits.
#define	CRC_CR_RESET_Pos   (0U)
#define	CRC_CR_RESET_Msk   (0x1UL << CRC_CR_RESET_Pos)
	0x00000001
#define	CRC_CR_RESET   CRC_CR_RESET_Msk
	RESET the CRC computation unit bit.
#define	CRC_CR_POLYSIZE_Pos   (3U)
#define	CRC_CR_POLYSIZE_Msk   (0x3UL << CRC_CR_POLYSIZE_Pos)
	0x00000018
#define	CRC_CR_POLYSIZE   CRC_CR_POLYSIZE_Msk
	Polynomial size bits.
#define	CRC_CR_POLYSIZE_0   (0x1UL << CRC_CR_POLYSIZE_Pos)
	0x00000008
#define	CRC_CR_POLYSIZE_1   (0x2UL << CRC_CR_POLYSIZE_Pos)
	0x00000010
#define	CRC_CR_REV_IN_Pos   (5U)
#define	CRC_CR_REV_IN_Msk   (0x3UL << CRC_CR_REV_IN_Pos)
	0x00000060
#define	CRC_CR_REV_IN   CRC_CR_REV_IN_Msk
	REV_IN Reverse Input Data bits.
#define	CRC_CR_REV_IN_0   (0x1UL << CRC_CR_REV_IN_Pos)
	0x00000020
#define	CRC_CR_REV_IN_1   (0x2UL << CRC_CR_REV_IN_Pos)
	0x00000040
#define	CRC_CR_REV_OUT_Pos   (7U)
#define	CRC_CR_REV_OUT_Msk   (0x1UL << CRC_CR_REV_OUT_Pos)
	0x00000080
#define	CRC_CR_REV_OUT   CRC_CR_REV_OUT_Msk
	REV_OUT Reverse Output Data bits.
#define	CRC_INIT_INIT_Pos   (0U)
#define	CRC_INIT_INIT_Msk   (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)
	0xFFFFFFFF
#define	CRC_INIT_INIT   CRC_INIT_INIT_Msk
	Initial CRC value bits.
#define	CRC_POL_POL_Pos   (0U)
#define	CRC_POL_POL_Msk   (0xFFFFFFFFUL << CRC_POL_POL_Pos)
	0xFFFFFFFF
#define	CRC_POL_POL   CRC_POL_POL_Msk
	Coefficients of the polynomial.
#define	CRS_CR_SYNCOKIE_Pos   (0U)
#define	CRS_CR_SYNCOKIE_Msk   (0x1UL << CRS_CR_SYNCOKIE_Pos)
	0x00000001
#define	CRS_CR_SYNCOKIE   CRS_CR_SYNCOKIE_Msk
	SYNC event OK interrupt enable.
#define	CRS_CR_SYNCWARNIE_Pos   (1U)
#define	CRS_CR_SYNCWARNIE_Msk   (0x1UL << CRS_CR_SYNCWARNIE_Pos)
	0x00000002
#define	CRS_CR_SYNCWARNIE   CRS_CR_SYNCWARNIE_Msk
	SYNC warning interrupt enable.
#define	CRS_CR_ERRIE_Pos   (2U)
#define	CRS_CR_ERRIE_Msk   (0x1UL << CRS_CR_ERRIE_Pos)
	0x00000004
#define	CRS_CR_ERRIE   CRS_CR_ERRIE_Msk
	SYNC error or trimming error interrupt enable.
#define	CRS_CR_ESYNCIE_Pos   (3U)
#define	CRS_CR_ESYNCIE_Msk   (0x1UL << CRS_CR_ESYNCIE_Pos)
	0x00000008
#define	CRS_CR_ESYNCIE   CRS_CR_ESYNCIE_Msk
	Expected SYNC interrupt enable.
#define	CRS_CR_CEN_Pos   (5U)
#define	CRS_CR_CEN_Msk   (0x1UL << CRS_CR_CEN_Pos)
	0x00000020
#define	CRS_CR_CEN   CRS_CR_CEN_Msk
	Frequency error counter enable.
#define	CRS_CR_AUTOTRIMEN_Pos   (6U)
#define	CRS_CR_AUTOTRIMEN_Msk   (0x1UL << CRS_CR_AUTOTRIMEN_Pos)
	0x00000040
#define	CRS_CR_AUTOTRIMEN   CRS_CR_AUTOTRIMEN_Msk
	Automatic trimming enable.
#define	CRS_CR_SWSYNC_Pos   (7U)
#define	CRS_CR_SWSYNC_Msk   (0x1UL << CRS_CR_SWSYNC_Pos)
	0x00000080
#define	CRS_CR_SWSYNC   CRS_CR_SWSYNC_Msk
	Generate software SYNC event.
#define	CRS_CR_TRIM_Pos   (8U)
#define	CRS_CR_TRIM_Msk   (0x3FUL << CRS_CR_TRIM_Pos)
	0x00003F00
#define	CRS_CR_TRIM   CRS_CR_TRIM_Msk
	HSI48 oscillator smooth trimming.
#define	CRS_CFGR_RELOAD_Pos   (0U)
#define	CRS_CFGR_RELOAD_Msk   (0xFFFFUL << CRS_CFGR_RELOAD_Pos)
	0x0000FFFF
#define	CRS_CFGR_RELOAD   CRS_CFGR_RELOAD_Msk
	Counter reload value.
#define	CRS_CFGR_FELIM_Pos   (16U)
#define	CRS_CFGR_FELIM_Msk   (0xFFUL << CRS_CFGR_FELIM_Pos)
	0x00FF0000
#define	CRS_CFGR_FELIM   CRS_CFGR_FELIM_Msk
	Frequency error limit.
#define	CRS_CFGR_SYNCDIV_Pos   (24U)
#define	CRS_CFGR_SYNCDIV_Msk   (0x7UL << CRS_CFGR_SYNCDIV_Pos)
	0x07000000
#define	CRS_CFGR_SYNCDIV   CRS_CFGR_SYNCDIV_Msk
	SYNC divider.
#define	CRS_CFGR_SYNCDIV_0   (0x1UL << CRS_CFGR_SYNCDIV_Pos)
	0x01000000
#define	CRS_CFGR_SYNCDIV_1   (0x2UL << CRS_CFGR_SYNCDIV_Pos)
	0x02000000
#define	CRS_CFGR_SYNCDIV_2   (0x4UL << CRS_CFGR_SYNCDIV_Pos)
	0x04000000
#define	CRS_CFGR_SYNCSRC_Pos   (28U)
#define	CRS_CFGR_SYNCSRC_Msk   (0x3UL << CRS_CFGR_SYNCSRC_Pos)
	0x30000000
#define	CRS_CFGR_SYNCSRC   CRS_CFGR_SYNCSRC_Msk
	SYNC signal source selection.
#define	CRS_CFGR_SYNCSRC_0   (0x1UL << CRS_CFGR_SYNCSRC_Pos)
	0x10000000
#define	CRS_CFGR_SYNCSRC_1   (0x2UL << CRS_CFGR_SYNCSRC_Pos)
	0x20000000
#define	CRS_CFGR_SYNCPOL_Pos   (31U)
#define	CRS_CFGR_SYNCPOL_Msk   (0x1UL << CRS_CFGR_SYNCPOL_Pos)
	0x80000000
#define	CRS_CFGR_SYNCPOL   CRS_CFGR_SYNCPOL_Msk
	SYNC polarity selection.
#define	CRS_ISR_SYNCOKF_Pos   (0U)
#define	CRS_ISR_SYNCOKF_Msk   (0x1UL << CRS_ISR_SYNCOKF_Pos)
	0x00000001
#define	CRS_ISR_SYNCOKF   CRS_ISR_SYNCOKF_Msk
	SYNC event OK flag.
#define	CRS_ISR_SYNCWARNF_Pos   (1U)
#define	CRS_ISR_SYNCWARNF_Msk   (0x1UL << CRS_ISR_SYNCWARNF_Pos)
	0x00000002
#define	CRS_ISR_SYNCWARNF   CRS_ISR_SYNCWARNF_Msk
	SYNC warning flag.
#define	CRS_ISR_ERRF_Pos   (2U)
#define	CRS_ISR_ERRF_Msk   (0x1UL << CRS_ISR_ERRF_Pos)
	0x00000004
#define	CRS_ISR_ERRF   CRS_ISR_ERRF_Msk
	Error flag.
#define	CRS_ISR_ESYNCF_Pos   (3U)
#define	CRS_ISR_ESYNCF_Msk   (0x1UL << CRS_ISR_ESYNCF_Pos)
	0x00000008
#define	CRS_ISR_ESYNCF   CRS_ISR_ESYNCF_Msk
	Expected SYNC flag.
#define	CRS_ISR_SYNCERR_Pos   (8U)
#define	CRS_ISR_SYNCERR_Msk   (0x1UL << CRS_ISR_SYNCERR_Pos)
	0x00000100
#define	CRS_ISR_SYNCERR   CRS_ISR_SYNCERR_Msk
	SYNC error.
#define	CRS_ISR_SYNCMISS_Pos   (9U)
#define	CRS_ISR_SYNCMISS_Msk   (0x1UL << CRS_ISR_SYNCMISS_Pos)
	0x00000200
#define	CRS_ISR_SYNCMISS   CRS_ISR_SYNCMISS_Msk
	SYNC missed.
#define	CRS_ISR_TRIMOVF_Pos   (10U)
#define	CRS_ISR_TRIMOVF_Msk   (0x1UL << CRS_ISR_TRIMOVF_Pos)
	0x00000400
#define	CRS_ISR_TRIMOVF   CRS_ISR_TRIMOVF_Msk
	Trimming overflow or underflow.
#define	CRS_ISR_FEDIR_Pos   (15U)
#define	CRS_ISR_FEDIR_Msk   (0x1UL << CRS_ISR_FEDIR_Pos)
	0x00008000
#define	CRS_ISR_FEDIR   CRS_ISR_FEDIR_Msk
	Frequency error direction.
#define	CRS_ISR_FECAP_Pos   (16U)
#define	CRS_ISR_FECAP_Msk   (0xFFFFUL << CRS_ISR_FECAP_Pos)
	0xFFFF0000
#define	CRS_ISR_FECAP   CRS_ISR_FECAP_Msk
	Frequency error capture.
#define	CRS_ICR_SYNCOKC_Pos   (0U)
#define	CRS_ICR_SYNCOKC_Msk   (0x1UL << CRS_ICR_SYNCOKC_Pos)
	0x00000001
#define	CRS_ICR_SYNCOKC   CRS_ICR_SYNCOKC_Msk
	SYNC event OK clear flag.
#define	CRS_ICR_SYNCWARNC_Pos   (1U)
#define	CRS_ICR_SYNCWARNC_Msk   (0x1UL << CRS_ICR_SYNCWARNC_Pos)
	0x00000002
#define	CRS_ICR_SYNCWARNC   CRS_ICR_SYNCWARNC_Msk
	SYNC warning clear flag.
#define	CRS_ICR_ERRC_Pos   (2U)
#define	CRS_ICR_ERRC_Msk   (0x1UL << CRS_ICR_ERRC_Pos)
	0x00000004
#define	CRS_ICR_ERRC   CRS_ICR_ERRC_Msk
	Error clear flag.
#define	CRS_ICR_ESYNCC_Pos   (3U)
#define	CRS_ICR_ESYNCC_Msk   (0x1UL << CRS_ICR_ESYNCC_Pos)
	0x00000008
#define	CRS_ICR_ESYNCC   CRS_ICR_ESYNCC_Msk
	Expected SYNC clear flag.
#define	DAC_CR_EN1_Pos   (0U)
#define	DAC_CR_EN1_Msk   (0x1UL << DAC_CR_EN1_Pos)
	0x00000001
#define	DAC_CR_EN1   DAC_CR_EN1_Msk
	DAC channel1 enable.
#define	DAC_CR_TEN1_Pos   (1U)
#define	DAC_CR_TEN1_Msk   (0x1UL << DAC_CR_TEN1_Pos)
	0x00000002
#define	DAC_CR_TEN1   DAC_CR_TEN1_Msk
	DAC channel1 Trigger enable.
#define	DAC_CR_TSEL1_Pos   (2U)
#define	DAC_CR_TSEL1_Msk   (0xFUL << DAC_CR_TSEL1_Pos)
	0x0000003C
#define	DAC_CR_TSEL1   DAC_CR_TSEL1_Msk
	TSEL1[2:0] (DAC channel1 Trigger selection).
#define	DAC_CR_TSEL1_0   (0x1UL << DAC_CR_TSEL1_Pos)
	0x00000004
#define	DAC_CR_TSEL1_1   (0x2UL << DAC_CR_TSEL1_Pos)
	0x00000008
#define	DAC_CR_TSEL1_2   (0x4UL << DAC_CR_TSEL1_Pos)
	0x00000010
#define	DAC_CR_TSEL1_3   (0x8UL << DAC_CR_TSEL1_Pos)
	0x00000020
#define	DAC_CR_WAVE1_Pos   (6U)
#define	DAC_CR_WAVE1_Msk   (0x3UL << DAC_CR_WAVE1_Pos)
	0x000000C0
#define	DAC_CR_WAVE1   DAC_CR_WAVE1_Msk
	WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable).
#define	DAC_CR_WAVE1_0   (0x1UL << DAC_CR_WAVE1_Pos)
	0x00000040
#define	DAC_CR_WAVE1_1   (0x2UL << DAC_CR_WAVE1_Pos)
	0x00000080
#define	DAC_CR_MAMP1_Pos   (8U)
#define	DAC_CR_MAMP1_Msk   (0xFUL << DAC_CR_MAMP1_Pos)
	0x00000F00
#define	DAC_CR_MAMP1   DAC_CR_MAMP1_Msk
	MAMP1[3:0] (DAC channel1 Mask/Amplitude selector).
#define	DAC_CR_MAMP1_0   (0x1UL << DAC_CR_MAMP1_Pos)
	0x00000100
#define	DAC_CR_MAMP1_1   (0x2UL << DAC_CR_MAMP1_Pos)
	0x00000200
#define	DAC_CR_MAMP1_2   (0x4UL << DAC_CR_MAMP1_Pos)
	0x00000400
#define	DAC_CR_MAMP1_3   (0x8UL << DAC_CR_MAMP1_Pos)
	0x00000800
#define	DAC_CR_DMAEN1_Pos   (12U)
#define	DAC_CR_DMAEN1_Msk   (0x1UL << DAC_CR_DMAEN1_Pos)
	0x00001000
#define	DAC_CR_DMAEN1   DAC_CR_DMAEN1_Msk
	DAC channel1 DMA enable.
#define	DAC_CR_DMAUDRIE1_Pos   (13U)
#define	DAC_CR_DMAUDRIE1_Msk   (0x1UL << DAC_CR_DMAUDRIE1_Pos)
	0x00002000
#define	DAC_CR_DMAUDRIE1   DAC_CR_DMAUDRIE1_Msk
	DAC channel 1 DMA underrun interrupt enable >.
#define	DAC_CR_CEN1_Pos   (14U)
#define	DAC_CR_CEN1_Msk   (0x1UL << DAC_CR_CEN1_Pos)
	0x00004000
#define	DAC_CR_CEN1   DAC_CR_CEN1_Msk
	DAC channel 1 calibration enable >.
#define	DAC_CR_EN2_Pos   (16U)
#define	DAC_CR_EN2_Msk   (0x1UL << DAC_CR_EN2_Pos)
	0x00010000
#define	DAC_CR_EN2   DAC_CR_EN2_Msk
	DAC channel2 enable.
#define	DAC_CR_TEN2_Pos   (17U)
#define	DAC_CR_TEN2_Msk   (0x1UL << DAC_CR_TEN2_Pos)
	0x00020000
#define	DAC_CR_TEN2   DAC_CR_TEN2_Msk
	DAC channel2 Trigger enable.
#define	DAC_CR_TSEL2_Pos   (18U)
#define	DAC_CR_TSEL2_Msk   (0xFUL << DAC_CR_TSEL2_Pos)
	0x003C0000
#define	DAC_CR_TSEL2   DAC_CR_TSEL2_Msk
	TSEL2[2:0] (DAC channel2 Trigger selection).
#define	DAC_CR_TSEL2_0   (0x1UL << DAC_CR_TSEL2_Pos)
	0x00040000
#define	DAC_CR_TSEL2_1   (0x2UL << DAC_CR_TSEL2_Pos)
	0x00080000
#define	DAC_CR_TSEL2_2   (0x4UL << DAC_CR_TSEL2_Pos)
	0x00100000
#define	DAC_CR_TSEL2_3   (0x8UL << DAC_CR_TSEL2_Pos)
	0x00200000
#define	DAC_CR_WAVE2_Pos   (22U)
#define	DAC_CR_WAVE2_Msk   (0x3UL << DAC_CR_WAVE2_Pos)
	0x00C00000
#define	DAC_CR_WAVE2   DAC_CR_WAVE2_Msk
	WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable).
#define	DAC_CR_WAVE2_0   (0x1UL << DAC_CR_WAVE2_Pos)
	0x00400000
#define	DAC_CR_WAVE2_1   (0x2UL << DAC_CR_WAVE2_Pos)
	0x00800000
#define	DAC_CR_MAMP2_Pos   (24U)
#define	DAC_CR_MAMP2_Msk   (0xFUL << DAC_CR_MAMP2_Pos)
	0x0F000000
#define	DAC_CR_MAMP2   DAC_CR_MAMP2_Msk
	MAMP2[3:0] (DAC channel2 Mask/Amplitude selector).
#define	DAC_CR_MAMP2_0   (0x1UL << DAC_CR_MAMP2_Pos)
	0x01000000
#define	DAC_CR_MAMP2_1   (0x2UL << DAC_CR_MAMP2_Pos)
	0x02000000
#define	DAC_CR_MAMP2_2   (0x4UL << DAC_CR_MAMP2_Pos)
	0x04000000
#define	DAC_CR_MAMP2_3   (0x8UL << DAC_CR_MAMP2_Pos)
	0x08000000
#define	DAC_CR_DMAEN2_Pos   (28U)
#define	DAC_CR_DMAEN2_Msk   (0x1UL << DAC_CR_DMAEN2_Pos)
	0x10000000
#define	DAC_CR_DMAEN2   DAC_CR_DMAEN2_Msk
	DAC channel2 DMA enabled.
#define	DAC_CR_DMAUDRIE2_Pos   (29U)
#define	DAC_CR_DMAUDRIE2_Msk   (0x1UL << DAC_CR_DMAUDRIE2_Pos)
	0x20000000
#define	DAC_CR_DMAUDRIE2   DAC_CR_DMAUDRIE2_Msk
	DAC channel2 DMA underrun interrupt enable >.
#define	DAC_CR_CEN2_Pos   (30U)
#define	DAC_CR_CEN2_Msk   (0x1UL << DAC_CR_CEN2_Pos)
	0x40000000
#define	DAC_CR_CEN2   DAC_CR_CEN2_Msk
	DAC channel2 calibration enable >.
#define	DAC_SWTRIGR_SWTRIG1_Pos   (0U)
#define	DAC_SWTRIGR_SWTRIG1_Msk   (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
	0x00000001
#define	DAC_SWTRIGR_SWTRIG1   DAC_SWTRIGR_SWTRIG1_Msk
	DAC channel1 software trigger.
#define	DAC_SWTRIGR_SWTRIG2_Pos   (1U)
#define	DAC_SWTRIGR_SWTRIG2_Msk   (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
	0x00000002
#define	DAC_SWTRIGR_SWTRIG2   DAC_SWTRIGR_SWTRIG2_Msk
	DAC channel2 software trigger.
#define	DAC_DHR12R1_DACC1DHR_Pos   (0U)
#define	DAC_DHR12R1_DACC1DHR_Msk   (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
	0x00000FFF
#define	DAC_DHR12R1_DACC1DHR   DAC_DHR12R1_DACC1DHR_Msk
	DAC channel1 12-bit Right aligned data.
#define	DAC_DHR12L1_DACC1DHR_Pos   (4U)
#define	DAC_DHR12L1_DACC1DHR_Msk   (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
	0x0000FFF0
#define	DAC_DHR12L1_DACC1DHR   DAC_DHR12L1_DACC1DHR_Msk
	DAC channel1 12-bit Left aligned data.
#define	DAC_DHR8R1_DACC1DHR_Pos   (0U)
#define	DAC_DHR8R1_DACC1DHR_Msk   (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
	0x000000FF
#define	DAC_DHR8R1_DACC1DHR   DAC_DHR8R1_DACC1DHR_Msk
	DAC channel1 8-bit Right aligned data.
#define	DAC_DHR12R2_DACC2DHR_Pos   (0U)
#define	DAC_DHR12R2_DACC2DHR_Msk   (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
	0x00000FFF
#define	DAC_DHR12R2_DACC2DHR   DAC_DHR12R2_DACC2DHR_Msk
	DAC channel2 12-bit Right aligned data.
#define	DAC_DHR12L2_DACC2DHR_Pos   (4U)
#define	DAC_DHR12L2_DACC2DHR_Msk   (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
	0x0000FFF0
#define	DAC_DHR12L2_DACC2DHR   DAC_DHR12L2_DACC2DHR_Msk
	DAC channel2 12-bit Left aligned data.
#define	DAC_DHR8R2_DACC2DHR_Pos   (0U)
#define	DAC_DHR8R2_DACC2DHR_Msk   (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
	0x000000FF
#define	DAC_DHR8R2_DACC2DHR   DAC_DHR8R2_DACC2DHR_Msk
	DAC channel2 8-bit Right aligned data.
#define	DAC_DHR12RD_DACC1DHR_Pos   (0U)
#define	DAC_DHR12RD_DACC1DHR_Msk   (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
	0x00000FFF
#define	DAC_DHR12RD_DACC1DHR   DAC_DHR12RD_DACC1DHR_Msk
	DAC channel1 12-bit Right aligned data.
#define	DAC_DHR12RD_DACC2DHR_Pos   (16U)
#define	DAC_DHR12RD_DACC2DHR_Msk   (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
	0x0FFF0000
#define	DAC_DHR12RD_DACC2DHR   DAC_DHR12RD_DACC2DHR_Msk
	DAC channel2 12-bit Right aligned data.
#define	DAC_DHR12LD_DACC1DHR_Pos   (4U)
#define	DAC_DHR12LD_DACC1DHR_Msk   (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
	0x0000FFF0
#define	DAC_DHR12LD_DACC1DHR   DAC_DHR12LD_DACC1DHR_Msk
	DAC channel1 12-bit Left aligned data.
#define	DAC_DHR12LD_DACC2DHR_Pos   (20U)
#define	DAC_DHR12LD_DACC2DHR_Msk   (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
	0xFFF00000
#define	DAC_DHR12LD_DACC2DHR   DAC_DHR12LD_DACC2DHR_Msk
	DAC channel2 12-bit Left aligned data.
#define	DAC_DHR8RD_DACC1DHR_Pos   (0U)
#define	DAC_DHR8RD_DACC1DHR_Msk   (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
	0x000000FF
#define	DAC_DHR8RD_DACC1DHR   DAC_DHR8RD_DACC1DHR_Msk
	DAC channel1 8-bit Right aligned data.
#define	DAC_DHR8RD_DACC2DHR_Pos   (8U)
#define	DAC_DHR8RD_DACC2DHR_Msk   (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
	0x0000FF00
#define	DAC_DHR8RD_DACC2DHR   DAC_DHR8RD_DACC2DHR_Msk
	DAC channel2 8-bit Right aligned data.
#define	DAC_DOR1_DACC1DOR_Pos   (0U)
#define	DAC_DOR1_DACC1DOR_Msk   (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
	0x00000FFF
#define	DAC_DOR1_DACC1DOR   DAC_DOR1_DACC1DOR_Msk
	DAC channel1 data output.
#define	DAC_DOR2_DACC2DOR_Pos   (0U)
#define	DAC_DOR2_DACC2DOR_Msk   (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
	0x00000FFF
#define	DAC_DOR2_DACC2DOR   DAC_DOR2_DACC2DOR_Msk
	DAC channel2 data output.
#define	DAC_SR_DMAUDR1_Pos   (13U)
#define	DAC_SR_DMAUDR1_Msk   (0x1UL << DAC_SR_DMAUDR1_Pos)
	0x00002000
#define	DAC_SR_DMAUDR1   DAC_SR_DMAUDR1_Msk
	DAC channel1 DMA underrun flag.
#define	DAC_SR_CAL_FLAG1_Pos   (14U)
#define	DAC_SR_CAL_FLAG1_Msk   (0x1UL << DAC_SR_CAL_FLAG1_Pos)
	0x00004000
#define	DAC_SR_CAL_FLAG1   DAC_SR_CAL_FLAG1_Msk
	DAC channel1 calibration offset status.
#define	DAC_SR_BWST1_Pos   (15U)
#define	DAC_SR_BWST1_Msk   (0x4001UL << DAC_SR_BWST1_Pos)
	0x20008000
#define	DAC_SR_BWST1   DAC_SR_BWST1_Msk
	DAC channel1 busy writing sample time flag.
#define	DAC_SR_DMAUDR2_Pos   (29U)
#define	DAC_SR_DMAUDR2_Msk   (0x1UL << DAC_SR_DMAUDR2_Pos)
	0x20000000
#define	DAC_SR_DMAUDR2   DAC_SR_DMAUDR2_Msk
	DAC channel2 DMA underrun flag.
#define	DAC_SR_CAL_FLAG2_Pos   (30U)
#define	DAC_SR_CAL_FLAG2_Msk   (0x1UL << DAC_SR_CAL_FLAG2_Pos)
	0x40000000
#define	DAC_SR_CAL_FLAG2   DAC_SR_CAL_FLAG2_Msk
	DAC channel2 calibration offset status.
#define	DAC_SR_BWST2_Pos   (31U)
#define	DAC_SR_BWST2_Msk   (0x1UL << DAC_SR_BWST2_Pos)
	0x80000000
#define	DAC_SR_BWST2   DAC_SR_BWST2_Msk
	DAC channel2 busy writing sample time flag.
#define	DAC_CCR_OTRIM1_Pos   (0U)
#define	DAC_CCR_OTRIM1_Msk   (0x1FUL << DAC_CCR_OTRIM1_Pos)
	0x0000001F
#define	DAC_CCR_OTRIM1   DAC_CCR_OTRIM1_Msk
	DAC channel1 offset trimming value.
#define	DAC_CCR_OTRIM2_Pos   (16U)
#define	DAC_CCR_OTRIM2_Msk   (0x1FUL << DAC_CCR_OTRIM2_Pos)
	0x001F0000
#define	DAC_CCR_OTRIM2   DAC_CCR_OTRIM2_Msk
	DAC channel2 offset trimming value.
#define	DAC_MCR_MODE1_Pos   (0U)
#define	DAC_MCR_MODE1_Msk   (0x7UL << DAC_MCR_MODE1_Pos)
	0x00000007
#define	DAC_MCR_MODE1   DAC_MCR_MODE1_Msk
	MODE1[2:0] (DAC channel1 mode).
#define	DAC_MCR_MODE1_0   (0x1UL << DAC_MCR_MODE1_Pos)
	0x00000001
#define	DAC_MCR_MODE1_1   (0x2UL << DAC_MCR_MODE1_Pos)
	0x00000002
#define	DAC_MCR_MODE1_2   (0x4UL << DAC_MCR_MODE1_Pos)
	0x00000004
#define	DAC_MCR_MODE2_Pos   (16U)
#define	DAC_MCR_MODE2_Msk   (0x7UL << DAC_MCR_MODE2_Pos)
	0x00070000
#define	DAC_MCR_MODE2   DAC_MCR_MODE2_Msk
	MODE2[2:0] (DAC channel2 mode).
#define	DAC_MCR_MODE2_0   (0x1UL << DAC_MCR_MODE2_Pos)
	0x00010000
#define	DAC_MCR_MODE2_1   (0x2UL << DAC_MCR_MODE2_Pos)
	0x00020000
#define	DAC_MCR_MODE2_2   (0x4UL << DAC_MCR_MODE2_Pos)
	0x00040000
#define	DAC_SHSR1_TSAMPLE1_Pos   (0U)
#define	DAC_SHSR1_TSAMPLE1_Msk   (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)
	0x000003FF
#define	DAC_SHSR1_TSAMPLE1   DAC_SHSR1_TSAMPLE1_Msk
	DAC channel1 sample time.
#define	DAC_SHSR2_TSAMPLE2_Pos   (0U)
#define	DAC_SHSR2_TSAMPLE2_Msk   (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)
	0x000003FF
#define	DAC_SHSR2_TSAMPLE2   DAC_SHSR2_TSAMPLE2_Msk
	DAC channel2 sample time.
#define	DAC_SHHR_THOLD1_Pos   (0U)
#define	DAC_SHHR_THOLD1_Msk   (0x3FFUL << DAC_SHHR_THOLD1_Pos)
	0x000003FF
#define	DAC_SHHR_THOLD1   DAC_SHHR_THOLD1_Msk
	DAC channel1 hold time.
#define	DAC_SHHR_THOLD2_Pos   (16U)
#define	DAC_SHHR_THOLD2_Msk   (0x3FFUL << DAC_SHHR_THOLD2_Pos)
	0x03FF0000
#define	DAC_SHHR_THOLD2   DAC_SHHR_THOLD2_Msk
	DAC channel2 hold time.
#define	DAC_SHRR_TREFRESH1_Pos   (0U)
#define	DAC_SHRR_TREFRESH1_Msk   (0xFFUL << DAC_SHRR_TREFRESH1_Pos)
	0x000000FF
#define	DAC_SHRR_TREFRESH1   DAC_SHRR_TREFRESH1_Msk
	DAC channel1 refresh time.
#define	DAC_SHRR_TREFRESH2_Pos   (16U)
#define	DAC_SHRR_TREFRESH2_Msk   (0xFFUL << DAC_SHRR_TREFRESH2_Pos)
	0x00FF0000
#define	DAC_SHRR_TREFRESH2   DAC_SHRR_TREFRESH2_Msk
	DAC channel2 refresh time.
#define	DCMI_CR_CAPTURE_Pos   (0U)
#define	DCMI_CR_CAPTURE_Msk   (0x1UL << DCMI_CR_CAPTURE_Pos)
	0x00000001
#define	DCMI_CR_CAPTURE   DCMI_CR_CAPTURE_Msk
#define	DCMI_CR_CM_Pos   (1U)
#define	DCMI_CR_CM_Msk   (0x1UL << DCMI_CR_CM_Pos)
	0x00000002
#define	DCMI_CR_CM   DCMI_CR_CM_Msk
#define	DCMI_CR_CROP_Pos   (2U)
#define	DCMI_CR_CROP_Msk   (0x1UL << DCMI_CR_CROP_Pos)
	0x00000004
#define	DCMI_CR_CROP   DCMI_CR_CROP_Msk
#define	DCMI_CR_JPEG_Pos   (3U)
#define	DCMI_CR_JPEG_Msk   (0x1UL << DCMI_CR_JPEG_Pos)
	0x00000008
#define	DCMI_CR_JPEG   DCMI_CR_JPEG_Msk
#define	DCMI_CR_ESS_Pos   (4U)
#define	DCMI_CR_ESS_Msk   (0x1UL << DCMI_CR_ESS_Pos)
	0x00000010
#define	DCMI_CR_ESS   DCMI_CR_ESS_Msk
#define	DCMI_CR_PCKPOL_Pos   (5U)
#define	DCMI_CR_PCKPOL_Msk   (0x1UL << DCMI_CR_PCKPOL_Pos)
	0x00000020
#define	DCMI_CR_PCKPOL   DCMI_CR_PCKPOL_Msk
#define	DCMI_CR_HSPOL_Pos   (6U)
#define	DCMI_CR_HSPOL_Msk   (0x1UL << DCMI_CR_HSPOL_Pos)
	0x00000040
#define	DCMI_CR_HSPOL   DCMI_CR_HSPOL_Msk
#define	DCMI_CR_VSPOL_Pos   (7U)
#define	DCMI_CR_VSPOL_Msk   (0x1UL << DCMI_CR_VSPOL_Pos)
	0x00000080
#define	DCMI_CR_VSPOL   DCMI_CR_VSPOL_Msk
#define	DCMI_CR_FCRC_0   (0x00000100U)
#define	DCMI_CR_FCRC_1   (0x00000200U)
#define	DCMI_CR_EDM_0   (0x00000400U)
#define	DCMI_CR_EDM_1   (0x00000800U)
#define	DCMI_CR_CRE_Pos   (12U)
#define	DCMI_CR_CRE_Msk   (0x1UL << DCMI_CR_CRE_Pos)
	0x00001000
#define	DCMI_CR_CRE   DCMI_CR_CRE_Msk
#define	DCMI_CR_ENABLE_Pos   (14U)
#define	DCMI_CR_ENABLE_Msk   (0x1UL << DCMI_CR_ENABLE_Pos)
	0x00004000
#define	DCMI_CR_ENABLE   DCMI_CR_ENABLE_Msk
#define	DCMI_CR_BSM_Pos   (16U)
#define	DCMI_CR_BSM_Msk   (0x3UL << DCMI_CR_BSM_Pos)
	0x00030000
#define	DCMI_CR_BSM   DCMI_CR_BSM_Msk
#define	DCMI_CR_BSM_0   (0x1UL << DCMI_CR_BSM_Pos)
	0x00010000
#define	DCMI_CR_BSM_1   (0x2UL << DCMI_CR_BSM_Pos)
	0x00020000
#define	DCMI_CR_OEBS_Pos   (18U)
#define	DCMI_CR_OEBS_Msk   (0x1UL << DCMI_CR_OEBS_Pos)
	0x00040000
#define	DCMI_CR_OEBS   DCMI_CR_OEBS_Msk
#define	DCMI_CR_LSM_Pos   (19U)
#define	DCMI_CR_LSM_Msk   (0x1UL << DCMI_CR_LSM_Pos)
	0x00080000
#define	DCMI_CR_LSM   DCMI_CR_LSM_Msk
#define	DCMI_CR_OELS_Pos   (20U)
#define	DCMI_CR_OELS_Msk   (0x1UL << DCMI_CR_OELS_Pos)
	0x00100000
#define	DCMI_CR_OELS   DCMI_CR_OELS_Msk
#define	DCMI_SR_HSYNC_Pos   (0U)
#define	DCMI_SR_HSYNC_Msk   (0x1UL << DCMI_SR_HSYNC_Pos)
	0x00000001
#define	DCMI_SR_HSYNC   DCMI_SR_HSYNC_Msk
#define	DCMI_SR_VSYNC_Pos   (1U)
#define	DCMI_SR_VSYNC_Msk   (0x1UL << DCMI_SR_VSYNC_Pos)
	0x00000002
#define	DCMI_SR_VSYNC   DCMI_SR_VSYNC_Msk
#define	DCMI_SR_FNE_Pos   (2U)
#define	DCMI_SR_FNE_Msk   (0x1UL << DCMI_SR_FNE_Pos)
	0x00000004
#define	DCMI_SR_FNE   DCMI_SR_FNE_Msk
#define	DCMI_RIS_FRAME_RIS_Pos   (0U)
#define	DCMI_RIS_FRAME_RIS_Msk   (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
	0x00000001
#define	DCMI_RIS_FRAME_RIS   DCMI_RIS_FRAME_RIS_Msk
#define	DCMI_RIS_OVR_RIS_Pos   (1U)
#define	DCMI_RIS_OVR_RIS_Msk   (0x1UL << DCMI_RIS_OVR_RIS_Pos)
	0x00000002
#define	DCMI_RIS_OVR_RIS   DCMI_RIS_OVR_RIS_Msk
#define	DCMI_RIS_ERR_RIS_Pos   (2U)
#define	DCMI_RIS_ERR_RIS_Msk   (0x1UL << DCMI_RIS_ERR_RIS_Pos)
	0x00000004
#define	DCMI_RIS_ERR_RIS   DCMI_RIS_ERR_RIS_Msk
#define	DCMI_RIS_VSYNC_RIS_Pos   (3U)
#define	DCMI_RIS_VSYNC_RIS_Msk   (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)
	0x00000008
#define	DCMI_RIS_VSYNC_RIS   DCMI_RIS_VSYNC_RIS_Msk
#define	DCMI_RIS_LINE_RIS_Pos   (4U)
#define	DCMI_RIS_LINE_RIS_Msk   (0x1UL << DCMI_RIS_LINE_RIS_Pos)
	0x00000010
#define	DCMI_RIS_LINE_RIS   DCMI_RIS_LINE_RIS_Msk
#define	DCMI_IER_FRAME_IE_Pos   (0U)
#define	DCMI_IER_FRAME_IE_Msk   (0x1UL << DCMI_IER_FRAME_IE_Pos)
	0x00000001
#define	DCMI_IER_FRAME_IE   DCMI_IER_FRAME_IE_Msk
#define	DCMI_IER_OVR_IE_Pos   (1U)
#define	DCMI_IER_OVR_IE_Msk   (0x1UL << DCMI_IER_OVR_IE_Pos)
	0x00000002
#define	DCMI_IER_OVR_IE   DCMI_IER_OVR_IE_Msk
#define	DCMI_IER_ERR_IE_Pos   (2U)
#define	DCMI_IER_ERR_IE_Msk   (0x1UL << DCMI_IER_ERR_IE_Pos)
	0x00000004
#define	DCMI_IER_ERR_IE   DCMI_IER_ERR_IE_Msk
#define	DCMI_IER_VSYNC_IE_Pos   (3U)
#define	DCMI_IER_VSYNC_IE_Msk   (0x1UL << DCMI_IER_VSYNC_IE_Pos)
	0x00000008
#define	DCMI_IER_VSYNC_IE   DCMI_IER_VSYNC_IE_Msk
#define	DCMI_IER_LINE_IE_Pos   (4U)
#define	DCMI_IER_LINE_IE_Msk   (0x1UL << DCMI_IER_LINE_IE_Pos)
	0x00000010
#define	DCMI_IER_LINE_IE   DCMI_IER_LINE_IE_Msk
#define	DCMI_MIS_FRAME_MIS_Pos   (0U)
#define	DCMI_MIS_FRAME_MIS_Msk   (0x1UL << DCMI_MIS_FRAME_MIS_Pos)
	0x00000001
#define	DCMI_MIS_FRAME_MIS   DCMI_MIS_FRAME_MIS_Msk
#define	DCMI_MIS_OVR_MIS_Pos   (1U)
#define	DCMI_MIS_OVR_MIS_Msk   (0x1UL << DCMI_MIS_OVR_MIS_Pos)
	0x00000002
#define	DCMI_MIS_OVR_MIS   DCMI_MIS_OVR_MIS_Msk
#define	DCMI_MIS_ERR_MIS_Pos   (2U)
#define	DCMI_MIS_ERR_MIS_Msk   (0x1UL << DCMI_MIS_ERR_MIS_Pos)
	0x00000004
#define	DCMI_MIS_ERR_MIS   DCMI_MIS_ERR_MIS_Msk
#define	DCMI_MIS_VSYNC_MIS_Pos   (3U)
#define	DCMI_MIS_VSYNC_MIS_Msk   (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)
	0x00000008
#define	DCMI_MIS_VSYNC_MIS   DCMI_MIS_VSYNC_MIS_Msk
#define	DCMI_MIS_LINE_MIS_Pos   (4U)
#define	DCMI_MIS_LINE_MIS_Msk   (0x1UL << DCMI_MIS_LINE_MIS_Pos)
	0x00000010
#define	DCMI_MIS_LINE_MIS   DCMI_MIS_LINE_MIS_Msk
#define	DCMI_ICR_FRAME_ISC_Pos   (0U)
#define	DCMI_ICR_FRAME_ISC_Msk   (0x1UL << DCMI_ICR_FRAME_ISC_Pos)
	0x00000001
#define	DCMI_ICR_FRAME_ISC   DCMI_ICR_FRAME_ISC_Msk
#define	DCMI_ICR_OVR_ISC_Pos   (1U)
#define	DCMI_ICR_OVR_ISC_Msk   (0x1UL << DCMI_ICR_OVR_ISC_Pos)
	0x00000002
#define	DCMI_ICR_OVR_ISC   DCMI_ICR_OVR_ISC_Msk
#define	DCMI_ICR_ERR_ISC_Pos   (2U)
#define	DCMI_ICR_ERR_ISC_Msk   (0x1UL << DCMI_ICR_ERR_ISC_Pos)
	0x00000004
#define	DCMI_ICR_ERR_ISC   DCMI_ICR_ERR_ISC_Msk
#define	DCMI_ICR_VSYNC_ISC_Pos   (3U)
#define	DCMI_ICR_VSYNC_ISC_Msk   (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)
	0x00000008
#define	DCMI_ICR_VSYNC_ISC   DCMI_ICR_VSYNC_ISC_Msk
#define	DCMI_ICR_LINE_ISC_Pos   (4U)
#define	DCMI_ICR_LINE_ISC_Msk   (0x1UL << DCMI_ICR_LINE_ISC_Pos)
	0x00000010
#define	DCMI_ICR_LINE_ISC   DCMI_ICR_LINE_ISC_Msk
#define	DCMI_ESCR_FSC_Pos   (0U)
#define	DCMI_ESCR_FSC_Msk   (0xFFUL << DCMI_ESCR_FSC_Pos)
	0x000000FF
#define	DCMI_ESCR_FSC   DCMI_ESCR_FSC_Msk
#define	DCMI_ESCR_LSC_Pos   (8U)
#define	DCMI_ESCR_LSC_Msk   (0xFFUL << DCMI_ESCR_LSC_Pos)
	0x0000FF00
#define	DCMI_ESCR_LSC   DCMI_ESCR_LSC_Msk
#define	DCMI_ESCR_LEC_Pos   (16U)
#define	DCMI_ESCR_LEC_Msk   (0xFFUL << DCMI_ESCR_LEC_Pos)
	0x00FF0000
#define	DCMI_ESCR_LEC   DCMI_ESCR_LEC_Msk
#define	DCMI_ESCR_FEC_Pos   (24U)
#define	DCMI_ESCR_FEC_Msk   (0xFFUL << DCMI_ESCR_FEC_Pos)
	0xFF000000
#define	DCMI_ESCR_FEC   DCMI_ESCR_FEC_Msk
#define	DCMI_ESUR_FSU_Pos   (0U)
#define	DCMI_ESUR_FSU_Msk   (0xFFUL << DCMI_ESUR_FSU_Pos)
	0x000000FF
#define	DCMI_ESUR_FSU   DCMI_ESUR_FSU_Msk
#define	DCMI_ESUR_LSU_Pos   (8U)
#define	DCMI_ESUR_LSU_Msk   (0xFFUL << DCMI_ESUR_LSU_Pos)
	0x0000FF00
#define	DCMI_ESUR_LSU   DCMI_ESUR_LSU_Msk
#define	DCMI_ESUR_LEU_Pos   (16U)
#define	DCMI_ESUR_LEU_Msk   (0xFFUL << DCMI_ESUR_LEU_Pos)
	0x00FF0000
#define	DCMI_ESUR_LEU   DCMI_ESUR_LEU_Msk
#define	DCMI_ESUR_FEU_Pos   (24U)
#define	DCMI_ESUR_FEU_Msk   (0xFFUL << DCMI_ESUR_FEU_Pos)
	0xFF000000
#define	DCMI_ESUR_FEU   DCMI_ESUR_FEU_Msk
#define	DCMI_CWSTRT_HOFFCNT_Pos   (0U)
#define	DCMI_CWSTRT_HOFFCNT_Msk   (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)
	0x00003FFF
#define	DCMI_CWSTRT_HOFFCNT   DCMI_CWSTRT_HOFFCNT_Msk
#define	DCMI_CWSTRT_VST_Pos   (16U)
#define	DCMI_CWSTRT_VST_Msk   (0x1FFFUL << DCMI_CWSTRT_VST_Pos)
	0x1FFF0000
#define	DCMI_CWSTRT_VST   DCMI_CWSTRT_VST_Msk
#define	DCMI_CWSIZE_CAPCNT_Pos   (0U)
#define	DCMI_CWSIZE_CAPCNT_Msk   (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)
	0x00003FFF
#define	DCMI_CWSIZE_CAPCNT   DCMI_CWSIZE_CAPCNT_Msk
#define	DCMI_CWSIZE_VLINE_Pos   (16U)
#define	DCMI_CWSIZE_VLINE_Msk   (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)
	0x3FFF0000
#define	DCMI_CWSIZE_VLINE   DCMI_CWSIZE_VLINE_Msk
#define	DCMI_DR_BYTE0_Pos   (0U)
#define	DCMI_DR_BYTE0_Msk   (0xFFUL << DCMI_DR_BYTE0_Pos)
	0x000000FF
#define	DCMI_DR_BYTE0   DCMI_DR_BYTE0_Msk
#define	DCMI_DR_BYTE1_Pos   (8U)
#define	DCMI_DR_BYTE1_Msk   (0xFFUL << DCMI_DR_BYTE1_Pos)
	0x0000FF00
#define	DCMI_DR_BYTE1   DCMI_DR_BYTE1_Msk
#define	DCMI_DR_BYTE2_Pos   (16U)
#define	DCMI_DR_BYTE2_Msk   (0xFFUL << DCMI_DR_BYTE2_Pos)
	0x00FF0000
#define	DCMI_DR_BYTE2   DCMI_DR_BYTE2_Msk
#define	DCMI_DR_BYTE3_Pos   (24U)
#define	DCMI_DR_BYTE3_Msk   (0xFFUL << DCMI_DR_BYTE3_Pos)
	0xFF000000
#define	DCMI_DR_BYTE3   DCMI_DR_BYTE3_Msk
#define	DFSDM_CHCFGR1_DFSDMEN_Pos   (31U)
#define	DFSDM_CHCFGR1_DFSDMEN_Msk   (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)
	0x80000000
#define	DFSDM_CHCFGR1_DFSDMEN   DFSDM_CHCFGR1_DFSDMEN_Msk
	Global enable for DFSDM interface.
#define	DFSDM_CHCFGR1_CKOUTSRC_Pos   (30U)
#define	DFSDM_CHCFGR1_CKOUTSRC_Msk   (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)
	0x40000000
#define	DFSDM_CHCFGR1_CKOUTSRC   DFSDM_CHCFGR1_CKOUTSRC_Msk
	Output serial clock source selection.
#define	DFSDM_CHCFGR1_CKOUTDIV_Pos   (16U)
#define	DFSDM_CHCFGR1_CKOUTDIV_Msk   (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos)
	0x00FF0000
#define	DFSDM_CHCFGR1_CKOUTDIV   DFSDM_CHCFGR1_CKOUTDIV_Msk
	CKOUTDIV[7:0] output serial clock divider.
#define	DFSDM_CHCFGR1_DATPACK_Pos   (14U)
#define	DFSDM_CHCFGR1_DATPACK_Msk   (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)
	0x0000C000
#define	DFSDM_CHCFGR1_DATPACK   DFSDM_CHCFGR1_DATPACK_Msk
	DATPACK[1:0] Data packing mode.
#define	DFSDM_CHCFGR1_DATPACK_1   (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)
	0x00008000
#define	DFSDM_CHCFGR1_DATPACK_0   (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)
	0x00004000
#define	DFSDM_CHCFGR1_DATMPX_Pos   (12U)
#define	DFSDM_CHCFGR1_DATMPX_Msk   (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)
	0x00003000
#define	DFSDM_CHCFGR1_DATMPX   DFSDM_CHCFGR1_DATMPX_Msk
	DATMPX[1:0] Input data multiplexer for channel y.
#define	DFSDM_CHCFGR1_DATMPX_1   (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)
	0x00002000
#define	DFSDM_CHCFGR1_DATMPX_0   (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)
	0x00001000
#define	DFSDM_CHCFGR1_CHINSEL_Pos   (8U)
#define	DFSDM_CHCFGR1_CHINSEL_Msk   (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)
	0x00000100
#define	DFSDM_CHCFGR1_CHINSEL   DFSDM_CHCFGR1_CHINSEL_Msk
	Serial inputs selection for channel y.
#define	DFSDM_CHCFGR1_CHEN_Pos   (7U)
#define	DFSDM_CHCFGR1_CHEN_Msk   (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)
	0x00000080
#define	DFSDM_CHCFGR1_CHEN   DFSDM_CHCFGR1_CHEN_Msk
	Channel y enable.
#define	DFSDM_CHCFGR1_CKABEN_Pos   (6U)
#define	DFSDM_CHCFGR1_CKABEN_Msk   (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)
	0x00000040
#define	DFSDM_CHCFGR1_CKABEN   DFSDM_CHCFGR1_CKABEN_Msk
	Clock absence detector enable on channel y.
#define	DFSDM_CHCFGR1_SCDEN_Pos   (5U)
#define	DFSDM_CHCFGR1_SCDEN_Msk   (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)
	0x00000020
#define	DFSDM_CHCFGR1_SCDEN   DFSDM_CHCFGR1_SCDEN_Msk
	Short circuit detector enable on channel y.
#define	DFSDM_CHCFGR1_SPICKSEL_Pos   (2U)
#define	DFSDM_CHCFGR1_SPICKSEL_Msk   (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
	0x0000000C
#define	DFSDM_CHCFGR1_SPICKSEL   DFSDM_CHCFGR1_SPICKSEL_Msk
	SPICKSEL[1:0] SPI clock select for channel y.
#define	DFSDM_CHCFGR1_SPICKSEL_1   (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
	0x00000008
#define	DFSDM_CHCFGR1_SPICKSEL_0   (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
	0x00000004
#define	DFSDM_CHCFGR1_SITP_Pos   (0U)
#define	DFSDM_CHCFGR1_SITP_Msk   (0x3UL << DFSDM_CHCFGR1_SITP_Pos)
	0x00000003
#define	DFSDM_CHCFGR1_SITP   DFSDM_CHCFGR1_SITP_Msk
	SITP[1:0] Serial interface type for channel y.
#define	DFSDM_CHCFGR1_SITP_1   (0x2UL << DFSDM_CHCFGR1_SITP_Pos)
	0x00000002
#define	DFSDM_CHCFGR1_SITP_0   (0x1UL << DFSDM_CHCFGR1_SITP_Pos)
	0x00000001
#define	DFSDM_CHCFGR2_OFFSET_Pos   (8U)
#define	DFSDM_CHCFGR2_OFFSET_Msk   (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos)
	0xFFFFFF00
#define	DFSDM_CHCFGR2_OFFSET   DFSDM_CHCFGR2_OFFSET_Msk
	OFFSET[23:0] 24-bit calibration offset for channel y.
#define	DFSDM_CHCFGR2_DTRBS_Pos   (3U)
#define	DFSDM_CHCFGR2_DTRBS_Msk   (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)
	0x000000F8
#define	DFSDM_CHCFGR2_DTRBS   DFSDM_CHCFGR2_DTRBS_Msk
	DTRBS[4:0] Data right bit-shift for channel y.
#define	DFSDM_CHAWSCDR_AWFORD_Pos   (22U)
#define	DFSDM_CHAWSCDR_AWFORD_Msk   (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)
	0x00C00000
#define	DFSDM_CHAWSCDR_AWFORD   DFSDM_CHAWSCDR_AWFORD_Msk
	AWFORD[1:0] Analog watchdog Sinc filter order on channel y.
#define	DFSDM_CHAWSCDR_AWFORD_1   (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)
	0x00800000
#define	DFSDM_CHAWSCDR_AWFORD_0   (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)
	0x00400000
#define	DFSDM_CHAWSCDR_AWFOSR_Pos   (16U)
#define	DFSDM_CHAWSCDR_AWFOSR_Msk   (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)
	0x001F0000
#define	DFSDM_CHAWSCDR_AWFOSR   DFSDM_CHAWSCDR_AWFOSR_Msk
	AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y.
#define	DFSDM_CHAWSCDR_BKSCD_Pos   (12U)
#define	DFSDM_CHAWSCDR_BKSCD_Msk   (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)
	0x0000F000
#define	DFSDM_CHAWSCDR_BKSCD   DFSDM_CHAWSCDR_BKSCD_Msk
	BKSCD[3:0] Break signal assignment for short circuit detector on channel y.
#define	DFSDM_CHAWSCDR_SCDT_Pos   (0U)
#define	DFSDM_CHAWSCDR_SCDT_Msk   (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)
	0x000000FF
#define	DFSDM_CHAWSCDR_SCDT   DFSDM_CHAWSCDR_SCDT_Msk
	SCDT[7:0] Short circuit detector threshold for channel y.
#define	DFSDM_CHWDATR_WDATA_Pos   (0U)
#define	DFSDM_CHWDATR_WDATA_Msk   (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)
	0x0000FFFF
#define	DFSDM_CHWDATR_WDATA   DFSDM_CHWDATR_WDATA_Msk
	WDATA[15:0] Input channel y watchdog data.
#define	DFSDM_CHDATINR_INDAT0_Pos   (0U)
#define	DFSDM_CHDATINR_INDAT0_Msk   (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos)
	0x0000FFFF
#define	DFSDM_CHDATINR_INDAT0   DFSDM_CHDATINR_INDAT0_Msk
	INDAT0[31:16] Input data for channel y or channel (y+1).
#define	DFSDM_CHDATINR_INDAT1_Pos   (16U)
#define	DFSDM_CHDATINR_INDAT1_Msk   (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos)
	0xFFFF0000
#define	DFSDM_CHDATINR_INDAT1   DFSDM_CHDATINR_INDAT1_Msk
	INDAT0[15:0] Input data for channel y.
#define	DFSDM_FLTCR1_AWFSEL_Pos   (30U)
#define	DFSDM_FLTCR1_AWFSEL_Msk   (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)
	0x40000000
#define	DFSDM_FLTCR1_AWFSEL   DFSDM_FLTCR1_AWFSEL_Msk
	Analog watchdog fast mode select.
#define	DFSDM_FLTCR1_FAST_Pos   (29U)
#define	DFSDM_FLTCR1_FAST_Msk   (0x1UL << DFSDM_FLTCR1_FAST_Pos)
	0x20000000
#define	DFSDM_FLTCR1_FAST   DFSDM_FLTCR1_FAST_Msk
	Fast conversion mode selection.
#define	DFSDM_FLTCR1_RCH_Pos   (24U)
#define	DFSDM_FLTCR1_RCH_Msk   (0x7UL << DFSDM_FLTCR1_RCH_Pos)
	0x07000000
#define	DFSDM_FLTCR1_RCH   DFSDM_FLTCR1_RCH_Msk
	RCH[2:0] Regular channel selection.
#define	DFSDM_FLTCR1_RDMAEN_Pos   (21U)
#define	DFSDM_FLTCR1_RDMAEN_Msk   (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)
	0x00200000
#define	DFSDM_FLTCR1_RDMAEN   DFSDM_FLTCR1_RDMAEN_Msk
	DMA channel enabled to read data for the regular conversion.
#define	DFSDM_FLTCR1_RSYNC_Pos   (19U)
#define	DFSDM_FLTCR1_RSYNC_Msk   (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)
	0x00080000
#define	DFSDM_FLTCR1_RSYNC   DFSDM_FLTCR1_RSYNC_Msk
	Launch regular conversion synchronously with DFSDMx.
#define	DFSDM_FLTCR1_RCONT_Pos   (18U)
#define	DFSDM_FLTCR1_RCONT_Msk   (0x1UL << DFSDM_FLTCR1_RCONT_Pos)
	0x00040000
#define	DFSDM_FLTCR1_RCONT   DFSDM_FLTCR1_RCONT_Msk
	Continuous mode selection for regular conversions.
#define	DFSDM_FLTCR1_RSWSTART_Pos   (17U)
#define	DFSDM_FLTCR1_RSWSTART_Msk   (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)
	0x00020000
#define	DFSDM_FLTCR1_RSWSTART   DFSDM_FLTCR1_RSWSTART_Msk
	Software start of a conversion on the regular channel.
#define	DFSDM_FLTCR1_JEXTEN_Pos   (13U)
#define	DFSDM_FLTCR1_JEXTEN_Msk   (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)
	0x00006000
#define	DFSDM_FLTCR1_JEXTEN   DFSDM_FLTCR1_JEXTEN_Msk
	JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions.
#define	DFSDM_FLTCR1_JEXTEN_1   (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)
	0x00004000
#define	DFSDM_FLTCR1_JEXTEN_0   (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)
	0x00002000
#define	DFSDM_FLTCR1_JEXTSEL_Pos   (8U)
#define	DFSDM_FLTCR1_JEXTSEL_Msk   (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)
	0x00001F00
#define	DFSDM_FLTCR1_JEXTSEL   DFSDM_FLTCR1_JEXTSEL_Msk
	JEXTSEL[4:0]Trigger signal selection for launching injected conversions.
#define	DFSDM_FLTCR1_JEXTSEL_0   (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)
	0x00000100
#define	DFSDM_FLTCR1_JEXTSEL_1   (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)
	0x00000200
#define	DFSDM_FLTCR1_JEXTSEL_2   (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)
	0x00000400
#define	DFSDM_FLTCR1_JEXTSEL_3   (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)
	0x00000800
#define	DFSDM_FLTCR1_JEXTSEL_4   (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)
	0x00001000
#define	DFSDM_FLTCR1_JDMAEN_Pos   (5U)
#define	DFSDM_FLTCR1_JDMAEN_Msk   (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)
	0x00000020
#define	DFSDM_FLTCR1_JDMAEN   DFSDM_FLTCR1_JDMAEN_Msk
	DMA channel enabled to read data for the injected channel group.
#define	DFSDM_FLTCR1_JSCAN_Pos   (4U)
#define	DFSDM_FLTCR1_JSCAN_Msk   (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)
	0x00000010
#define	DFSDM_FLTCR1_JSCAN   DFSDM_FLTCR1_JSCAN_Msk
	Scanning conversion in continuous mode selection for injected conversions.
#define	DFSDM_FLTCR1_JSYNC_Pos   (3U)
#define	DFSDM_FLTCR1_JSYNC_Msk   (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)
	0x00000008
#define	DFSDM_FLTCR1_JSYNC   DFSDM_FLTCR1_JSYNC_Msk
	Launch an injected conversion synchronously with DFSDMx JSWSTART trigger.
#define	DFSDM_FLTCR1_JSWSTART_Pos   (1U)
#define	DFSDM_FLTCR1_JSWSTART_Msk   (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)
	0x00000002
#define	DFSDM_FLTCR1_JSWSTART   DFSDM_FLTCR1_JSWSTART_Msk
	Start the conversion of the injected group of channels.
#define	DFSDM_FLTCR1_DFEN_Pos   (0U)
#define	DFSDM_FLTCR1_DFEN_Msk   (0x1UL << DFSDM_FLTCR1_DFEN_Pos)
	0x00000001
#define	DFSDM_FLTCR1_DFEN   DFSDM_FLTCR1_DFEN_Msk
	DFSDM enable.
#define	DFSDM_FLTCR2_AWDCH_Pos   (16U)
#define	DFSDM_FLTCR2_AWDCH_Msk   (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)
	0x00FF0000
#define	DFSDM_FLTCR2_AWDCH   DFSDM_FLTCR2_AWDCH_Msk
	AWDCH[7:0] Analog watchdog channel selection.
#define	DFSDM_FLTCR2_EXCH_Pos   (8U)
#define	DFSDM_FLTCR2_EXCH_Msk   (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)
	0x0000FF00
#define	DFSDM_FLTCR2_EXCH   DFSDM_FLTCR2_EXCH_Msk
	EXCH[7:0] Extreme detector channel selection.
#define	DFSDM_FLTCR2_CKABIE_Pos   (6U)
#define	DFSDM_FLTCR2_CKABIE_Msk   (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)
	0x00000040
#define	DFSDM_FLTCR2_CKABIE   DFSDM_FLTCR2_CKABIE_Msk
	Clock absence interrupt enable.
#define	DFSDM_FLTCR2_SCDIE_Pos   (5U)
#define	DFSDM_FLTCR2_SCDIE_Msk   (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)
	0x00000020
#define	DFSDM_FLTCR2_SCDIE   DFSDM_FLTCR2_SCDIE_Msk
	Short circuit detector interrupt enable.
#define	DFSDM_FLTCR2_AWDIE_Pos   (4U)
#define	DFSDM_FLTCR2_AWDIE_Msk   (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)
	0x00000010
#define	DFSDM_FLTCR2_AWDIE   DFSDM_FLTCR2_AWDIE_Msk
	Analog watchdog interrupt enable.
#define	DFSDM_FLTCR2_ROVRIE_Pos   (3U)
#define	DFSDM_FLTCR2_ROVRIE_Msk   (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)
	0x00000008
#define	DFSDM_FLTCR2_ROVRIE   DFSDM_FLTCR2_ROVRIE_Msk
	Regular data overrun interrupt enable.
#define	DFSDM_FLTCR2_JOVRIE_Pos   (2U)
#define	DFSDM_FLTCR2_JOVRIE_Msk   (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)
	0x00000004
#define	DFSDM_FLTCR2_JOVRIE   DFSDM_FLTCR2_JOVRIE_Msk
	Injected data overrun interrupt enable.
#define	DFSDM_FLTCR2_REOCIE_Pos   (1U)
#define	DFSDM_FLTCR2_REOCIE_Msk   (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)
	0x00000002
#define	DFSDM_FLTCR2_REOCIE   DFSDM_FLTCR2_REOCIE_Msk
	Regular end of conversion interrupt enable.
#define	DFSDM_FLTCR2_JEOCIE_Pos   (0U)
#define	DFSDM_FLTCR2_JEOCIE_Msk   (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)
	0x00000001
#define	DFSDM_FLTCR2_JEOCIE   DFSDM_FLTCR2_JEOCIE_Msk
	Injected end of conversion interrupt enable.
#define	DFSDM_FLTISR_SCDF_Pos   (24U)
#define	DFSDM_FLTISR_SCDF_Msk   (0xFFUL << DFSDM_FLTISR_SCDF_Pos)
	0xFF000000
#define	DFSDM_FLTISR_SCDF   DFSDM_FLTISR_SCDF_Msk
	SCDF[7:0] Short circuit detector flag.
#define	DFSDM_FLTISR_CKABF_Pos   (16U)
#define	DFSDM_FLTISR_CKABF_Msk   (0xFFUL << DFSDM_FLTISR_CKABF_Pos)
	0x00FF0000
#define	DFSDM_FLTISR_CKABF   DFSDM_FLTISR_CKABF_Msk
	CKABF[7:0] Clock absence flag.
#define	DFSDM_FLTISR_RCIP_Pos   (14U)
#define	DFSDM_FLTISR_RCIP_Msk   (0x1UL << DFSDM_FLTISR_RCIP_Pos)
	0x00004000
#define	DFSDM_FLTISR_RCIP   DFSDM_FLTISR_RCIP_Msk
	Regular conversion in progress status.
#define	DFSDM_FLTISR_JCIP_Pos   (13U)
#define	DFSDM_FLTISR_JCIP_Msk   (0x1UL << DFSDM_FLTISR_JCIP_Pos)
	0x00002000
#define	DFSDM_FLTISR_JCIP   DFSDM_FLTISR_JCIP_Msk
	Injected conversion in progress status.
#define	DFSDM_FLTISR_AWDF_Pos   (4U)
#define	DFSDM_FLTISR_AWDF_Msk   (0x1UL << DFSDM_FLTISR_AWDF_Pos)
	0x00000010
#define	DFSDM_FLTISR_AWDF   DFSDM_FLTISR_AWDF_Msk
	Analog watchdog.
#define	DFSDM_FLTISR_ROVRF_Pos   (3U)
#define	DFSDM_FLTISR_ROVRF_Msk   (0x1UL << DFSDM_FLTISR_ROVRF_Pos)
	0x00000008
#define	DFSDM_FLTISR_ROVRF   DFSDM_FLTISR_ROVRF_Msk
	Regular conversion overrun flag.
#define	DFSDM_FLTISR_JOVRF_Pos   (2U)
#define	DFSDM_FLTISR_JOVRF_Msk   (0x1UL << DFSDM_FLTISR_JOVRF_Pos)
	0x00000004
#define	DFSDM_FLTISR_JOVRF   DFSDM_FLTISR_JOVRF_Msk
	Injected conversion overrun flag.
#define	DFSDM_FLTISR_REOCF_Pos   (1U)
#define	DFSDM_FLTISR_REOCF_Msk   (0x1UL << DFSDM_FLTISR_REOCF_Pos)
	0x00000002
#define	DFSDM_FLTISR_REOCF   DFSDM_FLTISR_REOCF_Msk
	End of regular conversion flag.
#define	DFSDM_FLTISR_JEOCF_Pos   (0U)
#define	DFSDM_FLTISR_JEOCF_Msk   (0x1UL << DFSDM_FLTISR_JEOCF_Pos)
	0x00000001
#define	DFSDM_FLTISR_JEOCF   DFSDM_FLTISR_JEOCF_Msk
	End of injected conversion flag.
#define	DFSDM_FLTICR_CLRSCDF_Pos   (24U)
#define	DFSDM_FLTICR_CLRSCDF_Msk   (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)
	0xFF000000
#define	DFSDM_FLTICR_CLRSCDF   DFSDM_FLTICR_CLRSCDF_Msk
	CLRSCSDF[7:0] Clear the short circuit detector flag.
#define	DFSDM_FLTICR_CLRCKABF_Pos   (16U)
#define	DFSDM_FLTICR_CLRCKABF_Msk   (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)
	0x00FF0000
#define	DFSDM_FLTICR_CLRCKABF   DFSDM_FLTICR_CLRCKABF_Msk
	CLRCKABF[7:0] Clear the clock absence flag.
#define	DFSDM_FLTICR_CLRROVRF_Pos   (3U)
#define	DFSDM_FLTICR_CLRROVRF_Msk   (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)
	0x00000008
#define	DFSDM_FLTICR_CLRROVRF   DFSDM_FLTICR_CLRROVRF_Msk
	Clear the regular conversion overrun flag.
#define	DFSDM_FLTICR_CLRJOVRF_Pos   (2U)
#define	DFSDM_FLTICR_CLRJOVRF_Msk   (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)
	0x00000004
#define	DFSDM_FLTICR_CLRJOVRF   DFSDM_FLTICR_CLRJOVRF_Msk
	Clear the injected conversion overrun flag.
#define	DFSDM_FLTJCHGR_JCHG_Pos   (0U)
#define	DFSDM_FLTJCHGR_JCHG_Msk   (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)
	0x000000FF
#define	DFSDM_FLTJCHGR_JCHG   DFSDM_FLTJCHGR_JCHG_Msk
	JCHG[7:0] Injected channel group selection.
#define	DFSDM_FLTFCR_FORD_Pos   (29U)
#define	DFSDM_FLTFCR_FORD_Msk   (0x7UL << DFSDM_FLTFCR_FORD_Pos)
	0xE0000000
#define	DFSDM_FLTFCR_FORD   DFSDM_FLTFCR_FORD_Msk
	FORD[2:0] Sinc filter order.
#define	DFSDM_FLTFCR_FORD_2   (0x4UL << DFSDM_FLTFCR_FORD_Pos)
	0x80000000
#define	DFSDM_FLTFCR_FORD_1   (0x2UL << DFSDM_FLTFCR_FORD_Pos)
	0x40000000
#define	DFSDM_FLTFCR_FORD_0   (0x1UL << DFSDM_FLTFCR_FORD_Pos)
	0x20000000
#define	DFSDM_FLTFCR_FOSR_Pos   (16U)
#define	DFSDM_FLTFCR_FOSR_Msk   (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)
	0x03FF0000
#define	DFSDM_FLTFCR_FOSR   DFSDM_FLTFCR_FOSR_Msk
	FOSR[9:0] Sinc filter oversampling ratio (decimation rate).
#define	DFSDM_FLTFCR_IOSR_Pos   (0U)
#define	DFSDM_FLTFCR_IOSR_Msk   (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)
	0x000000FF
#define	DFSDM_FLTFCR_IOSR   DFSDM_FLTFCR_IOSR_Msk
	IOSR[7:0] Integrator oversampling ratio (averaging length).
#define	DFSDM_FLTJDATAR_JDATA_Pos   (8U)
#define	DFSDM_FLTJDATAR_JDATA_Msk   (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos)
	0xFFFFFF00
#define	DFSDM_FLTJDATAR_JDATA   DFSDM_FLTJDATAR_JDATA_Msk
	JDATA[23:0] Injected group conversion data.
#define	DFSDM_FLTJDATAR_JDATACH_Pos   (0U)
#define	DFSDM_FLTJDATAR_JDATACH_Msk   (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos)
	0x00000007
#define	DFSDM_FLTJDATAR_JDATACH   DFSDM_FLTJDATAR_JDATACH_Msk
	JDATACH[2:0] Injected channel most recently converted.
#define	DFSDM_FLTRDATAR_RDATA_Pos   (8U)
#define	DFSDM_FLTRDATAR_RDATA_Msk   (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos)
	0xFFFFFF00
#define	DFSDM_FLTRDATAR_RDATA   DFSDM_FLTRDATAR_RDATA_Msk
	RDATA[23:0] Regular channel conversion data.
#define	DFSDM_FLTRDATAR_RPEND_Pos   (4U)
#define	DFSDM_FLTRDATAR_RPEND_Msk   (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)
	0x00000010
#define	DFSDM_FLTRDATAR_RPEND   DFSDM_FLTRDATAR_RPEND_Msk
	RPEND Regular channel pending data.
#define	DFSDM_FLTRDATAR_RDATACH_Pos   (0U)
#define	DFSDM_FLTRDATAR_RDATACH_Msk   (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos)
	0x00000007
#define	DFSDM_FLTRDATAR_RDATACH   DFSDM_FLTRDATAR_RDATACH_Msk
	RDATACH[2:0] Regular channel most recently converted.
#define	DFSDM_FLTAWHTR_AWHT_Pos   (8U)
#define	DFSDM_FLTAWHTR_AWHT_Msk   (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos)
	0xFFFFFF00
#define	DFSDM_FLTAWHTR_AWHT   DFSDM_FLTAWHTR_AWHT_Msk
	AWHT[23:0] Analog watchdog high threshold.
#define	DFSDM_FLTAWHTR_BKAWH_Pos   (0U)
#define	DFSDM_FLTAWHTR_BKAWH_Msk   (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)
	0x0000000F
#define	DFSDM_FLTAWHTR_BKAWH   DFSDM_FLTAWHTR_BKAWH_Msk
	BKAWH[3:0] Break signal assignment to analog watchdog high threshold event.
#define	DFSDM_FLTAWLTR_AWLT_Pos   (8U)
#define	DFSDM_FLTAWLTR_AWLT_Msk   (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos)
	0xFFFFFF00
#define	DFSDM_FLTAWLTR_AWLT   DFSDM_FLTAWLTR_AWLT_Msk
	AWHT[23:0] Analog watchdog low threshold.
#define	DFSDM_FLTAWLTR_BKAWL_Pos   (0U)
#define	DFSDM_FLTAWLTR_BKAWL_Msk   (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)
	0x0000000F
#define	DFSDM_FLTAWLTR_BKAWL   DFSDM_FLTAWLTR_BKAWL_Msk
	BKAWL[3:0] Break signal assignment to analog watchdog low threshold event.
#define	DFSDM_FLTAWSR_AWHTF_Pos   (8U)
#define	DFSDM_FLTAWSR_AWHTF_Msk   (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)
	0x0000FF00
#define	DFSDM_FLTAWSR_AWHTF   DFSDM_FLTAWSR_AWHTF_Msk
	AWHTF[15:8] Analog watchdog high threshold error on given channels.
#define	DFSDM_FLTAWSR_AWLTF_Pos   (0U)
#define	DFSDM_FLTAWSR_AWLTF_Msk   (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)
	0x000000FF
#define	DFSDM_FLTAWSR_AWLTF   DFSDM_FLTAWSR_AWLTF_Msk
	AWLTF[7:0] Analog watchdog low threshold error on given channels.
#define	DFSDM_FLTAWCFR_CLRAWHTF_Pos   (8U)
#define	DFSDM_FLTAWCFR_CLRAWHTF_Msk   (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos)
	0x0000FF00
#define	DFSDM_FLTAWCFR_CLRAWHTF   DFSDM_FLTAWCFR_CLRAWHTF_Msk
	CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag.
#define	DFSDM_FLTAWCFR_CLRAWLTF_Pos   (0U)
#define	DFSDM_FLTAWCFR_CLRAWLTF_Msk   (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos)
	0x000000FF
#define	DFSDM_FLTAWCFR_CLRAWLTF   DFSDM_FLTAWCFR_CLRAWLTF_Msk
	CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag.
#define	DFSDM_FLTEXMAX_EXMAX_Pos   (8U)
#define	DFSDM_FLTEXMAX_EXMAX_Msk   (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos)
	0xFFFFFF00
#define	DFSDM_FLTEXMAX_EXMAX   DFSDM_FLTEXMAX_EXMAX_Msk
	EXMAX[23:0] Extreme detector maximum value.
#define	DFSDM_FLTEXMAX_EXMAXCH_Pos   (0U)
#define	DFSDM_FLTEXMAX_EXMAXCH_Msk   (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)
	0x00000007
#define	DFSDM_FLTEXMAX_EXMAXCH   DFSDM_FLTEXMAX_EXMAXCH_Msk
	EXMAXCH[2:0] Extreme detector maximum data channel.
#define	DFSDM_FLTEXMIN_EXMIN_Pos   (8U)
#define	DFSDM_FLTEXMIN_EXMIN_Msk   (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos)
	0xFFFFFF00
#define	DFSDM_FLTEXMIN_EXMIN   DFSDM_FLTEXMIN_EXMIN_Msk
	EXMIN[23:0] Extreme detector minimum value.
#define	DFSDM_FLTEXMIN_EXMINCH_Pos   (0U)
#define	DFSDM_FLTEXMIN_EXMINCH_Msk   (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)
	0x00000007
#define	DFSDM_FLTEXMIN_EXMINCH   DFSDM_FLTEXMIN_EXMINCH_Msk
	EXMINCH[2:0] Extreme detector minimum data channel.
#define	DFSDM_FLTCNVTIMR_CNVCNT_Pos   (4U)
#define	DFSDM_FLTCNVTIMR_CNVCNT_Msk   (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos)
	0xFFFFFFF0
#define	DFSDM_FLTCNVTIMR_CNVCNT   DFSDM_FLTCNVTIMR_CNVCNT_Msk
	CNVCNT[27:0]: 28-bit timer counting conversion time.
#define	BDMA_ISR_GIF0_Pos   (0U)
#define	BDMA_ISR_GIF0_Msk   (0x1UL << BDMA_ISR_GIF0_Pos)
	0x00000001
#define	BDMA_ISR_GIF0   BDMA_ISR_GIF0_Msk
	Channel 0 Global interrupt flag.
#define	BDMA_ISR_TCIF0_Pos   (1U)
#define	BDMA_ISR_TCIF0_Msk   (0x1UL << BDMA_ISR_TCIF0_Pos)
	0x00000002
#define	BDMA_ISR_TCIF0   BDMA_ISR_TCIF0_Msk
	Channel 0 Transfer Complete flag.
#define	BDMA_ISR_HTIF0_Pos   (2U)
#define	BDMA_ISR_HTIF0_Msk   (0x1UL << BDMA_ISR_HTIF0_Pos)
	0x00000004
#define	BDMA_ISR_HTIF0   BDMA_ISR_HTIF0_Msk
	Channel 0 Half Transfer flag.
#define	BDMA_ISR_TEIF0_Pos   (3U)
#define	BDMA_ISR_TEIF0_Msk   (0x1UL << BDMA_ISR_TEIF0_Pos)
	0x00000008
#define	BDMA_ISR_TEIF0   BDMA_ISR_TEIF0_Msk
	Channel 0 Transfer Error flag.
#define	BDMA_ISR_GIF1_Pos   (4U)
#define	BDMA_ISR_GIF1_Msk   (0x1UL << BDMA_ISR_GIF1_Pos)
	0x00000010
#define	BDMA_ISR_GIF1   BDMA_ISR_GIF1_Msk
	Channel 1 Global interrupt flag.
#define	BDMA_ISR_TCIF1_Pos   (5U)
#define	BDMA_ISR_TCIF1_Msk   (0x1UL << BDMA_ISR_TCIF1_Pos)
	0x00000020
#define	BDMA_ISR_TCIF1   BDMA_ISR_TCIF1_Msk
	Channel 1 Transfer Complete flag.
#define	BDMA_ISR_HTIF1_Pos   (6U)
#define	BDMA_ISR_HTIF1_Msk   (0x1UL << BDMA_ISR_HTIF1_Pos)
	0x00000040
#define	BDMA_ISR_HTIF1   BDMA_ISR_HTIF1_Msk
	Channel 1 Half Transfer flag.
#define	BDMA_ISR_TEIF1_Pos   (7U)
#define	BDMA_ISR_TEIF1_Msk   (0x1UL << BDMA_ISR_TEIF1_Pos)
	0x00000080
#define	BDMA_ISR_TEIF1   BDMA_ISR_TEIF1_Msk
	Channel 1 Transfer Error flag.
#define	BDMA_ISR_GIF2_Pos   (8U)
#define	BDMA_ISR_GIF2_Msk   (0x1UL << BDMA_ISR_GIF2_Pos)
	0x00000100
#define	BDMA_ISR_GIF2   BDMA_ISR_GIF2_Msk
	Channel 2 Global interrupt flag.
#define	BDMA_ISR_TCIF2_Pos   (9U)
#define	BDMA_ISR_TCIF2_Msk   (0x1UL << BDMA_ISR_TCIF2_Pos)
	0x00000200
#define	BDMA_ISR_TCIF2   BDMA_ISR_TCIF2_Msk
	Channel 2 Transfer Complete flag.
#define	BDMA_ISR_HTIF2_Pos   (10U)
#define	BDMA_ISR_HTIF2_Msk   (0x1UL << BDMA_ISR_HTIF2_Pos)
	0x00000400
#define	BDMA_ISR_HTIF2   BDMA_ISR_HTIF2_Msk
	Channel 2 Half Transfer flag.
#define	BDMA_ISR_TEIF2_Pos   (11U)
#define	BDMA_ISR_TEIF2_Msk   (0x1UL << BDMA_ISR_TEIF2_Pos)
	0x00000800
#define	BDMA_ISR_TEIF2   BDMA_ISR_TEIF2_Msk
	Channel 2 Transfer Error flag.
#define	BDMA_ISR_GIF3_Pos   (12U)
#define	BDMA_ISR_GIF3_Msk   (0x1UL << BDMA_ISR_GIF3_Pos)
	0x00001000
#define	BDMA_ISR_GIF3   BDMA_ISR_GIF3_Msk
	Channel 3 Global interrupt flag.
#define	BDMA_ISR_TCIF3_Pos   (13U)
#define	BDMA_ISR_TCIF3_Msk   (0x1UL << BDMA_ISR_TCIF3_Pos)
	0x00002000
#define	BDMA_ISR_TCIF3   BDMA_ISR_TCIF3_Msk
	Channel 3 Transfer Complete flag.
#define	BDMA_ISR_HTIF3_Pos   (14U)
#define	BDMA_ISR_HTIF3_Msk   (0x1UL << BDMA_ISR_HTIF3_Pos)
	0x00004000
#define	BDMA_ISR_HTIF3   BDMA_ISR_HTIF3_Msk
	Channel 3 Half Transfer flag.
#define	BDMA_ISR_TEIF3_Pos   (15U)
#define	BDMA_ISR_TEIF3_Msk   (0x1UL << BDMA_ISR_TEIF3_Pos)
	0x00008000
#define	BDMA_ISR_TEIF3   BDMA_ISR_TEIF3_Msk
	Channel 3 Transfer Error flag.
#define	BDMA_ISR_GIF4_Pos   (16U)
#define	BDMA_ISR_GIF4_Msk   (0x1UL << BDMA_ISR_GIF4_Pos)
	0x00010000
#define	BDMA_ISR_GIF4   BDMA_ISR_GIF4_Msk
	Channel 4 Global interrupt flag.
#define	BDMA_ISR_TCIF4_Pos   (17U)
#define	BDMA_ISR_TCIF4_Msk   (0x1UL << BDMA_ISR_TCIF4_Pos)
	0x00020000
#define	BDMA_ISR_TCIF4   BDMA_ISR_TCIF4_Msk
	Channel 4 Transfer Complete flag.
#define	BDMA_ISR_HTIF4_Pos   (18U)
#define	BDMA_ISR_HTIF4_Msk   (0x1UL << BDMA_ISR_HTIF4_Pos)
	0x00040000
#define	BDMA_ISR_HTIF4   BDMA_ISR_HTIF4_Msk
	Channel 4 Half Transfer flag.
#define	BDMA_ISR_TEIF4_Pos   (19U)
#define	BDMA_ISR_TEIF4_Msk   (0x1UL << BDMA_ISR_TEIF4_Pos)
	0x00080000
#define	BDMA_ISR_TEIF4   BDMA_ISR_TEIF4_Msk
	Channel 4 Transfer Error flag.
#define	BDMA_ISR_GIF5_Pos   (20U)
#define	BDMA_ISR_GIF5_Msk   (0x1UL << BDMA_ISR_GIF5_Pos)
	0x00100000
#define	BDMA_ISR_GIF5   BDMA_ISR_GIF5_Msk
	Channel 5 Global interrupt flag.
#define	BDMA_ISR_TCIF5_Pos   (21U)
#define	BDMA_ISR_TCIF5_Msk   (0x1UL << BDMA_ISR_TCIF5_Pos)
	0x00200000
#define	BDMA_ISR_TCIF5   BDMA_ISR_TCIF5_Msk
	Channel 5 Transfer Complete flag.
#define	BDMA_ISR_HTIF5_Pos   (22U)
#define	BDMA_ISR_HTIF5_Msk   (0x1UL << BDMA_ISR_HTIF5_Pos)
	0x00400000
#define	BDMA_ISR_HTIF5   BDMA_ISR_HTIF5_Msk
	Channel 5 Half Transfer flag.
#define	BDMA_ISR_TEIF5_Pos   (23U)
#define	BDMA_ISR_TEIF5_Msk   (0x1UL << BDMA_ISR_TEIF5_Pos)
	0x00800000
#define	BDMA_ISR_TEIF5   BDMA_ISR_TEIF5_Msk
	Channel 5 Transfer Error flag.
#define	BDMA_ISR_GIF6_Pos   (24U)
#define	BDMA_ISR_GIF6_Msk   (0x1UL << BDMA_ISR_GIF6_Pos)
	0x01000000
#define	BDMA_ISR_GIF6   BDMA_ISR_GIF6_Msk
	Channel 6 Global interrupt flag.
#define	BDMA_ISR_TCIF6_Pos   (25U)
#define	BDMA_ISR_TCIF6_Msk   (0x1UL << BDMA_ISR_TCIF6_Pos)
	0x02000000
#define	BDMA_ISR_TCIF6   BDMA_ISR_TCIF6_Msk
	Channel 6 Transfer Complete flag.
#define	BDMA_ISR_HTIF6_Pos   (26U)
#define	BDMA_ISR_HTIF6_Msk   (0x1UL << BDMA_ISR_HTIF6_Pos)
	0x04000000
#define	BDMA_ISR_HTIF6   BDMA_ISR_HTIF6_Msk
	Channel 6 Half Transfer flag.
#define	BDMA_ISR_TEIF6_Pos   (27U)
#define	BDMA_ISR_TEIF6_Msk   (0x1UL << BDMA_ISR_TEIF6_Pos)
	0x08000000
#define	BDMA_ISR_TEIF6   BDMA_ISR_TEIF6_Msk
	Channel 6 Transfer Error flag.
#define	BDMA_ISR_GIF7_Pos   (28U)
#define	BDMA_ISR_GIF7_Msk   (0x1UL << BDMA_ISR_GIF7_Pos)
	0x10000000
#define	BDMA_ISR_GIF7   BDMA_ISR_GIF7_Msk
	Channel 7 Global interrupt flag.
#define	BDMA_ISR_TCIF7_Pos   (29U)
#define	BDMA_ISR_TCIF7_Msk   (0x1UL << BDMA_ISR_TCIF7_Pos)
	0x20000000
#define	BDMA_ISR_TCIF7   BDMA_ISR_TCIF7_Msk
	Channel 7 Transfer Complete flag.
#define	BDMA_ISR_HTIF7_Pos   (30U)
#define	BDMA_ISR_HTIF7_Msk   (0x1UL << BDMA_ISR_HTIF7_Pos)
	0x40000000
#define	BDMA_ISR_HTIF7   BDMA_ISR_HTIF7_Msk
	Channel 7 Half Transfer flag.
#define	BDMA_ISR_TEIF7_Pos   (31U)
#define	BDMA_ISR_TEIF7_Msk   (0x1UL << BDMA_ISR_TEIF7_Pos)
	0x80000000
#define	BDMA_ISR_TEIF7   BDMA_ISR_TEIF7_Msk
	Channel 7 Transfer Error flag.
#define	BDMA_IFCR_CGIF0_Pos   (0U)
#define	BDMA_IFCR_CGIF0_Msk   (0x1UL << BDMA_IFCR_CGIF0_Pos)
	0x00000001
#define	BDMA_IFCR_CGIF0   BDMA_IFCR_CGIF0_Msk
	Channel 0 Global interrupt clearr.
#define	BDMA_IFCR_CTCIF0_Pos   (1U)
#define	BDMA_IFCR_CTCIF0_Msk   (0x1UL << BDMA_IFCR_CTCIF0_Pos)
	0x00000002
#define	BDMA_IFCR_CTCIF0   BDMA_IFCR_CTCIF0_Msk
	Channel 0 Transfer Complete clear.
#define	BDMA_IFCR_CHTIF0_Pos   (2U)
#define	BDMA_IFCR_CHTIF0_Msk   (0x1UL << BDMA_IFCR_CHTIF0_Pos)
	0x00000004
#define	BDMA_IFCR_CHTIF0   BDMA_IFCR_CHTIF0_Msk
	Channel 0 Half Transfer clear.
#define	BDMA_IFCR_CTEIF0_Pos   (3U)
#define	BDMA_IFCR_CTEIF0_Msk   (0x1UL << BDMA_IFCR_CTEIF0_Pos)
	0x00000008
#define	BDMA_IFCR_CTEIF0   BDMA_IFCR_CTEIF0_Msk
	Channel 0 Transfer Error clear.
#define	BDMA_IFCR_CGIF1_Pos   (4U)
#define	BDMA_IFCR_CGIF1_Msk   (0x1UL << BDMA_IFCR_CGIF1_Pos)
	0x00000010
#define	BDMA_IFCR_CGIF1   BDMA_IFCR_CGIF1_Msk
	Channel 1 Global interrupt clear.
#define	BDMA_IFCR_CTCIF1_Pos   (5U)
#define	BDMA_IFCR_CTCIF1_Msk   (0x1UL << BDMA_IFCR_CTCIF1_Pos)
	0x00000020
#define	BDMA_IFCR_CTCIF1   BDMA_IFCR_CTCIF1_Msk
	Channel 1 Transfer Complete clear.
#define	BDMA_IFCR_CHTIF1_Pos   (6U)
#define	BDMA_IFCR_CHTIF1_Msk   (0x1UL << BDMA_IFCR_CHTIF1_Pos)
	0x00000040
#define	BDMA_IFCR_CHTIF1   BDMA_IFCR_CHTIF1_Msk
	Channel 1 Half Transfer clear.
#define	BDMA_IFCR_CTEIF1_Pos   (7U)
#define	BDMA_IFCR_CTEIF1_Msk   (0x1UL << BDMA_IFCR_CTEIF1_Pos)
	0x00000080
#define	BDMA_IFCR_CTEIF1   BDMA_IFCR_CTEIF1_Msk
	Channel 1 Transfer Error clear.
#define	BDMA_IFCR_CGIF2_Pos   (8U)
#define	BDMA_IFCR_CGIF2_Msk   (0x1UL << BDMA_IFCR_CGIF2_Pos)
	0x00000100
#define	BDMA_IFCR_CGIF2   BDMA_IFCR_CGIF2_Msk
	Channel 2 Global interrupt clear.
#define	BDMA_IFCR_CTCIF2_Pos   (9U)
#define	BDMA_IFCR_CTCIF2_Msk   (0x1UL << BDMA_IFCR_CTCIF2_Pos)
	0x00000200
#define	BDMA_IFCR_CTCIF2   BDMA_IFCR_CTCIF2_Msk
	Channel 2 Transfer Complete clear.
#define	BDMA_IFCR_CHTIF2_Pos   (10U)
#define	BDMA_IFCR_CHTIF2_Msk   (0x1UL << BDMA_IFCR_CHTIF2_Pos)
	0x00000400
#define	BDMA_IFCR_CHTIF2   BDMA_IFCR_CHTIF2_Msk
	Channel 2 Half Transfer clear.
#define	BDMA_IFCR_CTEIF2_Pos   (11U)
#define	BDMA_IFCR_CTEIF2_Msk   (0x1UL << BDMA_IFCR_CTEIF2_Pos)
	0x00000800
#define	BDMA_IFCR_CTEIF2   BDMA_IFCR_CTEIF2_Msk
	Channel 2 Transfer Error clear.
#define	BDMA_IFCR_CGIF3_Pos   (12U)
#define	BDMA_IFCR_CGIF3_Msk   (0x1UL << BDMA_IFCR_CGIF3_Pos)
	0x00001000
#define	BDMA_IFCR_CGIF3   BDMA_IFCR_CGIF3_Msk
	Channel 3 Global interrupt clear.
#define	BDMA_IFCR_CTCIF3_Pos   (13U)
#define	BDMA_IFCR_CTCIF3_Msk   (0x1UL << BDMA_IFCR_CTCIF3_Pos)
	0x00002000
#define	BDMA_IFCR_CTCIF3   BDMA_IFCR_CTCIF3_Msk
	Channel 3 Transfer Complete clear.
#define	BDMA_IFCR_CHTIF3_Pos   (14U)
#define	BDMA_IFCR_CHTIF3_Msk   (0x1UL << BDMA_IFCR_CHTIF3_Pos)
	0x00004000
#define	BDMA_IFCR_CHTIF3   BDMA_IFCR_CHTIF3_Msk
	Channel 3 Half Transfer clear.
#define	BDMA_IFCR_CTEIF3_Pos   (15U)
#define	BDMA_IFCR_CTEIF3_Msk   (0x1UL << BDMA_IFCR_CTEIF3_Pos)
	0x00008000
#define	BDMA_IFCR_CTEIF3   BDMA_IFCR_CTEIF3_Msk
	Channel 3 Transfer Error clear.
#define	BDMA_IFCR_CGIF4_Pos   (16U)
#define	BDMA_IFCR_CGIF4_Msk   (0x1UL << BDMA_IFCR_CGIF4_Pos)
	0x00010000
#define	BDMA_IFCR_CGIF4   BDMA_IFCR_CGIF4_Msk
	Channel 4 Global interrupt clear.
#define	BDMA_IFCR_CTCIF4_Pos   (17U)
#define	BDMA_IFCR_CTCIF4_Msk   (0x1UL << BDMA_IFCR_CTCIF4_Pos)
	0x00020000
#define	BDMA_IFCR_CTCIF4   BDMA_IFCR_CTCIF4_Msk
	Channel 4 Transfer Complete clear.
#define	BDMA_IFCR_CHTIF4_Pos   (18U)
#define	BDMA_IFCR_CHTIF4_Msk   (0x1UL << BDMA_IFCR_CHTIF4_Pos)
	0x00040000
#define	BDMA_IFCR_CHTIF4   BDMA_IFCR_CHTIF4_Msk
	Channel 4 Half Transfer clear.
#define	BDMA_IFCR_CTEIF4_Pos   (19U)
#define	BDMA_IFCR_CTEIF4_Msk   (0x1UL << BDMA_IFCR_CTEIF4_Pos)
	0x00080000
#define	BDMA_IFCR_CTEIF4   BDMA_IFCR_CTEIF4_Msk
	Channel 4 Transfer Error clear.
#define	BDMA_IFCR_CGIF5_Pos   (20U)
#define	BDMA_IFCR_CGIF5_Msk   (0x1UL << BDMA_IFCR_CGIF5_Pos)
	0x00100000
#define	BDMA_IFCR_CGIF5   BDMA_IFCR_CGIF5_Msk
	Channel 5 Global interrupt clear.
#define	BDMA_IFCR_CTCIF5_Pos   (21U)
#define	BDMA_IFCR_CTCIF5_Msk   (0x1UL << BDMA_IFCR_CTCIF5_Pos)
	0x00200000
#define	BDMA_IFCR_CTCIF5   BDMA_IFCR_CTCIF5_Msk
	Channel 5 Transfer Complete clear.
#define	BDMA_IFCR_CHTIF5_Pos   (22U)
#define	BDMA_IFCR_CHTIF5_Msk   (0x1UL << BDMA_IFCR_CHTIF5_Pos)
	0x00400000
#define	BDMA_IFCR_CHTIF5   BDMA_IFCR_CHTIF5_Msk
	Channel 5 Half Transfer clear.
#define	BDMA_IFCR_CTEIF5_Pos   (23U)
#define	BDMA_IFCR_CTEIF5_Msk   (0x1UL << BDMA_IFCR_CTEIF5_Pos)
	0x00800000
#define	BDMA_IFCR_CTEIF5   BDMA_IFCR_CTEIF5_Msk
	Channel 5 Transfer Error clear.
#define	BDMA_IFCR_CGIF6_Pos   (24U)
#define	BDMA_IFCR_CGIF6_Msk   (0x1UL << BDMA_IFCR_CGIF6_Pos)
	0x01000000
#define	BDMA_IFCR_CGIF6   BDMA_IFCR_CGIF6_Msk
	Channel 6 Global interrupt clear.
#define	BDMA_IFCR_CTCIF6_Pos   (25U)
#define	BDMA_IFCR_CTCIF6_Msk   (0x1UL << BDMA_IFCR_CTCIF6_Pos)
	0x02000000
#define	BDMA_IFCR_CTCIF6   BDMA_IFCR_CTCIF6_Msk
	Channel 6 Transfer Complete clear.
#define	BDMA_IFCR_CHTIF6_Pos   (26U)
#define	BDMA_IFCR_CHTIF6_Msk   (0x1UL << BDMA_IFCR_CHTIF6_Pos)
	0x04000000
#define	BDMA_IFCR_CHTIF6   BDMA_IFCR_CHTIF6_Msk
	Channel 6 Half Transfer clear.
#define	BDMA_IFCR_CTEIF6_Pos   (27U)
#define	BDMA_IFCR_CTEIF6_Msk   (0x1UL << BDMA_IFCR_CTEIF6_Pos)
	0x08000000
#define	BDMA_IFCR_CTEIF6   BDMA_IFCR_CTEIF6_Msk
	Channel 6 Transfer Error clear.
#define	BDMA_IFCR_CGIF7_Pos   (28U)
#define	BDMA_IFCR_CGIF7_Msk   (0x1UL << BDMA_IFCR_CGIF7_Pos)
	0x10000000
#define	BDMA_IFCR_CGIF7   BDMA_IFCR_CGIF7_Msk
	Channel 7 Global interrupt clear.
#define	BDMA_IFCR_CTCIF7_Pos   (29U)
#define	BDMA_IFCR_CTCIF7_Msk   (0x1UL << BDMA_IFCR_CTCIF7_Pos)
	0x20000000
#define	BDMA_IFCR_CTCIF7   BDMA_IFCR_CTCIF7_Msk
	Channel 7 Transfer Complete clear.
#define	BDMA_IFCR_CHTIF7_Pos   (30U)
#define	BDMA_IFCR_CHTIF7_Msk   (0x1UL << BDMA_IFCR_CHTIF7_Pos)
	0x40000000
#define	BDMA_IFCR_CHTIF7   BDMA_IFCR_CHTIF7_Msk
	Channel 7 Half Transfer clear.
#define	BDMA_IFCR_CTEIF7_Pos   (31U)
#define	BDMA_IFCR_CTEIF7_Msk   (0x1UL << BDMA_IFCR_CTEIF7_Pos)
	0x80000000
#define	BDMA_IFCR_CTEIF7   BDMA_IFCR_CTEIF7_Msk
	Channel 7 Transfer Error clear.
#define	BDMA_CCR_EN_Pos   (0U)
#define	BDMA_CCR_EN_Msk   (0x1UL << BDMA_CCR_EN_Pos)
	0x00000001
#define	BDMA_CCR_EN   BDMA_CCR_EN_Msk
	Channel enable.
#define	BDMA_CCR_TCIE_Pos   (1U)
#define	BDMA_CCR_TCIE_Msk   (0x1UL << BDMA_CCR_TCIE_Pos)
	0x00000002
#define	BDMA_CCR_TCIE   BDMA_CCR_TCIE_Msk
	Transfer complete interrupt enable.
#define	BDMA_CCR_HTIE_Pos   (2U)
#define	BDMA_CCR_HTIE_Msk   (0x1UL << BDMA_CCR_HTIE_Pos)
	0x00000004
#define	BDMA_CCR_HTIE   BDMA_CCR_HTIE_Msk
	Half Transfer interrupt enable.
#define	BDMA_CCR_TEIE_Pos   (3U)
#define	BDMA_CCR_TEIE_Msk   (0x1UL << BDMA_CCR_TEIE_Pos)
	0x00000008
#define	BDMA_CCR_TEIE   BDMA_CCR_TEIE_Msk
	Transfer error interrupt enable.
#define	BDMA_CCR_DIR_Pos   (4U)
#define	BDMA_CCR_DIR_Msk   (0x1UL << BDMA_CCR_DIR_Pos)
	0x00000010
#define	BDMA_CCR_DIR   BDMA_CCR_DIR_Msk
	Data transfer direction.
#define	BDMA_CCR_CIRC_Pos   (5U)
#define	BDMA_CCR_CIRC_Msk   (0x1UL << BDMA_CCR_CIRC_Pos)
	0x00000020
#define	BDMA_CCR_CIRC   BDMA_CCR_CIRC_Msk
	Circular mode.
#define	BDMA_CCR_PINC_Pos   (6U)
#define	BDMA_CCR_PINC_Msk   (0x1UL << BDMA_CCR_PINC_Pos)
	0x00000040
#define	BDMA_CCR_PINC   BDMA_CCR_PINC_Msk
	Peripheral increment mode.
#define	BDMA_CCR_MINC_Pos   (7U)
#define	BDMA_CCR_MINC_Msk   (0x1UL << BDMA_CCR_MINC_Pos)
	0x00000080
#define	BDMA_CCR_MINC   BDMA_CCR_MINC_Msk
	Memory increment mode.
#define	BDMA_CCR_PSIZE_Pos   (8U)
#define	BDMA_CCR_PSIZE_Msk   (0x3UL << BDMA_CCR_PSIZE_Pos)
	0x00000300
#define	BDMA_CCR_PSIZE   BDMA_CCR_PSIZE_Msk
	PSIZE[1:0] bits (Peripheral size).
#define	BDMA_CCR_PSIZE_0   (0x1UL << BDMA_CCR_PSIZE_Pos)
	0x00000100
#define	BDMA_CCR_PSIZE_1   (0x2UL << BDMA_CCR_PSIZE_Pos)
	0x00000200
#define	BDMA_CCR_MSIZE_Pos   (10U)
#define	BDMA_CCR_MSIZE_Msk   (0x3UL << BDMA_CCR_MSIZE_Pos)
	0x00000C00
#define	BDMA_CCR_MSIZE   BDMA_CCR_MSIZE_Msk
	MSIZE[1:0] bits (Memory size).
#define	BDMA_CCR_MSIZE_0   (0x1UL << BDMA_CCR_MSIZE_Pos)
	0x00000400
#define	BDMA_CCR_MSIZE_1   (0x2UL << BDMA_CCR_MSIZE_Pos)
	0x00000800
#define	BDMA_CCR_PL_Pos   (12U)
#define	BDMA_CCR_PL_Msk   (0x3UL << BDMA_CCR_PL_Pos)
	0x00003000
#define	BDMA_CCR_PL   BDMA_CCR_PL_Msk
	PL[1:0] bits(Channel Priority level).
#define	BDMA_CCR_PL_0   (0x1UL << BDMA_CCR_PL_Pos)
	0x00001000
#define	BDMA_CCR_PL_1   (0x2UL << BDMA_CCR_PL_Pos)
	0x00002000
#define	BDMA_CCR_MEM2MEM_Pos   (14U)
#define	BDMA_CCR_MEM2MEM_Msk   (0x1UL << BDMA_CCR_MEM2MEM_Pos)
	0x00004000
#define	BDMA_CCR_MEM2MEM   BDMA_CCR_MEM2MEM_Msk
	Memory to memory mode.
#define	BDMA_CCR_DBM_Pos   (15U)
#define	BDMA_CCR_DBM_Msk   (0x1UL << BDMA_CCR_DBM_Pos)
	0x0000A000
#define	BDMA_CCR_DBM   BDMA_CCR_DBM_Msk
	Memory to memory mode.
#define	BDMA_CCR_CT_Pos   (16U)
#define	BDMA_CCR_CT_Msk   (0x1UL << BDMA_CCR_CT_Pos)
	0x00010000
#define	BDMA_CCR_CT   BDMA_CCR_CT_Msk
	Memory to memory mode.
#define	BDMA_CNDTR_NDT_Pos   (0U)
#define	BDMA_CNDTR_NDT_Msk   (0xFFFFUL << BDMA_CNDTR_NDT_Pos)
	0x0000FFFF
#define	BDMA_CNDTR_NDT   BDMA_CNDTR_NDT_Msk
	Number of data to Transfer.
#define	BDMA_CPAR_PA_Pos   (0U)
#define	BDMA_CPAR_PA_Msk   (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)
	0xFFFFFFFF
#define	BDMA_CPAR_PA   BDMA_CPAR_PA_Msk
	Peripheral Address.
#define	BDMA_CM0AR_MA_Pos   (0U)
#define	BDMA_CM0AR_MA_Msk   (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)
	0xFFFFFFFF
#define	BDMA_CM0AR_MA   BDMA_CM0AR_MA_Msk
	Memory Address.
#define	BDMA_CM1AR_MA_Pos   (0U)
#define	BDMA_CM1AR_MA_Msk   (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)
	0xFFFFFFFF
#define	BDMA_CM1AR_MA   BDMA_CM1AR_MA_Msk
	Memory Address.
#define	ETH_MACCR_ARP_Pos   (31U)
#define	ETH_MACCR_ARP_Msk   (0x1UL << ETH_MACCR_ARP_Pos)
	0x80000000
#define	ETH_MACCR_ARP   ETH_MACCR_ARP_Msk /* ARP Offload Enable */
#define	ETH_MACCR_SARC_Pos   (28U)
#define	ETH_MACCR_SARC_Msk   (0x7UL << ETH_MACCR_SARC_Pos)
	0x70000000
#define	ETH_MACCR_SARC   ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
#define	ETH_MACCR_SARC_MTIATI   (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
#define	ETH_MACCR_SARC_INSADDR0_Pos   (29U)
#define	ETH_MACCR_SARC_INSADDR0_Msk   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos)
	0x20000000
#define	ETH_MACCR_SARC_INSADDR0   ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
#define	ETH_MACCR_SARC_INSADDR1_Pos   (29U)
#define	ETH_MACCR_SARC_INSADDR1_Msk   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos)
	0x60000000
#define	ETH_MACCR_SARC_INSADDR1   ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
#define	ETH_MACCR_SARC_REPADDR0_Pos   (28U)
#define	ETH_MACCR_SARC_REPADDR0_Msk   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos)
	0x30000000
#define	ETH_MACCR_SARC_REPADDR0   ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
#define	ETH_MACCR_SARC_REPADDR1_Pos   (28U)
#define	ETH_MACCR_SARC_REPADDR1_Msk   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos)
	0x70000000
#define	ETH_MACCR_SARC_REPADDR1   ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
#define	ETH_MACCR_IPC_Pos   (27U)
#define	ETH_MACCR_IPC_Msk   (0x1UL << ETH_MACCR_IPC_Pos)
	0x08000000
#define	ETH_MACCR_IPC   ETH_MACCR_IPC_Msk /* Checksum Offload */
#define	ETH_MACCR_IPG_Pos   (24U)
#define	ETH_MACCR_IPG_Msk   (0x7UL << ETH_MACCR_IPG_Pos)
	0x07000000
#define	ETH_MACCR_IPG   ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
#define	ETH_MACCR_IPG_96BIT   (0U) /* Minimum IFG between Packets during transmission is 96Bit */
#define	ETH_MACCR_IPG_88BIT   (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */
#define	ETH_MACCR_IPG_80BIT   (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */
#define	ETH_MACCR_IPG_72BIT   (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */
#define	ETH_MACCR_IPG_64BIT   (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */
#define	ETH_MACCR_IPG_56BIT   (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */
#define	ETH_MACCR_IPG_48BIT   (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */
#define	ETH_MACCR_IPG_40BIT   (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */
#define	ETH_MACCR_GPSLCE_Pos   (23U)
#define	ETH_MACCR_GPSLCE_Msk   (0x1UL << ETH_MACCR_GPSLCE_Pos)
	0x00800000
#define	ETH_MACCR_GPSLCE   ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
#define	ETH_MACCR_S2KP_Pos   (22U)
#define	ETH_MACCR_S2KP_Msk   (0x1UL << ETH_MACCR_S2KP_Pos)
	0x00400000
#define	ETH_MACCR_S2KP   ETH_MACCR_S2KP_Msk /* IEEE 802.3as Support for 2K Packets */
#define	ETH_MACCR_CST_Pos   (21U)
#define	ETH_MACCR_CST_Msk   (0x1UL << ETH_MACCR_CST_Pos)
	0x00200000
#define	ETH_MACCR_CST   ETH_MACCR_CST_Msk /* CRC stripping for Type packets */
#define	ETH_MACCR_ACS_Pos   (20U)
#define	ETH_MACCR_ACS_Msk   (0x1UL << ETH_MACCR_ACS_Pos)
	0x00100000
#define	ETH_MACCR_ACS   ETH_MACCR_ACS_Msk /* Automatic Pad or CRC Stripping */
#define	ETH_MACCR_WD_Pos   (19U)
#define	ETH_MACCR_WD_Msk   (0x1UL << ETH_MACCR_WD_Pos)
	0x00080000
#define	ETH_MACCR_WD   ETH_MACCR_WD_Msk /* Watchdog disable */
#define	ETH_MACCR_JD_Pos   (17U)
#define	ETH_MACCR_JD_Msk   (0x1UL << ETH_MACCR_JD_Pos)
	0x00020000
#define	ETH_MACCR_JD   ETH_MACCR_JD_Msk /* Jabber disable */
#define	ETH_MACCR_JE_Pos   (16U)
#define	ETH_MACCR_JE_Msk   (0x1UL << ETH_MACCR_JE_Pos)
	0x00010000
#define	ETH_MACCR_JE   ETH_MACCR_JE_Msk /* Jumbo Packet Enable */
#define	ETH_MACCR_FES_Pos   (14U)
#define	ETH_MACCR_FES_Msk   (0x1UL << ETH_MACCR_FES_Pos)
	0x00004000
#define	ETH_MACCR_FES   ETH_MACCR_FES_Msk /* Fast ethernet speed */
#define	ETH_MACCR_DM_Pos   (13U)
#define	ETH_MACCR_DM_Msk   (0x1UL << ETH_MACCR_DM_Pos)
	0x00002000
#define	ETH_MACCR_DM   ETH_MACCR_DM_Msk /* Duplex mode */
#define	ETH_MACCR_LM_Pos   (12U)
#define	ETH_MACCR_LM_Msk   (0x1UL << ETH_MACCR_LM_Pos)
	0x00001000
#define	ETH_MACCR_LM   ETH_MACCR_LM_Msk /* loopback mode */
#define	ETH_MACCR_ECRSFD_Pos   (11U)
#define	ETH_MACCR_ECRSFD_Msk   (0x1UL << ETH_MACCR_ECRSFD_Pos)
	0x00000800
#define	ETH_MACCR_ECRSFD   ETH_MACCR_ECRSFD_Msk /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
#define	ETH_MACCR_DO_Pos   (10U)
#define	ETH_MACCR_DO_Msk   (0x1UL << ETH_MACCR_DO_Pos)
	0x00000400
#define	ETH_MACCR_DO   ETH_MACCR_DO_Msk /* Disable Receive own */
#define	ETH_MACCR_DCRS_Pos   (9U)
#define	ETH_MACCR_DCRS_Msk   (0x1UL << ETH_MACCR_DCRS_Pos)
	0x00000200
#define	ETH_MACCR_DCRS   ETH_MACCR_DCRS_Msk /* Disable Carrier Sense During Transmission */
#define	ETH_MACCR_DR_Pos   (8U)
#define	ETH_MACCR_DR_Msk   (0x1UL << ETH_MACCR_DR_Pos)
	0x00000100
#define	ETH_MACCR_DR   ETH_MACCR_DR_Msk /* Disable Retry */
#define	ETH_MACCR_BL_Pos   (5U)
#define	ETH_MACCR_BL_Msk   (0x3UL << ETH_MACCR_BL_Pos)
	0x00000060
#define	ETH_MACCR_BL   ETH_MACCR_BL_Msk /* Back-off limit mask */
#define	ETH_MACCR_BL_10   (0x0UL << ETH_MACCR_BL_Pos)
	0x00000000
#define	ETH_MACCR_BL_8   (0x1UL << ETH_MACCR_BL_Pos)
	0x00000020
#define	ETH_MACCR_BL_4   (0x2UL << ETH_MACCR_BL_Pos)
	0x00000040
#define	ETH_MACCR_BL_1   (0x3UL << ETH_MACCR_BL_Pos)
	0x00000060
#define	ETH_MACCR_DC_Pos   (4U)
#define	ETH_MACCR_DC_Msk   (0x1UL << ETH_MACCR_DC_Pos)
	0x00000010
#define	ETH_MACCR_DC   ETH_MACCR_DC_Msk /* Defferal check */
#define	ETH_MACCR_PRELEN_Pos   (2U)
#define	ETH_MACCR_PRELEN_Msk   (0x3UL << ETH_MACCR_PRELEN_Pos)
	0x0000000C
#define	ETH_MACCR_PRELEN   ETH_MACCR_PRELEN_Msk /* Preamble Length for Transmit packets */
#define	ETH_MACCR_PRELEN_7   (0x0UL << ETH_MACCR_PRELEN_Pos)
	0x00000000
#define	ETH_MACCR_PRELEN_5   (0x1UL << ETH_MACCR_PRELEN_Pos)
	0x00000004
#define	ETH_MACCR_PRELEN_3   (0x2UL << ETH_MACCR_PRELEN_Pos)
	0x00000008
#define	ETH_MACCR_TE_Pos   (1U)
#define	ETH_MACCR_TE_Msk   (0x1UL << ETH_MACCR_TE_Pos)
	0x00000002
#define	ETH_MACCR_TE   ETH_MACCR_TE_Msk /* Transmitter enable */
#define	ETH_MACCR_RE_Pos   (0U)
#define	ETH_MACCR_RE_Msk   (0x1UL << ETH_MACCR_RE_Pos)
	0x00000001
#define	ETH_MACCR_RE   ETH_MACCR_RE_Msk /* Receiver enable */
#define	ETH_MACECR_EIPG_Pos   (25U)
#define	ETH_MACECR_EIPG_Msk   (0x1FUL << ETH_MACECR_EIPG_Pos)
	0x3E000000
#define	ETH_MACECR_EIPG   ETH_MACECR_EIPG_Msk /* Extended Inter-Packet Gap */
#define	ETH_MACECR_EIPGEN_Pos   (24U)
#define	ETH_MACECR_EIPGEN_Msk   (0x1UL << ETH_MACECR_EIPGEN_Pos)
	0x01000000
#define	ETH_MACECR_EIPGEN   ETH_MACECR_EIPGEN_Msk /* Extended Inter-Packet Gap Enable */
#define	ETH_MACECR_USP_Pos   (18U)
#define	ETH_MACECR_USP_Msk   (0x1UL << ETH_MACECR_USP_Pos)
	0x00040000
#define	ETH_MACECR_USP   ETH_MACECR_USP_Msk /* Unicast Slow Protocol Packet Detect */
#define	ETH_MACECR_SPEN_Pos   (17U)
#define	ETH_MACECR_SPEN_Msk   (0x1UL << ETH_MACECR_SPEN_Pos)
	0x00020000
#define	ETH_MACECR_SPEN   ETH_MACECR_SPEN_Msk /* Slow Protocol Detection Enable */
#define	ETH_MACECR_DCRCC_Pos   (16U)
#define	ETH_MACECR_DCRCC_Msk   (0x1UL << ETH_MACECR_DCRCC_Pos)
	0x00010000
#define	ETH_MACECR_DCRCC   ETH_MACECR_DCRCC_Msk /* Disable CRC Checking for Received Packets */
#define	ETH_MACECR_GPSL_Pos   (0U)
#define	ETH_MACECR_GPSL_Msk   (0x3FFFUL << ETH_MACECR_GPSL_Pos)
	0x00003FFF
#define	ETH_MACECR_GPSL   ETH_MACECR_GPSL_Msk /* Giant Packet Size Limit */
#define	ETH_MACPFR_RA_Pos   (31U)
#define	ETH_MACPFR_RA_Msk   (0x1UL << ETH_MACPFR_RA_Pos)
	0x80000000
#define	ETH_MACPFR_RA   ETH_MACPFR_RA_Msk /* Receive all */
#define	ETH_MACPFR_DNTU_Pos   (21U)
#define	ETH_MACPFR_DNTU_Msk   (0x1UL << ETH_MACPFR_DNTU_Pos)
	0x00200000
#define	ETH_MACPFR_DNTU   ETH_MACPFR_DNTU_Msk /* Drop Non-TCP/UDP over IP Packets */
#define	ETH_MACPFR_IPFE_Pos   (20U)
#define	ETH_MACPFR_IPFE_Msk   (0x1UL << ETH_MACPFR_IPFE_Pos)
	0x00100000
#define	ETH_MACPFR_IPFE   ETH_MACPFR_IPFE_Msk /* Layer 3 and Layer 4 Filter Enable */
#define	ETH_MACPFR_VTFE_Pos   (16U)
#define	ETH_MACPFR_VTFE_Msk   (0x1UL << ETH_MACPFR_VTFE_Pos)
	0x00010000
#define	ETH_MACPFR_VTFE   ETH_MACPFR_VTFE_Msk /* VLAN Tag Filter Enable */
#define	ETH_MACPFR_HPF_Pos   (10U)
#define	ETH_MACPFR_HPF_Msk   (0x1UL << ETH_MACPFR_HPF_Pos)
	0x00000400
#define	ETH_MACPFR_HPF   ETH_MACPFR_HPF_Msk /* Hash or perfect filter */
#define	ETH_MACPFR_SAF_Pos   (9U)
#define	ETH_MACPFR_SAF_Msk   (0x1UL << ETH_MACPFR_SAF_Pos)
	0x00000200
#define	ETH_MACPFR_SAF   ETH_MACPFR_SAF_Msk /* Source address filter enable */
#define	ETH_MACPFR_SAIF_Pos   (8U)
#define	ETH_MACPFR_SAIF_Msk   (0x1UL << ETH_MACPFR_SAIF_Pos)
	0x00000100
#define	ETH_MACPFR_SAIF   ETH_MACPFR_SAIF_Msk /* SA inverse filtering */
#define	ETH_MACPFR_PCF_Pos   (6U)
#define	ETH_MACPFR_PCF_Msk   (0x3UL << ETH_MACPFR_PCF_Pos)
	0x000000C0
#define	ETH_MACPFR_PCF   ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
#define	ETH_MACPFR_PCF_BLOCKALL   (0U) /* MAC filters all control frames from reaching the application */
#define	ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos   (6U)
#define	ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk   (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos)
	0x00000040
#define	ETH_MACPFR_PCF_FORWARDALLEXCEPTPA   ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
#define	ETH_MACPFR_PCF_FORWARDALL_Pos   (7U)
#define	ETH_MACPFR_PCF_FORWARDALL_Msk   (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos)
	0x00000080
#define	ETH_MACPFR_PCF_FORWARDALL   ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
#define	ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos   (6U)
#define	ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk   (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos)
	0x000000C0
#define	ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER   ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
#define	ETH_MACPFR_DBF_Pos   (5U)
#define	ETH_MACPFR_DBF_Msk   (0x1UL << ETH_MACPFR_DBF_Pos)
	0x00000020
#define	ETH_MACPFR_DBF   ETH_MACPFR_DBF_Msk /* Disable Broadcast Packets */
#define	ETH_MACPFR_PM_Pos   (4U)
#define	ETH_MACPFR_PM_Msk   (0x1UL << ETH_MACPFR_PM_Pos)
	0x00000010
#define	ETH_MACPFR_PM   ETH_MACPFR_PM_Msk /* Pass all mutlicast */
#define	ETH_MACPFR_DAIF_Pos   (3U)
#define	ETH_MACPFR_DAIF_Msk   (0x1UL << ETH_MACPFR_DAIF_Pos)
	0x00000008
#define	ETH_MACPFR_DAIF   ETH_MACPFR_DAIF_Msk /* DA Inverse filtering */
#define	ETH_MACPFR_HMC_Pos   (2U)
#define	ETH_MACPFR_HMC_Msk   (0x1UL << ETH_MACPFR_HMC_Pos)
	0x00000004
#define	ETH_MACPFR_HMC   ETH_MACPFR_HMC_Msk /* Hash multicast */
#define	ETH_MACPFR_HUC_Pos   (1U)
#define	ETH_MACPFR_HUC_Msk   (0x1UL << ETH_MACPFR_HUC_Pos)
	0x00000002
#define	ETH_MACPFR_HUC   ETH_MACPFR_HUC_Msk /* Hash unicast */
#define	ETH_MACPFR_PR_Pos   (0U)
#define	ETH_MACPFR_PR_Msk   (0x1UL << ETH_MACPFR_PR_Pos)
	0x00000001
#define	ETH_MACPFR_PR   ETH_MACPFR_PR_Msk /* Promiscuous mode */
#define	ETH_MACWTR_PWE_Pos   (8U)
#define	ETH_MACWTR_PWE_Msk   (0x1UL << ETH_MACWTR_PWE_Pos)
	0x00000100
#define	ETH_MACWTR_PWE   ETH_MACWTR_PWE_Msk /* Programmable Watchdog Enable */
#define	ETH_MACWTR_WTO_Pos   (0U)
#define	ETH_MACWTR_WTO_Msk   (0xFUL << ETH_MACWTR_WTO_Pos)
	0x0000000F
#define	ETH_MACWTR_WTO   ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
#define	ETH_MACWTR_WTO_2KB   (0U) /* Maximum received packet length 2KB*/
#define	ETH_MACWTR_WTO_3KB   (0x00000001U) /* Maximum received packet length 3KB */
#define	ETH_MACWTR_WTO_4KB   (0x00000002U) /* Maximum received packet length 4KB */
#define	ETH_MACWTR_WTO_5KB   (0x00000003U) /* Maximum received packet length 5KB */
#define	ETH_MACWTR_WTO_6KB   (0x00000004U) /* Maximum received packet length 6KB */
#define	ETH_MACWTR_WTO_7KB   (0x00000005U) /* Maximum received packet length 7KB */
#define	ETH_MACWTR_WTO_8KB   (0x00000006U) /* Maximum received packet length 8KB */
#define	ETH_MACWTR_WTO_9KB   (0x00000007U) /* Maximum received packet length 9KB */
#define	ETH_MACWTR_WTO_10KB   (0x00000008U) /* Maximum received packet length 10KB */
#define	ETH_MACWTR_WTO_11KB   (0x00000009U) /* Maximum received packet length 11KB */
#define	ETH_MACWTR_WTO_12KB   (0x0000000AU) /* Maximum received packet length 12KB */
#define	ETH_MACWTR_WTO_13KB   (0x0000000BU) /* Maximum received packet length 13KB */
#define	ETH_MACWTR_WTO_14KB   (0x0000000CU) /* Maximum received packet length 14KB */
#define	ETH_MACWTR_WTO_15KB   (0x0000000DU) /* Maximum received packet length 15KB */
#define	ETH_MACWTR_WTO_16KB   (0x0000000EU) /* Maximum received packet length 16KB */
#define	ETH_MACHTHR_HTH_Pos   (0U)
#define	ETH_MACHTHR_HTH_Msk   (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)
	0xFFFFFFFF
#define	ETH_MACHTHR_HTH   ETH_MACHTHR_HTH_Msk /* Hash table high */
#define	ETH_MACHTLR_HTL_Pos   (0U)
#define	ETH_MACHTLR_HTL_Msk   (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)
	0xFFFFFFFF
#define	ETH_MACHTLR_HTL   ETH_MACHTLR_HTL_Msk /* Hash table low */
#define	ETH_MACVTR_EIVLRXS_Pos   (31U)
#define	ETH_MACVTR_EIVLRXS_Msk   (0x1UL << ETH_MACVTR_EIVLRXS_Pos)
	0x80000000
#define	ETH_MACVTR_EIVLRXS   ETH_MACVTR_EIVLRXS_Msk /* Enable Inner VLAN Tag in Rx Status */
#define	ETH_MACVTR_EIVLS_Pos   (28U)
#define	ETH_MACVTR_EIVLS_Msk   (0x3UL << ETH_MACVTR_EIVLS_Pos)
	0x30000000
#define	ETH_MACVTR_EIVLS   ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
#define	ETH_MACVTR_EIVLS_DONOTSTRIP   (0U) /* Do not strip */
#define	ETH_MACVTR_EIVLS_STRIPIFPASS_Pos   (28U)
#define	ETH_MACVTR_EIVLS_STRIPIFPASS_Msk   (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos)
	0x10000000
#define	ETH_MACVTR_EIVLS_STRIPIFPASS   ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
#define	ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos   (29U)
#define	ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk   (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos)
	0x20000000
#define	ETH_MACVTR_EIVLS_STRIPIFFAILS   ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
#define	ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos   (28U)
#define	ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk   (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos)
	0x30000000
#define	ETH_MACVTR_EIVLS_ALWAYSSTRIP   ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
#define	ETH_MACVTR_ERIVLT_Pos   (27U)
#define	ETH_MACVTR_ERIVLT_Msk   (0x1UL << ETH_MACVTR_ERIVLT_Pos)
	0x08000000
#define	ETH_MACVTR_ERIVLT   ETH_MACVTR_ERIVLT_Msk /* Enable Inner VLAN Tag */
#define	ETH_MACVTR_EDVLP_Pos   (26U)
#define	ETH_MACVTR_EDVLP_Msk   (0x1UL << ETH_MACVTR_EDVLP_Pos)
	0x04000000
#define	ETH_MACVTR_EDVLP   ETH_MACVTR_EDVLP_Msk /* Enable Double VLAN Processing */
#define	ETH_MACVTR_VTHM_Pos   (25U)
#define	ETH_MACVTR_VTHM_Msk   (0x1UL << ETH_MACVTR_VTHM_Pos)
	0x02000000
#define	ETH_MACVTR_VTHM   ETH_MACVTR_VTHM_Msk /* VLAN Tag Hash Table Match Enable */
#define	ETH_MACVTR_EVLRXS_Pos   (24U)
#define	ETH_MACVTR_EVLRXS_Msk   (0x1UL << ETH_MACVTR_EVLRXS_Pos)
	0x01000000
#define	ETH_MACVTR_EVLRXS   ETH_MACVTR_EVLRXS_Msk /* Enable VLAN Tag in Rx status */
#define	ETH_MACVTR_EVLS_Pos   (21U)
#define	ETH_MACVTR_EVLS_Msk   (0x3UL << ETH_MACVTR_EVLS_Pos)
	0x00600000
#define	ETH_MACVTR_EVLS   ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
#define	ETH_MACVTR_EVLS_DONOTSTRIP   (0U) /* Do not strip */
#define	ETH_MACVTR_EVLS_STRIPIFPASS_Pos   (21U)
#define	ETH_MACVTR_EVLS_STRIPIFPASS_Msk   (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos)
	0x00200000
#define	ETH_MACVTR_EVLS_STRIPIFPASS   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
#define	ETH_MACVTR_EVLS_STRIPIFFAILS_Pos   (22U)
#define	ETH_MACVTR_EVLS_STRIPIFFAILS_Msk   (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos)
	0x00400000
#define	ETH_MACVTR_EVLS_STRIPIFFAILS   ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
#define	ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos   (21U)
#define	ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk   (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos)
	0x00600000
#define	ETH_MACVTR_EVLS_ALWAYSSTRIP   ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
#define	ETH_MACVTR_DOVLTC_Pos   (20U)
#define	ETH_MACVTR_DOVLTC_Msk   (0x1UL << ETH_MACVTR_DOVLTC_Pos)
	0x00100000
#define	ETH_MACVTR_DOVLTC   ETH_MACVTR_DOVLTC_Msk /* Disable VLAN Type Check */
#define	ETH_MACVTR_ERSVLM_Pos   (19U)
#define	ETH_MACVTR_ERSVLM_Msk   (0x1UL << ETH_MACVTR_ERSVLM_Pos)
	0x00080000
#define	ETH_MACVTR_ERSVLM   ETH_MACVTR_ERSVLM_Msk /* Enable Receive S-VLAN Match */
#define	ETH_MACVTR_ESVL_Pos   (18U)
#define	ETH_MACVTR_ESVL_Msk   (0x1UL << ETH_MACVTR_ESVL_Pos)
	0x00040000
#define	ETH_MACVTR_ESVL   ETH_MACVTR_ESVL_Msk /* Enable S-VLAN */
#define	ETH_MACVTR_VTIM_Pos   (17U)
#define	ETH_MACVTR_VTIM_Msk   (0x1UL << ETH_MACVTR_VTIM_Pos)
	0x00020000
#define	ETH_MACVTR_VTIM   ETH_MACVTR_VTIM_Msk /* VLAN Tag Inverse Match Enable */
#define	ETH_MACVTR_ETV_Pos   (16U)
#define	ETH_MACVTR_ETV_Msk   (0x1UL << ETH_MACVTR_ETV_Pos)
	0x00010000
#define	ETH_MACVTR_ETV   ETH_MACVTR_ETV_Msk /* Enable 12-Bit VLAN Tag Comparison */
#define	ETH_MACVTR_VL_Pos   (0U)
#define	ETH_MACVTR_VL_Msk   (0xFFFFUL << ETH_MACVTR_VL_Pos)
	0x0000FFFF
#define	ETH_MACVTR_VL   ETH_MACVTR_VL_Msk /* VLAN Tag Identifier for Receive Packets */
#define	ETH_MACVTR_VL_UP_Pos   (13U)
#define	ETH_MACVTR_VL_UP_Msk   (0x7UL << ETH_MACVTR_VL_UP_Pos)
	0x0000E000
#define	ETH_MACVTR_VL_UP   ETH_MACVTR_VL_UP_Msk /* User Priority */
#define	ETH_MACVTR_VL_CFIDEI_Pos   (12U)
#define	ETH_MACVTR_VL_CFIDEI_Msk   (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos)
	0x00001000
#define	ETH_MACVTR_VL_CFIDEI   ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
#define	ETH_MACVTR_VL_VID_Pos   (0U)
#define	ETH_MACVTR_VL_VID_Msk   (0xFFFUL << ETH_MACVTR_VL_VID_Pos)
	0x00000FFF
#define	ETH_MACVTR_VL_VID   ETH_MACVTR_VL_VID_Msk /* VLAN Identifier field of VLAN tag */
#define	ETH_MACVHTR_VLHT_Pos   (0U)
#define	ETH_MACVHTR_VLHT_Msk   (0xFFFFUL << ETH_MACVHTR_VLHT_Pos)
	0x0000FFFF
#define	ETH_MACVHTR_VLHT   ETH_MACVHTR_VLHT_Msk /* VLAN Hash Table */
#define	ETH_MACVIR_VLTI_Pos   (20U)
#define	ETH_MACVIR_VLTI_Msk   (0x1UL << ETH_MACVIR_VLTI_Pos)
	0x00100000
#define	ETH_MACVIR_VLTI   ETH_MACVIR_VLTI_Msk /* VLAN Tag Input */
#define	ETH_MACVIR_CSVL_Pos   (19U)
#define	ETH_MACVIR_CSVL_Msk   (0x1UL << ETH_MACVIR_CSVL_Pos)
	0x00080000
#define	ETH_MACVIR_CSVL   ETH_MACVIR_CSVL_Msk /* C-VLAN or S-VLAN */
#define	ETH_MACVIR_VLP_Pos   (18U)
#define	ETH_MACVIR_VLP_Msk   (0x1UL << ETH_MACVIR_VLP_Pos)
	0x00040000
#define	ETH_MACVIR_VLP   ETH_MACVIR_VLP_Msk /* VLAN Priority Control */
#define	ETH_MACVIR_VLC_Pos   (16U)
#define	ETH_MACVIR_VLC_Msk   (0x3UL << ETH_MACVIR_VLC_Pos)
	0x00030000
#define	ETH_MACVIR_VLC   ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
#define	ETH_MACVIR_VLC_NOVLANTAG   (0U) /* No VLAN tag deletion, insertion, or replacement */
#define	ETH_MACVIR_VLC_VLANTAGDELETE_Pos   (16U)
#define	ETH_MACVIR_VLC_VLANTAGDELETE_Msk   (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos)
	0x00010000
#define	ETH_MACVIR_VLC_VLANTAGDELETE   ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
#define	ETH_MACVIR_VLC_VLANTAGINSERT_Pos   (17U)
#define	ETH_MACVIR_VLC_VLANTAGINSERT_Msk   (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos)
	0x00020000
#define	ETH_MACVIR_VLC_VLANTAGINSERT   ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
#define	ETH_MACVIR_VLC_VLANTAGREPLACE_Pos   (16U)
#define	ETH_MACVIR_VLC_VLANTAGREPLACE_Msk   (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos)
	0x00030000
#define	ETH_MACVIR_VLC_VLANTAGREPLACE   ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
#define	ETH_MACVIR_VLT_Pos   (0U)
#define	ETH_MACVIR_VLT_Msk   (0xFFFFUL << ETH_MACVIR_VLT_Pos)
	0x0000FFFF
#define	ETH_MACVIR_VLT   ETH_MACVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
#define	ETH_MACVIR_VLT_UP_Pos   (13U)
#define	ETH_MACVIR_VLT_UP_Msk   (0x7UL << ETH_MACVIR_VLT_UP_Pos)
	0x0000E000
#define	ETH_MACVIR_VLT_UP   ETH_MACVIR_VLT_UP_Msk /* User Priority */
#define	ETH_MACVIR_VLT_CFIDEI_Pos   (12U)
#define	ETH_MACVIR_VLT_CFIDEI_Msk   (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos)
	0x00001000
#define	ETH_MACVIR_VLT_CFIDEI   ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
#define	ETH_MACVIR_VLT_VID_Pos   (0U)
#define	ETH_MACVIR_VLT_VID_Msk   (0xFFFUL << ETH_MACVIR_VLT_VID_Pos)
	0x00000FFF
#define	ETH_MACVIR_VLT_VID   ETH_MACVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
#define	ETH_MACIVIR_VLTI_Pos   (20U)
#define	ETH_MACIVIR_VLTI_Msk   (0x1UL << ETH_MACIVIR_VLTI_Pos)
	0x00100000
#define	ETH_MACIVIR_VLTI   ETH_MACIVIR_VLTI_Msk /* VLAN Tag Input */
#define	ETH_MACIVIR_CSVL_Pos   (19U)
#define	ETH_MACIVIR_CSVL_Msk   (0x1UL << ETH_MACIVIR_CSVL_Pos)
	0x00080000
#define	ETH_MACIVIR_CSVL   ETH_MACIVIR_CSVL_Msk /* C-VLAN or S-VLAN */
#define	ETH_MACIVIR_VLP_Pos   (18U)
#define	ETH_MACIVIR_VLP_Msk   (0x1UL << ETH_MACIVIR_VLP_Pos)
	0x00040000
#define	ETH_MACIVIR_VLP   ETH_MACIVIR_VLP_Msk /* VLAN Priority Control */
#define	ETH_MACIVIR_VLC_Pos   (16U)
#define	ETH_MACIVIR_VLC_Msk   (0x3UL << ETH_MACIVIR_VLC_Pos)
	0x00030000
#define	ETH_MACIVIR_VLC   ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
#define	ETH_MACIVIR_VLC_NOVLANTAG   (0U) /* No VLAN tag deletion, insertion, or replacement */
#define	ETH_MACIVIR_VLC_VLANTAGDELETE_Pos   (16U)
#define	ETH_MACIVIR_VLC_VLANTAGDELETE_Msk   (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos)
	0x00010000
#define	ETH_MACIVIR_VLC_VLANTAGDELETE   ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
#define	ETH_MACIVIR_VLC_VLANTAGINSERT_Pos   (17U)
#define	ETH_MACIVIR_VLC_VLANTAGINSERT_Msk   (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos)
	0x00020000
#define	ETH_MACIVIR_VLC_VLANTAGINSERT   ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
#define	ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos   (16U)
#define	ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk   (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos)
	0x00030000
#define	ETH_MACIVIR_VLC_VLANTAGREPLACE   ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
#define	ETH_MACIVIR_VLT_Pos   (0U)
#define	ETH_MACIVIR_VLT_Msk   (0xFFFFUL << ETH_MACIVIR_VLT_Pos)
	0x0000FFFF
#define	ETH_MACIVIR_VLT   ETH_MACIVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
#define	ETH_MACIVIR_VLT_UP_Pos   (13U)
#define	ETH_MACIVIR_VLT_UP_Msk   (0x7UL << ETH_MACIVIR_VLT_UP_Pos)
	0x0000E000
#define	ETH_MACIVIR_VLT_UP   ETH_MACIVIR_VLT_UP_Msk /* User Priority */
#define	ETH_MACIVIR_VLT_CFIDEI_Pos   (12U)
#define	ETH_MACIVIR_VLT_CFIDEI_Msk   (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos)
	0x00001000
#define	ETH_MACIVIR_VLT_CFIDEI   ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
#define	ETH_MACIVIR_VLT_VID_Pos   (0U)
#define	ETH_MACIVIR_VLT_VID_Msk   (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos)
	0x00000FFF
#define	ETH_MACIVIR_VLT_VID   ETH_MACIVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
#define	ETH_MACTFCR_PT_Pos   (16U)
#define	ETH_MACTFCR_PT_Msk   (0xFFFFUL << ETH_MACTFCR_PT_Pos)
	0xFFFF0000
#define	ETH_MACTFCR_PT   ETH_MACTFCR_PT_Msk /* Pause Time */
#define	ETH_MACTFCR_DZPQ_Pos   (7U)
#define	ETH_MACTFCR_DZPQ_Msk   (0x1UL << ETH_MACTFCR_DZPQ_Pos)
	0x00000080
#define	ETH_MACTFCR_DZPQ   ETH_MACTFCR_DZPQ_Msk /* Disable Zero-Quanta Pause */
#define	ETH_MACTFCR_PLT_Pos   (4U)
#define	ETH_MACTFCR_PLT_Msk   (0x7UL << ETH_MACTFCR_PLT_Pos)
	0x00000070
#define	ETH_MACTFCR_PLT   ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
#define	ETH_MACTFCR_PLT_MINUS4   (0U) /* Pause time minus 4 slot times */
#define	ETH_MACTFCR_PLT_MINUS28_Pos   (4U)
#define	ETH_MACTFCR_PLT_MINUS28_Msk   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos)
	0x00000010
#define	ETH_MACTFCR_PLT_MINUS28   ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
#define	ETH_MACTFCR_PLT_MINUS36_Pos   (5U)
#define	ETH_MACTFCR_PLT_MINUS36_Msk   (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos)
	0x00000020
#define	ETH_MACTFCR_PLT_MINUS36   ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
#define	ETH_MACTFCR_PLT_MINUS144_Pos   (4U)
#define	ETH_MACTFCR_PLT_MINUS144_Msk   (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos)
	0x00000030
#define	ETH_MACTFCR_PLT_MINUS144   ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
#define	ETH_MACTFCR_PLT_MINUS256_Pos   (6U)
#define	ETH_MACTFCR_PLT_MINUS256_Msk   (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos)
	0x00000040
#define	ETH_MACTFCR_PLT_MINUS256   ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
#define	ETH_MACTFCR_PLT_MINUS512_Pos   (4U)
#define	ETH_MACTFCR_PLT_MINUS512_Msk   (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos)
	0x00000050
#define	ETH_MACTFCR_PLT_MINUS512   ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
#define	ETH_MACTFCR_TFE_Pos   (1U)
#define	ETH_MACTFCR_TFE_Msk   (0x1UL << ETH_MACTFCR_TFE_Pos)
	0x00000002
#define	ETH_MACTFCR_TFE   ETH_MACTFCR_TFE_Msk /* Transmit Flow Control Enable */
#define	ETH_MACTFCR_FCB_Pos   (0U)
#define	ETH_MACTFCR_FCB_Msk   (0x1UL << ETH_MACTFCR_FCB_Pos)
	0x00000001
#define	ETH_MACTFCR_FCB   ETH_MACTFCR_FCB_Msk /* Flow Control Busy or Backpressure Activate */
#define	ETH_MACRFCR_UP_Pos   (1U)
#define	ETH_MACRFCR_UP_Msk   (0x1UL << ETH_MACRFCR_UP_Pos)
	0x00000002
#define	ETH_MACRFCR_UP   ETH_MACRFCR_UP_Msk /* Unicast Pause Packet Detect */
#define	ETH_MACRFCR_RFE_Pos   (0U)
#define	ETH_MACRFCR_RFE_Msk   (0x1UL << ETH_MACRFCR_RFE_Pos)
	0x00000001
#define	ETH_MACRFCR_RFE   ETH_MACRFCR_RFE_Msk /* Receive Flow Control Enable */
#define	ETH_MACISR_RXSTSIS_Pos   (14U)
#define	ETH_MACISR_RXSTSIS_Msk   (0x1UL << ETH_MACISR_RXSTSIS_Pos)
	0x00004000
#define	ETH_MACISR_RXSTSIS   ETH_MACISR_RXSTSIS_Msk /* Receive Status Interrupt */
#define	ETH_MACISR_TXSTSIS_Pos   (13U)
#define	ETH_MACISR_TXSTSIS_Msk   (0x1UL << ETH_MACISR_TXSTSIS_Pos)
	0x00002000
#define	ETH_MACISR_TXSTSIS   ETH_MACISR_TXSTSIS_Msk /* Transmit Status Interrupt */
#define	ETH_MACISR_TSIS_Pos   (12U)
#define	ETH_MACISR_TSIS_Msk   (0x1UL << ETH_MACISR_TSIS_Pos)
	0x00001000
#define	ETH_MACISR_TSIS   ETH_MACISR_TSIS_Msk /* Timestamp Interrupt Status */
#define	ETH_MACISR_MMCTXIS_Pos   (10U)
#define	ETH_MACISR_MMCTXIS_Msk   (0x1UL << ETH_MACISR_MMCTXIS_Pos)
	0x00000400
#define	ETH_MACISR_MMCTXIS   ETH_MACISR_MMCTXIS_Msk /* MMC Transmit Interrupt Status */
#define	ETH_MACISR_MMCRXIS_Pos   (9U)
#define	ETH_MACISR_MMCRXIS_Msk   (0x1UL << ETH_MACISR_MMCRXIS_Pos)
	0x00000200
#define	ETH_MACISR_MMCRXIS   ETH_MACISR_MMCRXIS_Msk /* MMC Receive Interrupt Status */
#define	ETH_MACISR_MMCIS_Pos   (8U)
#define	ETH_MACISR_MMCIS_Msk   (0x1UL << ETH_MACISR_MMCIS_Pos)
	0x00000100
#define	ETH_MACISR_MMCIS   ETH_MACISR_MMCIS_Msk /* MMC Interrupt Status */
#define	ETH_MACISR_LPIIS_Pos   (5U)
#define	ETH_MACISR_LPIIS_Msk   (0x1UL << ETH_MACISR_LPIIS_Pos)
	0x00000020
#define	ETH_MACISR_LPIIS   ETH_MACISR_LPIIS_Msk /* LPI Interrupt Status */
#define	ETH_MACISR_PMTIS_Pos   (4U)
#define	ETH_MACISR_PMTIS_Msk   (0x1UL << ETH_MACISR_PMTIS_Pos)
	0x00000010
#define	ETH_MACISR_PMTIS   ETH_MACISR_PMTIS_Msk /* PMT Interrupt Status */
#define	ETH_MACISR_PHYIS_Pos   (3U)
#define	ETH_MACISR_PHYIS_Msk   (0x1UL << ETH_MACISR_PHYIS_Pos)
	0x00000008
#define	ETH_MACISR_PHYIS   ETH_MACISR_PHYIS_Msk /* PHY Interrupt */
#define	ETH_MACIER_RXSTSIE_Pos   (14U)
#define	ETH_MACIER_RXSTSIE_Msk   (0x1UL << ETH_MACIER_RXSTSIE_Pos)
	0x00004000
#define	ETH_MACIER_RXSTSIE   ETH_MACIER_RXSTSIE_Msk /* Receive Status Interrupt Enable */
#define	ETH_MACIER_TXSTSIE_Pos   (13U)
#define	ETH_MACIER_TXSTSIE_Msk   (0x1UL << ETH_MACIER_TXSTSIE_Pos)
	0x00002000
#define	ETH_MACIER_TXSTSIE   ETH_MACIER_TXSTSIE_Msk /* Transmit Status Interrupt Enable */
#define	ETH_MACIER_TSIE_Pos   (12U)
#define	ETH_MACIER_TSIE_Msk   (0x1UL << ETH_MACIER_TSIE_Pos)
	0x00001000
#define	ETH_MACIER_TSIE   ETH_MACIER_TSIE_Msk /* Timestamp Interrupt Enable */
#define	ETH_MACIER_LPIIE_Pos   (5U)
#define	ETH_MACIER_LPIIE_Msk   (0x1UL << ETH_MACIER_LPIIE_Pos)
	0x00000020
#define	ETH_MACIER_LPIIE   ETH_MACIER_LPIIE_Msk /* LPI Interrupt Enable */
#define	ETH_MACIER_PMTIE_Pos   (4U)
#define	ETH_MACIER_PMTIE_Msk   (0x1UL << ETH_MACIER_PMTIE_Pos)
	0x00000010
#define	ETH_MACIER_PMTIE   ETH_MACIER_PMTIE_Msk /* PMT Interrupt Enable */
#define	ETH_MACIER_PHYIE_Pos   (3U)
#define	ETH_MACIER_PHYIE_Msk   (0x1UL << ETH_MACIER_PHYIE_Pos)
	0x00000008
#define	ETH_MACIER_PHYIE   ETH_MACIER_PHYIE_Msk /* PHY Interrupt Enable */
#define	ETH_MACRXTXSR_RWT_Pos   (8U)
#define	ETH_MACRXTXSR_RWT_Msk   (0x1UL << ETH_MACRXTXSR_RWT_Pos)
	0x00000100
#define	ETH_MACRXTXSR_RWT   ETH_MACRXTXSR_RWT_Msk /* Receive Watchdog Timeout */
#define	ETH_MACRXTXSR_EXCOL_Pos   (5U)
#define	ETH_MACRXTXSR_EXCOL_Msk   (0x1UL << ETH_MACRXTXSR_EXCOL_Pos)
	0x00000020
#define	ETH_MACRXTXSR_EXCOL   ETH_MACRXTXSR_EXCOL_Msk /* Excessive Collisions */
#define	ETH_MACRXTXSR_LCOL_Pos   (4U)
#define	ETH_MACRXTXSR_LCOL_Msk   (0x1UL << ETH_MACRXTXSR_LCOL_Pos)
	0x00000010
#define	ETH_MACRXTXSR_LCOL   ETH_MACRXTXSR_LCOL_Msk /* Late Collision */
#define	ETH_MACRXTXSR_EXDEF_Pos   (3U)
#define	ETH_MACRXTXSR_EXDEF_Msk   (0x1UL << ETH_MACRXTXSR_EXDEF_Pos)
	0x00000008
#define	ETH_MACRXTXSR_EXDEF   ETH_MACRXTXSR_EXDEF_Msk /* Excessive Deferral */
#define	ETH_MACRXTXSR_LCARR_Pos   (2U)
#define	ETH_MACRXTXSR_LCARR_Msk   (0x1UL << ETH_MACRXTXSR_LCARR_Pos)
	0x00000004
#define	ETH_MACRXTXSR_LCARR   ETH_MACRXTXSR_LCARR_Msk /* Loss of Carrier */
#define	ETH_MACRXTXSR_NCARR_Pos   (1U)
#define	ETH_MACRXTXSR_NCARR_Msk   (0x1UL << ETH_MACRXTXSR_NCARR_Pos)
	0x00000002
#define	ETH_MACRXTXSR_NCARR   ETH_MACRXTXSR_NCARR_Msk /* No Carrier */
#define	ETH_MACRXTXSR_TJT_Pos   (0U)
#define	ETH_MACRXTXSR_TJT_Msk   (0x1UL << ETH_MACRXTXSR_TJT_Pos)
	0x00000001
#define	ETH_MACRXTXSR_TJT   ETH_MACRXTXSR_TJT_Msk /* Transmit Jabber Timeout */
#define	ETH_MACPCSR_RWKFILTRST_Pos   (31U)
#define	ETH_MACPCSR_RWKFILTRST_Msk   (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos)
	0x80000000
#define	ETH_MACPCSR_RWKFILTRST   ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
#define	ETH_MACPCSR_RWKPTR_Pos   (24U)
#define	ETH_MACPCSR_RWKPTR_Msk   (0x1FUL << ETH_MACPCSR_RWKPTR_Pos)
	0x1F000000
#define	ETH_MACPCSR_RWKPTR   ETH_MACPCSR_RWKPTR_Msk /* Remote Wake-up FIFO Pointer */
#define	ETH_MACPCSR_RWKPFE_Pos   (10U)
#define	ETH_MACPCSR_RWKPFE_Msk   (0x1UL << ETH_MACPCSR_RWKPFE_Pos)
	0x00000400
#define	ETH_MACPCSR_RWKPFE   ETH_MACPCSR_RWKPFE_Msk /* Remote Wake-up Packet Forwarding Enable */
#define	ETH_MACPCSR_GLBLUCAST_Pos   (9U)
#define	ETH_MACPCSR_GLBLUCAST_Msk   (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos)
	0x00000200
#define	ETH_MACPCSR_GLBLUCAST   ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
#define	ETH_MACPCSR_RWKPRCVD_Pos   (6U)
#define	ETH_MACPCSR_RWKPRCVD_Msk   (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos)
	0x00000040
#define	ETH_MACPCSR_RWKPRCVD   ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
#define	ETH_MACPCSR_MGKPRCVD_Pos   (5U)
#define	ETH_MACPCSR_MGKPRCVD_Msk   (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos)
	0x00000020
#define	ETH_MACPCSR_MGKPRCVD   ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
#define	ETH_MACPCSR_RWKPKTEN_Pos   (2U)
#define	ETH_MACPCSR_RWKPKTEN_Msk   (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos)
	0x00000004
#define	ETH_MACPCSR_RWKPKTEN   ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
#define	ETH_MACPCSR_MGKPKTEN_Pos   (1U)
#define	ETH_MACPCSR_MGKPKTEN_Msk   (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos)
	0x00000002
#define	ETH_MACPCSR_MGKPKTEN   ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
#define	ETH_MACPCSR_PWRDWN_Pos   (0U)
#define	ETH_MACPCSR_PWRDWN_Msk   (0x1UL << ETH_MACPCSR_PWRDWN_Pos)
	0x00000001
#define	ETH_MACPCSR_PWRDWN   ETH_MACPCSR_PWRDWN_Msk /* Power Down */
#define	ETH_MACRWUPFR_D_Pos   (0U)
#define	ETH_MACRWUPFR_D_Msk   (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos)
	0xFFFFFFFF
#define	ETH_MACRWUPFR_D   ETH_MACRWUPFR_D_Msk /* Wake-up Packet filter register data */
#define	ETH_MACLCSR_LPITCSE_Pos   (21U)
#define	ETH_MACLCSR_LPITCSE_Msk   (0x1UL << ETH_MACLCSR_LPITCSE_Pos)
	0x00200000
#define	ETH_MACLCSR_LPITCSE   ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */
#define	ETH_MACLCSR_LPITE_Pos   (20U)
#define	ETH_MACLCSR_LPITE_Msk   (0x1UL << ETH_MACLCSR_LPITE_Pos)
	0x00100000
#define	ETH_MACLCSR_LPITE   ETH_MACLCSR_LPITE_Msk /* LPI Timer Enable */
#define	ETH_MACLCSR_LPITXA_Pos   (19U)
#define	ETH_MACLCSR_LPITXA_Msk   (0x1UL << ETH_MACLCSR_LPITXA_Pos)
	0x00080000
#define	ETH_MACLCSR_LPITXA   ETH_MACLCSR_LPITXA_Msk /* LPI Tx Automate */
#define	ETH_MACLCSR_PLS_Pos   (17U)
#define	ETH_MACLCSR_PLS_Msk   (0x1UL << ETH_MACLCSR_PLS_Pos)
	0x00020000
#define	ETH_MACLCSR_PLS   ETH_MACLCSR_PLS_Msk /* PHY Link Status */
#define	ETH_MACLCSR_LPIEN_Pos   (16U)
#define	ETH_MACLCSR_LPIEN_Msk   (0x1UL << ETH_MACLCSR_LPIEN_Pos)
	0x00010000
#define	ETH_MACLCSR_LPIEN   ETH_MACLCSR_LPIEN_Msk /* LPI Enable */
#define	ETH_MACLCSR_RLPIST_Pos   (9U)
#define	ETH_MACLCSR_RLPIST_Msk   (0x1UL << ETH_MACLCSR_RLPIST_Pos)
	0x00000200
#define	ETH_MACLCSR_RLPIST   ETH_MACLCSR_RLPIST_Msk /* Receive LPI State */
#define	ETH_MACLCSR_TLPIST_Pos   (8U)
#define	ETH_MACLCSR_TLPIST_Msk   (0x1UL << ETH_MACLCSR_TLPIST_Pos)
	0x00000100
#define	ETH_MACLCSR_TLPIST   ETH_MACLCSR_TLPIST_Msk /* Transmit LPI State */
#define	ETH_MACLCSR_RLPIEX_Pos   (3U)
#define	ETH_MACLCSR_RLPIEX_Msk   (0x1UL << ETH_MACLCSR_RLPIEX_Pos)
	0x00000008
#define	ETH_MACLCSR_RLPIEX   ETH_MACLCSR_RLPIEX_Msk /* Receive LPI Exit */
#define	ETH_MACLCSR_RLPIEN_Pos   (2U)
#define	ETH_MACLCSR_RLPIEN_Msk   (0x1UL << ETH_MACLCSR_RLPIEN_Pos)
	0x00000004
#define	ETH_MACLCSR_RLPIEN   ETH_MACLCSR_RLPIEN_Msk /* Receive LPI Entry */
#define	ETH_MACLCSR_TLPIEX_Pos   (1U)
#define	ETH_MACLCSR_TLPIEX_Msk   (0x1UL << ETH_MACLCSR_TLPIEX_Pos)
	0x00000002
#define	ETH_MACLCSR_TLPIEX   ETH_MACLCSR_TLPIEX_Msk /* Transmit LPI Exit */
#define	ETH_MACLCSR_TLPIEN_Pos   (0U)
#define	ETH_MACLCSR_TLPIEN_Msk   (0x1UL << ETH_MACLCSR_TLPIEN_Pos)
	0x00000001
#define	ETH_MACLCSR_TLPIEN   ETH_MACLCSR_TLPIEN_Msk /* Transmit LPI Entry */
#define	ETH_MACLTCR_LST_Pos   (16U)
#define	ETH_MACLTCR_LST_Msk   (0x3FFUL << ETH_MACLTCR_LST_Pos)
	0x03FF0000
#define	ETH_MACLTCR_LST   ETH_MACLTCR_LST_Msk /* LPI LS TIMER */
#define	ETH_MACLTCR_TWT_Pos   (0U)
#define	ETH_MACLTCR_TWT_Msk   (0xFFFFUL << ETH_MACLTCR_TWT_Pos)
	0x0000FFFF
#define	ETH_MACLTCR_TWT   ETH_MACLTCR_TWT_Msk /* LPI TW TIMER */
#define	ETH_MACLETR_LPIET_Pos   (0U)
#define	ETH_MACLETR_LPIET_Msk   (0xFFFFFUL << ETH_MACLETR_LPIET_Pos)
	0x000FFFFF
#define	ETH_MACLETR_LPIET   ETH_MACLETR_LPIET_Msk /* LPI Entry Timer */
#define	ETH_MAC1USTCR_TIC1USCNTR_Pos   (0U)
#define	ETH_MAC1USTCR_TIC1USCNTR_Msk   (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos)
	0x00000FFF
#define	ETH_MAC1USTCR_TIC1USCNTR   ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
#define	ETH_MACVR_USERVER_Pos   (8U)
#define	ETH_MACVR_USERVER_Msk   (0xFFUL << ETH_MACVR_USERVER_Pos)
	0x0000FF00
#define	ETH_MACVR_USERVER   ETH_MACVR_USERVER_Msk /* User-defined Version */
#define	ETH_MACVR_SNPSVER_Pos   (0U)
#define	ETH_MACVR_SNPSVER_Msk   (0xFFUL << ETH_MACVR_SNPSVER_Pos)
	0x000000FF
#define	ETH_MACVR_SNPSVER   ETH_MACVR_SNPSVER_Msk /* Synopsys-defined Version */
#define	ETH_MACDR_TFCSTS_Pos   (17U)
#define	ETH_MACDR_TFCSTS_Msk   (0x3UL << ETH_MACDR_TFCSTS_Pos)
	0x00060000
#define	ETH_MACDR_TFCSTS   ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
#define	ETH_MACDR_TFCSTS_IDLE   (0U) /* Idle state */
#define	ETH_MACDR_TFCSTS_WAIT_Pos   (17U)
#define	ETH_MACDR_TFCSTS_WAIT_Msk   (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos)
	0x00020000
#define	ETH_MACDR_TFCSTS_WAIT   ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
#define	ETH_MACDR_TFCSTS_GENERATEPCP_Pos   (18U)
#define	ETH_MACDR_TFCSTS_GENERATEPCP_Msk   (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos)
	0x00040000
#define	ETH_MACDR_TFCSTS_GENERATEPCP   ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
#define	ETH_MACDR_TFCSTS_TRASFERIP_Pos   (17U)
#define	ETH_MACDR_TFCSTS_TRASFERIP_Msk   (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos)
	0x00060000
#define	ETH_MACDR_TFCSTS_TRASFERIP   ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
#define	ETH_MACDR_TPESTS_Pos   (16U)
#define	ETH_MACDR_TPESTS_Msk   (0x1UL << ETH_MACDR_TPESTS_Pos)
	0x00010000
#define	ETH_MACDR_TPESTS   ETH_MACDR_TPESTS_Msk /* MAC Receive Packet Controller FIFO Status */
#define	ETH_MACDR_RFCFCSTS_Pos   (1U)
#define	ETH_MACDR_RFCFCSTS_Msk   (0x3UL << ETH_MACDR_RFCFCSTS_Pos)
	0x00000006
#define	ETH_MACDR_RFCFCSTS   ETH_MACDR_RFCFCSTS_Msk /* MAC MII Transmit Protocol Engine Status */
#define	ETH_MACDR_RPESTS_Pos   (0U)
#define	ETH_MACDR_RPESTS_Msk   (0x1UL << ETH_MACDR_RPESTS_Pos)
	0x00000001
#define	ETH_MACDR_RPESTS   ETH_MACDR_RPESTS_Msk /* MAC MII Receive Protocol Engine Status */
#define	ETH_MACHWF0R_ACTPHYSEL_Pos   (28U)
#define	ETH_MACHWF0R_ACTPHYSEL_Msk   (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos)
	0x70000000
#define	ETH_MACHWF0R_ACTPHYSEL   ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
#define	ETH_MACHWF0R_ACTPHYSEL_MII   (0U) /* MII */
#define	ETH_MACHWF0R_ACTPHYSEL_RMII_Pos   (30U)
#define	ETH_MACHWF0R_ACTPHYSEL_RMII_Msk   (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos)
	0x40000000
#define	ETH_MACHWF0R_ACTPHYSEL_RMII   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
#define	ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos   (28U)
#define	ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk   (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos)
	0x70000000
#define	ETH_MACHWF0R_ACTPHYSEL_REVMII   ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */
#define	ETH_MACHWF0R_SAVLANINS_Pos   (27U)
#define	ETH_MACHWF0R_SAVLANINS_Msk   (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos)
	0x08000000
#define	ETH_MACHWF0R_SAVLANINS   ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
#define	ETH_MACHWF0R_TSSTSSEL_Pos   (25U)
#define	ETH_MACHWF0R_TSSTSSEL_Msk   (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos)
	0x06000000
#define	ETH_MACHWF0R_TSSTSSEL   ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
#define	ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos   (25U)
#define	ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk   (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos)
	0x02000000
#define	ETH_MACHWF0R_TSSTSSEL_INTERNAL   ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
#define	ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos   (26U)
#define	ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk   (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos)
	0x04000000
#define	ETH_MACHWF0R_TSSTSSEL_EXTERNAL   ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
#define	ETH_MACHWF0R_TSSTSSEL_BOTH_Pos   (25U)
#define	ETH_MACHWF0R_TSSTSSEL_BOTH_Msk   (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos)
	0x06000000
#define	ETH_MACHWF0R_TSSTSSEL_BOTH   ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
#define	ETH_MACHWF0R_MACADR64SEL_Pos   (24U)
#define	ETH_MACHWF0R_MACADR64SEL_Msk   (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos)
	0x01000000
#define	ETH_MACHWF0R_MACADR64SEL   ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
#define	ETH_MACHWF0R_MACADR32SEL_Pos   (23U)
#define	ETH_MACHWF0R_MACADR32SEL_Msk   (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos)
	0x00800000
#define	ETH_MACHWF0R_MACADR32SEL   ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
#define	ETH_MACHWF0R_ADDMACADRSEL_Pos   (18U)
#define	ETH_MACHWF0R_ADDMACADRSEL_Msk   (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos)
	0x007C0000
#define	ETH_MACHWF0R_ADDMACADRSEL   ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
#define	ETH_MACHWF0R_RXCOESEL_Pos   (16U)
#define	ETH_MACHWF0R_RXCOESEL_Msk   (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos)
	0x00010000
#define	ETH_MACHWF0R_RXCOESEL   ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
#define	ETH_MACHWF0R_TXCOESEL_Pos   (14U)
#define	ETH_MACHWF0R_TXCOESEL_Msk   (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos)
	0x00004000
#define	ETH_MACHWF0R_TXCOESEL   ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
#define	ETH_MACHWF0R_EEESEL_Pos   (13U)
#define	ETH_MACHWF0R_EEESEL_Msk   (0x1UL << ETH_MACHWF0R_EEESEL_Pos)
	0x00002000
#define	ETH_MACHWF0R_EEESEL   ETH_MACHWF0R_EEESEL_Msk /* Energy Efficient Ethernet Enabled */
#define	ETH_MACHWF0R_TSSEL_Pos   (12U)
#define	ETH_MACHWF0R_TSSEL_Msk   (0x1UL << ETH_MACHWF0R_TSSEL_Pos)
	0x00001000
#define	ETH_MACHWF0R_TSSEL   ETH_MACHWF0R_TSSEL_Msk /* IEEE 1588-2008 Timestamp Enabled */
#define	ETH_MACHWF0R_ARPOFFSEL_Pos   (9U)
#define	ETH_MACHWF0R_ARPOFFSEL_Msk   (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos)
	0x00000200
#define	ETH_MACHWF0R_ARPOFFSEL   ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
#define	ETH_MACHWF0R_MMCSEL_Pos   (8U)
#define	ETH_MACHWF0R_MMCSEL_Msk   (0x1UL << ETH_MACHWF0R_MMCSEL_Pos)
	0x00000100
#define	ETH_MACHWF0R_MMCSEL   ETH_MACHWF0R_MMCSEL_Msk /* RMON Module Enable */
#define	ETH_MACHWF0R_MGKSEL_Pos   (7U)
#define	ETH_MACHWF0R_MGKSEL_Msk   (0x1UL << ETH_MACHWF0R_MGKSEL_Pos)
	0x00000080
#define	ETH_MACHWF0R_MGKSEL   ETH_MACHWF0R_MGKSEL_Msk /* PMT Magic Packet Enable */
#define	ETH_MACHWF0R_RWKSEL_Pos   (6U)
#define	ETH_MACHWF0R_RWKSEL_Msk   (0x1UL << ETH_MACHWF0R_RWKSEL_Pos)
	0x00000040
#define	ETH_MACHWF0R_RWKSEL   ETH_MACHWF0R_RWKSEL_Msk /* PMT Remote Wake-up Packet Enable */
#define	ETH_MACHWF0R_SMASEL_Pos   (5U)
#define	ETH_MACHWF0R_SMASEL_Msk   (0x1UL << ETH_MACHWF0R_SMASEL_Pos)
	0x00000020
#define	ETH_MACHWF0R_SMASEL   ETH_MACHWF0R_SMASEL_Msk /* SMA (MDIO) Interface */
#define	ETH_MACHWF0R_VLHASH_Pos   (4U)
#define	ETH_MACHWF0R_VLHASH_Msk   (0x1UL << ETH_MACHWF0R_VLHASH_Pos)
	0x00000010
#define	ETH_MACHWF0R_VLHASH   ETH_MACHWF0R_VLHASH_Msk /* VLAN Hash Filter Selected */
#define	ETH_MACHWF0R_PCSSEL_Pos   (3U)
#define	ETH_MACHWF0R_PCSSEL_Msk   (0x1UL << ETH_MACHWF0R_PCSSEL_Pos)
	0x00000008
#define	ETH_MACHWF0R_PCSSEL   ETH_MACHWF0R_PCSSEL_Msk /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
#define	ETH_MACHWF0R_HDSEL_Pos   (2U)
#define	ETH_MACHWF0R_HDSEL_Msk   (0x1UL << ETH_MACHWF0R_HDSEL_Pos)
	0x00000004
#define	ETH_MACHWF0R_HDSEL   ETH_MACHWF0R_HDSEL_Msk /* Half-duplex Support */
#define	ETH_MACHWF0R_GMIISEL_Pos   (1U)
#define	ETH_MACHWF0R_GMIISEL_Msk   (0x1UL << ETH_MACHWF0R_GMIISEL_Pos)
	0x00000002
#define	ETH_MACHWF0R_GMIISEL   ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
#define	ETH_MACHWF0R_MIISEL_Pos   (0U)
#define	ETH_MACHWF0R_MIISEL_Msk   (0x1UL << ETH_MACHWF0R_MIISEL_Pos)
	0x00000001
#define	ETH_MACHWF0R_MIISEL   ETH_MACHWF0R_MIISEL_Msk /* 10 or 100 Mbps Support */
#define	ETH_MACHWF1R_L3L4FNUM_Pos   (27U)
#define	ETH_MACHWF1R_L3L4FNUM_Msk   (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos)
	0x78000000
#define	ETH_MACHWF1R_L3L4FNUM   ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
#define	ETH_MACHWF1R_HASHTBLSZ_Pos   (24U)
#define	ETH_MACHWF1R_HASHTBLSZ_Msk   (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos)
	0x03000000
#define	ETH_MACHWF1R_HASHTBLSZ   ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
#define	ETH_MACHWF1R_AVSEL_Pos   (20U)
#define	ETH_MACHWF1R_AVSEL_Msk   (0x1UL << ETH_MACHWF1R_AVSEL_Pos)
	0x00100000
#define	ETH_MACHWF1R_AVSEL   ETH_MACHWF1R_AVSEL_Msk /* AV Feature Enabled */
#define	ETH_MACHWF1R_DBGMEMA_Pos   (19U)
#define	ETH_MACHWF1R_DBGMEMA_Msk   (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos)
	0x00080000
#define	ETH_MACHWF1R_DBGMEMA   ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
#define	ETH_MACHWF1R_TSOEN_Pos   (18U)
#define	ETH_MACHWF1R_TSOEN_Msk   (0x1UL << ETH_MACHWF1R_TSOEN_Pos)
	0x00040000
#define	ETH_MACHWF1R_TSOEN   ETH_MACHWF1R_TSOEN_Msk /* TCP Segmentation Offload Enable */
#define	ETH_MACHWF1R_SPHEN_Pos   (17U)
#define	ETH_MACHWF1R_SPHEN_Msk   (0x1UL << ETH_MACHWF1R_SPHEN_Pos)
	0x00020000
#define	ETH_MACHWF1R_SPHEN   ETH_MACHWF1R_SPHEN_Msk /* Split Header Feature Enable */
#define	ETH_MACHWF1R_DCBEN_Pos   (16U)
#define	ETH_MACHWF1R_DCBEN_Msk   (0x1UL << ETH_MACHWF1R_DCBEN_Pos)
	0x00010000
#define	ETH_MACHWF1R_DCBEN   ETH_MACHWF1R_DCBEN_Msk /* DCB Feature Enable */
#define	ETH_MACHWF1R_ADDR64_Pos   (14U)
#define	ETH_MACHWF1R_ADDR64_Msk   (0x3UL << ETH_MACHWF1R_ADDR64_Pos)
	0x0000C000
#define	ETH_MACHWF1R_ADDR64   ETH_MACHWF1R_ADDR64_Msk /* Address Width */
#define	ETH_MACHWF1R_ADDR64_32   (0x0UL << ETH_MACHWF1R_ADDR64_Pos)
	0x00000000
#define	ETH_MACHWF1R_ADDR64_40   (0x1UL << ETH_MACHWF1R_ADDR64_Pos)
	0x00004000
#define	ETH_MACHWF1R_ADDR64_48   (0x2UL << ETH_MACHWF1R_ADDR64_Pos)
	0x00008000
#define	ETH_MACHWF1R_ADVTHWORD_Pos   (13U)
#define	ETH_MACHWF1R_ADVTHWORD_Msk   (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos)
	0x00002000
#define	ETH_MACHWF1R_ADVTHWORD   ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
#define	ETH_MACHWF1R_PTOEN_Pos   (12U)
#define	ETH_MACHWF1R_PTOEN_Msk   (0x1UL << ETH_MACHWF1R_PTOEN_Pos)
	0x00001000
#define	ETH_MACHWF1R_PTOEN   ETH_MACHWF1R_PTOEN_Msk /* PTP Offload Enable */
#define	ETH_MACHWF1R_OSTEN_Pos   (11U)
#define	ETH_MACHWF1R_OSTEN_Msk   (0x1UL << ETH_MACHWF1R_OSTEN_Pos)
	0x00000800
#define	ETH_MACHWF1R_OSTEN   ETH_MACHWF1R_OSTEN_Msk /* One-Step Timestamping Enable */
#define	ETH_MACHWF1R_TXFIFOSIZE_Pos   (6U)
#define	ETH_MACHWF1R_TXFIFOSIZE_Msk   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos)
	0x000007C0
#define	ETH_MACHWF1R_TXFIFOSIZE   ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
#define	ETH_MACHWF1R_RXFIFOSIZE_Pos   (0U)
#define	ETH_MACHWF1R_RXFIFOSIZE_Msk   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos)
	0x0000001F
#define	ETH_MACHWF1R_RXFIFOSIZE   ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
#define	ETH_MACHWF2R_AUXSNAPNUM_Pos   (28U)
#define	ETH_MACHWF2R_AUXSNAPNUM_Msk   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos)
	0x70000000
#define	ETH_MACHWF2R_AUXSNAPNUM   ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
#define	ETH_MACHWF2R_PPSOUTNUM_Pos   (24U)
#define	ETH_MACHWF2R_PPSOUTNUM_Msk   (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos)
	0x07000000
#define	ETH_MACHWF2R_PPSOUTNUM   ETH_MACHWF2R_PPSOUTNUM_Msk /* Number of PPS Outputs */
#define	ETH_MACHWF2R_TXCHCNT_Pos   (18U)
#define	ETH_MACHWF2R_TXCHCNT_Msk   (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos)
	0x003C0000
#define	ETH_MACHWF2R_TXCHCNT   ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
#define	ETH_MACHWF2R_RXCHCNT_Pos   (13U)
#define	ETH_MACHWF2R_RXCHCNT_Msk   (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos)
	0x0000E000
#define	ETH_MACHWF2R_RXCHCNT   ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
#define	ETH_MACHWF2R_TXQCNT_Pos   (6U)
#define	ETH_MACHWF2R_TXQCNT_Msk   (0xFUL << ETH_MACHWF2R_TXQCNT_Pos)
	0x000003C0
#define	ETH_MACHWF2R_TXQCNT   ETH_MACHWF2R_TXQCNT_Msk /* Number of MTL Transmit Queues */
#define	ETH_MACHWF2R_RXQCNT_Pos   (0U)
#define	ETH_MACHWF2R_RXQCNT_Msk   (0xFUL << ETH_MACHWF2R_RXQCNT_Pos)
	0x0000000F
#define	ETH_MACHWF2R_RXQCNT   ETH_MACHWF2R_RXQCNT_Msk /* Number of MTL Receive Queues */
#define	ETH_MACMDIOAR_PSE_Pos   (27U)
#define	ETH_MACMDIOAR_PSE_Msk   (0x1UL << ETH_MACMDIOAR_PSE_Pos)
	0x08000000
#define	ETH_MACMDIOAR_PSE   ETH_MACMDIOAR_PSE_Msk /* Preamble Suppression Enable */
#define	ETH_MACMDIOAR_BTB_Pos   (26U)
#define	ETH_MACMDIOAR_BTB_Msk   (0x1UL << ETH_MACMDIOAR_BTB_Pos)
	0x04000000
#define	ETH_MACMDIOAR_BTB   ETH_MACMDIOAR_BTB_Msk /* Back to Back transactions */
#define	ETH_MACMDIOAR_PA_Pos   (21U)
#define	ETH_MACMDIOAR_PA_Msk   (0x1FUL << ETH_MACMDIOAR_PA_Pos)
	0x03E00000
#define	ETH_MACMDIOAR_PA   ETH_MACMDIOAR_PA_Msk /* Physical Layer Address */
#define	ETH_MACMDIOAR_RDA_Pos   (16U)
#define	ETH_MACMDIOAR_RDA_Msk   (0x1FUL << ETH_MACMDIOAR_RDA_Pos)
	0x001F0000
#define	ETH_MACMDIOAR_RDA   ETH_MACMDIOAR_RDA_Msk /* Register/Device Address */
#define	ETH_MACMDIOAR_NTC_Pos   (12U)
#define	ETH_MACMDIOAR_NTC_Msk   (0x7UL << ETH_MACMDIOAR_NTC_Pos)
	0x00007000
#define	ETH_MACMDIOAR_NTC   ETH_MACMDIOAR_NTC_Msk /* Number of Trailing Clocks */
#define	ETH_MACMDIOAR_CR_Pos   (8U)
#define	ETH_MACMDIOAR_CR_Msk   (0xFUL << ETH_MACMDIOAR_CR_Pos)
	0x00000F00
#define	ETH_MACMDIOAR_CR   ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
#define	ETH_MACMDIOAR_CR_DIV42   (0U) /* CSR clock/42 */
#define	ETH_MACMDIOAR_CR_DIV62_Pos   (8U)
#define	ETH_MACMDIOAR_CR_DIV62_Msk   (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos)
	0x00000100
#define	ETH_MACMDIOAR_CR_DIV62   ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
#define	ETH_MACMDIOAR_CR_DIV16_Pos   (9U)
#define	ETH_MACMDIOAR_CR_DIV16_Msk   (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos)
	0x00000200
#define	ETH_MACMDIOAR_CR_DIV16   ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
#define	ETH_MACMDIOAR_CR_DIV26_Pos   (8U)
#define	ETH_MACMDIOAR_CR_DIV26_Msk   (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos)
	0x00000300
#define	ETH_MACMDIOAR_CR_DIV26   ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
#define	ETH_MACMDIOAR_CR_DIV102_Pos   (10U)
#define	ETH_MACMDIOAR_CR_DIV102_Msk   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos)
	0x00000400
#define	ETH_MACMDIOAR_CR_DIV102   ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
#define	ETH_MACMDIOAR_CR_DIV124_Pos   (8U)
#define	ETH_MACMDIOAR_CR_DIV124_Msk   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos)
	0x00000500
#define	ETH_MACMDIOAR_CR_DIV124   ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
#define	ETH_MACMDIOAR_CR_DIV4AR_Pos   (11U)
#define	ETH_MACMDIOAR_CR_DIV4AR_Msk   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos)
	0x00000800
#define	ETH_MACMDIOAR_CR_DIV4AR   ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
#define	ETH_MACMDIOAR_CR_DIV6AR_Pos   (8U)
#define	ETH_MACMDIOAR_CR_DIV6AR_Msk   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos)
	0x00000900
#define	ETH_MACMDIOAR_CR_DIV6AR   ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
#define	ETH_MACMDIOAR_CR_DIV8AR_Pos   (9U)
#define	ETH_MACMDIOAR_CR_DIV8AR_Msk   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos)
	0x00000A00
#define	ETH_MACMDIOAR_CR_DIV8AR   ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
#define	ETH_MACMDIOAR_CR_DIV10AR_Pos   (8U)
#define	ETH_MACMDIOAR_CR_DIV10AR_Msk   (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos)
	0x00000B00
#define	ETH_MACMDIOAR_CR_DIV10AR   ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
#define	ETH_MACMDIOAR_CR_DIV12AR_Pos   (10U)
#define	ETH_MACMDIOAR_CR_DIV12AR_Msk   (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos)
	0x00000C00
#define	ETH_MACMDIOAR_CR_DIV12AR   ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
#define	ETH_MACMDIOAR_CR_DIV14AR_Pos   (8U)
#define	ETH_MACMDIOAR_CR_DIV14AR_Msk   (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos)
	0x00000D00
#define	ETH_MACMDIOAR_CR_DIV14AR   ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
#define	ETH_MACMDIOAR_CR_DIV16AR_Pos   (9U)
#define	ETH_MACMDIOAR_CR_DIV16AR_Msk   (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos)
	0x00000E00
#define	ETH_MACMDIOAR_CR_DIV16AR   ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
#define	ETH_MACMDIOAR_CR_DIV18AR_Pos   (8U)
#define	ETH_MACMDIOAR_CR_DIV18AR_Msk   (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos)
	0x00000F00
#define	ETH_MACMDIOAR_CR_DIV18AR   ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
#define	ETH_MACMDIOAR_SKAP_Pos   (4U)
#define	ETH_MACMDIOAR_SKAP_Msk   (0x1UL << ETH_MACMDIOAR_SKAP_Pos)
	0x00000010
#define	ETH_MACMDIOAR_SKAP   ETH_MACMDIOAR_SKAP_Msk /* Skip Address Packet */
#define	ETH_MACMDIOAR_MOC_Pos   (2U)
#define	ETH_MACMDIOAR_MOC_Msk   (0x3UL << ETH_MACMDIOAR_MOC_Pos)
	0x0000000C
#define	ETH_MACMDIOAR_MOC   ETH_MACMDIOAR_MOC_Msk /* MII Operation Command */
#define	ETH_MACMDIOAR_MOC_WR_Pos   (2U)
#define	ETH_MACMDIOAR_MOC_WR_Msk   (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos)
	0x00000004
#define	ETH_MACMDIOAR_MOC_WR   ETH_MACMDIOAR_MOC_WR_Msk /* Write */
#define	ETH_MACMDIOAR_MOC_PRDIA_Pos   (3U)
#define	ETH_MACMDIOAR_MOC_PRDIA_Msk   (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos)
	0x00000008
#define	ETH_MACMDIOAR_MOC_PRDIA   ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */
#define	ETH_MACMDIOAR_MOC_RD_Pos   (2U)
#define	ETH_MACMDIOAR_MOC_RD_Msk   (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos)
	0x0000000C
#define	ETH_MACMDIOAR_MOC_RD   ETH_MACMDIOAR_MOC_RD_Msk /* Read */
#define	ETH_MACMDIOAR_C45E_Pos   (1U)
#define	ETH_MACMDIOAR_C45E_Msk   (0x1UL << ETH_MACMDIOAR_C45E_Pos)
	0x00000002
#define	ETH_MACMDIOAR_C45E   ETH_MACMDIOAR_C45E_Msk /* Clause 45 PHY Enable */
#define	ETH_MACMDIOAR_MB_Pos   (0U)
#define	ETH_MACMDIOAR_MB_Msk   (0x1UL << ETH_MACMDIOAR_MB_Pos)
	0x00000001
#define	ETH_MACMDIOAR_MB   ETH_MACMDIOAR_MB_Msk /* MII Busy */
#define	ETH_MACMDIODR_RA_Pos   (16U)
#define	ETH_MACMDIODR_RA_Msk   (0xFFFFUL << ETH_MACMDIODR_RA_Pos)
	0xFFFF0000
#define	ETH_MACMDIODR_RA   ETH_MACMDIODR_RA_Msk /* Register Address */
#define	ETH_MACMDIODR_MD_Pos   (0U)
#define	ETH_MACMDIODR_MD_Msk   (0xFFFFUL << ETH_MACMDIODR_MD_Pos)
	0x0000FFFF
#define	ETH_MACMDIODR_MD   ETH_MACMDIODR_MD_Msk /* MII Data */
#define	ETH_MACARPAR_ARPPA_Pos   (0U)
#define	ETH_MACARPAR_ARPPA_Msk   (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos)
	0xFFFFFFFF
#define	ETH_MACARPAR_ARPPA   ETH_MACARPAR_ARPPA_Msk /* ARP Protocol Address */
#define	ETH_MACA0HR_AE_Pos   (31U)
#define	ETH_MACA0HR_AE_Msk   (0x1UL << ETH_MACA0HR_AE_Pos)
	0x80000000
#define	ETH_MACA0HR_AE   ETH_MACA0HR_AE_Msk /* Address Enable*/
#define	ETH_MACA0HR_ADDRHI_Pos   (0U)
#define	ETH_MACA0HR_ADDRHI_Msk   (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos)
	0x0000FFFF
#define	ETH_MACA0HR_ADDRHI   ETH_MACA0HR_ADDRHI_Msk /* MAC Address 0*/
#define	ETH_MACA0LR_ADDRLO_Pos   (0U)
#define	ETH_MACA0LR_ADDRLO_Msk   (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos)
	0xFFFFFFFF
#define	ETH_MACA0LR_ADDRLO   ETH_MACA0LR_ADDRLO_Msk /* MAC Address 0*/
#define	ETH_MACA1HR_AE_Pos   (31U)
#define	ETH_MACA1HR_AE_Msk   (0x1UL << ETH_MACA1HR_AE_Pos)
	0x80000000
#define	ETH_MACA1HR_AE   ETH_MACA1HR_AE_Msk /* Address Enable*/
#define	ETH_MACA1HR_SA_Pos   (30U)
#define	ETH_MACA1HR_SA_Msk   (0x1UL << ETH_MACA1HR_SA_Pos)
	0x40000000
#define	ETH_MACA1HR_SA   ETH_MACA1HR_SA_Msk /* Source Address */
#define	ETH_MACA1HR_MBC_Pos   (24U)
#define	ETH_MACA1HR_MBC_Msk   (0x3FUL << ETH_MACA1HR_MBC_Pos)
	0x3F000000
#define	ETH_MACA1HR_MBC   ETH_MACA1HR_MBC_Msk /* Mask Byte Control */
#define	ETH_MACA1HR_ADDRHI_Pos   (0U)
#define	ETH_MACA1HR_ADDRHI_Msk   (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos)
	0x0000FFFF
#define	ETH_MACA1HR_ADDRHI   ETH_MACA1HR_ADDRHI_Msk /* MAC Address 1*/
#define	ETH_MACA1LR_ADDRLO_Pos   (0U)
#define	ETH_MACA1LR_ADDRLO_Msk   (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos)
	0xFFFFFFFF
#define	ETH_MACA1LR_ADDRLO   ETH_MACA1LR_ADDRLO_Msk /* MAC Address 1*/
#define	ETH_MACA2HR_AE_Pos   (31U)
#define	ETH_MACA2HR_AE_Msk   (0x1UL << ETH_MACA2HR_AE_Pos)
	0x80000000
#define	ETH_MACA2HR_AE   ETH_MACA2HR_AE_Msk /* Address Enable*/
#define	ETH_MACA2HR_SA_Pos   (30U)
#define	ETH_MACA2HR_SA_Msk   (0x1UL << ETH_MACA2HR_SA_Pos)
	0x40000000
#define	ETH_MACA2HR_SA   ETH_MACA2HR_SA_Msk /* Source Address */
#define	ETH_MACA2HR_MBC_Pos   (24U)
#define	ETH_MACA2HR_MBC_Msk   (0x3FUL << ETH_MACA2HR_MBC_Pos)
	0x3F000000
#define	ETH_MACA2HR_MBC   ETH_MACA2HR_MBC_Msk /* Mask Byte Control */
#define	ETH_MACA2HR_ADDRHI_Pos   (0U)
#define	ETH_MACA2HR_ADDRHI_Msk   (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos)
	0x0000FFFF
#define	ETH_MACA2HR_ADDRHI   ETH_MACA2HR_ADDRHI_Msk /* MAC Address 1*/
#define	ETH_MACA2LR_ADDRLO_Pos   (0U)
#define	ETH_MACA2LR_ADDRLO_Msk   (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos)
	0xFFFFFFFF
#define	ETH_MACA2LR_ADDRLO   ETH_MACA2LR_ADDRLO_Msk /* MAC Address 2*/
#define	ETH_MACA3HR_AE_Pos   (31U)
#define	ETH_MACA3HR_AE_Msk   (0x1UL << ETH_MACA3HR_AE_Pos)
	0x80000000
#define	ETH_MACA3HR_AE   ETH_MACA3HR_AE_Msk /* Address Enable*/
#define	ETH_MACA3HR_SA_Pos   (30U)
#define	ETH_MACA3HR_SA_Msk   (0x1UL << ETH_MACA3HR_SA_Pos)
	0x40000000
#define	ETH_MACA3HR_SA   ETH_MACA3HR_SA_Msk /* Source Address */
#define	ETH_MACA3HR_MBC_Pos   (24U)
#define	ETH_MACA3HR_MBC_Msk   (0x3FUL << ETH_MACA3HR_MBC_Pos)
	0x3F000000
#define	ETH_MACA3HR_MBC   ETH_MACA3HR_MBC_Msk /* Mask Byte Control */
#define	ETH_MACA3HR_ADDRHI_Pos   (0U)
#define	ETH_MACA3HR_ADDRHI_Msk   (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos)
	0x0000FFFF
#define	ETH_MACA3HR_ADDRHI   ETH_MACA3HR_ADDRHI_Msk /* MAC Address 1*/
#define	ETH_MACA3LR_ADDRLO_Pos   (0U)
#define	ETH_MACA3LR_ADDRLO_Msk   (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos)
	0xFFFFFFFF
#define	ETH_MACA3LR_ADDRLO   ETH_MACA3LR_ADDRLO_Msk /* MAC Address 3*/
#define	ETH_MACAHR_AE_Pos   (31U)
#define	ETH_MACAHR_AE_Msk   (0x1UL << ETH_MACAHR_AE_Pos)
	0x80000000
#define	ETH_MACAHR_AE   ETH_MACAHR_AE_Msk /* Address enable */
#define	ETH_MACAHR_SA_Pos   (30U)
#define	ETH_MACAHR_SA_Msk   (0x1UL << ETH_MACAHR_SA_Pos)
	0x40000000
#define	ETH_MACAHR_SA   ETH_MACAHR_SA_Msk /* Source address */
#define	ETH_MACAHR_MBC_Pos   (24U)
#define	ETH_MACAHR_MBC_Msk   (0x3FUL << ETH_MACAHR_MBC_Pos)
	0x3F000000
#define	ETH_MACAHR_MBC   ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
#define	ETH_MACAHR_MBC_HBITS15_8   (0x20000000U) /* Mask MAC Address high reg bits [15:8] */
#define	ETH_MACAHR_MBC_HBITS7_0   (0x10000000U) /* Mask MAC Address high reg bits [7:0] */
#define	ETH_MACAHR_MBC_LBITS31_24   (0x08000000U) /* Mask MAC Address low reg bits [31:24] */
#define	ETH_MACAHR_MBC_LBITS23_16   (0x04000000U) /* Mask MAC Address low reg bits [23:16] */
#define	ETH_MACAHR_MBC_LBITS15_8   (0x02000000U) /* Mask MAC Address low reg bits [15:8] */
#define	ETH_MACAHR_MBC_LBITS7_0   (0x01000000U) /* Mask MAC Address low reg bits [7:0] */
#define	ETH_MACAHR_MACAH_Pos   (0U)
#define	ETH_MACAHR_MACAH_Msk   (0xFFFFUL << ETH_MACAHR_MACAH_Pos)
	0x0000FFFF
#define	ETH_MACAHR_MACAH   ETH_MACAHR_MACAH_Msk /* MAC address high */
#define	ETH_MACALR_MACAL_Pos   (0U)
#define	ETH_MACALR_MACAL_Msk   (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos)
	0xFFFFFFFF
#define	ETH_MACALR_MACAL   ETH_MACALR_MACAL_Msk /* MAC address low */
#define	ETH_MMCCR_UCDBC_Pos   (8U)
#define	ETH_MMCCR_UCDBC_Msk   (0x1UL << ETH_MMCCR_UCDBC_Pos)
	0x00000100
#define	ETH_MMCCR_UCDBC   ETH_MMCCR_UCDBC_Msk /* Update MMC Counters for Dropped Broadcast Packets */
#define	ETH_MMCCR_CNTPRSTLVL_Pos   (5U)
#define	ETH_MMCCR_CNTPRSTLVL_Msk   (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos)
	0x00000020
#define	ETH_MMCCR_CNTPRSTLVL   ETH_MMCCR_CNTPRSTLVL_Msk /* Full-Half Preset */
#define	ETH_MMCCR_CNTPRST_Pos   (4U)
#define	ETH_MMCCR_CNTPRST_Msk   (0x1UL << ETH_MMCCR_CNTPRST_Pos)
	0x00000010
#define	ETH_MMCCR_CNTPRST   ETH_MMCCR_CNTPRST_Msk /* Counters Reset */
#define	ETH_MMCCR_CNTFREEZ_Pos   (3U)
#define	ETH_MMCCR_CNTFREEZ_Msk   (0x1UL << ETH_MMCCR_CNTFREEZ_Pos)
	0x00000008
#define	ETH_MMCCR_CNTFREEZ   ETH_MMCCR_CNTFREEZ_Msk /* MMC Counter Freeze */
#define	ETH_MMCCR_RSTONRD_Pos   (2U)
#define	ETH_MMCCR_RSTONRD_Msk   (0x1UL << ETH_MMCCR_RSTONRD_Pos)
	0x00000004
#define	ETH_MMCCR_RSTONRD   ETH_MMCCR_RSTONRD_Msk /* Reset On Read */
#define	ETH_MMCCR_CNTSTOPRO_Pos   (1U)
#define	ETH_MMCCR_CNTSTOPRO_Msk   (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos)
	0x00000002
#define	ETH_MMCCR_CNTSTOPRO   ETH_MMCCR_CNTSTOPRO_Msk /* Counter Stop Rollover */
#define	ETH_MMCCR_CNTRST_Pos   (0U)
#define	ETH_MMCCR_CNTRST_Msk   (0x1UL << ETH_MMCCR_CNTRST_Pos)
	0x00000001
#define	ETH_MMCCR_CNTRST   ETH_MMCCR_CNTRST_Msk /* Counters Reset */
#define	ETH_MMCRIR_RXLPITRCIS_Pos   (27U)
#define	ETH_MMCRIR_RXLPITRCIS_Msk   (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos)
	0x08000000
#define	ETH_MMCRIR_RXLPITRCIS   ETH_MMCRIR_RXLPITRCIS_Msk /* MMC Receive LPI transition counter interrupt status */
#define	ETH_MMCRIR_RXLPIUSCIS_Pos   (26U)
#define	ETH_MMCRIR_RXLPIUSCIS_Msk   (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos)
	0x04000000
#define	ETH_MMCRIR_RXLPIUSCIS   ETH_MMCRIR_RXLPIUSCIS_Msk /* MMC Receive LPI microsecond counter interrupt status */
#define	ETH_MMCRIR_RXUCGPIS_Pos   (17U)
#define	ETH_MMCRIR_RXUCGPIS_Msk   (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos)
	0x00020000
#define	ETH_MMCRIR_RXUCGPIS   ETH_MMCRIR_RXUCGPIS_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Status */
#define	ETH_MMCRIR_RXALGNERPIS_Pos   (6U)
#define	ETH_MMCRIR_RXALGNERPIS_Msk   (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos)
	0x00000040
#define	ETH_MMCRIR_RXALGNERPIS   ETH_MMCRIR_RXALGNERPIS_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Status */
#define	ETH_MMCRIR_RXCRCERPIS_Pos   (5U)
#define	ETH_MMCRIR_RXCRCERPIS_Msk   (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos)
	0x00000020
#define	ETH_MMCRIR_RXCRCERPIS   ETH_MMCRIR_RXCRCERPIS_Msk /* MMC Receive CRC Error Packet Counter Interrupt Status */
#define	ETH_MMCTIR_TXLPITRCIS_Pos   (27U)
#define	ETH_MMCTIR_TXLPITRCIS_Msk   (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos)
	0x08000000
#define	ETH_MMCTIR_TXLPITRCIS   ETH_MMCTIR_TXLPITRCIS_Msk /* MMC Transmit LPI transition counter interrupt status */
#define	ETH_MMCTIR_TXLPIUSCIS_Pos   (26U)
#define	ETH_MMCTIR_TXLPIUSCIS_Msk   (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos)
	0x04000000
#define	ETH_MMCTIR_TXLPIUSCIS   ETH_MMCTIR_TXLPIUSCIS_Msk /* MMC Transmit LPI microsecond counter interrupt status */
#define	ETH_MMCTIR_TXGPKTIS_Pos   (21U)
#define	ETH_MMCTIR_TXGPKTIS_Msk   (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos)
	0x00200000
#define	ETH_MMCTIR_TXGPKTIS   ETH_MMCTIR_TXGPKTIS_Msk /* MMC Transmit Good Packet Counter Interrupt Status */
#define	ETH_MMCTIR_TXMCOLGPIS_Pos   (15U)
#define	ETH_MMCTIR_TXMCOLGPIS_Msk   (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos)
	0x00008000
#define	ETH_MMCTIR_TXMCOLGPIS   ETH_MMCTIR_TXMCOLGPIS_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
#define	ETH_MMCTIR_TXSCOLGPIS_Pos   (14U)
#define	ETH_MMCTIR_TXSCOLGPIS_Msk   (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos)
	0x00004000
#define	ETH_MMCTIR_TXSCOLGPIS   ETH_MMCTIR_TXSCOLGPIS_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */
#define	ETH_MMCRIMR_RXLPITRCIM_Pos   (27U)
#define	ETH_MMCRIMR_RXLPITRCIM_Msk   (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos)
	0x08000000
#define	ETH_MMCRIMR_RXLPITRCIM   ETH_MMCRIMR_RXLPITRCIM_Msk /* MMC Receive LPI transition counter interrupt Mask */
#define	ETH_MMCRIMR_RXLPIUSCIM_Pos   (26U)
#define	ETH_MMCRIMR_RXLPIUSCIM_Msk   (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos)
	0x04000000
#define	ETH_MMCRIMR_RXLPIUSCIM   ETH_MMCRIMR_RXLPIUSCIM_Msk /* MMC Receive LPI microsecond counter interrupt Mask */
#define	ETH_MMCRIMR_RXUCGPIM_Pos   (17U)
#define	ETH_MMCRIMR_RXUCGPIM_Msk   (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos)
	0x00020000
#define	ETH_MMCRIMR_RXUCGPIM   ETH_MMCRIMR_RXUCGPIM_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
#define	ETH_MMCRIMR_RXALGNERPIM_Pos   (6U)
#define	ETH_MMCRIMR_RXALGNERPIM_Msk   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos)
	0x00000040
#define	ETH_MMCRIMR_RXALGNERPIM   ETH_MMCRIMR_RXALGNERPIM_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
#define	ETH_MMCRIMR_RXCRCERPIM_Pos   (5U)
#define	ETH_MMCRIMR_RXCRCERPIM_Msk   (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos)
	0x00000020
#define	ETH_MMCRIMR_RXCRCERPIM   ETH_MMCRIMR_RXCRCERPIM_Msk /* MMC Receive CRC Error Packet Counter Interrupt Mask */
#define	ETH_MMCTIMR_TXLPITRCIM_Pos   (27U)
#define	ETH_MMCTIMR_TXLPITRCIM_Msk   (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos)
	0x08000000
#define	ETH_MMCTIMR_TXLPITRCIM   ETH_MMCTIMR_TXLPITRCIM_Msk /* MMC Transmit LPI transition counter interrupt Mask*/
#define	ETH_MMCTIMR_TXLPIUSCIM_Pos   (26U)
#define	ETH_MMCTIMR_TXLPIUSCIM_Msk   (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos)
	0x04000000
#define	ETH_MMCTIMR_TXLPIUSCIM   ETH_MMCTIMR_TXLPIUSCIM_Msk /* MMC Transmit LPI microsecond counter interrupt Mask*/
#define	ETH_MMCTIMR_TXGPKTIM_Pos   (21U)
#define	ETH_MMCTIMR_TXGPKTIM_Msk   (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos)
	0x00200000
#define	ETH_MMCTIMR_TXGPKTIM   ETH_MMCTIMR_TXGPKTIM_Msk /* MMC Transmit Good Packet Counter Interrupt Mask*/
#define	ETH_MMCTIMR_TXMCOLGPIM_Pos   (15U)
#define	ETH_MMCTIMR_TXMCOLGPIM_Msk   (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos)
	0x00008000
#define	ETH_MMCTIMR_TXMCOLGPIM   ETH_MMCTIMR_TXMCOLGPIM_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
#define	ETH_MMCTIMR_TXSCOLGPIM_Pos   (14U)
#define	ETH_MMCTIMR_TXSCOLGPIM_Msk   (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos)
	0x00004000
#define	ETH_MMCTIMR_TXSCOLGPIM   ETH_MMCTIMR_TXSCOLGPIM_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
#define	ETH_MMCTSCGPR_TXSNGLCOLG_Pos   (0U)
#define	ETH_MMCTSCGPR_TXSNGLCOLG_msk   (0xFFFFFFFFUL << ETH_MMCTSCGPR_TXSNGLCOLG_Pos)
	0xFFFFFFFF
#define	ETH_MMCTSCGPR_TXSNGLCOLG   ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */
#define	ETH_MMCTMCGPR_TXMULTCOLG_Pos   (0U)
#define	ETH_MMCTMCGPR_TXMULTCOLG_msk   (0xFFFFFFFFUL << ETH_MMCTMCGPR_TXMULTCOLG_Pos)
	0xFFFFFFFF
#define	ETH_MMCTMCGPR_TXMULTCOLG   ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */
#define	ETH_MMCTPCGR_TXPKTG_Pos   (0U)
#define	ETH_MMCTPCGR_TXPKTG_msk   (0xFFFFFFFFUL << ETH_MMCTPCGR_TXPKTG_Pos)
	0xFFFFFFFF
#define	ETH_MMCTPCGR_TXPKTG   ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */
#define	ETH_MMCRCRCEPR_RXCRCERR_Pos   (0U)
#define	ETH_MMCRCRCEPR_RXCRCERR_msk   (0xFFFFFFFFUL << ETH_MMCRCRCEPR_RXCRCERR_Pos)
	0xFFFFFFFF
#define	ETH_MMCRCRCEPR_RXCRCERR   ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */
#define	ETH_MMCRAEPR_RXALGNERR_Pos   (0U)
#define	ETH_MMCRAEPR_RXALGNERR_msk   (0xFFFFFFFFUL << ETH_MMCRAEPR_RXALGNERR_Pos)
	0xFFFFFFFF
#define	ETH_MMCRAEPR_RXALGNERR   ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */
#define	ETH_MMCRUPGR_RXUCASTG_Pos   (0U)
#define	ETH_MMCRUPGR_RXUCASTG_msk   (0xFFFFFFFFUL << ETH_MMCRUPGR_RXUCASTG_Pos)
	0xFFFFFFFF
#define	ETH_MMCRUPGR_RXUCASTG   ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */
#define	ETH_MMCTLPIMSTR_TXLPIUSC_Pos   (0U)
#define	ETH_MMCTLPIMSTR_TXLPIUSC_msk   (0xFFFFFFFFUL << ETH_MMCTLPIMSTR_TXLPIUSC_Pos)
	0xFFFFFFFF
#define	ETH_MMCTLPIMSTR_TXLPIUSC   ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */
#define	ETH_MMCTLPITCR_TXLPITRC_Pos   (0U)
#define	ETH_MMCTLPITCR_TXLPITRC_msk   (0xFFFFFFFFUL << ETH_MMCTLPITCR_TXLPITRC_Pos)
	0xFFFFFFFF
#define	ETH_MMCTLPITCR_TXLPITRC   ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */
#define	ETH_MMCRLPIMSTR_RXLPIUSC_Pos   (0U)
#define	ETH_MMCRLPIMSTR_RXLPIUSC_msk   (0xFFFFFFFFUL << ETH_MMCRLPIMSTR_RXLPIUSC_Pos)
	0xFFFFFFFF
#define	ETH_MMCRLPIMSTR_RXLPIUSC   ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */
#define	ETH_MMCRLPITCR_RXLPITRC_Pos   (0U)
#define	ETH_MMCRLPITCR_RXLPITRC_msk   (0xFFFFFFFFUL << ETH_MMCRLPITCR_RXLPITRC_Pos)
	0xFFFFFFFF
#define	ETH_MMCRLPITCR_RXLPITRC   ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */
#define	ETH_MACL3L4CR_L4DPIM_Pos   (21U)
#define	ETH_MACL3L4CR_L4DPIM_Msk   (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos)
	0x00200000
#define	ETH_MACL3L4CR_L4DPIM   ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */
#define	ETH_MACL3L4CR_L4DPM_Pos   (20U)
#define	ETH_MACL3L4CR_L4DPM_Msk   (0x1UL << ETH_MACL3L4CR_L4DPM_Pos)
	0x00100000
#define	ETH_MACL3L4CR_L4DPM   ETH_MACL3L4CR_L4DPM_Msk /* Layer 4 Destination Port Match Enable */
#define	ETH_MACL3L4CR_L4SPIM_Pos   (19U)
#define	ETH_MACL3L4CR_L4SPIM_Msk   (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos)
	0x00080000
#define	ETH_MACL3L4CR_L4SPIM   ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */
#define	ETH_MACL3L4CR_L4SPM_Pos   (18U)
#define	ETH_MACL3L4CR_L4SPM_Msk   (0x1UL << ETH_MACL3L4CR_L4SPM_Pos)
	0x00040000
#define	ETH_MACL3L4CR_L4SPM   ETH_MACL3L4CR_L4SPM_Msk /* Layer 4 Source Port Match Enable */
#define	ETH_MACL3L4CR_L4PEN_Pos   (16U)
#define	ETH_MACL3L4CR_L4PEN_Msk   (0x1UL << ETH_MACL3L4CR_L4PEN_Pos)
	0x00010000
#define	ETH_MACL3L4CR_L4PEN   ETH_MACL3L4CR_L4PEN_Msk /* Layer 4 Protocol Enable */
#define	ETH_MACL3L4CR_L3HDBM_Pos   (11U)
#define	ETH_MACL3L4CR_L3HDBM_Msk   (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos)
	0x0000F800
#define	ETH_MACL3L4CR_L3HDBM   ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */
#define	ETH_MACL3L4CR_L3HSBM_Pos   (6U)
#define	ETH_MACL3L4CR_L3HSBM_Msk   (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos)
	0x000007C0
#define	ETH_MACL3L4CR_L3HSBM   ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */
#define	ETH_MACL3L4CR_L3DAIM_Pos   (5U)
#define	ETH_MACL3L4CR_L3DAIM_Msk   (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos)
	0x00000020
#define	ETH_MACL3L4CR_L3DAIM   ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */
#define	ETH_MACL3L4CR_L3DAM_Pos   (4U)
#define	ETH_MACL3L4CR_L3DAM_Msk   (0x1UL << ETH_MACL3L4CR_L3DAM_Pos)
	0x00000010
#define	ETH_MACL3L4CR_L3DAM   ETH_MACL3L4CR_L3DAM_Msk /* Layer 3 IP DA Match Enable */
#define	ETH_MACL3L4CR_L3SAIM_Pos   (3U)
#define	ETH_MACL3L4CR_L3SAIM_Msk   (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos)
	0x00000008
#define	ETH_MACL3L4CR_L3SAIM   ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */
#define	ETH_MACL3L4CR_L3SAM_Pos   (2U)
#define	ETH_MACL3L4CR_L3SAM_Msk   (0x1UL << ETH_MACL3L4CR_L3SAM_Pos)
	0x00000004
#define	ETH_MACL3L4CR_L3SAM   ETH_MACL3L4CR_L3SAM_Msk /* Layer 3 IP SA Match Enable*/
#define	ETH_MACL3L4CR_L3PEN_Pos   (0U)
#define	ETH_MACL3L4CR_L3PEN_Msk   (0x1UL << ETH_MACL3L4CR_L3PEN_Pos)
	0x00000001
#define	ETH_MACL3L4CR_L3PEN   ETH_MACL3L4CR_L3PEN_Msk /* Layer 3 Protocol Enable */
#define	ETH_MACL4AR_L4DP_Pos   (16U)
#define	ETH_MACL4AR_L4DP_Msk   (0xFFFFUL << ETH_MACL4AR_L4DP_Pos)
	0xFFFF0000
#define	ETH_MACL4AR_L4DP   ETH_MACL4AR_L4DP_Msk /* Layer 4 Destination Port Number Field */
#define	ETH_MACL4AR_L4SP_Pos   (0U)
#define	ETH_MACL4AR_L4SP_Msk   (0xFFFFUL << ETH_MACL4AR_L4SP_Pos)
	0x0000FFFF
#define	ETH_MACL4AR_L4SP   ETH_MACL4AR_L4SP_Msk /* Layer 4 Source Port Number Field */
#define	ETH_MACL3A0R_L3A0_Pos   (0U)
#define	ETH_MACL3A0R_L3A0_Msk   (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos)
	0xFFFFFFFF
#define	ETH_MACL3A0R_L3A0   ETH_MACL3A0R_L3A0_Msk /* Layer 3 Address 0 Field */
#define	ETH_MACL3A1R_L3A1_Pos   (0U)
#define	ETH_MACL3A1R_L3A1_Msk   (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos)
	0xFFFFFFFF
#define	ETH_MACL3A1R_L3A1   ETH_MACL3A1R_L3A1_Msk /* Layer 3 Address 1 Field */
#define	ETH_MACL3A2R_L3A2_Pos   (0U)
#define	ETH_MACL3A2R_L3A2_Msk   (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos)
	0xFFFFFFFF
#define	ETH_MACL3A2R_L3A2   ETH_MACL3A2R_L3A2_Msk /* Layer 3 Address 2 Field */
#define	ETH_MACL3A3R_L3A3_Pos   (0U)
#define	ETH_MACL3A3R_L3A3_Msk   (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos)
	0xFFFFFFFF
#define	ETH_MACL3A3R_L3A3   ETH_MACL3A3R_L3A3_Msk /* Layer 3 Address 3 Field */
#define	ETH_MACTSCR_TXTSSTSM_Pos   (24U)
#define	ETH_MACTSCR_TXTSSTSM_Msk   (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos)
	0x01000000
#define	ETH_MACTSCR_TXTSSTSM   ETH_MACTSCR_TXTSSTSM_Msk /* Transmit Timestamp Status Mode */
#define	ETH_MACTSCR_CSC_Pos   (19U)
#define	ETH_MACTSCR_CSC_Msk   (0x1UL << ETH_MACTSCR_CSC_Pos)
	0x00080000
#define	ETH_MACTSCR_CSC   ETH_MACTSCR_CSC_Msk /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */
#define	ETH_MACTSCR_TSENMACADDR_Pos   (18U)
#define	ETH_MACTSCR_TSENMACADDR_Msk   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos)
	0x00040000
#define	ETH_MACTSCR_TSENMACADDR   ETH_MACTSCR_TSENMACADDR_Msk /* Enable MAC Address for PTP Packet Filtering */
#define	ETH_MACTSCR_SNAPTYPSEL_Pos   (16U)
#define	ETH_MACTSCR_SNAPTYPSEL_Msk   (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos)
	0x00030000
#define	ETH_MACTSCR_SNAPTYPSEL   ETH_MACTSCR_SNAPTYPSEL_Msk /* Select PTP packets for Taking Snapshots */
#define	ETH_MACTSCR_TSMSTRENA_Pos   (15U)
#define	ETH_MACTSCR_TSMSTRENA_Msk   (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos)
	0x00008000
#define	ETH_MACTSCR_TSMSTRENA   ETH_MACTSCR_TSMSTRENA_Msk /* Enable Snapshot for Messages Relevant to Master */
#define	ETH_MACTSCR_TSEVNTENA_Pos   (14U)
#define	ETH_MACTSCR_TSEVNTENA_Msk   (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos)
	0x00004000
#define	ETH_MACTSCR_TSEVNTENA   ETH_MACTSCR_TSEVNTENA_Msk /* Enable Timestamp Snapshot for Event Messages */
#define	ETH_MACTSCR_TSIPV4ENA_Pos   (13U)
#define	ETH_MACTSCR_TSIPV4ENA_Msk   (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos)
	0x00002000
#define	ETH_MACTSCR_TSIPV4ENA   ETH_MACTSCR_TSIPV4ENA_Msk /* Enable Processing of PTP Packets Sent over IPv4-UDP */
#define	ETH_MACTSCR_TSIPV6ENA_Pos   (12U)
#define	ETH_MACTSCR_TSIPV6ENA_Msk   (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos)
	0x00001000
#define	ETH_MACTSCR_TSIPV6ENA   ETH_MACTSCR_TSIPV6ENA_Msk /* Enable Processing of PTP Packets Sent over IPv6-UDP */
#define	ETH_MACTSCR_TSIPENA_Pos   (11U)
#define	ETH_MACTSCR_TSIPENA_Msk   (0x1UL << ETH_MACTSCR_TSIPENA_Pos)
	0x00000800
#define	ETH_MACTSCR_TSIPENA   ETH_MACTSCR_TSIPENA_Msk /* Enable Processing of PTP over Ethernet Packets */
#define	ETH_MACTSCR_TSVER2ENA_Pos   (10U)
#define	ETH_MACTSCR_TSVER2ENA_Msk   (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos)
	0x00000400
#define	ETH_MACTSCR_TSVER2ENA   ETH_MACTSCR_TSVER2ENA_Msk /* Enable PTP Packet Processing for Version 2 Format */
#define	ETH_MACTSCR_TSCTRLSSR_Pos   (9U)
#define	ETH_MACTSCR_TSCTRLSSR_Msk   (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos)
	0x00000200
#define	ETH_MACTSCR_TSCTRLSSR   ETH_MACTSCR_TSCTRLSSR_Msk /* Timestamp Digital or Binary Rollover Control */
#define	ETH_MACTSCR_TSENALL_Pos   (8U)
#define	ETH_MACTSCR_TSENALL_Msk   (0x1UL << ETH_MACTSCR_TSENALL_Pos)
	0x00000100
#define	ETH_MACTSCR_TSENALL   ETH_MACTSCR_TSENALL_Msk /* Enable Timestamp for All Packets */
#define	ETH_MACTSCR_TSADDREG_Pos   (5U)
#define	ETH_MACTSCR_TSADDREG_Msk   (0x1UL << ETH_MACTSCR_TSADDREG_Pos)
	0x00000020
#define	ETH_MACTSCR_TSADDREG   ETH_MACTSCR_TSADDREG_Msk /* Update Addend Register */
#define	ETH_MACTSCR_TSUPDT_Pos   (3U)
#define	ETH_MACTSCR_TSUPDT_Msk   (0x1UL << ETH_MACTSCR_TSUPDT_Pos)
	0x00000008
#define	ETH_MACTSCR_TSUPDT   ETH_MACTSCR_TSUPDT_Msk /* Update Timestamp */
#define	ETH_MACTSCR_TSINIT_Pos   (2U)
#define	ETH_MACTSCR_TSINIT_Msk   (0x1UL << ETH_MACTSCR_TSINIT_Pos)
	0x00000004
#define	ETH_MACTSCR_TSINIT   ETH_MACTSCR_TSINIT_Msk /* Initialize Timestamp */
#define	ETH_MACTSCR_TSCFUPDT_Pos   (1U)
#define	ETH_MACTSCR_TSCFUPDT_Msk   (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos)
	0x00000002
#define	ETH_MACTSCR_TSCFUPDT   ETH_MACTSCR_TSCFUPDT_Msk /* Fine or Coarse Timestamp Update*/
#define	ETH_MACTSCR_TSENA_Pos   (0U)
#define	ETH_MACTSCR_TSENA_Msk   (0x1UL << ETH_MACTSCR_TSENA_Pos)
	0x00000001
#define	ETH_MACTSCR_TSENA   ETH_MACTSCR_TSENA_Msk /* Enable Timestamp */
#define	ETH_MACMACSSIR_SSINC_Pos   (16U)
#define	ETH_MACMACSSIR_SSINC_Msk   (0xFFUL << ETH_MACMACSSIR_SSINC_Pos)
	0x0000FF00
#define	ETH_MACMACSSIR_SSINC   ETH_MACMACSSIR_SSINC_Msk /* Sub-second Increment Value */
#define	ETH_MACMACSSIR_SNSINC_Pos   (8U)
#define	ETH_MACMACSSIR_SNSINC_Msk   (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos)
	0x000000FF
#define	ETH_MACMACSSIR_SNSINC   ETH_MACMACSSIR_SNSINC_Msk /* Sub-nanosecond Increment Value */
#define	ETH_MACSTSR_TSS_Pos   (0U)
#define	ETH_MACSTSR_TSS_Msk   (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos)
	0xFFFFFFFF
#define	ETH_MACSTSR_TSS   ETH_MACSTSR_TSS_Msk /* Timestamp Second */
#define	ETH_MACSTNR_TSSS_Pos   (0U)
#define	ETH_MACSTNR_TSSS_Msk   (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos)
	0x7FFFFFFF
#define	ETH_MACSTNR_TSSS   ETH_MACSTNR_TSSS_Msk /* Timestamp Sub-seconds */
#define	ETH_MACSTSUR_TSS_Pos   (0U)
#define	ETH_MACSTSUR_TSS_Msk   (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos)
	0xFFFFFFFF
#define	ETH_MACSTSUR_TSS   ETH_MACSTSUR_TSS_Msk /* Timestamp Seconds */
#define	ETH_MACSTNUR_ADDSUB_Pos   (31U)
#define	ETH_MACSTNUR_ADDSUB_Msk   (0x1UL << ETH_MACSTNUR_ADDSUB_Pos)
	0x80000000
#define	ETH_MACSTNUR_ADDSUB   ETH_MACSTNUR_ADDSUB_Msk /* Add or Subtract Time */
#define	ETH_MACSTNUR_TSSS_Pos   (0U)
#define	ETH_MACSTNUR_TSSS_Msk   (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos)
	0x7FFFFFFF
#define	ETH_MACSTNUR_TSSS   ETH_MACSTNUR_TSSS_Msk /* Timestamp Sub-seconds */
#define	ETH_MACTSAR_TSAR_Pos   (0U)
#define	ETH_MACTSAR_TSAR_Msk   (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos)
	0xFFFFFFFF
#define	ETH_MACTSAR_TSAR   ETH_MACTSAR_TSAR_Msk /* Timestamp Addend Register */
#define	ETH_MACTSSR_ATSNS_Pos   (25U)
#define	ETH_MACTSSR_ATSNS_Msk   (0x1FUL << ETH_MACTSSR_ATSNS_Pos)
	0x3E000000
#define	ETH_MACTSSR_ATSNS   ETH_MACTSSR_ATSNS_Msk /* Number of Auxiliary Timestamp Snapshots */
#define	ETH_MACTSSR_ATSSTM_Pos   (24U)
#define	ETH_MACTSSR_ATSSTM_Msk   (0x1UL << ETH_MACTSSR_ATSSTM_Pos)
	0x01000000
#define	ETH_MACTSSR_ATSSTM   ETH_MACTSSR_ATSSTM_Msk /* Auxiliary Timestamp Snapshot Trigger Missed */
#define	ETH_MACTSSR_ATSSTN_Pos   (16U)
#define	ETH_MACTSSR_ATSSTN_Msk   (0xFUL << ETH_MACTSSR_ATSSTN_Pos)
	0x000F0000
#define	ETH_MACTSSR_ATSSTN   ETH_MACTSSR_ATSSTN_Msk /* Auxiliary Timestamp Snapshot Trigger Identifier */
#define	ETH_MACTSSR_TXTSSIS_Pos   (15U)
#define	ETH_MACTSSR_TXTSSIS_Msk   (0x1UL << ETH_MACTSSR_TXTSSIS_Pos)
	0x00008000
#define	ETH_MACTSSR_TXTSSIS   ETH_MACTSSR_TXTSSIS_Msk /* Tx Timestamp Status Interrupt Status */
#define	ETH_MACTSSR_TSTRGTERR0_Pos   (3U)
#define	ETH_MACTSSR_TSTRGTERR0_Msk   (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos)
	0x00000008
#define	ETH_MACTSSR_TSTRGTERR0   ETH_MACTSSR_TSTRGTERR0_Msk /* Timestamp Target Time Error */
#define	ETH_MACTSSR_AUXTSTRIG_Pos   (2U)
#define	ETH_MACTSSR_AUXTSTRIG_Msk   (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos)
	0x00000004
#define	ETH_MACTSSR_AUXTSTRIG   ETH_MACTSSR_AUXTSTRIG_Msk /* Auxiliary Timestamp Trigger Snapshot*/
#define	ETH_MACTSSR_TSTARGT0_Pos   (1U)
#define	ETH_MACTSSR_TSTARGT0_Msk   (0x1UL << ETH_MACTSSR_TSTARGT0_Pos)
	0x00000002
#define	ETH_MACTSSR_TSTARGT0   ETH_MACTSSR_TSTARGT0_Msk /* Timestamp Target Time Reached */
#define	ETH_MACTSSR_TSSOVF_Pos   (0U)
#define	ETH_MACTSSR_TSSOVF_Msk   (0x1UL << ETH_MACTSSR_TSSOVF_Pos)
	0x00000001
#define	ETH_MACTSSR_TSSOVF   ETH_MACTSSR_TSSOVF_Msk /* Timestamp Seconds Overflow */
#define	ETH_MACTTSSNR_TXTSSMIS_Pos   (31U)
#define	ETH_MACTTSSNR_TXTSSMIS_Msk   (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos)
	0x80000000
#define	ETH_MACTTSSNR_TXTSSMIS   ETH_MACTTSSNR_TXTSSMIS_Msk /* Transmit Timestamp Status Missed */
#define	ETH_MACTTSSNR_TXTSSLO_Pos   (0U)
#define	ETH_MACTTSSNR_TXTSSLO_Msk   (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos)
	0x7FFFFFFF
#define	ETH_MACTTSSNR_TXTSSLO   ETH_MACTTSSNR_TXTSSLO_Msk /* Transmit Timestamp Status Low */
#define	ETH_MACTTSSSR_TXTSSHI_Pos   (0U)
#define	ETH_MACTTSSSR_TXTSSHI_Msk   (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos)
	0xFFFFFFFF
#define	ETH_MACTTSSSR_TXTSSHI   ETH_MACTTSSSR_TXTSSHI_Msk /* Transmit Timestamp Status High */
#define	ETH_MACACR_ATSEN3_Pos   (7U)
#define	ETH_MACACR_ATSEN3_Msk   (0x1UL << ETH_MACACR_ATSEN3_Pos)
	0x00000080
#define	ETH_MACACR_ATSEN3   ETH_MACACR_ATSEN3_Msk /* Auxiliary Snapshot 3 Enable */
#define	ETH_MACACR_ATSEN2_Pos   (6U)
#define	ETH_MACACR_ATSEN2_Msk   (0x1UL << ETH_MACACR_ATSEN2_Pos)
	0x00000040
#define	ETH_MACACR_ATSEN2   ETH_MACACR_ATSEN2_Msk /* Auxiliary Snapshot 2 Enable */
#define	ETH_MACACR_ATSEN1_Pos   (5U)
#define	ETH_MACACR_ATSEN1_Msk   (0x1UL << ETH_MACACR_ATSEN1_Pos)
	0x00000020
#define	ETH_MACACR_ATSEN1   ETH_MACACR_ATSEN1_Msk /* Auxiliary Snapshot 1 Enable */
#define	ETH_MACACR_ATSEN0_Pos   (4U)
#define	ETH_MACACR_ATSEN0_Msk   (0x1UL << ETH_MACACR_ATSEN0_Pos)
	0x00000010
#define	ETH_MACACR_ATSEN0   ETH_MACACR_ATSEN0_Msk /* Auxiliary Snapshot 0 Enable */
#define	ETH_MACACR_ATSFC_Pos   (0U)
#define	ETH_MACACR_ATSFC_Msk   (0x1UL << ETH_MACACR_ATSFC_Pos)
	0x00000001
#define	ETH_MACACR_ATSFC   ETH_MACACR_ATSFC_Msk /* Auxiliary Snapshot FIFO Clear */
#define	ETH_MACATSNR_AUXTSLO_Pos   (0U)
#define	ETH_MACATSNR_AUXTSLO_Msk   (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos)
	0x7FFFFFFF
#define	ETH_MACATSNR_AUXTSLO   ETH_MACATSNR_AUXTSLO_Msk /* Auxiliary Timestamp */
#define	ETH_MACATSSR_AUXTSHI_Pos   (0U)
#define	ETH_MACATSSR_AUXTSHI_Msk   (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos)
	0xFFFFFFFF
#define	ETH_MACATSSR_AUXTSHI   ETH_MACATSSR_AUXTSHI_Msk /* Auxiliary Timestamp */
#define	ETH_MACTSIACR_OSTIAC_Pos   (0U)
#define	ETH_MACTSIACR_OSTIAC_Msk   (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos)
	0xFFFFFFFF
#define	ETH_MACTSIACR_OSTIAC   ETH_MACTSIACR_OSTIAC_Msk /* One-Step Timestamp Ingress Asymmetry Correction */
#define	ETH_MACTSEACR_OSTEAC_Pos   (0U)
#define	ETH_MACTSEACR_OSTEAC_Msk   (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos)
	0xFFFFFFFF
#define	ETH_MACTSEACR_OSTEAC   ETH_MACTSEACR_OSTEAC_Msk /* One-Step Timestamp Egress Asymmetry Correction */
#define	ETH_MACTSICNR_TSIC_Pos   (0U)
#define	ETH_MACTSICNR_TSIC_Msk   (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos)
	0xFFFFFFFF
#define	ETH_MACTSICNR_TSIC   ETH_MACTSICNR_TSIC_Msk /* Timestamp Ingress Correction */
#define	ETH_MACTSECNR_TSEC_Pos   (0U)
#define	ETH_MACTSECNR_TSEC_Msk   (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos)
	0xFFFFFFFF
#define	ETH_MACTSECNR_TSEC   ETH_MACTSECNR_TSEC_Msk /* Timestamp Egress Correction */
#define	ETH_MACPPSCR_TRGTMODSEL0_Pos   (5U)
#define	ETH_MACPPSCR_TRGTMODSEL0_Msk   (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos)
	0x00000060
#define	ETH_MACPPSCR_TRGTMODSEL0   ETH_MACPPSCR_TRGTMODSEL0_Msk /* Target Time Register Mode for PPS Output */
#define	ETH_MACPPSCR_PPSEN0_Pos   (4U)
#define	ETH_MACPPSCR_PPSEN0_Msk   (0x1UL << ETH_MACPPSCR_PPSEN0_Pos)
	0x00000010
#define	ETH_MACPPSCR_PPSEN0   ETH_MACPPSCR_PPSEN0_Msk /* Flexible PPS Output Mode Enable */
#define	ETH_MACPPSCR_PPSCTRL_Pos   (0U)
#define	ETH_MACPPSCR_PPSCTRL_Msk   (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos)
	0x0000000F
#define	ETH_MACPPSCR_PPSCTRL   ETH_MACPPSCR_PPSCTRL_Msk /* PPS Output Frequency Control */
#define	ETH_MACPPSTTSR_TSTRH0_Pos   (0U)
#define	ETH_MACPPSTTSR_TSTRH0_Msk   (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos)
	0xFFFFFFFF
#define	ETH_MACPPSTTSR_TSTRH0   ETH_MACPPSTTSR_TSTRH0_Msk /* PPS Target Time Seconds Register */
#define	ETH_MACPPSTTNR_TRGTBUSY0_Pos   (31U)
#define	ETH_MACPPSTTNR_TRGTBUSY0_Msk   (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos)
	0x80000000
#define	ETH_MACPPSTTNR_TRGTBUSY0   ETH_MACPPSTTNR_TRGTBUSY0_Msk /* PPS Target Time Register Busy */
#define	ETH_MACPPSTTNR_TTSL0_Pos   (0U)
#define	ETH_MACPPSTTNR_TTSL0_Msk   (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos)
	0x7FFFFFFF
#define	ETH_MACPPSTTNR_TTSL0   ETH_MACPPSTTNR_TTSL0_Msk /* Target Time Low for PPS Register */
#define	ETH_MACPPSIR_PPSINT0_Pos   (0U)
#define	ETH_MACPPSIR_PPSINT0_Msk   (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos)
	0xFFFFFFFF
#define	ETH_MACPPSIR_PPSINT0   ETH_MACPPSIR_PPSINT0_Msk /* PPS Output Signal Interval */
#define	ETH_MACPPSWR_PPSWIDTH0_Pos   (0U)
#define	ETH_MACPPSWR_PPSWIDTH0_Msk   (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos)
	0xFFFFFFFF
#define	ETH_MACPPSWR_PPSWIDTH0   ETH_MACPPSWR_PPSWIDTH0_Msk /* PPS Output Signal Width */
#define	ETH_MACPOCR_DN_Pos   (8U)
#define	ETH_MACPOCR_DN_Msk   (0xFFUL << ETH_MACPOCR_DN_Pos)
	0x0000FF00
#define	ETH_MACPOCR_DN   ETH_MACPOCR_DN_Msk /* Domain Number */
#define	ETH_MACPOCR_DRRDIS_Pos   (6U)
#define	ETH_MACPOCR_DRRDIS_Msk   (0x1UL << ETH_MACPOCR_DRRDIS_Pos)
	0x00000040
#define	ETH_MACPOCR_DRRDIS   ETH_MACPOCR_DRRDIS_Msk /* Disable PTO Delay Request/Response response generation */
#define	ETH_MACPOCR_APDREQTRIG_Pos   (5U)
#define	ETH_MACPOCR_APDREQTRIG_Msk   (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos)
	0x00000020
#define	ETH_MACPOCR_APDREQTRIG   ETH_MACPOCR_APDREQTRIG_Msk /* Automatic PTP Pdelay_Req message Trigger */
#define	ETH_MACPOCR_ASYNCTRIG_Pos   (4U)
#define	ETH_MACPOCR_ASYNCTRIG_Msk   (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos)
	0x00000010
#define	ETH_MACPOCR_ASYNCTRIG   ETH_MACPOCR_ASYNCTRIG_Msk /* Automatic PTP SYNC message Trigger */
#define	ETH_MACPOCR_APDREQEN_Pos   (2U)
#define	ETH_MACPOCR_APDREQEN_Msk   (0x1UL << ETH_MACPOCR_APDREQEN_Pos)
	0x00000004
#define	ETH_MACPOCR_APDREQEN   ETH_MACPOCR_APDREQEN_Msk /* Automatic PTP Pdelay_Req message Enable */
#define	ETH_MACPOCR_ASYNCEN_Pos   (1U)
#define	ETH_MACPOCR_ASYNCEN_Msk   (0x1UL << ETH_MACPOCR_ASYNCEN_Pos)
	0x00000002
#define	ETH_MACPOCR_ASYNCEN   ETH_MACPOCR_ASYNCEN_Msk /* Automatic PTP SYNC message Enable */
#define	ETH_MACPOCR_PTOEN_Pos   (0U)
#define	ETH_MACPOCR_PTOEN_Msk   (0x1UL << ETH_MACPOCR_PTOEN_Pos)
	0x00000001
#define	ETH_MACPOCR_PTOEN   ETH_MACPOCR_PTOEN_Msk /* PTP Offload Enable */
#define	ETH_MACSPI0R_SPI0_Pos   (0U)
#define	ETH_MACSPI0R_SPI0_Msk   (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos)
	0xFFFFFFFF
#define	ETH_MACSPI0R_SPI0   ETH_MACSPI0R_SPI0_Msk /* Source Port Identity 0 */
#define	ETH_MACSPI1R_SPI1_Pos   (0U)
#define	ETH_MACSPI1R_SPI1_Msk   (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos)
	0xFFFFFFFF
#define	ETH_MACSPI1R_SPI1   ETH_MACSPI1R_SPI1_Msk /* Source Port Identity 1 */
#define	ETH_MACSPI2R_SPI2_Pos   (0U)
#define	ETH_MACSPI2R_SPI2_Msk   (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos)
	0x0000FFFF
#define	ETH_MACSPI2R_SPI2   ETH_MACSPI2R_SPI2_Msk /* Source Port Identity 2 */
#define	ETH_MACLMIR_LMPDRI_Pos   (24U)
#define	ETH_MACLMIR_LMPDRI_Msk   (0xFFUL << ETH_MACLMIR_LMPDRI_Pos)
	0xFF000000
#define	ETH_MACLMIR_LMPDRI   ETH_MACLMIR_LMPDRI_Msk /* Log Min Pdelay_Req Interval */
#define	ETH_MACLMIR_DRSYNCR_Pos   (8U)
#define	ETH_MACLMIR_DRSYNCR_Msk   (0x7UL << ETH_MACLMIR_DRSYNCR_Pos)
	0x00000700
#define	ETH_MACLMIR_DRSYNCR   ETH_MACLMIR_DRSYNCR_Msk /* Delay_Req to SYNC Ratio */
#define	ETH_MACLMIR_LSI_Pos   (0U)
#define	ETH_MACLMIR_LSI_Msk   (0xFFUL << ETH_MACLMIR_LSI_Pos)
	0x000000FF
#define	ETH_MACLMIR_LSI   ETH_MACLMIR_LSI_Msk /* Log Sync Interval */
#define	ETH_MTLOMR_CNTCLR_Pos   (9U)
#define	ETH_MTLOMR_CNTCLR_Msk   (0x1UL << ETH_MTLOMR_CNTCLR_Pos)
	0x00000200
#define	ETH_MTLOMR_CNTCLR   ETH_MTLOMR_CNTCLR_Msk /* Counters Reset */
#define	ETH_MTLOMR_CNTPRST_Pos   (8U)
#define	ETH_MTLOMR_CNTPRST_Msk   (0x1UL << ETH_MTLOMR_CNTPRST_Pos)
	0x00000100
#define	ETH_MTLOMR_CNTPRST   ETH_MTLOMR_CNTPRST_Msk /* Counters Preset */
#define	ETH_MTLOMR_DTXSTS_Pos   (1U)
#define	ETH_MTLOMR_DTXSTS_Msk   (0x1UL << ETH_MTLOMR_DTXSTS_Pos)
	0x00000002
#define	ETH_MTLOMR_DTXSTS   ETH_MTLOMR_DTXSTS_Msk /* Drop Transmit Status */
#define	ETH_MTLISR_MACIS_Pos   (16U)
#define	ETH_MTLISR_MACIS_Msk   (0x1UL << ETH_MTLISR_MACIS_Pos)
	0x00010000
#define	ETH_MTLISR_MACIS   ETH_MTLISR_MACIS_Msk /* MAC Interrupt Status */
#define	ETH_MTLISR_QIS_Pos   (0U)
#define	ETH_MTLISR_QIS_Msk   (0x1UL << ETH_MTLISR_QIS_Pos)
	0x00000001
#define	ETH_MTLISR_QIS   ETH_MTLISR_QIS_Msk /* Queue Interrupt status */
#define	ETH_MTLTQOMR_TTC_Pos   (4U)
#define	ETH_MTLTQOMR_TTC_Msk   (0x7UL << ETH_MTLTQOMR_TTC_Pos)
	0x00000070
#define	ETH_MTLTQOMR_TTC   ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
#define	ETH_MTLTQOMR_TTC_32BITS   (0U) /* 32 bits Threshold */
#define	ETH_MTLTQOMR_TTC_64BITS   (0x00000010U) /* 64 bits Threshold */
#define	ETH_MTLTQOMR_TTC_96BITS   (0x00000020U) /* 96 bits Threshold */
#define	ETH_MTLTQOMR_TTC_128BITS   (0x00000030U) /* 128 bits Threshold */
#define	ETH_MTLTQOMR_TTC_192BITS   (0x00000040U) /* 192 bits Threshold */
#define	ETH_MTLTQOMR_TTC_256BITS   (0x00000050U) /* 256 bits Threshold */
#define	ETH_MTLTQOMR_TTC_384BITS   (0x00000060U) /* 384 bits Threshold */
#define	ETH_MTLTQOMR_TTC_512BITS   (0x00000070U) /* 512 bits Threshold */
#define	ETH_MTLTQOMR_TSF_Pos   (1U)
#define	ETH_MTLTQOMR_TSF_Msk   (0x1UL << ETH_MTLTQOMR_TSF_Pos)
	0x00000002
#define	ETH_MTLTQOMR_TSF   ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
#define	ETH_MTLTQOMR_FTQ_Pos   (0U)
#define	ETH_MTLTQOMR_FTQ_Msk   (0x1UL << ETH_MTLTQOMR_FTQ_Pos)
	0x00000001
#define	ETH_MTLTQOMR_FTQ   ETH_MTLTQOMR_FTQ_Msk /* Flush Transmit Queue */
#define	ETH_MTLTQUR_UFCNTOVF_Pos   (11U)
#define	ETH_MTLTQUR_UFCNTOVF_Msk   (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos)
	0x00000800
#define	ETH_MTLTQUR_UFCNTOVF   ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
#define	ETH_MTLTQUR_UFPKTCNT_Pos   (0U)
#define	ETH_MTLTQUR_UFPKTCNT_Msk   (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos)
	0x000007FF
#define	ETH_MTLTQUR_UFPKTCNT   ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */
#define	ETH_MTLTQDR_STXSTSF_Pos   (20U)
#define	ETH_MTLTQDR_STXSTSF_Msk   (0x7UL << ETH_MTLTQDR_STXSTSF_Pos)
	0x00700000
#define	ETH_MTLTQDR_STXSTSF   ETH_MTLTQDR_STXSTSF_Msk /* Number of Status Words in the Tx Status FIFO of Queue */
#define	ETH_MTLTQDR_PTXQ_Pos   (16U)
#define	ETH_MTLTQDR_PTXQ_Msk   (0x7UL << ETH_MTLTQDR_PTXQ_Pos)
	0x00070000
#define	ETH_MTLTQDR_PTXQ   ETH_MTLTQDR_PTXQ_Msk /* Number of Packets in the Transmit Queue */
#define	ETH_MTLTQDR_TXSTSFSTS_Pos   (5U)
#define	ETH_MTLTQDR_TXSTSFSTS_Msk   (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos)
	0x00000020
#define	ETH_MTLTQDR_TXSTSFSTS   ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
#define	ETH_MTLTQDR_TXQSTS_Pos   (4U)
#define	ETH_MTLTQDR_TXQSTS_Msk   (0x1UL << ETH_MTLTQDR_TXQSTS_Pos)
	0x00000010
#define	ETH_MTLTQDR_TXQSTS   ETH_MTLTQDR_TXQSTS_Msk /* MTL Tx Queue Not Empty Status */
#define	ETH_MTLTQDR_TWCSTS_Pos   (3U)
#define	ETH_MTLTQDR_TWCSTS_Msk   (0x1UL << ETH_MTLTQDR_TWCSTS_Pos)
	0x00000008
#define	ETH_MTLTQDR_TWCSTS   ETH_MTLTQDR_TWCSTS_Msk /* MTL Tx Queue Write Controller Status */
#define	ETH_MTLTQDR_TRCSTS_Pos   (1U)
#define	ETH_MTLTQDR_TRCSTS_Msk   (0x3UL << ETH_MTLTQDR_TRCSTS_Pos)
	0x00000006
#define	ETH_MTLTQDR_TRCSTS   ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
#define	ETH_MTLTQDR_TRCSTS_IDLE   (0U) /* Idle state */
#define	ETH_MTLTQDR_TRCSTS_READ   (0x00000002U) /* Read state (transferring data to the MAC transmitter) */
#define	ETH_MTLTQDR_TRCSTS_WAITING   (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */
#define	ETH_MTLTQDR_TRCSTS_FLUSHING   (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
#define	ETH_MTLTQDR_TXQPAUSED_Pos   (0U)
#define	ETH_MTLTQDR_TXQPAUSED_Msk   (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos)
	0x00000001
#define	ETH_MTLTQDR_TXQPAUSED   ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
#define	ETH_MTLQICSR_RXOIE_Pos   (24U)
#define	ETH_MTLQICSR_RXOIE_Msk   (0x1UL << ETH_MTLQICSR_RXOIE_Pos)
	0x01000000
#define	ETH_MTLQICSR_RXOIE   ETH_MTLQICSR_RXOIE_Msk /* Receive Queue Overflow Interrupt Enable */
#define	ETH_MTLQICSR_RXOVFIS_Pos   (16U)
#define	ETH_MTLQICSR_RXOVFIS_Msk   (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos)
	0x00010000
#define	ETH_MTLQICSR_RXOVFIS   ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
#define	ETH_MTLQICSR_TXUIE_Pos   (8U)
#define	ETH_MTLQICSR_TXUIE_Msk   (0x1UL << ETH_MTLQICSR_TXUIE_Pos)
	0x00000100
#define	ETH_MTLQICSR_TXUIE   ETH_MTLQICSR_TXUIE_Msk /* Transmit Queue Underflow Interrupt Enable */
#define	ETH_MTLQICSR_TXUNFIS_Pos   (0U)
#define	ETH_MTLQICSR_TXUNFIS_Msk   (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos)
	0x00000001
#define	ETH_MTLQICSR_TXUNFIS   ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
#define	ETH_MTLRQOMR_RQS_Pos   (20U)
#define	ETH_MTLRQOMR_RQS_Msk   (0x7UL << ETH_MTLRQOMR_RQS_Pos)
	0x00700000
#define	ETH_MTLRQOMR_RQS   ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */
#define	ETH_MTLRQOMR_RFD_Pos   (14U)
#define	ETH_MTLRQOMR_RFD_Msk   (0x7UL << ETH_MTLRQOMR_RFD_Pos)
	0x0001C000
#define	ETH_MTLRQOMR_RFD   ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
#define	ETH_MTLRQOMR_RFA_Pos   (8U)
#define	ETH_MTLRQOMR_RFA_Msk   (0x7UL << ETH_MTLRQOMR_RFA_Pos)
	0x00000700
#define	ETH_MTLRQOMR_RFA   ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
#define	ETH_MTLRQOMR_EHFC_Pos   (7U)
#define	ETH_MTLRQOMR_EHFC_Msk   (0x1UL << ETH_MTLRQOMR_EHFC_Pos)
	0x00000080
#define	ETH_MTLRQOMR_EHFC   ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */
#define	ETH_MTLRQOMR_DISTCPEF_Pos   (6U)
#define	ETH_MTLRQOMR_DISTCPEF_Msk   (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos)
	0x00000040
#define	ETH_MTLRQOMR_DISTCPEF   ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
#define	ETH_MTLRQOMR_RSF_Pos   (5U)
#define	ETH_MTLRQOMR_RSF_Msk   (0x1UL << ETH_MTLRQOMR_RSF_Pos)
	0x00000020
#define	ETH_MTLRQOMR_RSF   ETH_MTLRQOMR_RSF_Msk /* Receive Queue Store and Forward */
#define	ETH_MTLRQOMR_FEP_Pos   (4U)
#define	ETH_MTLRQOMR_FEP_Msk   (0x1UL << ETH_MTLRQOMR_FEP_Pos)
	0x00000010
#define	ETH_MTLRQOMR_FEP   ETH_MTLRQOMR_FEP_Msk /* Forward Error Packets */
#define	ETH_MTLRQOMR_FUP_Pos   (3U)
#define	ETH_MTLRQOMR_FUP_Msk   (0x1UL << ETH_MTLRQOMR_FUP_Pos)
	0x00000008
#define	ETH_MTLRQOMR_FUP   ETH_MTLRQOMR_FUP_Msk /* Forward Undersized Good Packets */
#define	ETH_MTLRQOMR_RTC_Pos   (0U)
#define	ETH_MTLRQOMR_RTC_Msk   (0x3UL << ETH_MTLRQOMR_RTC_Pos)
	0x00000003
#define	ETH_MTLRQOMR_RTC   ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
#define	ETH_MTLRQOMR_RTC_64BITS   (0U) /* 64 bits Threshold */
#define	ETH_MTLRQOMR_RTC_32BITS   (0x00000001U) /* 32 bits Threshold */
#define	ETH_MTLRQOMR_RTC_96BITS   (0x00000002U) /* 96 bits Threshold */
#define	ETH_MTLRQOMR_RTC_128BITS   (0x00000003U) /* 128 bits Threshold */
#define	ETH_MTLRQMPOCR_MISCNTOVF_Pos   (27U)
#define	ETH_MTLRQMPOCR_MISCNTOVF_Msk   (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos)
	0x08000000
#define	ETH_MTLRQMPOCR_MISCNTOVF   ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
#define	ETH_MTLRQMPOCR_MISPKTCNT_Pos   (16U)
#define	ETH_MTLRQMPOCR_MISPKTCNT_Msk   (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos)
	0x07FF0000
#define	ETH_MTLRQMPOCR_MISPKTCNT   ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
#define	ETH_MTLRQMPOCR_OVFCNTOVF_Pos   (11U)
#define	ETH_MTLRQMPOCR_OVFCNTOVF_Msk   (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos)
	0x00000800
#define	ETH_MTLRQMPOCR_OVFCNTOVF   ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
#define	ETH_MTLRQMPOCR_OVFPKTCNT_Pos   (0U)
#define	ETH_MTLRQMPOCR_OVFPKTCNT_Msk   (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos)
	0x000007FF
#define	ETH_MTLRQMPOCR_OVFPKTCNT   ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
#define	ETH_MTLRQDR_PRXQ_Pos   (16U)
#define	ETH_MTLRQDR_PRXQ_Msk   (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos)
	0x3FFF0000
#define	ETH_MTLRQDR_PRXQ   ETH_MTLRQDR_PRXQ_Msk /* Number of Packets in Receive Queue */
#define	ETH_MTLRQDR_RXQSTS_Pos   (4U)
#define	ETH_MTLRQDR_RXQSTS_Msk   (0x3UL << ETH_MTLRQDR_RXQSTS_Pos)
	0x00000030
#define	ETH_MTLRQDR_RXQSTS   ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
#define	ETH_MTLRQDR_RXQSTS_EMPTY   (0U) /* Rx Queue empty */
#define	ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos   (4U)
#define	ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk   (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos)
	0x00000010
#define	ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD   ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
#define	ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos   (5U)
#define	ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk   (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos)
	0x00000020
#define	ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD   ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
#define	ETH_MTLRQDR_RXQSTS_FULL_Pos   (4U)
#define	ETH_MTLRQDR_RXQSTS_FULL_Msk   (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos)
	0x00000030
#define	ETH_MTLRQDR_RXQSTS_FULL   ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */
#define	ETH_MTLRQDR_RRCSTS_Pos   (1U)
#define	ETH_MTLRQDR_RRCSTS_Msk   (0x3UL << ETH_MTLRQDR_RRCSTS_Pos)
	0x00000006
#define	ETH_MTLRQDR_RRCSTS   ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
#define	ETH_MTLRQDR_RRCSTS_IDLE   (0U) /* Idle state */
#define	ETH_MTLRQDR_RRCSTS_READINGDATA_Pos   (1U)
#define	ETH_MTLRQDR_RRCSTS_READINGDATA_Msk   (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos)
	0x00000002
#define	ETH_MTLRQDR_RRCSTS_READINGDATA   ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
#define	ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos   (2U)
#define	ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk   (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos)
	0x00000004
#define	ETH_MTLRQDR_RRCSTS_READINGSTATUS   ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
#define	ETH_MTLRQDR_RRCSTS_FLUSHING_Pos   (1U)
#define	ETH_MTLRQDR_RRCSTS_FLUSHING_Msk   (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos)
	0x00000006
#define	ETH_MTLRQDR_RRCSTS_FLUSHING   ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
#define	ETH_MTLRQDR_RWCSTS_Pos   (0U)
#define	ETH_MTLRQDR_RWCSTS_Msk   (0x1UL << ETH_MTLRQDR_RWCSTS_Pos)
	0x00000001
#define	ETH_MTLRQDR_RWCSTS   ETH_MTLRQDR_RWCSTS_Msk /* MTL Rx Queue Write Controller Active Status */
#define	ETH_MTLRQCR_RQPA_Pos   (3U)
#define	ETH_MTLRQCR_RQPA_Msk   (0x1UL << ETH_MTLRQCR_RQPA_Pos)
	0x00000008
#define	ETH_MTLRQCR_RQPA   ETH_MTLRQCR_RQPA_Msk /* Receive Queue Packet Arbitration */
#define	ETH_MTLRQCR_RQW_Pos   (0U)
#define	ETH_MTLRQCR_RQW_Msk   (0x7UL << ETH_MTLRQCR_RQW_Pos)
	0x00000007
#define	ETH_MTLRQCR_RQW   ETH_MTLRQCR_RQW_Msk /* Receive Queue Weight */
#define	ETH_DMAMR_INTM_Pos   (16U)
#define	ETH_DMAMR_INTM_Msk   (0x3UL << ETH_DMAMR_INTM_Pos)
	0x00030000
#define	ETH_DMAMR_INTM   ETH_DMAMR_INTM_Msk /* This field defines the interrupt mode */
#define	ETH_DMAMR_INTM_0   (0x0UL << ETH_DMAMR_INTM_Pos)
	0x00000000
#define	ETH_DMAMR_INTM_1   (0x1UL << ETH_DMAMR_INTM_Pos)
	0x00010000
#define	ETH_DMAMR_INTM_2   (0x2UL << ETH_DMAMR_INTM_Pos)
	0x00020000
#define	ETH_DMAMR_PR_Pos   (12U)
#define	ETH_DMAMR_PR_Msk   (0x7UL << ETH_DMAMR_PR_Pos)
	0x00007000
#define	ETH_DMAMR_PR   ETH_DMAMR_PR_Msk /* Priority Ratio */
#define	ETH_DMAMR_PR_1_1   (0U) /* The priority ratio is 1:1 */
#define	ETH_DMAMR_PR_2_1   (0x00001000U) /* The priority ratio is 2:1 */
#define	ETH_DMAMR_PR_3_1   (0x00002000U) /* The priority ratio is 3:1 */
#define	ETH_DMAMR_PR_4_1   (0x00003000U) /* The priority ratio is 4:1 */
#define	ETH_DMAMR_PR_5_1   (0x00004000U) /* The priority ratio is 5:1 */
#define	ETH_DMAMR_PR_6_1   (0x00005000U) /* The priority ratio is 6:1 */
#define	ETH_DMAMR_PR_7_1   (0x00006000U) /* The priority ratio is 7:1 */
#define	ETH_DMAMR_PR_8_1   (0x00007000U) /* The priority ratio is 8:1 */
#define	ETH_DMAMR_TXPR_Pos   (11U)
#define	ETH_DMAMR_TXPR_Msk   (0x1UL << ETH_DMAMR_TXPR_Pos)
	0x00000800
#define	ETH_DMAMR_TXPR   ETH_DMAMR_TXPR_Msk /* Transmit Priority */
#define	ETH_DMAMR_DA_Pos   (1U)
#define	ETH_DMAMR_DA_Msk   (0x1UL << ETH_DMAMR_DA_Pos)
	0x00000002
#define	ETH_DMAMR_DA   ETH_DMAMR_DA_Msk /* DMA Tx or Rx Arbitration Scheme */
#define	ETH_DMAMR_SWR_Pos   (0U)
#define	ETH_DMAMR_SWR_Msk   (0x1UL << ETH_DMAMR_SWR_Pos)
	0x00000001
#define	ETH_DMAMR_SWR   ETH_DMAMR_SWR_Msk /* Software Reset */
#define	ETH_DMASBMR_RB_Pos   (15U)
#define	ETH_DMASBMR_RB_Msk   (0x1UL << ETH_DMASBMR_RB_Pos)
	0x00008000
#define	ETH_DMASBMR_RB   ETH_DMASBMR_RB_Msk /* Rebuild INCRx Burst */
#define	ETH_DMASBMR_MB_Pos   (14U)
#define	ETH_DMASBMR_MB_Msk   (0x1UL << ETH_DMASBMR_MB_Pos)
	0x00004000
#define	ETH_DMASBMR_MB   ETH_DMASBMR_MB_Msk /* Mixed Burst */
#define	ETH_DMASBMR_AAL_Pos   (12U)
#define	ETH_DMASBMR_AAL_Msk   (0x1UL << ETH_DMASBMR_AAL_Pos)
	0x00001000
#define	ETH_DMASBMR_AAL   ETH_DMASBMR_AAL_Msk /* Address-Aligned Beats */
#define	ETH_DMASBMR_FB_Pos   (0U)
#define	ETH_DMASBMR_FB_Msk   (0x1UL << ETH_DMASBMR_FB_Pos)
	0x00000001
#define	ETH_DMASBMR_FB   ETH_DMASBMR_FB_Msk /* Fixed Burst Length */
#define	ETH_DMAISR_MACIS_Pos   (17U)
#define	ETH_DMAISR_MACIS_Msk   (0x1UL << ETH_DMAISR_MACIS_Pos)
	0x00020000
#define	ETH_DMAISR_MACIS   ETH_DMAISR_MACIS_Msk /* MAC Interrupt Status */
#define	ETH_DMAISR_MTLIS_Pos   (16U)
#define	ETH_DMAISR_MTLIS_Msk   (0x1UL << ETH_DMAISR_MTLIS_Pos)
	0x00010000
#define	ETH_DMAISR_MTLIS   ETH_DMAISR_MTLIS_Msk /* MAC Interrupt Status */
#define	ETH_DMAISR_DMACIS_Pos   (0U)
#define	ETH_DMAISR_DMACIS_Msk   (0x1UL << ETH_DMAISR_DMACIS_Pos)
	0x00000001
#define	ETH_DMAISR_DMACIS   ETH_DMAISR_DMACIS_Msk /* DMA Channel Interrupt Status */
#define	ETH_DMADSR_TPS_Pos   (12U)
#define	ETH_DMADSR_TPS_Msk   (0xFUL << ETH_DMADSR_TPS_Pos)
	0x0000F000
#define	ETH_DMADSR_TPS   ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
#define	ETH_DMADSR_TPS_STOPPED   (0U) /* Stopped (Reset or Stop Transmit Command issued) */
#define	ETH_DMADSR_TPS_FETCHING_Pos   (12U)
#define	ETH_DMADSR_TPS_FETCHING_Msk   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos)
	0x00001000
#define	ETH_DMADSR_TPS_FETCHING   ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
#define	ETH_DMADSR_TPS_WAITING_Pos   (13U)
#define	ETH_DMADSR_TPS_WAITING_Msk   (0x1UL << ETH_DMADSR_TPS_WAITING_Pos)
	0x00002000
#define	ETH_DMADSR_TPS_WAITING   ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */
#define	ETH_DMADSR_TPS_READING_Pos   (12U)
#define	ETH_DMADSR_TPS_READING_Msk   (0x3UL << ETH_DMADSR_TPS_READING_Pos)
	0x00003000
#define	ETH_DMADSR_TPS_READING   ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
#define	ETH_DMADSR_TPS_TIMESTAMP_WR_Pos   (14U)
#define	ETH_DMADSR_TPS_TIMESTAMP_WR_Msk   (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos)
	0x00004000
#define	ETH_DMADSR_TPS_TIMESTAMP_WR   ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */
#define	ETH_DMADSR_TPS_SUSPENDED_Pos   (13U)
#define	ETH_DMADSR_TPS_SUSPENDED_Msk   (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos)
	0x00006000
#define	ETH_DMADSR_TPS_SUSPENDED   ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
#define	ETH_DMADSR_TPS_CLOSING_Pos   (12U)
#define	ETH_DMADSR_TPS_CLOSING_Msk   (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos)
	0x00007000
#define	ETH_DMADSR_TPS_CLOSING   ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */
#define	ETH_DMADSR_RPS_Pos   (8U)
#define	ETH_DMADSR_RPS_Msk   (0xFUL << ETH_DMADSR_RPS_Pos)
	0x00000F00
#define	ETH_DMADSR_RPS   ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
#define	ETH_DMADSR_RPS_STOPPED   (0U) /* Stopped (Reset or Stop Receive Command issued) */
#define	ETH_DMADSR_RPS_FETCHING_Pos   (12U)
#define	ETH_DMADSR_RPS_FETCHING_Msk   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos)
	0x00001000
#define	ETH_DMADSR_RPS_FETCHING   ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
#define	ETH_DMADSR_RPS_WAITING_Pos   (12U)
#define	ETH_DMADSR_RPS_WAITING_Msk   (0x3UL << ETH_DMADSR_RPS_WAITING_Pos)
	0x00003000
#define	ETH_DMADSR_RPS_WAITING   ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */
#define	ETH_DMADSR_RPS_SUSPENDED_Pos   (14U)
#define	ETH_DMADSR_RPS_SUSPENDED_Msk   (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos)
	0x00004000
#define	ETH_DMADSR_RPS_SUSPENDED   ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
#define	ETH_DMADSR_RPS_CLOSING_Pos   (12U)
#define	ETH_DMADSR_RPS_CLOSING_Msk   (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos)
	0x00005000
#define	ETH_DMADSR_RPS_CLOSING   ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
#define	ETH_DMADSR_RPS_TIMESTAMP_WR_Pos   (13U)
#define	ETH_DMADSR_RPS_TIMESTAMP_WR_Msk   (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos)
	0x00006000
#define	ETH_DMADSR_RPS_TIMESTAMP_WR   ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */
#define	ETH_DMADSR_RPS_TRANSFERRING_Pos   (12U)
#define	ETH_DMADSR_RPS_TRANSFERRING_Msk   (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos)
	0x00007000
#define	ETH_DMADSR_RPS_TRANSFERRING   ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
#define	ETH_DMACCR_DSL_Pos   (18U)
#define	ETH_DMACCR_DSL_Msk   (0x7UL << ETH_DMACCR_DSL_Pos)
	0x001C0000
#define	ETH_DMACCR_DSL   ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
#define	ETH_DMACCR_DSL_0BIT   (0U)
#define	ETH_DMACCR_DSL_32BIT   (0x00040000U)
#define	ETH_DMACCR_DSL_64BIT   (0x00080000U)
#define	ETH_DMACCR_DSL_128BIT   (0x00100000U)
#define	ETH_DMACCR_8PBL   (0x00010000U) /* 8xPBL mode */
#define	ETH_DMACCR_MSS_Pos   (0U)
#define	ETH_DMACCR_MSS_Msk   (0x3FFFUL << ETH_DMACCR_MSS_Pos)
	0x00003FFF
#define	ETH_DMACCR_MSS   ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
#define	ETH_DMACTCR_TPBL_Pos   (16U)
#define	ETH_DMACTCR_TPBL_Msk   (0x3FUL << ETH_DMACTCR_TPBL_Pos)
	0x003F0000
#define	ETH_DMACTCR_TPBL   ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
#define	ETH_DMACTCR_TPBL_1PBL   (0x00010000U) /* Transmit Programmable Burst Length 1 */
#define	ETH_DMACTCR_TPBL_2PBL   (0x00020000U) /* Transmit Programmable Burst Length 2 */
#define	ETH_DMACTCR_TPBL_4PBL   (0x00040000U) /* Transmit Programmable Burst Length 4 */
#define	ETH_DMACTCR_TPBL_8PBL   (0x00080000U) /* Transmit Programmable Burst Length 8 */
#define	ETH_DMACTCR_TPBL_16PBL   (0x00100000U) /* Transmit Programmable Burst Length 16 */
#define	ETH_DMACTCR_TPBL_32PBL   (0x00200000U) /* Transmit Programmable Burst Length 32 */
#define	ETH_DMACTCR_TSE_Pos   (12U)
#define	ETH_DMACTCR_TSE_Msk   (0x1UL << ETH_DMACTCR_TSE_Pos)
	0x00001000
#define	ETH_DMACTCR_TSE   ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
#define	ETH_DMACTCR_OSP_Pos   (4U)
#define	ETH_DMACTCR_OSP_Msk   (0x1UL << ETH_DMACTCR_OSP_Pos)
	0x00000010
#define	ETH_DMACTCR_OSP   ETH_DMACTCR_OSP_Msk /* Operate on Second Packet */
#define	ETH_DMACTCR_ST_Pos   (0U)
#define	ETH_DMACTCR_ST_Msk   (0x1UL << ETH_DMACTCR_ST_Pos)
	0x00000001
#define	ETH_DMACTCR_ST   ETH_DMACTCR_ST_Msk /* Start or Stop Transmission Command */
#define	ETH_DMACRCR_RPF_Pos   (31U)
#define	ETH_DMACRCR_RPF_Msk   (0x1UL << ETH_DMACRCR_RPF_Pos)
	0x80000000
#define	ETH_DMACRCR_RPF   ETH_DMACRCR_RPF_Msk /* Rx Packet Flush */
#define	ETH_DMACRCR_RPBL_Pos   (16U)
#define	ETH_DMACRCR_RPBL_Msk   (0x3FUL << ETH_DMACRCR_RPBL_Pos)
	0x003F0000
#define	ETH_DMACRCR_RPBL   ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
#define	ETH_DMACRCR_RPBL_1PBL   (0x00010000U) /* Receive Programmable Burst Length 1 */
#define	ETH_DMACRCR_RPBL_2PBL   (0x00020000U) /* Receive Programmable Burst Length 2 */
#define	ETH_DMACRCR_RPBL_4PBL   (0x00040000U) /* Receive Programmable Burst Length 4 */
#define	ETH_DMACRCR_RPBL_8PBL   (0x00080000U) /* Receive Programmable Burst Length 8 */
#define	ETH_DMACRCR_RPBL_16PBL   (0x00100000U) /* Receive Programmable Burst Length 16 */
#define	ETH_DMACRCR_RPBL_32PBL   (0x00200000U) /* Receive Programmable Burst Length 32 */
#define	ETH_DMACRCR_RBSZ_Pos   (1U)
#define	ETH_DMACRCR_RBSZ_Msk   (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos)
	0x00007FFE
#define	ETH_DMACRCR_RBSZ   ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
#define	ETH_DMACRCR_SR_Pos   (0U)
#define	ETH_DMACRCR_SR_Msk   (0x1UL << ETH_DMACRCR_SR_Pos)
	0x00000001
#define	ETH_DMACRCR_SR   ETH_DMACRCR_SR_Msk /* Start or Stop Receive */
#define	ETH_DMACTDLAR_TDESLA_Pos   (2U)
#define	ETH_DMACTDLAR_TDESLA_Msk   (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos)
	0xFFFFFFFC
#define	ETH_DMACTDLAR_TDESLA   ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */
#define	ETH_DMACRDLAR_RDESLA_Pos   (2U)
#define	ETH_DMACRDLAR_RDESLA_Msk   (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos)
	0xFFFFFFFC
#define	ETH_DMACRDLAR_RDESLA   ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */
#define	ETH_DMACTDTPR_TDT_Pos   (2U)
#define	ETH_DMACTDTPR_TDT_Msk   (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos)
	0xFFFFFFFC
#define	ETH_DMACTDTPR_TDT   ETH_DMACTDTPR_TDT_Msk /* Transmit Descriptor Tail Pointer */
#define	ETH_DMACRDTPR_RDT_Pos   (2U)
#define	ETH_DMACRDTPR_RDT_Msk   (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos)
	0xFFFFFFFC
#define	ETH_DMACRDTPR_RDT   ETH_DMACRDTPR_RDT_Msk /* Receive Descriptor Tail Pointer */
#define	ETH_DMACTDRLR_TDRL_Pos   (0U)
#define	ETH_DMACTDRLR_TDRL_Msk   (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos)
	0x000003FF
#define	ETH_DMACTDRLR_TDRL   ETH_DMACTDRLR_TDRL_Msk /* Transmit Descriptor Ring Length */
#define	ETH_DMACRDRLR_RDRL_Pos   (0U)
#define	ETH_DMACRDRLR_RDRL_Msk   (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos)
	0x000003FF
#define	ETH_DMACRDRLR_RDRL   ETH_DMACRDRLR_RDRL_Msk /* Receive Descriptor Ring Length */
#define	ETH_DMACIER_NIE_Pos   (15U)
#define	ETH_DMACIER_NIE_Msk   (0x1UL << ETH_DMACIER_NIE_Pos)
	0x00008000
#define	ETH_DMACIER_NIE   ETH_DMACIER_NIE_Msk /* Normal Interrupt Summary Enable */
#define	ETH_DMACIER_AIE_Pos   (14U)
#define	ETH_DMACIER_AIE_Msk   (0x1UL << ETH_DMACIER_AIE_Pos)
	0x00004000
#define	ETH_DMACIER_AIE   ETH_DMACIER_AIE_Msk /* Abnormal Interrupt Summary Enable */
#define	ETH_DMACIER_CDEE_Pos   (13U)
#define	ETH_DMACIER_CDEE_Msk   (0x1UL << ETH_DMACIER_CDEE_Pos)
	0x00002000
#define	ETH_DMACIER_CDEE   ETH_DMACIER_CDEE_Msk /* Context Descriptor Error Enable */
#define	ETH_DMACIER_FBEE_Pos   (12U)
#define	ETH_DMACIER_FBEE_Msk   (0x1UL << ETH_DMACIER_FBEE_Pos)
	0x00001000
#define	ETH_DMACIER_FBEE   ETH_DMACIER_FBEE_Msk /* Fatal Bus Error Enable */
#define	ETH_DMACIER_ERIE_Pos   (11U)
#define	ETH_DMACIER_ERIE_Msk   (0x1UL << ETH_DMACIER_ERIE_Pos)
	0x00000800
#define	ETH_DMACIER_ERIE   ETH_DMACIER_ERIE_Msk /* Early Receive Interrupt Enable */
#define	ETH_DMACIER_ETIE_Pos   (10U)
#define	ETH_DMACIER_ETIE_Msk   (0x1UL << ETH_DMACIER_ETIE_Pos)
	0x00000400
#define	ETH_DMACIER_ETIE   ETH_DMACIER_ETIE_Msk /* Early Transmit Interrupt Enable */
#define	ETH_DMACIER_RWTE_Pos   (9U)
#define	ETH_DMACIER_RWTE_Msk   (0x1UL << ETH_DMACIER_RWTE_Pos)
	0x00000200
#define	ETH_DMACIER_RWTE   ETH_DMACIER_RWTE_Msk /* Receive Watchdog Timeout Enable */
#define	ETH_DMACIER_RSE_Pos   (8U)
#define	ETH_DMACIER_RSE_Msk   (0x1UL << ETH_DMACIER_RSE_Pos)
	0x00000100
#define	ETH_DMACIER_RSE   ETH_DMACIER_RSE_Msk /* Receive Stopped Enable */
#define	ETH_DMACIER_RBUE_Pos   (7U)
#define	ETH_DMACIER_RBUE_Msk   (0x1UL << ETH_DMACIER_RBUE_Pos)
	0x00000080
#define	ETH_DMACIER_RBUE   ETH_DMACIER_RBUE_Msk /* Receive Buffer Unavailable Enable */
#define	ETH_DMACIER_RIE_Pos   (6U)
#define	ETH_DMACIER_RIE_Msk   (0x1UL << ETH_DMACIER_RIE_Pos)
	0x00000040
#define	ETH_DMACIER_RIE   ETH_DMACIER_RIE_Msk /* Receive Interrupt Enable */
#define	ETH_DMACIER_TBUE_Pos   (2U)
#define	ETH_DMACIER_TBUE_Msk   (0x1UL << ETH_DMACIER_TBUE_Pos)
	0x00000004
#define	ETH_DMACIER_TBUE   ETH_DMACIER_TBUE_Msk /* Transmit Buffer Unavailable Enable */
#define	ETH_DMACIER_TXSE_Pos   (1U)
#define	ETH_DMACIER_TXSE_Msk   (0x1UL << ETH_DMACIER_TXSE_Pos)
	0x00000002
#define	ETH_DMACIER_TXSE   ETH_DMACIER_TXSE_Msk /* Transmit Stopped Enable */
#define	ETH_DMACIER_TIE_Pos   (0U)
#define	ETH_DMACIER_TIE_Msk   (0x1UL << ETH_DMACIER_TIE_Pos)
	0x00000001
#define	ETH_DMACIER_TIE   ETH_DMACIER_TIE_Msk /* Transmit Interrupt Enable */
#define	ETH_DMACRIWTR_RWT_Pos   (0U)
#define	ETH_DMACRIWTR_RWT_Msk   (0xFFUL << ETH_DMACRIWTR_RWT_Pos)
	0x000000FF
#define	ETH_DMACRIWTR_RWT   ETH_DMACRIWTR_RWT_Msk /* Receive Interrupt Watchdog Timer Count */
#define	ETH_DMACCATDR_CURTDESAPTR_Pos   (0U)
#define	ETH_DMACCATDR_CURTDESAPTR_Msk   (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos)
	0xFFFFFFFF
#define	ETH_DMACCATDR_CURTDESAPTR   ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
#define	ETH_DMACCARDR_CURRDESAPTR_Pos   (0U)
#define	ETH_DMACCARDR_CURRDESAPTR_Msk   (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos)
	0xFFFFFFFF
#define	ETH_DMACCARDR_CURRDESAPTR   ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */
#define	ETH_DMACCATBR_CURTBUFAPTR_Pos   (0U)
#define	ETH_DMACCATBR_CURTBUFAPTR_Msk   (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos)
	0xFFFFFFFF
#define	ETH_DMACCATBR_CURTBUFAPTR   ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
#define	ETH_DMACCARBR_CURRBUFAPTR_Pos   (0U)
#define	ETH_DMACCARBR_CURRBUFAPTR_Msk   (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos)
	0xFFFFFFFF
#define	ETH_DMACCARBR_CURRBUFAPTR   ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
#define	ETH_DMACSR_REB_Pos   (19U)
#define	ETH_DMACSR_REB_Msk   (0x7UL << ETH_DMACSR_REB_Pos)
	0x00380000
#define	ETH_DMACSR_REB   ETH_DMACSR_REB_Msk /* Rx DMA Error Bits */
#define	ETH_DMACSR_TEB_Pos   (16U)
#define	ETH_DMACSR_TEB_Msk   (0x7UL << ETH_DMACSR_TEB_Pos)
	0x00070000
#define	ETH_DMACSR_TEB   ETH_DMACSR_TEB_Msk /* Tx DMA Error Bits */
#define	ETH_DMACSR_NIS_Pos   (15U)
#define	ETH_DMACSR_NIS_Msk   (0x1UL << ETH_DMACSR_NIS_Pos)
	0x00008000
#define	ETH_DMACSR_NIS   ETH_DMACSR_NIS_Msk /* Normal Interrupt Summary */
#define	ETH_DMACSR_AIS_Pos   (14U)
#define	ETH_DMACSR_AIS_Msk   (0x1UL << ETH_DMACSR_AIS_Pos)
	0x00004000
#define	ETH_DMACSR_AIS   ETH_DMACSR_AIS_Msk /* Abnormal Interrupt Summary */
#define	ETH_DMACSR_CDE_Pos   (13U)
#define	ETH_DMACSR_CDE_Msk   (0x1UL << ETH_DMACSR_CDE_Pos)
	0x00002000
#define	ETH_DMACSR_CDE   ETH_DMACSR_CDE_Msk /* Context Descriptor Error */
#define	ETH_DMACSR_FBE_Pos   (12U)
#define	ETH_DMACSR_FBE_Msk   (0x1UL << ETH_DMACSR_FBE_Pos)
	0x00001000
#define	ETH_DMACSR_FBE   ETH_DMACSR_FBE_Msk /* Fatal Bus Error */
#define	ETH_DMACSR_ERI_Pos   (11U)
#define	ETH_DMACSR_ERI_Msk   (0x1UL << ETH_DMACSR_ERI_Pos)
	0x00000800
#define	ETH_DMACSR_ERI   ETH_DMACSR_ERI_Msk /* Early Receive Interrupt */
#define	ETH_DMACSR_ETI_Pos   (10U)
#define	ETH_DMACSR_ETI_Msk   (0x1UL << ETH_DMACSR_ETI_Pos)
	0x00000400
#define	ETH_DMACSR_ETI   ETH_DMACSR_ETI_Msk /* Early Transmit Interrupt */
#define	ETH_DMACSR_RWT_Pos   (9U)
#define	ETH_DMACSR_RWT_Msk   (0x1UL << ETH_DMACSR_RWT_Pos)
	0x00000200
#define	ETH_DMACSR_RWT   ETH_DMACSR_RWT_Msk /* Receive Watchdog Timeout */
#define	ETH_DMACSR_RPS_Pos   (8U)
#define	ETH_DMACSR_RPS_Msk   (0x1UL << ETH_DMACSR_RPS_Pos)
	0x00000100
#define	ETH_DMACSR_RPS   ETH_DMACSR_RPS_Msk /* Receive Process Stopped */
#define	ETH_DMACSR_RBU_Pos   (7U)
#define	ETH_DMACSR_RBU_Msk   (0x1UL << ETH_DMACSR_RBU_Pos)
	0x00000080
#define	ETH_DMACSR_RBU   ETH_DMACSR_RBU_Msk /* Receive Buffer Unavailable */
#define	ETH_DMACSR_RI_Pos   (6U)
#define	ETH_DMACSR_RI_Msk   (0x1UL << ETH_DMACSR_RI_Pos)
	0x00000040
#define	ETH_DMACSR_RI   ETH_DMACSR_RI_Msk /* Receive Interrupt */
#define	ETH_DMACSR_TBU_Pos   (2U)
#define	ETH_DMACSR_TBU_Msk   (0x1UL << ETH_DMACSR_TBU_Pos)
	0x00000004
#define	ETH_DMACSR_TBU   ETH_DMACSR_TBU_Msk /* Transmit Buffer Unavailable */
#define	ETH_DMACSR_TPS_Pos   (1U)
#define	ETH_DMACSR_TPS_Msk   (0x1UL << ETH_DMACSR_TPS_Pos)
	0x00000002
#define	ETH_DMACSR_TPS   ETH_DMACSR_TPS_Msk /* Transmit Process Stopped */
#define	ETH_DMACSR_TI_Pos   (0U)
#define	ETH_DMACSR_TI_Msk   (0x1UL << ETH_DMACSR_TI_Pos)
	0x00000001
#define	ETH_DMACSR_TI   ETH_DMACSR_TI_Msk /* Transmit Interrupt */
#define	ETH_DMACMFCR_MFCO_Pos   (15U)
#define	ETH_DMACMFCR_MFCO_Msk   (0x1UL << ETH_DMACMFCR_MFCO_Pos)
	0x00008000
#define	ETH_DMACMFCR_MFCO   ETH_DMACMFCR_MFCO_Msk /* Overflow status of the MFC Counter */
#define	ETH_DMACMFCR_MFC_Pos   (0U)
#define	ETH_DMACMFCR_MFC_Msk   (0x7FFUL << ETH_DMACMFCR_MFC_Pos)
	0x000007FF
#define	ETH_DMACMFCR_MFC   ETH_DMACMFCR_MFC_Msk /* The number of packet counters dropped by the DMA */
#define	DMA_SxCR_MBURST_Pos   (23U)
#define	DMA_SxCR_MBURST_Msk   (0x3UL << DMA_SxCR_MBURST_Pos)
	0x01800000
#define	DMA_SxCR_MBURST   DMA_SxCR_MBURST_Msk
	Memory burst transfer configuration.
#define	DMA_SxCR_MBURST_0   (0x1UL << DMA_SxCR_MBURST_Pos)
	0x00800000
#define	DMA_SxCR_MBURST_1   (0x2UL << DMA_SxCR_MBURST_Pos)
	0x01000000
#define	DMA_SxCR_PBURST_Pos   (21U)
#define	DMA_SxCR_PBURST_Msk   (0x3UL << DMA_SxCR_PBURST_Pos)
	0x00600000
#define	DMA_SxCR_PBURST   DMA_SxCR_PBURST_Msk
	Peripheral burst transfer configuration.
#define	DMA_SxCR_PBURST_0   (0x1UL << DMA_SxCR_PBURST_Pos)
	0x00200000
#define	DMA_SxCR_PBURST_1   (0x2UL << DMA_SxCR_PBURST_Pos)
	0x00400000
#define	DMA_SxCR_TRBUFF_Pos   (20U)
#define	DMA_SxCR_TRBUFF_Msk   (0x1UL << DMA_SxCR_TRBUFF_Pos)
	0x00100000
#define	DMA_SxCR_TRBUFF   DMA_SxCR_TRBUFF_Msk
	bufferable transfers enabled/disable
#define	DMA_SxCR_CT_Pos   (19U)
#define	DMA_SxCR_CT_Msk   (0x1UL << DMA_SxCR_CT_Pos)
	0x00080000
#define	DMA_SxCR_CT   DMA_SxCR_CT_Msk
	Current target (only in double buffer mode).
#define	DMA_SxCR_DBM_Pos   (18U)
#define	DMA_SxCR_DBM_Msk   (0x1UL << DMA_SxCR_DBM_Pos)
	0x00040000
#define	DMA_SxCR_DBM   DMA_SxCR_DBM_Msk
	Double buffer mode.
#define	DMA_SxCR_PL_Pos   (16U)
#define	DMA_SxCR_PL_Msk   (0x3UL << DMA_SxCR_PL_Pos)
	0x00030000
#define	DMA_SxCR_PL   DMA_SxCR_PL_Msk
	Priority level.
#define	DMA_SxCR_PL_0   (0x1UL << DMA_SxCR_PL_Pos)
	0x00010000
#define	DMA_SxCR_PL_1   (0x2UL << DMA_SxCR_PL_Pos)
	0x00020000
#define	DMA_SxCR_PINCOS_Pos   (15U)
#define	DMA_SxCR_PINCOS_Msk   (0x1UL << DMA_SxCR_PINCOS_Pos)
	0x00008000
#define	DMA_SxCR_PINCOS   DMA_SxCR_PINCOS_Msk
	Peripheral increment offset size.
#define	DMA_SxCR_MSIZE_Pos   (13U)
#define	DMA_SxCR_MSIZE_Msk   (0x3UL << DMA_SxCR_MSIZE_Pos)
	0x00006000
#define	DMA_SxCR_MSIZE   DMA_SxCR_MSIZE_Msk
	Memory data size.
#define	DMA_SxCR_MSIZE_0   (0x1UL << DMA_SxCR_MSIZE_Pos)
	0x00002000
#define	DMA_SxCR_MSIZE_1   (0x2UL << DMA_SxCR_MSIZE_Pos)
	0x00004000
#define	DMA_SxCR_PSIZE_Pos   (11U)
#define	DMA_SxCR_PSIZE_Msk   (0x3UL << DMA_SxCR_PSIZE_Pos)
	0x00001800
#define	DMA_SxCR_PSIZE   DMA_SxCR_PSIZE_Msk /*< Peripheral data size */
#define	DMA_SxCR_PSIZE_0   (0x1UL << DMA_SxCR_PSIZE_Pos)
	0x00000800
#define	DMA_SxCR_PSIZE_1   (0x2UL << DMA_SxCR_PSIZE_Pos)
	0x00001000
#define	DMA_SxCR_MINC_Pos   (10U)
#define	DMA_SxCR_MINC_Msk   (0x1UL << DMA_SxCR_MINC_Pos)
	0x00000400
#define	DMA_SxCR_MINC   DMA_SxCR_MINC_Msk
	Memory increment mode.
#define	DMA_SxCR_PINC_Pos   (9U)
#define	DMA_SxCR_PINC_Msk   (0x1UL << DMA_SxCR_PINC_Pos)
	0x00000200
#define	DMA_SxCR_PINC   DMA_SxCR_PINC_Msk
	Peripheral increment mode.
#define	DMA_SxCR_CIRC_Pos   (8U)
#define	DMA_SxCR_CIRC_Msk   (0x1UL << DMA_SxCR_CIRC_Pos)
	0x00000100
#define	DMA_SxCR_CIRC   DMA_SxCR_CIRC_Msk
	Circular mode.
#define	DMA_SxCR_DIR_Pos   (6U)
#define	DMA_SxCR_DIR_Msk   (0x3UL << DMA_SxCR_DIR_Pos)
	0x000000C0
#define	DMA_SxCR_DIR   DMA_SxCR_DIR_Msk
	Data transfer direction.
#define	DMA_SxCR_DIR_0   (0x1UL << DMA_SxCR_DIR_Pos)
	0x00000040
#define	DMA_SxCR_DIR_1   (0x2UL << DMA_SxCR_DIR_Pos)
	0x00000080
#define	DMA_SxCR_PFCTRL_Pos   (5U)
#define	DMA_SxCR_PFCTRL_Msk   (0x1UL << DMA_SxCR_PFCTRL_Pos)
	0x00000020
#define	DMA_SxCR_PFCTRL   DMA_SxCR_PFCTRL_Msk
	Peripheral flow controller.
#define	DMA_SxCR_TCIE_Pos   (4U)
#define	DMA_SxCR_TCIE_Msk   (0x1UL << DMA_SxCR_TCIE_Pos)
	0x00000010
#define	DMA_SxCR_TCIE   DMA_SxCR_TCIE_Msk
	Transfer complete interrupt enable.
#define	DMA_SxCR_HTIE_Pos   (3U)
#define	DMA_SxCR_HTIE_Msk   (0x1UL << DMA_SxCR_HTIE_Pos)
	0x00000008
#define	DMA_SxCR_HTIE   DMA_SxCR_HTIE_Msk
	Half transfer interrupt enable.
#define	DMA_SxCR_TEIE_Pos   (2U)
#define	DMA_SxCR_TEIE_Msk   (0x1UL << DMA_SxCR_TEIE_Pos)
	0x00000004
#define	DMA_SxCR_TEIE   DMA_SxCR_TEIE_Msk
	Transfer error interrupt enable.
#define	DMA_SxCR_DMEIE_Pos   (1U)
#define	DMA_SxCR_DMEIE_Msk   (0x1UL << DMA_SxCR_DMEIE_Pos)
	0x00000002
#define	DMA_SxCR_DMEIE   DMA_SxCR_DMEIE_Msk
	Direct mode error interrupt enable.
#define	DMA_SxCR_EN_Pos   (0U)
#define	DMA_SxCR_EN_Msk   (0x1UL << DMA_SxCR_EN_Pos)
	0x00000001
#define	DMA_SxCR_EN   DMA_SxCR_EN_Msk
	Stream enable / flag stream ready when read low.
#define	DMA_SxNDT_Pos   (0U)
#define	DMA_SxNDT_Msk   (0xFFFFUL << DMA_SxNDT_Pos)
	0x0000FFFF
#define	DMA_SxNDT   DMA_SxNDT_Msk
	Number of data items to transfer.
#define	DMA_SxNDT_0   (0x0001UL << DMA_SxNDT_Pos)
	0x00000001
#define	DMA_SxNDT_1   (0x0002UL << DMA_SxNDT_Pos)
	0x00000002
#define	DMA_SxNDT_2   (0x0004UL << DMA_SxNDT_Pos)
	0x00000004
#define	DMA_SxNDT_3   (0x0008UL << DMA_SxNDT_Pos)
	0x00000008
#define	DMA_SxNDT_4   (0x0010UL << DMA_SxNDT_Pos)
	0x00000010
#define	DMA_SxNDT_5   (0x0020UL << DMA_SxNDT_Pos)
	0x00000020
#define	DMA_SxNDT_6   (0x0040UL << DMA_SxNDT_Pos)
	0x00000040
#define	DMA_SxNDT_7   (0x0080UL << DMA_SxNDT_Pos)
	0x00000080
#define	DMA_SxNDT_8   (0x0100UL << DMA_SxNDT_Pos)
	0x00000100
#define	DMA_SxNDT_9   (0x0200UL << DMA_SxNDT_Pos)
	0x00000200
#define	DMA_SxNDT_10   (0x0400UL << DMA_SxNDT_Pos)
	0x00000400
#define	DMA_SxNDT_11   (0x0800UL << DMA_SxNDT_Pos)
	0x00000800
#define	DMA_SxNDT_12   (0x1000UL << DMA_SxNDT_Pos)
	0x00001000
#define	DMA_SxNDT_13   (0x2000UL << DMA_SxNDT_Pos)
	0x00002000
#define	DMA_SxNDT_14   (0x4000UL << DMA_SxNDT_Pos)
	0x00004000
#define	DMA_SxNDT_15   (0x8000UL << DMA_SxNDT_Pos)
	0x00008000
#define	DMA_SxFCR_FEIE_Pos   (7U)
#define	DMA_SxFCR_FEIE_Msk   (0x1UL << DMA_SxFCR_FEIE_Pos)
	0x00000080
#define	DMA_SxFCR_FEIE   DMA_SxFCR_FEIE_Msk
	FIFO error interrupt enable.
#define	DMA_SxFCR_FS_Pos   (3U)
#define	DMA_SxFCR_FS_Msk   (0x7UL << DMA_SxFCR_FS_Pos)
	0x00000038
#define	DMA_SxFCR_FS   DMA_SxFCR_FS_Msk
	FIFO status.
#define	DMA_SxFCR_FS_0   (0x1UL << DMA_SxFCR_FS_Pos)
	0x00000008
#define	DMA_SxFCR_FS_1   (0x2UL << DMA_SxFCR_FS_Pos)
	0x00000010
#define	DMA_SxFCR_FS_2   (0x4UL << DMA_SxFCR_FS_Pos)
	0x00000020
#define	DMA_SxFCR_DMDIS_Pos   (2U)
#define	DMA_SxFCR_DMDIS_Msk   (0x1UL << DMA_SxFCR_DMDIS_Pos)
	0x00000004
#define	DMA_SxFCR_DMDIS   DMA_SxFCR_DMDIS_Msk
	Direct mode disable.
#define	DMA_SxFCR_FTH_Pos   (0U)
#define	DMA_SxFCR_FTH_Msk   (0x3UL << DMA_SxFCR_FTH_Pos)
	0x00000003
#define	DMA_SxFCR_FTH   DMA_SxFCR_FTH_Msk
	FIFO threshold selection.
#define	DMA_SxFCR_FTH_0   (0x1UL << DMA_SxFCR_FTH_Pos)
	0x00000001
#define	DMA_SxFCR_FTH_1   (0x2UL << DMA_SxFCR_FTH_Pos)
	0x00000002
#define	DMA_LISR_TCIF3_Pos   (27U)
#define	DMA_LISR_TCIF3_Msk   (0x1UL << DMA_LISR_TCIF3_Pos)
	0x08000000
#define	DMA_LISR_TCIF3   DMA_LISR_TCIF3_Msk
	Stream 3 transfer complete interrupt flag.
#define	DMA_LISR_HTIF3_Pos   (26U)
#define	DMA_LISR_HTIF3_Msk   (0x1UL << DMA_LISR_HTIF3_Pos)
	0x04000000
#define	DMA_LISR_HTIF3   DMA_LISR_HTIF3_Msk
	Stream 3 half transfer interrupt flag.
#define	DMA_LISR_TEIF3_Pos   (25U)
#define	DMA_LISR_TEIF3_Msk   (0x1UL << DMA_LISR_TEIF3_Pos)
	0x02000000
#define	DMA_LISR_TEIF3   DMA_LISR_TEIF3_Msk
	Stream 3 transfer error interrupt flag.
#define	DMA_LISR_DMEIF3_Pos   (24U)
#define	DMA_LISR_DMEIF3_Msk   (0x1UL << DMA_LISR_DMEIF3_Pos)
	0x01000000
#define	DMA_LISR_DMEIF3   DMA_LISR_DMEIF3_Msk
	Stream 3 direct mode error interrupt flag.
#define	DMA_LISR_FEIF3_Pos   (22U)
#define	DMA_LISR_FEIF3_Msk   (0x1UL << DMA_LISR_FEIF3_Pos)
	0x00400000
#define	DMA_LISR_FEIF3   DMA_LISR_FEIF3_Msk
	Stream 3 FIFO error interrupt flag.
#define	DMA_LISR_TCIF2_Pos   (21U)
#define	DMA_LISR_TCIF2_Msk   (0x1UL << DMA_LISR_TCIF2_Pos)
	0x00200000
#define	DMA_LISR_TCIF2   DMA_LISR_TCIF2_Msk
	Stream 2 transfer complete interrupt flag.
#define	DMA_LISR_HTIF2_Pos   (20U)
#define	DMA_LISR_HTIF2_Msk   (0x1UL << DMA_LISR_HTIF2_Pos)
	0x00100000
#define	DMA_LISR_HTIF2   DMA_LISR_HTIF2_Msk
	Stream 2 half transfer interrupt flag.
#define	DMA_LISR_TEIF2_Pos   (19U)
#define	DMA_LISR_TEIF2_Msk   (0x1UL << DMA_LISR_TEIF2_Pos)
	0x00080000
#define	DMA_LISR_TEIF2   DMA_LISR_TEIF2_Msk
	Stream 2 transfer error interrupt flag.
#define	DMA_LISR_DMEIF2_Pos   (18U)
#define	DMA_LISR_DMEIF2_Msk   (0x1UL << DMA_LISR_DMEIF2_Pos)
	0x00040000
#define	DMA_LISR_DMEIF2   DMA_LISR_DMEIF2_Msk
	Stream 2 direct mode error interrupt flag.
#define	DMA_LISR_FEIF2_Pos   (16U)
#define	DMA_LISR_FEIF2_Msk   (0x1UL << DMA_LISR_FEIF2_Pos)
	0x00010000
#define	DMA_LISR_FEIF2   DMA_LISR_FEIF2_Msk
	Stream 2 FIFO error interrupt flag.
#define	DMA_LISR_TCIF1_Pos   (11U)
#define	DMA_LISR_TCIF1_Msk   (0x1UL << DMA_LISR_TCIF1_Pos)
	0x00000800
#define	DMA_LISR_TCIF1   DMA_LISR_TCIF1_Msk
	Stream 1 transfer complete interrupt flag.
#define	DMA_LISR_HTIF1_Pos   (10U)
#define	DMA_LISR_HTIF1_Msk   (0x1UL << DMA_LISR_HTIF1_Pos)
	0x00000400
#define	DMA_LISR_HTIF1   DMA_LISR_HTIF1_Msk
	Stream 1 half transfer interrupt flag.
#define	DMA_LISR_TEIF1_Pos   (9U)
#define	DMA_LISR_TEIF1_Msk   (0x1UL << DMA_LISR_TEIF1_Pos)
	0x00000200
#define	DMA_LISR_TEIF1   DMA_LISR_TEIF1_Msk
	Stream 1 transfer error interrupt flag.
#define	DMA_LISR_DMEIF1_Pos   (8U)
#define	DMA_LISR_DMEIF1_Msk   (0x1UL << DMA_LISR_DMEIF1_Pos)
	0x00000100
#define	DMA_LISR_DMEIF1   DMA_LISR_DMEIF1_Msk
	Stream 1 direct mode error interrupt flag.
#define	DMA_LISR_FEIF1_Pos   (6U)
#define	DMA_LISR_FEIF1_Msk   (0x1UL << DMA_LISR_FEIF1_Pos)
	0x00000040
#define	DMA_LISR_FEIF1   DMA_LISR_FEIF1_Msk
	Stream 1 FIFO error interrupt flag.
#define	DMA_LISR_TCIF0_Pos   (5U)
#define	DMA_LISR_TCIF0_Msk   (0x1UL << DMA_LISR_TCIF0_Pos)
	0x00000020
#define	DMA_LISR_TCIF0   DMA_LISR_TCIF0_Msk
	Stream 0 transfer complete interrupt flag.
#define	DMA_LISR_HTIF0_Pos   (4U)
#define	DMA_LISR_HTIF0_Msk   (0x1UL << DMA_LISR_HTIF0_Pos)
	0x00000010
#define	DMA_LISR_HTIF0   DMA_LISR_HTIF0_Msk
	Stream 0 half transfer interrupt flag.
#define	DMA_LISR_TEIF0_Pos   (3U)
#define	DMA_LISR_TEIF0_Msk   (0x1UL << DMA_LISR_TEIF0_Pos)
	0x00000008
#define	DMA_LISR_TEIF0   DMA_LISR_TEIF0_Msk
	Stream 0 transfer error interrupt flag.
#define	DMA_LISR_DMEIF0_Pos   (2U)
#define	DMA_LISR_DMEIF0_Msk   (0x1UL << DMA_LISR_DMEIF0_Pos)
	0x00000004
#define	DMA_LISR_DMEIF0   DMA_LISR_DMEIF0_Msk
	Stream 0 direct mode error interrupt flag.
#define	DMA_LISR_FEIF0_Pos   (0U)
#define	DMA_LISR_FEIF0_Msk   (0x1UL << DMA_LISR_FEIF0_Pos)
	0x00000001
#define	DMA_LISR_FEIF0   DMA_LISR_FEIF0_Msk
	Stream 0 FIFO error interrupt flag.
#define	DMA_HISR_TCIF7_Pos   (27U)
#define	DMA_HISR_TCIF7_Msk   (0x1UL << DMA_HISR_TCIF7_Pos)
	0x08000000
#define	DMA_HISR_TCIF7   DMA_HISR_TCIF7_Msk
	Stream 7 transfer complete interrupt flag.
#define	DMA_HISR_HTIF7_Pos   (26U)
#define	DMA_HISR_HTIF7_Msk   (0x1UL << DMA_HISR_HTIF7_Pos)
	0x04000000
#define	DMA_HISR_HTIF7   DMA_HISR_HTIF7_Msk
	Stream 7 half transfer interrupt flag.
#define	DMA_HISR_TEIF7_Pos   (25U)
#define	DMA_HISR_TEIF7_Msk   (0x1UL << DMA_HISR_TEIF7_Pos)
	0x02000000
#define	DMA_HISR_TEIF7   DMA_HISR_TEIF7_Msk
	Stream 7 transfer error interrupt flag.
#define	DMA_HISR_DMEIF7_Pos   (24U)
#define	DMA_HISR_DMEIF7_Msk   (0x1UL << DMA_HISR_DMEIF7_Pos)
	0x01000000
#define	DMA_HISR_DMEIF7   DMA_HISR_DMEIF7_Msk
	Stream 7 direct mode error interrupt flag.
#define	DMA_HISR_FEIF7_Pos   (22U)
#define	DMA_HISR_FEIF7_Msk   (0x1UL << DMA_HISR_FEIF7_Pos)
	0x00400000
#define	DMA_HISR_FEIF7   DMA_HISR_FEIF7_Msk
	Stream 7 FIFO error interrupt flag.
#define	DMA_HISR_TCIF6_Pos   (21U)
#define	DMA_HISR_TCIF6_Msk   (0x1UL << DMA_HISR_TCIF6_Pos)
	0x00200000
#define	DMA_HISR_TCIF6   DMA_HISR_TCIF6_Msk
	Stream 6 transfer complete interrupt flag.
#define	DMA_HISR_HTIF6_Pos   (20U)
#define	DMA_HISR_HTIF6_Msk   (0x1UL << DMA_HISR_HTIF6_Pos)
	0x00100000
#define	DMA_HISR_HTIF6   DMA_HISR_HTIF6_Msk
	Stream 6 half transfer interrupt flag.
#define	DMA_HISR_TEIF6_Pos   (19U)
#define	DMA_HISR_TEIF6_Msk   (0x1UL << DMA_HISR_TEIF6_Pos)
	0x00080000
#define	DMA_HISR_TEIF6   DMA_HISR_TEIF6_Msk
	Stream 6 transfer error interrupt flag.
#define	DMA_HISR_DMEIF6_Pos   (18U)
#define	DMA_HISR_DMEIF6_Msk   (0x1UL << DMA_HISR_DMEIF6_Pos)
	0x00040000
#define	DMA_HISR_DMEIF6   DMA_HISR_DMEIF6_Msk
	Stream 6 direct mode error interrupt flag.
#define	DMA_HISR_FEIF6_Pos   (16U)
#define	DMA_HISR_FEIF6_Msk   (0x1UL << DMA_HISR_FEIF6_Pos)
	0x00010000
#define	DMA_HISR_FEIF6   DMA_HISR_FEIF6_Msk
	Stream 6 FIFO error interrupt flag.
#define	DMA_HISR_TCIF5_Pos   (11U)
#define	DMA_HISR_TCIF5_Msk   (0x1UL << DMA_HISR_TCIF5_Pos)
	0x00000800
#define	DMA_HISR_TCIF5   DMA_HISR_TCIF5_Msk
	Stream 5 transfer complete interrupt flag.
#define	DMA_HISR_HTIF5_Pos   (10U)
#define	DMA_HISR_HTIF5_Msk   (0x1UL << DMA_HISR_HTIF5_Pos)
	0x00000400
#define	DMA_HISR_HTIF5   DMA_HISR_HTIF5_Msk
	Stream 5 half transfer interrupt flag.
#define	DMA_HISR_TEIF5_Pos   (9U)
#define	DMA_HISR_TEIF5_Msk   (0x1UL << DMA_HISR_TEIF5_Pos)
	0x00000200
#define	DMA_HISR_TEIF5   DMA_HISR_TEIF5_Msk
	Stream 5 transfer error interrupt flag.
#define	DMA_HISR_DMEIF5_Pos   (8U)
#define	DMA_HISR_DMEIF5_Msk   (0x1UL << DMA_HISR_DMEIF5_Pos)
	0x00000100
#define	DMA_HISR_DMEIF5   DMA_HISR_DMEIF5_Msk
	Stream 5 direct mode error interrupt flag.
#define	DMA_HISR_FEIF5_Pos   (6U)
#define	DMA_HISR_FEIF5_Msk   (0x1UL << DMA_HISR_FEIF5_Pos)
	0x00000040
#define	DMA_HISR_FEIF5   DMA_HISR_FEIF5_Msk
	Stream 5 FIFO error interrupt flag.
#define	DMA_HISR_TCIF4_Pos   (5U)
#define	DMA_HISR_TCIF4_Msk   (0x1UL << DMA_HISR_TCIF4_Pos)
	0x00000020
#define	DMA_HISR_TCIF4   DMA_HISR_TCIF4_Msk
	Stream 4 transfer complete interrupt flag.
#define	DMA_HISR_HTIF4_Pos   (4U)
#define	DMA_HISR_HTIF4_Msk   (0x1UL << DMA_HISR_HTIF4_Pos)
	0x00000010
#define	DMA_HISR_HTIF4   DMA_HISR_HTIF4_Msk
	Stream 4 half transfer interrupt flag.
#define	DMA_HISR_TEIF4_Pos   (3U)
#define	DMA_HISR_TEIF4_Msk   (0x1UL << DMA_HISR_TEIF4_Pos)
	0x00000008
#define	DMA_HISR_TEIF4   DMA_HISR_TEIF4_Msk
	Stream 4 transfer error interrupt flag.
#define	DMA_HISR_DMEIF4_Pos   (2U)
#define	DMA_HISR_DMEIF4_Msk   (0x1UL << DMA_HISR_DMEIF4_Pos)
	0x00000004
#define	DMA_HISR_DMEIF4   DMA_HISR_DMEIF4_Msk
	Stream 4 direct mode error interrupt flag.
#define	DMA_HISR_FEIF4_Pos   (0U)
#define	DMA_HISR_FEIF4_Msk   (0x1UL << DMA_HISR_FEIF4_Pos)
	0x00000001
#define	DMA_HISR_FEIF4   DMA_HISR_FEIF4_Msk
	Stream 4 FIFO error interrupt flag.
#define	DMA_LIFCR_CTCIF3_Pos   (27U)
#define	DMA_LIFCR_CTCIF3_Msk   (0x1UL << DMA_LIFCR_CTCIF3_Pos)
	0x08000000
#define	DMA_LIFCR_CTCIF3   DMA_LIFCR_CTCIF3_Msk
	Stream 3 clear transfer complete interrupt flag.
#define	DMA_LIFCR_CHTIF3_Pos   (26U)
#define	DMA_LIFCR_CHTIF3_Msk   (0x1UL << DMA_LIFCR_CHTIF3_Pos)
	0x04000000
#define	DMA_LIFCR_CHTIF3   DMA_LIFCR_CHTIF3_Msk
	Stream 3 clear half transfer interrupt flag.
#define	DMA_LIFCR_CTEIF3_Pos   (25U)
#define	DMA_LIFCR_CTEIF3_Msk   (0x1UL << DMA_LIFCR_CTEIF3_Pos)
	0x02000000
#define	DMA_LIFCR_CTEIF3   DMA_LIFCR_CTEIF3_Msk
	Stream 3 clear transfer error interrupt flag.
#define	DMA_LIFCR_CDMEIF3_Pos   (24U)
#define	DMA_LIFCR_CDMEIF3_Msk   (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
	0x01000000
#define	DMA_LIFCR_CDMEIF3   DMA_LIFCR_CDMEIF3_Msk
	Stream 3 clear direct mode error interrupt flag.
#define	DMA_LIFCR_CFEIF3_Pos   (22U)
#define	DMA_LIFCR_CFEIF3_Msk   (0x1UL << DMA_LIFCR_CFEIF3_Pos)
	0x00400000
#define	DMA_LIFCR_CFEIF3   DMA_LIFCR_CFEIF3_Msk
	Stream 3 clear FIFO error interrupt flag.
#define	DMA_LIFCR_CTCIF2_Pos   (21U)
#define	DMA_LIFCR_CTCIF2_Msk   (0x1UL << DMA_LIFCR_CTCIF2_Pos)
	0x00200000
#define	DMA_LIFCR_CTCIF2   DMA_LIFCR_CTCIF2_Msk
	Stream 2 clear transfer complete interrupt flag.
#define	DMA_LIFCR_CHTIF2_Pos   (20U)
#define	DMA_LIFCR_CHTIF2_Msk   (0x1UL << DMA_LIFCR_CHTIF2_Pos)
	0x00100000
#define	DMA_LIFCR_CHTIF2   DMA_LIFCR_CHTIF2_Msk
	Stream 2 clear half transfer interrupt flag.
#define	DMA_LIFCR_CTEIF2_Pos   (19U)
#define	DMA_LIFCR_CTEIF2_Msk   (0x1UL << DMA_LIFCR_CTEIF2_Pos)
	0x00080000
#define	DMA_LIFCR_CTEIF2   DMA_LIFCR_CTEIF2_Msk
	Stream 2 clear transfer error interrupt flag.
#define	DMA_LIFCR_CDMEIF2_Pos   (18U)
#define	DMA_LIFCR_CDMEIF2_Msk   (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
	0x00040000
#define	DMA_LIFCR_CDMEIF2   DMA_LIFCR_CDMEIF2_Msk
	Stream 2 clear direct mode error interrupt flag.
#define	DMA_LIFCR_CFEIF2_Pos   (16U)
#define	DMA_LIFCR_CFEIF2_Msk   (0x1UL << DMA_LIFCR_CFEIF2_Pos)
	0x00010000
#define	DMA_LIFCR_CFEIF2   DMA_LIFCR_CFEIF2_Msk
	Stream 2 clear FIFO error interrupt flag.
#define	DMA_LIFCR_CTCIF1_Pos   (11U)
#define	DMA_LIFCR_CTCIF1_Msk   (0x1UL << DMA_LIFCR_CTCIF1_Pos)
	0x00000800
#define	DMA_LIFCR_CTCIF1   DMA_LIFCR_CTCIF1_Msk
	Stream 1 clear transfer complete interrupt flag.
#define	DMA_LIFCR_CHTIF1_Pos   (10U)
#define	DMA_LIFCR_CHTIF1_Msk   (0x1UL << DMA_LIFCR_CHTIF1_Pos)
	0x00000400
#define	DMA_LIFCR_CHTIF1   DMA_LIFCR_CHTIF1_Msk
	Stream 1 clear half transfer interrupt flag.
#define	DMA_LIFCR_CTEIF1_Pos   (9U)
#define	DMA_LIFCR_CTEIF1_Msk   (0x1UL << DMA_LIFCR_CTEIF1_Pos)
	0x00000200
#define	DMA_LIFCR_CTEIF1   DMA_LIFCR_CTEIF1_Msk
	Stream 1 clear transfer error interrupt flag.
#define	DMA_LIFCR_CDMEIF1_Pos   (8U)
#define	DMA_LIFCR_CDMEIF1_Msk   (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
	0x00000100
#define	DMA_LIFCR_CDMEIF1   DMA_LIFCR_CDMEIF1_Msk
	Stream 1 clear direct mode error interrupt flag.
#define	DMA_LIFCR_CFEIF1_Pos   (6U)
#define	DMA_LIFCR_CFEIF1_Msk   (0x1UL << DMA_LIFCR_CFEIF1_Pos)
	0x00000040
#define	DMA_LIFCR_CFEIF1   DMA_LIFCR_CFEIF1_Msk
	Stream 1 clear FIFO error interrupt flag.
#define	DMA_LIFCR_CTCIF0_Pos   (5U)
#define	DMA_LIFCR_CTCIF0_Msk   (0x1UL << DMA_LIFCR_CTCIF0_Pos)
	0x00000020
#define	DMA_LIFCR_CTCIF0   DMA_LIFCR_CTCIF0_Msk
	Stream 0 clear transfer complete interrupt flag.
#define	DMA_LIFCR_CHTIF0_Pos   (4U)
#define	DMA_LIFCR_CHTIF0_Msk   (0x1UL << DMA_LIFCR_CHTIF0_Pos)
	0x00000010
#define	DMA_LIFCR_CHTIF0   DMA_LIFCR_CHTIF0_Msk
	Stream 0 clear half transfer interrupt flag.
#define	DMA_LIFCR_CTEIF0_Pos   (3U)
#define	DMA_LIFCR_CTEIF0_Msk   (0x1UL << DMA_LIFCR_CTEIF0_Pos)
	0x00000008
#define	DMA_LIFCR_CTEIF0   DMA_LIFCR_CTEIF0_Msk
	Stream 0 clear transfer error interrupt flag.
#define	DMA_LIFCR_CDMEIF0_Pos   (2U)
#define	DMA_LIFCR_CDMEIF0_Msk   (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
	0x00000004
#define	DMA_LIFCR_CDMEIF0   DMA_LIFCR_CDMEIF0_Msk
	Stream 0 clear direct mode error interrupt flag.
#define	DMA_LIFCR_CFEIF0_Pos   (0U)
#define	DMA_LIFCR_CFEIF0_Msk   (0x1UL << DMA_LIFCR_CFEIF0_Pos)
	0x00000001
#define	DMA_LIFCR_CFEIF0   DMA_LIFCR_CFEIF0_Msk
	Stream 0 clear FIFO error interrupt flag.
#define	DMA_HIFCR_CTCIF7_Pos   (27U)
#define	DMA_HIFCR_CTCIF7_Msk   (0x1UL << DMA_HIFCR_CTCIF7_Pos)
	0x08000000
#define	DMA_HIFCR_CTCIF7   DMA_HIFCR_CTCIF7_Msk
	Stream 7 clear transfer complete interrupt flag.
#define	DMA_HIFCR_CHTIF7_Pos   (26U)
#define	DMA_HIFCR_CHTIF7_Msk   (0x1UL << DMA_HIFCR_CHTIF7_Pos)
	0x04000000
#define	DMA_HIFCR_CHTIF7   DMA_HIFCR_CHTIF7_Msk
	Stream 7 clear half transfer interrupt flag.
#define	DMA_HIFCR_CTEIF7_Pos   (25U)
#define	DMA_HIFCR_CTEIF7_Msk   (0x1UL << DMA_HIFCR_CTEIF7_Pos)
	0x02000000
#define	DMA_HIFCR_CTEIF7   DMA_HIFCR_CTEIF7_Msk
	Stream 7 clear transfer error interrupt flag.
#define	DMA_HIFCR_CDMEIF7_Pos   (24U)
#define	DMA_HIFCR_CDMEIF7_Msk   (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
	0x01000000
#define	DMA_HIFCR_CDMEIF7   DMA_HIFCR_CDMEIF7_Msk
	Stream 7 clear direct mode error interrupt flag.
#define	DMA_HIFCR_CFEIF7_Pos   (22U)
#define	DMA_HIFCR_CFEIF7_Msk   (0x1UL << DMA_HIFCR_CFEIF7_Pos)
	0x00400000
#define	DMA_HIFCR_CFEIF7   DMA_HIFCR_CFEIF7_Msk
	Stream 7 clear FIFO error interrupt flag.
#define	DMA_HIFCR_CTCIF6_Pos   (21U)
#define	DMA_HIFCR_CTCIF6_Msk   (0x1UL << DMA_HIFCR_CTCIF6_Pos)
	0x00200000
#define	DMA_HIFCR_CTCIF6   DMA_HIFCR_CTCIF6_Msk
	Stream 6 clear transfer complete interrupt flag.
#define	DMA_HIFCR_CHTIF6_Pos   (20U)
#define	DMA_HIFCR_CHTIF6_Msk   (0x1UL << DMA_HIFCR_CHTIF6_Pos)
	0x00100000
#define	DMA_HIFCR_CHTIF6   DMA_HIFCR_CHTIF6_Msk
	Stream 6 clear half transfer interrupt flag.
#define	DMA_HIFCR_CTEIF6_Pos   (19U)
#define	DMA_HIFCR_CTEIF6_Msk   (0x1UL << DMA_HIFCR_CTEIF6_Pos)
	0x00080000
#define	DMA_HIFCR_CTEIF6   DMA_HIFCR_CTEIF6_Msk
	Stream 6 clear transfer error interrupt flag.
#define	DMA_HIFCR_CDMEIF6_Pos   (18U)
#define	DMA_HIFCR_CDMEIF6_Msk   (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
	0x00040000
#define	DMA_HIFCR_CDMEIF6   DMA_HIFCR_CDMEIF6_Msk
	Stream 6 clear direct mode error interrupt flag.
#define	DMA_HIFCR_CFEIF6_Pos   (16U)
#define	DMA_HIFCR_CFEIF6_Msk   (0x1UL << DMA_HIFCR_CFEIF6_Pos)
	0x00010000
#define	DMA_HIFCR_CFEIF6   DMA_HIFCR_CFEIF6_Msk
	Stream 6 clear FIFO error interrupt flag.
#define	DMA_HIFCR_CTCIF5_Pos   (11U)
#define	DMA_HIFCR_CTCIF5_Msk   (0x1UL << DMA_HIFCR_CTCIF5_Pos)
	0x00000800
#define	DMA_HIFCR_CTCIF5   DMA_HIFCR_CTCIF5_Msk
	Stream 5 clear transfer complete interrupt flag.
#define	DMA_HIFCR_CHTIF5_Pos   (10U)
#define	DMA_HIFCR_CHTIF5_Msk   (0x1UL << DMA_HIFCR_CHTIF5_Pos)
	0x00000400
#define	DMA_HIFCR_CHTIF5   DMA_HIFCR_CHTIF5_Msk
	Stream 5 clear half transfer interrupt flag.
#define	DMA_HIFCR_CTEIF5_Pos   (9U)
#define	DMA_HIFCR_CTEIF5_Msk   (0x1UL << DMA_HIFCR_CTEIF5_Pos)
	0x00000200
#define	DMA_HIFCR_CTEIF5   DMA_HIFCR_CTEIF5_Msk
	Stream 5 clear transfer error interrupt flag.
#define	DMA_HIFCR_CDMEIF5_Pos   (8U)
#define	DMA_HIFCR_CDMEIF5_Msk   (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
	0x00000100
#define	DMA_HIFCR_CDMEIF5   DMA_HIFCR_CDMEIF5_Msk
	Stream 5 clear direct mode error interrupt flag.
#define	DMA_HIFCR_CFEIF5_Pos   (6U)
#define	DMA_HIFCR_CFEIF5_Msk   (0x1UL << DMA_HIFCR_CFEIF5_Pos)
	0x00000040
#define	DMA_HIFCR_CFEIF5   DMA_HIFCR_CFEIF5_Msk
	Stream 5 clear FIFO error interrupt flag.
#define	DMA_HIFCR_CTCIF4_Pos   (5U)
#define	DMA_HIFCR_CTCIF4_Msk   (0x1UL << DMA_HIFCR_CTCIF4_Pos)
	0x00000020
#define	DMA_HIFCR_CTCIF4   DMA_HIFCR_CTCIF4_Msk
	Stream 4 clear transfer complete interrupt flag.
#define	DMA_HIFCR_CHTIF4_Pos   (4U)
#define	DMA_HIFCR_CHTIF4_Msk   (0x1UL << DMA_HIFCR_CHTIF4_Pos)
	0x00000010
#define	DMA_HIFCR_CHTIF4   DMA_HIFCR_CHTIF4_Msk
	Stream 4 clear half transfer interrupt flag.
#define	DMA_HIFCR_CTEIF4_Pos   (3U)
#define	DMA_HIFCR_CTEIF4_Msk   (0x1UL << DMA_HIFCR_CTEIF4_Pos)
	0x00000008
#define	DMA_HIFCR_CTEIF4   DMA_HIFCR_CTEIF4_Msk
	Stream 4 clear transfer error interrupt flag.
#define	DMA_HIFCR_CDMEIF4_Pos   (2U)
#define	DMA_HIFCR_CDMEIF4_Msk   (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
	0x00000004
#define	DMA_HIFCR_CDMEIF4   DMA_HIFCR_CDMEIF4_Msk
	Stream 4 clear direct mode error interrupt flag.
#define	DMA_HIFCR_CFEIF4_Pos   (0U)
#define	DMA_HIFCR_CFEIF4_Msk   (0x1UL << DMA_HIFCR_CFEIF4_Pos)
	0x00000001
#define	DMA_HIFCR_CFEIF4   DMA_HIFCR_CFEIF4_Msk
	Stream 4 clear FIFO error interrupt flag.
#define	DMA_SxPAR_PA_Pos   (0U)
#define	DMA_SxPAR_PA_Msk   (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
	0xFFFFFFFF
#define	DMA_SxPAR_PA   DMA_SxPAR_PA_Msk
	Peripheral Address.
#define	DMA_SxM0AR_M0A_Pos   (0U)
#define	DMA_SxM0AR_M0A_Msk   (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
	0xFFFFFFFF
#define	DMA_SxM0AR_M0A   DMA_SxM0AR_M0A_Msk
	Memory 0 Address.
#define	DMA_SxM1AR_M1A_Pos   (0U)
#define	DMA_SxM1AR_M1A_Msk   (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
	0xFFFFFFFF
#define	DMA_SxM1AR_M1A   DMA_SxM1AR_M1A_Msk
	Memory 1 Address.
#define	DMAMUX_CxCR_DMAREQ_ID_Pos   (0U)
#define	DMAMUX_CxCR_DMAREQ_ID_Msk   (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)
	0x000000FF
#define	DMAMUX_CxCR_DMAREQ_ID   DMAMUX_CxCR_DMAREQ_ID_Msk
	DMA request identification.
#define	DMAMUX_CxCR_DMAREQ_ID_0   (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
	0x00000001
#define	DMAMUX_CxCR_DMAREQ_ID_1   (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
	0x00000002
#define	DMAMUX_CxCR_DMAREQ_ID_2   (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
	0x00000004
#define	DMAMUX_CxCR_DMAREQ_ID_3   (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
	0x00000008
#define	DMAMUX_CxCR_DMAREQ_ID_4   (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
	0x00000010
#define	DMAMUX_CxCR_DMAREQ_ID_5   (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
	0x00000020
#define	DMAMUX_CxCR_DMAREQ_ID_6   (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
	0x00000040
#define	DMAMUX_CxCR_DMAREQ_ID_7   (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
	0x00000080
#define	DMAMUX_CxCR_SOIE_Pos   (8U)
#define	DMAMUX_CxCR_SOIE_Msk   (0x1UL << DMAMUX_CxCR_SOIE_Pos)
	0x00000100
#define	DMAMUX_CxCR_SOIE   DMAMUX_CxCR_SOIE_Msk
	Synchronization overrun interrupt enable.
#define	DMAMUX_CxCR_EGE_Pos   (9U)
#define	DMAMUX_CxCR_EGE_Msk   (0x1UL << DMAMUX_CxCR_EGE_Pos)
	0x00000200
#define	DMAMUX_CxCR_EGE   DMAMUX_CxCR_EGE_Msk
	Event generation enable.
#define	DMAMUX_CxCR_SE_Pos   (16U)
#define	DMAMUX_CxCR_SE_Msk   (0x1UL << DMAMUX_CxCR_SE_Pos)
	0x00010000
#define	DMAMUX_CxCR_SE   DMAMUX_CxCR_SE_Msk
	Synchronization enable.
#define	DMAMUX_CxCR_SPOL_Pos   (17U)
#define	DMAMUX_CxCR_SPOL_Msk   (0x3UL << DMAMUX_CxCR_SPOL_Pos)
	0x00060000
#define	DMAMUX_CxCR_SPOL   DMAMUX_CxCR_SPOL_Msk
	Synchronization polarity.
#define	DMAMUX_CxCR_SPOL_0   (0x1UL << DMAMUX_CxCR_SPOL_Pos)
	0x00020000
#define	DMAMUX_CxCR_SPOL_1   (0x2UL << DMAMUX_CxCR_SPOL_Pos)
	0x00040000
#define	DMAMUX_CxCR_NBREQ_Pos   (19U)
#define	DMAMUX_CxCR_NBREQ_Msk   (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)
	0x00F80000
#define	DMAMUX_CxCR_NBREQ   DMAMUX_CxCR_NBREQ_Msk
	Number of DMA requests minus 1 to forward.
#define	DMAMUX_CxCR_NBREQ_0   (0x01UL << DMAMUX_CxCR_NBREQ_Pos)
	0x00080000
#define	DMAMUX_CxCR_NBREQ_1   (0x02UL << DMAMUX_CxCR_NBREQ_Pos)
	0x00100000
#define	DMAMUX_CxCR_NBREQ_2   (0x04UL << DMAMUX_CxCR_NBREQ_Pos)
	0x00200000
#define	DMAMUX_CxCR_NBREQ_3   (0x08UL << DMAMUX_CxCR_NBREQ_Pos)
	0x00400000
#define	DMAMUX_CxCR_NBREQ_4   (0x10UL << DMAMUX_CxCR_NBREQ_Pos)
	0x00800000
#define	DMAMUX_CxCR_SYNC_ID_Pos   (24U)
#define	DMAMUX_CxCR_SYNC_ID_Msk   (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)
	0x1F000000
#define	DMAMUX_CxCR_SYNC_ID   DMAMUX_CxCR_SYNC_ID_Msk
	Synchronization identification.
#define	DMAMUX_CxCR_SYNC_ID_0   (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)
	0x01000000
#define	DMAMUX_CxCR_SYNC_ID_1   (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)
	0x02000000
#define	DMAMUX_CxCR_SYNC_ID_2   (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)
	0x04000000
#define	DMAMUX_CxCR_SYNC_ID_3   (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)
	0x08000000
#define	DMAMUX_CxCR_SYNC_ID_4   (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)
	0x10000000
#define	DMAMUX_CSR_SOF0_Pos   (0U)
#define	DMAMUX_CSR_SOF0_Msk   (0x1UL << DMAMUX_CSR_SOF0_Pos)
	0x00000001
#define	DMAMUX_CSR_SOF0   DMAMUX_CSR_SOF0_Msk
	Channel 0 Synchronization overrun event flag.
#define	DMAMUX_CSR_SOF1_Pos   (1U)
#define	DMAMUX_CSR_SOF1_Msk   (0x1UL << DMAMUX_CSR_SOF1_Pos)
	0x00000002
#define	DMAMUX_CSR_SOF1   DMAMUX_CSR_SOF1_Msk
	Channel 1 Synchronization overrun event flag.
#define	DMAMUX_CSR_SOF2_Pos   (2U)
#define	DMAMUX_CSR_SOF2_Msk   (0x1UL << DMAMUX_CSR_SOF2_Pos)
	0x00000004
#define	DMAMUX_CSR_SOF2   DMAMUX_CSR_SOF2_Msk
	Channel 2 Synchronization overrun event flag.
#define	DMAMUX_CSR_SOF3_Pos   (3U)
#define	DMAMUX_CSR_SOF3_Msk   (0x1UL << DMAMUX_CSR_SOF3_Pos)
	0x00000008
#define	DMAMUX_CSR_SOF3   DMAMUX_CSR_SOF3_Msk
	Channel 3 Synchronization overrun event flag.
#define	DMAMUX_CSR_SOF4_Pos   (4U)
#define	DMAMUX_CSR_SOF4_Msk   (0x1UL << DMAMUX_CSR_SOF4_Pos)
	0x00000010
#define	DMAMUX_CSR_SOF4   DMAMUX_CSR_SOF4_Msk
	Channel 4 Synchronization overrun event flag.
#define	DMAMUX_CSR_SOF5_Pos   (5U)
#define	DMAMUX_CSR_SOF5_Msk   (0x1UL << DMAMUX_CSR_SOF5_Pos)
	0x00000020
#define	DMAMUX_CSR_SOF5   DMAMUX_CSR_SOF5_Msk
	Channel 5 Synchronization overrun event flag.
#define	DMAMUX_CSR_SOF6_Pos   (6U)
#define	DMAMUX_CSR_SOF6_Msk   (0x1UL << DMAMUX_CSR_SOF6_Pos)
	0x00000040
#define	DMAMUX_CSR_SOF6   DMAMUX_CSR_SOF6_Msk
	Channel 6 Synchronization overrun event flag.
#define	DMAMUX_CSR_SOF7_Pos   (7U)
#define	DMAMUX_CSR_SOF7_Msk   (0x1UL << DMAMUX_CSR_SOF7_Pos)
	0x00000080
#define	DMAMUX_CSR_SOF7   DMAMUX_CSR_SOF7_Msk
	Channel 7 Synchronization overrun event flag.
#define	DMAMUX_CSR_SOF8_Pos   (8U)
#define	DMAMUX_CSR_SOF8_Msk   (0x1UL << DMAMUX_CSR_SOF8_Pos)
	0x00000100
#define	DMAMUX_CSR_SOF8   DMAMUX_CSR_SOF8_Msk
	Channel 8 Synchronization overrun event flag.
#define	DMAMUX_CSR_SOF9_Pos   (9U)
#define	DMAMUX_CSR_SOF9_Msk   (0x1UL << DMAMUX_CSR_SOF9_Pos)
	0x00000200
#define	DMAMUX_CSR_SOF9   DMAMUX_CSR_SOF9_Msk
	Channel 9 Synchronization overrun event flag.
#define	DMAMUX_CSR_SOF10_Pos   (10U)
#define	DMAMUX_CSR_SOF10_Msk   (0x1UL << DMAMUX_CSR_SOF10_Pos)
	0x00000400
#define	DMAMUX_CSR_SOF10   DMAMUX_CSR_SOF10_Msk
	Channel 10 Synchronization overrun event flag.
#define	DMAMUX_CSR_SOF11_Pos   (11U)
#define	DMAMUX_CSR_SOF11_Msk   (0x1UL << DMAMUX_CSR_SOF11_Pos)
	0x00000800
#define	DMAMUX_CSR_SOF11   DMAMUX_CSR_SOF11_Msk
	Channel 11 Synchronization overrun event flag.
#define	DMAMUX_CSR_SOF12_Pos   (12U)
#define	DMAMUX_CSR_SOF12_Msk   (0x1UL << DMAMUX_CSR_SOF12_Pos)
	0x00001000
#define	DMAMUX_CSR_SOF12   DMAMUX_CSR_SOF12_Msk
	Channel 12 Synchronization overrun event flag.
#define	DMAMUX_CSR_SOF13_Pos   (13U)
#define	DMAMUX_CSR_SOF13_Msk   (0x1UL << DMAMUX_CSR_SOF13_Pos)
	0x00002000
#define	DMAMUX_CSR_SOF13   DMAMUX_CSR_SOF13_Msk
	Channel 13 Synchronization overrun event flag.
#define	DMAMUX_CSR_SOF14_Pos   (14U)
#define	DMAMUX_CSR_SOF14_Msk   (0x1UL << DMAMUX_CSR_SOF14_Pos)
	0x00004000
#define	DMAMUX_CSR_SOF14   DMAMUX_CSR_SOF14_Msk
	Channel 14 Synchronization overrun event flag.
#define	DMAMUX_CSR_SOF15_Pos   (15U)
#define	DMAMUX_CSR_SOF15_Msk   (0x1UL << DMAMUX_CSR_SOF15_Pos)
	0x00008000
#define	DMAMUX_CSR_SOF15   DMAMUX_CSR_SOF15_Msk
	Channel 15 Synchronization overrun event flag.
#define	DMAMUX_CFR_CSOF0_Pos   (0U)
#define	DMAMUX_CFR_CSOF0_Msk   (0x1UL << DMAMUX_CFR_CSOF0_Pos)
	0x00000001
#define	DMAMUX_CFR_CSOF0   DMAMUX_CFR_CSOF0_Msk
	Channel 0 Clear synchronization overrun event flag.
#define	DMAMUX_CFR_CSOF1_Pos   (1U)
#define	DMAMUX_CFR_CSOF1_Msk   (0x1UL << DMAMUX_CFR_CSOF1_Pos)
	0x00000002
#define	DMAMUX_CFR_CSOF1   DMAMUX_CFR_CSOF1_Msk
	Channel 1 Clear synchronization overrun event flag.
#define	DMAMUX_CFR_CSOF2_Pos   (2U)
#define	DMAMUX_CFR_CSOF2_Msk   (0x1UL << DMAMUX_CFR_CSOF2_Pos)
	0x00000004
#define	DMAMUX_CFR_CSOF2   DMAMUX_CFR_CSOF2_Msk
	Channel 2 Clear synchronization overrun event flag.
#define	DMAMUX_CFR_CSOF3_Pos   (3U)
#define	DMAMUX_CFR_CSOF3_Msk   (0x1UL << DMAMUX_CFR_CSOF3_Pos)
	0x00000008
#define	DMAMUX_CFR_CSOF3   DMAMUX_CFR_CSOF3_Msk
	Channel 3 Clear synchronization overrun event flag.
#define	DMAMUX_CFR_CSOF4_Pos   (4U)
#define	DMAMUX_CFR_CSOF4_Msk   (0x1UL << DMAMUX_CFR_CSOF4_Pos)
	0x00000010
#define	DMAMUX_CFR_CSOF4   DMAMUX_CFR_CSOF4_Msk
	Channel 4 Clear synchronization overrun event flag.
#define	DMAMUX_CFR_CSOF5_Pos   (5U)
#define	DMAMUX_CFR_CSOF5_Msk   (0x1UL << DMAMUX_CFR_CSOF5_Pos)
	0x00000020
#define	DMAMUX_CFR_CSOF5   DMAMUX_CFR_CSOF5_Msk
	Channel 5 Clear synchronization overrun event flag.
#define	DMAMUX_CFR_CSOF6_Pos   (6U)
#define	DMAMUX_CFR_CSOF6_Msk   (0x1UL << DMAMUX_CFR_CSOF6_Pos)
	0x00000040
#define	DMAMUX_CFR_CSOF6   DMAMUX_CFR_CSOF6_Msk
	Channel 6 Clear synchronization overrun event flag.
#define	DMAMUX_CFR_CSOF7_Pos   (7U)
#define	DMAMUX_CFR_CSOF7_Msk   (0x1UL << DMAMUX_CFR_CSOF7_Pos)
	0x00000080
#define	DMAMUX_CFR_CSOF7   DMAMUX_CFR_CSOF7_Msk
	Channel 7 Clear synchronization overrun event flag.
#define	DMAMUX_CFR_CSOF8_Pos   (8U)
#define	DMAMUX_CFR_CSOF8_Msk   (0x1UL << DMAMUX_CFR_CSOF8_Pos)
	0x00000100
#define	DMAMUX_CFR_CSOF8   DMAMUX_CFR_CSOF8_Msk
	Channel 8 Clear synchronization overrun event flag.
#define	DMAMUX_CFR_CSOF9_Pos   (9U)
#define	DMAMUX_CFR_CSOF9_Msk   (0x1UL << DMAMUX_CFR_CSOF9_Pos)
	0x00000200
#define	DMAMUX_CFR_CSOF9   DMAMUX_CFR_CSOF9_Msk
	Channel 9 Clear synchronization overrun event flag.
#define	DMAMUX_CFR_CSOF10_Pos   (10U)
#define	DMAMUX_CFR_CSOF10_Msk   (0x1UL << DMAMUX_CFR_CSOF10_Pos)
	0x00000400
#define	DMAMUX_CFR_CSOF10   DMAMUX_CFR_CSOF10_Msk
	Channel 10 Clear synchronization overrun event flag.
#define	DMAMUX_CFR_CSOF11_Pos   (11U)
#define	DMAMUX_CFR_CSOF11_Msk   (0x1UL << DMAMUX_CFR_CSOF11_Pos)
	0x00000800
#define	DMAMUX_CFR_CSOF11   DMAMUX_CFR_CSOF11_Msk
	Channel 11 Clear synchronization overrun event flag.
#define	DMAMUX_CFR_CSOF12_Pos   (12U)
#define	DMAMUX_CFR_CSOF12_Msk   (0x1UL << DMAMUX_CFR_CSOF12_Pos)
	0x00001000
#define	DMAMUX_CFR_CSOF12   DMAMUX_CFR_CSOF12_Msk
	Channel 12 Clear synchronization overrun event flag.
#define	DMAMUX_CFR_CSOF13_Pos   (13U)
#define	DMAMUX_CFR_CSOF13_Msk   (0x1UL << DMAMUX_CFR_CSOF13_Pos)
	0x00002000
#define	DMAMUX_CFR_CSOF13   DMAMUX_CFR_CSOF13_Msk
	Channel 13 Clear synchronization overrun event flag.
#define	DMAMUX_CFR_CSOF14_Pos   (14U)
#define	DMAMUX_CFR_CSOF14_Msk   (0x1UL << DMAMUX_CFR_CSOF14_Pos)
	0x00004000
#define	DMAMUX_CFR_CSOF14   DMAMUX_CFR_CSOF14_Msk
	Channel 14 Clear synchronization overrun event flag.
#define	DMAMUX_CFR_CSOF15_Pos   (15U)
#define	DMAMUX_CFR_CSOF15_Msk   (0x1UL << DMAMUX_CFR_CSOF15_Pos)
	0x00008000
#define	DMAMUX_CFR_CSOF15   DMAMUX_CFR_CSOF15_Msk
	Channel 15 Clear synchronization overrun event flag.
#define	DMAMUX_RGxCR_SIG_ID_Pos   (0U)
#define	DMAMUX_RGxCR_SIG_ID_Msk   (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)
	0x0000001F
#define	DMAMUX_RGxCR_SIG_ID   DMAMUX_RGxCR_SIG_ID_Msk
	Signal identification.
#define	DMAMUX_RGxCR_SIG_ID_0   (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)
	0x00000001
#define	DMAMUX_RGxCR_SIG_ID_1   (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)
	0x00000002
#define	DMAMUX_RGxCR_SIG_ID_2   (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)
	0x00000004
#define	DMAMUX_RGxCR_SIG_ID_3   (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)
	0x00000008
#define	DMAMUX_RGxCR_SIG_ID_4   (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)
	0x00000010
#define	DMAMUX_RGxCR_OIE_Pos   (8U)
#define	DMAMUX_RGxCR_OIE_Msk   (0x1UL << DMAMUX_RGxCR_OIE_Pos)
	0x00000100
#define	DMAMUX_RGxCR_OIE   DMAMUX_RGxCR_OIE_Msk
	Trigger overrun interrupt enable.
#define	DMAMUX_RGxCR_GE_Pos   (16U)
#define	DMAMUX_RGxCR_GE_Msk   (0x1UL << DMAMUX_RGxCR_GE_Pos)
	0x00010000
#define	DMAMUX_RGxCR_GE   DMAMUX_RGxCR_GE_Msk
	DMA request generator enable.
#define	DMAMUX_RGxCR_GPOL_Pos   (17U)
#define	DMAMUX_RGxCR_GPOL_Msk   (0x3UL << DMAMUX_RGxCR_GPOL_Pos)
	0x00060000
#define	DMAMUX_RGxCR_GPOL   DMAMUX_RGxCR_GPOL_Msk
	DMA request generator trigger polarity.
#define	DMAMUX_RGxCR_GPOL_0   (0x1UL << DMAMUX_RGxCR_GPOL_Pos)
	0x00020000
#define	DMAMUX_RGxCR_GPOL_1   (0x2UL << DMAMUX_RGxCR_GPOL_Pos)
	0x00040000
#define	DMAMUX_RGxCR_GNBREQ_Pos   (19U)
#define	DMAMUX_RGxCR_GNBREQ_Msk   (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)
	0x00F80000
#define	DMAMUX_RGxCR_GNBREQ   DMAMUX_RGxCR_GNBREQ_Msk
	Number of DMA requests to be generated.
#define	DMAMUX_RGxCR_GNBREQ_0   (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)
	0x00080000
#define	DMAMUX_RGxCR_GNBREQ_1   (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)
	0x00100000
#define	DMAMUX_RGxCR_GNBREQ_2   (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)
	0x00200000
#define	DMAMUX_RGxCR_GNBREQ_3   (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)
	0x00400000
#define	DMAMUX_RGxCR_GNBREQ_4   (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)
	0x00800000
#define	DMAMUX_RGSR_OF0_Pos   (0U)
#define	DMAMUX_RGSR_OF0_Msk   (0x1UL << DMAMUX_RGSR_OF0_Pos)
	0x00000001
#define	DMAMUX_RGSR_OF0   DMAMUX_RGSR_OF0_Msk
	Request generator channel 0 Trigger overrun event flag.
#define	DMAMUX_RGSR_OF1_Pos   (1U)
#define	DMAMUX_RGSR_OF1_Msk   (0x1UL << DMAMUX_RGSR_OF1_Pos)
	0x00000002
#define	DMAMUX_RGSR_OF1   DMAMUX_RGSR_OF1_Msk
	Request generator channel 1 Trigger overrun event flag.
#define	DMAMUX_RGSR_OF2_Pos   (2U)
#define	DMAMUX_RGSR_OF2_Msk   (0x1UL << DMAMUX_RGSR_OF2_Pos)
	0x00000004
#define	DMAMUX_RGSR_OF2   DMAMUX_RGSR_OF2_Msk
	Request generator channel 2 Trigger overrun event flag.
#define	DMAMUX_RGSR_OF3_Pos   (3U)
#define	DMAMUX_RGSR_OF3_Msk   (0x1UL << DMAMUX_RGSR_OF3_Pos)
	0x00000008
#define	DMAMUX_RGSR_OF3   DMAMUX_RGSR_OF3_Msk
	Request generator channel 3 Trigger overrun event flag.
#define	DMAMUX_RGSR_OF4_Pos   (4U)
#define	DMAMUX_RGSR_OF4_Msk   (0x1UL << DMAMUX_RGSR_OF4_Pos)
	0x00000010
#define	DMAMUX_RGSR_OF4   DMAMUX_RGSR_OF4_Msk
	Request generator channel 4 Trigger overrun event flag.
#define	DMAMUX_RGSR_OF5_Pos   (5U)
#define	DMAMUX_RGSR_OF5_Msk   (0x1UL << DMAMUX_RGSR_OF5_Pos)
	0x00000020
#define	DMAMUX_RGSR_OF5   DMAMUX_RGSR_OF5_Msk
	Request generator channel 5 Trigger overrun event flag.
#define	DMAMUX_RGSR_OF6_Pos   (6U)
#define	DMAMUX_RGSR_OF6_Msk   (0x1UL << DMAMUX_RGSR_OF6_Pos)
	0x00000040
#define	DMAMUX_RGSR_OF6   DMAMUX_RGSR_OF6_Msk
	Request generator channel 6 Trigger overrun event flag.
#define	DMAMUX_RGSR_OF7_Pos   (7U)
#define	DMAMUX_RGSR_OF7_Msk   (0x1UL << DMAMUX_RGSR_OF7_Pos)
	0x00000080
#define	DMAMUX_RGSR_OF7   DMAMUX_RGSR_OF7_Msk
	Request generator channel 7 Trigger overrun event flag.
#define	DMAMUX_RGCFR_COF0_Pos   (0U)
#define	DMAMUX_RGCFR_COF0_Msk   (0x1UL << DMAMUX_RGCFR_COF0_Pos)
	0x00000001
#define	DMAMUX_RGCFR_COF0   DMAMUX_RGCFR_COF0_Msk
	Request generator channel 0 Clear trigger overrun event flag.
#define	DMAMUX_RGCFR_COF1_Pos   (1U)
#define	DMAMUX_RGCFR_COF1_Msk   (0x1UL << DMAMUX_RGCFR_COF1_Pos)
	0x00000002
#define	DMAMUX_RGCFR_COF1   DMAMUX_RGCFR_COF1_Msk
	Request generator channel 1 Clear trigger overrun event flag.
#define	DMAMUX_RGCFR_COF2_Pos   (2U)
#define	DMAMUX_RGCFR_COF2_Msk   (0x1UL << DMAMUX_RGCFR_COF2_Pos)
	0x00000004
#define	DMAMUX_RGCFR_COF2   DMAMUX_RGCFR_COF2_Msk
	Request generator channel 2 Clear trigger overrun event flag.
#define	DMAMUX_RGCFR_COF3_Pos   (3U)
#define	DMAMUX_RGCFR_COF3_Msk   (0x1UL << DMAMUX_RGCFR_COF3_Pos)
	0x00000008
#define	DMAMUX_RGCFR_COF3   DMAMUX_RGCFR_COF3_Msk
	Request generator channel 3 Clear trigger overrun event flag.
#define	DMAMUX_RGCFR_COF4_Pos   (4U)
#define	DMAMUX_RGCFR_COF4_Msk   (0x1UL << DMAMUX_RGCFR_COF4_Pos)
	0x00000010
#define	DMAMUX_RGCFR_COF4   DMAMUX_RGCFR_COF4_Msk
	Request generator channel 4 Clear trigger overrun event flag.
#define	DMAMUX_RGCFR_COF5_Pos   (5U)
#define	DMAMUX_RGCFR_COF5_Msk   (0x1UL << DMAMUX_RGCFR_COF5_Pos)
	0x00000020
#define	DMAMUX_RGCFR_COF5   DMAMUX_RGCFR_COF5_Msk
	Request generator channel 5 Clear trigger overrun event flag.
#define	DMAMUX_RGCFR_COF6_Pos   (6U)
#define	DMAMUX_RGCFR_COF6_Msk   (0x1UL << DMAMUX_RGCFR_COF6_Pos)
	0x00000040
#define	DMAMUX_RGCFR_COF6   DMAMUX_RGCFR_COF6_Msk
	Request generator channel 6 Clear trigger overrun event flag.
#define	DMAMUX_RGCFR_COF7_Pos   (7U)
#define	DMAMUX_RGCFR_COF7_Msk   (0x1UL << DMAMUX_RGCFR_COF7_Pos)
	0x00000080
#define	DMAMUX_RGCFR_COF7   DMAMUX_RGCFR_COF7_Msk
	Request generator channel 7 Clear trigger overrun event flag.
#define	DMA2D_CR_START_Pos   (0U)
#define	DMA2D_CR_START_Msk   (0x1UL << DMA2D_CR_START_Pos)
	0x00000001
#define	DMA2D_CR_START   DMA2D_CR_START_Msk
	Start transfer.
#define	DMA2D_CR_SUSP_Pos   (1U)
#define	DMA2D_CR_SUSP_Msk   (0x1UL << DMA2D_CR_SUSP_Pos)
	0x00000002
#define	DMA2D_CR_SUSP   DMA2D_CR_SUSP_Msk
	Suspend transfer.
#define	DMA2D_CR_ABORT_Pos   (2U)
#define	DMA2D_CR_ABORT_Msk   (0x1UL << DMA2D_CR_ABORT_Pos)
	0x00000004
#define	DMA2D_CR_ABORT   DMA2D_CR_ABORT_Msk
	Abort transfer.
#define	DMA2D_CR_LOM_Pos   (6U)
#define	DMA2D_CR_LOM_Msk   (0x1UL << DMA2D_CR_LOM_Pos)
	0x00000040
#define	DMA2D_CR_LOM   DMA2D_CR_LOM_Msk
	Line Offset Mode.
#define	DMA2D_CR_TEIE_Pos   (8U)
#define	DMA2D_CR_TEIE_Msk   (0x1UL << DMA2D_CR_TEIE_Pos)
	0x00000100
#define	DMA2D_CR_TEIE   DMA2D_CR_TEIE_Msk
	Transfer Error Interrupt Enable.
#define	DMA2D_CR_TCIE_Pos   (9U)
#define	DMA2D_CR_TCIE_Msk   (0x1UL << DMA2D_CR_TCIE_Pos)
	0x00000200
#define	DMA2D_CR_TCIE   DMA2D_CR_TCIE_Msk
	Transfer Complete Interrupt Enable.
#define	DMA2D_CR_TWIE_Pos   (10U)
#define	DMA2D_CR_TWIE_Msk   (0x1UL << DMA2D_CR_TWIE_Pos)
	0x00000400
#define	DMA2D_CR_TWIE   DMA2D_CR_TWIE_Msk
	Transfer Watermark Interrupt Enable.
#define	DMA2D_CR_CAEIE_Pos   (11U)
#define	DMA2D_CR_CAEIE_Msk   (0x1UL << DMA2D_CR_CAEIE_Pos)
	0x00000800
#define	DMA2D_CR_CAEIE   DMA2D_CR_CAEIE_Msk
	CLUT Access Error Interrupt Enable.
#define	DMA2D_CR_CTCIE_Pos   (12U)
#define	DMA2D_CR_CTCIE_Msk   (0x1UL << DMA2D_CR_CTCIE_Pos)
	0x00001000
#define	DMA2D_CR_CTCIE   DMA2D_CR_CTCIE_Msk
	CLUT Transfer Complete Interrupt Enable.
#define	DMA2D_CR_CEIE_Pos   (13U)
#define	DMA2D_CR_CEIE_Msk   (0x1UL << DMA2D_CR_CEIE_Pos)
	0x00002000
#define	DMA2D_CR_CEIE   DMA2D_CR_CEIE_Msk
	Configuration Error Interrupt Enable.
#define	DMA2D_CR_MODE_Pos   (16U)
#define	DMA2D_CR_MODE_Msk   (0x7UL << DMA2D_CR_MODE_Pos)
	0x00070000
#define	DMA2D_CR_MODE   DMA2D_CR_MODE_Msk
	DMA2D Mode[2:0].
#define	DMA2D_CR_MODE_0   (0x1UL << DMA2D_CR_MODE_Pos)
	0x00010000
#define	DMA2D_CR_MODE_1   (0x2UL << DMA2D_CR_MODE_Pos)
	0x00020000
#define	DMA2D_CR_MODE_2   (0x4UL << DMA2D_CR_MODE_Pos)
	0x00040000
#define	DMA2D_ISR_TEIF_Pos   (0U)
#define	DMA2D_ISR_TEIF_Msk   (0x1UL << DMA2D_ISR_TEIF_Pos)
	0x00000001
#define	DMA2D_ISR_TEIF   DMA2D_ISR_TEIF_Msk
	Transfer Error Interrupt Flag.
#define	DMA2D_ISR_TCIF_Pos   (1U)
#define	DMA2D_ISR_TCIF_Msk   (0x1UL << DMA2D_ISR_TCIF_Pos)
	0x00000002
#define	DMA2D_ISR_TCIF   DMA2D_ISR_TCIF_Msk
	Transfer Complete Interrupt Flag.
#define	DMA2D_ISR_TWIF_Pos   (2U)
#define	DMA2D_ISR_TWIF_Msk   (0x1UL << DMA2D_ISR_TWIF_Pos)
	0x00000004
#define	DMA2D_ISR_TWIF   DMA2D_ISR_TWIF_Msk
	Transfer Watermark Interrupt Flag.
#define	DMA2D_ISR_CAEIF_Pos   (3U)
#define	DMA2D_ISR_CAEIF_Msk   (0x1UL << DMA2D_ISR_CAEIF_Pos)
	0x00000008
#define	DMA2D_ISR_CAEIF   DMA2D_ISR_CAEIF_Msk
	CLUT Access Error Interrupt Flag.
#define	DMA2D_ISR_CTCIF_Pos   (4U)
#define	DMA2D_ISR_CTCIF_Msk   (0x1UL << DMA2D_ISR_CTCIF_Pos)
	0x00000010
#define	DMA2D_ISR_CTCIF   DMA2D_ISR_CTCIF_Msk
	CLUT Transfer Complete Interrupt Flag.
#define	DMA2D_ISR_CEIF_Pos   (5U)
#define	DMA2D_ISR_CEIF_Msk   (0x1UL << DMA2D_ISR_CEIF_Pos)
	0x00000020
#define	DMA2D_ISR_CEIF   DMA2D_ISR_CEIF_Msk
	Configuration Error Interrupt Flag.
#define	DMA2D_IFCR_CTEIF_Pos   (0U)
#define	DMA2D_IFCR_CTEIF_Msk   (0x1UL << DMA2D_IFCR_CTEIF_Pos)
	0x00000001
#define	DMA2D_IFCR_CTEIF   DMA2D_IFCR_CTEIF_Msk
	Clears Transfer Error Interrupt Flag.
#define	DMA2D_IFCR_CTCIF_Pos   (1U)
#define	DMA2D_IFCR_CTCIF_Msk   (0x1UL << DMA2D_IFCR_CTCIF_Pos)
	0x00000002
#define	DMA2D_IFCR_CTCIF   DMA2D_IFCR_CTCIF_Msk
	Clears Transfer Complete Interrupt Flag.
#define	DMA2D_IFCR_CTWIF_Pos   (2U)
#define	DMA2D_IFCR_CTWIF_Msk   (0x1UL << DMA2D_IFCR_CTWIF_Pos)
	0x00000004
#define	DMA2D_IFCR_CTWIF   DMA2D_IFCR_CTWIF_Msk
	Clears Transfer Watermark Interrupt Flag.
#define	DMA2D_IFCR_CAECIF_Pos   (3U)
#define	DMA2D_IFCR_CAECIF_Msk   (0x1UL << DMA2D_IFCR_CAECIF_Pos)
	0x00000008
#define	DMA2D_IFCR_CAECIF   DMA2D_IFCR_CAECIF_Msk
	Clears CLUT Access Error Interrupt Flag.
#define	DMA2D_IFCR_CCTCIF_Pos   (4U)
#define	DMA2D_IFCR_CCTCIF_Msk   (0x1UL << DMA2D_IFCR_CCTCIF_Pos)
	0x00000010
#define	DMA2D_IFCR_CCTCIF   DMA2D_IFCR_CCTCIF_Msk
	Clears CLUT Transfer Complete Interrupt Flag.
#define	DMA2D_IFCR_CCEIF_Pos   (5U)
#define	DMA2D_IFCR_CCEIF_Msk   (0x1UL << DMA2D_IFCR_CCEIF_Pos)
	0x00000020
#define	DMA2D_IFCR_CCEIF   DMA2D_IFCR_CCEIF_Msk
	Clears Configuration Error Interrupt Flag.
#define	DMA2D_FGMAR_MA_Pos   (0U)
#define	DMA2D_FGMAR_MA_Msk   (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)
	0xFFFFFFFF
#define	DMA2D_FGMAR_MA   DMA2D_FGMAR_MA_Msk
	Foreground Memory Address.
#define	DMA2D_FGOR_LO_Pos   (0U)
#define	DMA2D_FGOR_LO_Msk   (0xFFFFUL << DMA2D_FGOR_LO_Pos)
	0x0000FFFF
#define	DMA2D_FGOR_LO   DMA2D_FGOR_LO_Msk
	Line Offset.
#define	DMA2D_BGMAR_MA_Pos   (0U)
#define	DMA2D_BGMAR_MA_Msk   (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)
	0xFFFFFFFF
#define	DMA2D_BGMAR_MA   DMA2D_BGMAR_MA_Msk
	Background Memory Address.
#define	DMA2D_BGOR_LO_Pos   (0U)
#define	DMA2D_BGOR_LO_Msk   (0xFFFFUL << DMA2D_BGOR_LO_Pos)
	0x0000FFFF
#define	DMA2D_BGOR_LO   DMA2D_BGOR_LO_Msk
	Line Offset.
#define	DMA2D_FGPFCCR_CM_Pos   (0U)
#define	DMA2D_FGPFCCR_CM_Msk   (0xFUL << DMA2D_FGPFCCR_CM_Pos)
	0x0000000F
#define	DMA2D_FGPFCCR_CM   DMA2D_FGPFCCR_CM_Msk
	Input color mode CM[3:0].
#define	DMA2D_FGPFCCR_CM_0   (0x1UL << DMA2D_FGPFCCR_CM_Pos)
	0x00000001
#define	DMA2D_FGPFCCR_CM_1   (0x2UL << DMA2D_FGPFCCR_CM_Pos)
	0x00000002
#define	DMA2D_FGPFCCR_CM_2   (0x4UL << DMA2D_FGPFCCR_CM_Pos)
	0x00000004
#define	DMA2D_FGPFCCR_CM_3   (0x8UL << DMA2D_FGPFCCR_CM_Pos)
	0x00000008
#define	DMA2D_FGPFCCR_CCM_Pos   (4U)
#define	DMA2D_FGPFCCR_CCM_Msk   (0x1UL << DMA2D_FGPFCCR_CCM_Pos)
	0x00000010
#define	DMA2D_FGPFCCR_CCM   DMA2D_FGPFCCR_CCM_Msk
	CLUT Color mode.
#define	DMA2D_FGPFCCR_START_Pos   (5U)
#define	DMA2D_FGPFCCR_START_Msk   (0x1UL << DMA2D_FGPFCCR_START_Pos)
	0x00000020
#define	DMA2D_FGPFCCR_START   DMA2D_FGPFCCR_START_Msk
	Start.
#define	DMA2D_FGPFCCR_CS_Pos   (8U)
#define	DMA2D_FGPFCCR_CS_Msk   (0xFFUL << DMA2D_FGPFCCR_CS_Pos)
	0x0000FF00
#define	DMA2D_FGPFCCR_CS   DMA2D_FGPFCCR_CS_Msk
	CLUT size.
#define	DMA2D_FGPFCCR_AM_Pos   (16U)
#define	DMA2D_FGPFCCR_AM_Msk   (0x3UL << DMA2D_FGPFCCR_AM_Pos)
	0x00030000
#define	DMA2D_FGPFCCR_AM   DMA2D_FGPFCCR_AM_Msk
	Alpha mode AM[1:0].
#define	DMA2D_FGPFCCR_AM_0   (0x1UL << DMA2D_FGPFCCR_AM_Pos)
	0x00010000
#define	DMA2D_FGPFCCR_AM_1   (0x2UL << DMA2D_FGPFCCR_AM_Pos)
	0x00020000
#define	DMA2D_FGPFCCR_CSS_Pos   (18U)
#define	DMA2D_FGPFCCR_CSS_Msk   (0x3UL << DMA2D_FGPFCCR_CSS_Pos)
	0x000C0000
#define	DMA2D_FGPFCCR_CSS   DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sampling */
#define	DMA2D_FGPFCCR_CSS_0   (0x1UL << DMA2D_FGPFCCR_CSS_Pos)
	0x00040000
#define	DMA2D_FGPFCCR_CSS_1   (0x2UL << DMA2D_FGPFCCR_CSS_Pos)
	0x00080000
#define	DMA2D_FGPFCCR_AI_Pos   (20U)
#define	DMA2D_FGPFCCR_AI_Msk   (0x1UL << DMA2D_FGPFCCR_AI_Pos)
	0x00100000
#define	DMA2D_FGPFCCR_AI   DMA2D_FGPFCCR_AI_Msk
	Foreground Input Alpha Inverted.
#define	DMA2D_FGPFCCR_RBS_Pos   (21U)
#define	DMA2D_FGPFCCR_RBS_Msk   (0x1UL << DMA2D_FGPFCCR_RBS_Pos)
	0x00200000
#define	DMA2D_FGPFCCR_RBS   DMA2D_FGPFCCR_RBS_Msk
	Foreground Input Red Blue Swap.
#define	DMA2D_FGPFCCR_ALPHA_Pos   (24U)
#define	DMA2D_FGPFCCR_ALPHA_Msk   (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)
	0xFF000000
#define	DMA2D_FGPFCCR_ALPHA   DMA2D_FGPFCCR_ALPHA_Msk
	Alpha value.
#define	DMA2D_FGCOLR_BLUE_Pos   (0U)
#define	DMA2D_FGCOLR_BLUE_Msk   (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)
	0x000000FF
#define	DMA2D_FGCOLR_BLUE   DMA2D_FGCOLR_BLUE_Msk
	Foreground Blue Value.
#define	DMA2D_FGCOLR_GREEN_Pos   (8U)
#define	DMA2D_FGCOLR_GREEN_Msk   (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)
	0x0000FF00
#define	DMA2D_FGCOLR_GREEN   DMA2D_FGCOLR_GREEN_Msk
	Foreground Green Value.
#define	DMA2D_FGCOLR_RED_Pos   (16U)
#define	DMA2D_FGCOLR_RED_Msk   (0xFFUL << DMA2D_FGCOLR_RED_Pos)
	0x00FF0000
#define	DMA2D_FGCOLR_RED   DMA2D_FGCOLR_RED_Msk
	Foreground Red Value.
#define	DMA2D_BGPFCCR_CM_Pos   (0U)
#define	DMA2D_BGPFCCR_CM_Msk   (0xFUL << DMA2D_BGPFCCR_CM_Pos)
	0x0000000F
#define	DMA2D_BGPFCCR_CM   DMA2D_BGPFCCR_CM_Msk
	Input color mode CM[3:0].
#define	DMA2D_BGPFCCR_CM_0   (0x1UL << DMA2D_BGPFCCR_CM_Pos)
	0x00000001
#define	DMA2D_BGPFCCR_CM_1   (0x2UL << DMA2D_BGPFCCR_CM_Pos)
	0x00000002
#define	DMA2D_BGPFCCR_CM_2   (0x4UL << DMA2D_BGPFCCR_CM_Pos)
	0x00000004
#define	DMA2D_BGPFCCR_CM_3   (0x8UL << DMA2D_BGPFCCR_CM_Pos)
	0x00000008
#define	DMA2D_BGPFCCR_CCM_Pos   (4U)
#define	DMA2D_BGPFCCR_CCM_Msk   (0x1UL << DMA2D_BGPFCCR_CCM_Pos)
	0x00000010
#define	DMA2D_BGPFCCR_CCM   DMA2D_BGPFCCR_CCM_Msk
	CLUT Color mode.
#define	DMA2D_BGPFCCR_START_Pos   (5U)
#define	DMA2D_BGPFCCR_START_Msk   (0x1UL << DMA2D_BGPFCCR_START_Pos)
	0x00000020
#define	DMA2D_BGPFCCR_START   DMA2D_BGPFCCR_START_Msk
	Start.
#define	DMA2D_BGPFCCR_CS_Pos   (8U)
#define	DMA2D_BGPFCCR_CS_Msk   (0xFFUL << DMA2D_BGPFCCR_CS_Pos)
	0x0000FF00
#define	DMA2D_BGPFCCR_CS   DMA2D_BGPFCCR_CS_Msk
	CLUT size.
#define	DMA2D_BGPFCCR_AM_Pos   (16U)
#define	DMA2D_BGPFCCR_AM_Msk   (0x3UL << DMA2D_BGPFCCR_AM_Pos)
	0x00030000
#define	DMA2D_BGPFCCR_AM   DMA2D_BGPFCCR_AM_Msk
	Alpha mode AM[1:0].
#define	DMA2D_BGPFCCR_AM_0   (0x1UL << DMA2D_BGPFCCR_AM_Pos)
	0x00010000
#define	DMA2D_BGPFCCR_AM_1   (0x2UL << DMA2D_BGPFCCR_AM_Pos)
	0x00020000
#define	DMA2D_BGPFCCR_AI_Pos   (20U)
#define	DMA2D_BGPFCCR_AI_Msk   (0x1UL << DMA2D_BGPFCCR_AI_Pos)
	0x00100000
#define	DMA2D_BGPFCCR_AI   DMA2D_BGPFCCR_AI_Msk
	background Input Alpha Inverted
#define	DMA2D_BGPFCCR_RBS_Pos   (21U)
#define	DMA2D_BGPFCCR_RBS_Msk   (0x1UL << DMA2D_BGPFCCR_RBS_Pos)
	0x00200000
#define	DMA2D_BGPFCCR_RBS   DMA2D_BGPFCCR_RBS_Msk
	Background Input Red Blue Swap.
#define	DMA2D_BGPFCCR_ALPHA_Pos   (24U)
#define	DMA2D_BGPFCCR_ALPHA_Msk   (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)
	0xFF000000
#define	DMA2D_BGPFCCR_ALPHA   DMA2D_BGPFCCR_ALPHA_Msk
	background Input Alpha value
#define	DMA2D_BGCOLR_BLUE_Pos   (0U)
#define	DMA2D_BGCOLR_BLUE_Msk   (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)
	0x000000FF
#define	DMA2D_BGCOLR_BLUE   DMA2D_BGCOLR_BLUE_Msk
	Background Blue Value.
#define	DMA2D_BGCOLR_GREEN_Pos   (8U)
#define	DMA2D_BGCOLR_GREEN_Msk   (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)
	0x0000FF00
#define	DMA2D_BGCOLR_GREEN   DMA2D_BGCOLR_GREEN_Msk
	Background Green Value.
#define	DMA2D_BGCOLR_RED_Pos   (16U)
#define	DMA2D_BGCOLR_RED_Msk   (0xFFUL << DMA2D_BGCOLR_RED_Pos)
	0x00FF0000
#define	DMA2D_BGCOLR_RED   DMA2D_BGCOLR_RED_Msk
	Background Red Value.
#define	DMA2D_FGCMAR_MA_Pos   (0U)
#define	DMA2D_FGCMAR_MA_Msk   (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)
	0xFFFFFFFF
#define	DMA2D_FGCMAR_MA   DMA2D_FGCMAR_MA_Msk
	Foreground CLUT Memory Address.
#define	DMA2D_BGCMAR_MA_Pos   (0U)
#define	DMA2D_BGCMAR_MA_Msk   (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)
	0xFFFFFFFF
#define	DMA2D_BGCMAR_MA   DMA2D_BGCMAR_MA_Msk
	Background CLUT Memory Address.
#define	DMA2D_OPFCCR_CM_Pos   (0U)
#define	DMA2D_OPFCCR_CM_Msk   (0x7UL << DMA2D_OPFCCR_CM_Pos)
	0x00000007
#define	DMA2D_OPFCCR_CM   DMA2D_OPFCCR_CM_Msk
	Output Color mode CM[2:0].
#define	DMA2D_OPFCCR_CM_0   (0x1UL << DMA2D_OPFCCR_CM_Pos)
	0x00000001
#define	DMA2D_OPFCCR_CM_1   (0x2UL << DMA2D_OPFCCR_CM_Pos)
	0x00000002
#define	DMA2D_OPFCCR_CM_2   (0x4UL << DMA2D_OPFCCR_CM_Pos)
	0x00000004
#define	DMA2D_OPFCCR_SB_Pos   (8U)
#define	DMA2D_OPFCCR_SB_Msk   (0x1UL << DMA2D_OPFCCR_SB_Pos)
	0x00000100
#define	DMA2D_OPFCCR_SB   DMA2D_OPFCCR_SB_Msk
	Swap Bytes.
#define	DMA2D_OPFCCR_AI_Pos   (20U)
#define	DMA2D_OPFCCR_AI_Msk   (0x1UL << DMA2D_OPFCCR_AI_Pos)
	0x00100000
#define	DMA2D_OPFCCR_AI   DMA2D_OPFCCR_AI_Msk
	Output Alpha Inverted.
#define	DMA2D_OPFCCR_RBS_Pos   (21U)
#define	DMA2D_OPFCCR_RBS_Msk   (0x1UL << DMA2D_OPFCCR_RBS_Pos)
	0x00200000
#define	DMA2D_OPFCCR_RBS   DMA2D_OPFCCR_RBS_Msk
	Output Red Blue Swap.
#define	DMA2D_OCOLR_BLUE_1_Pos   (0U)
	<Mode_ARGB8888/RGB888
#define	DMA2D_OCOLR_BLUE_1_Msk   (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos) /*0x000000FFU*/
#define	DMA2D_OCOLR_BLUE_1   DMA2D_OCOLR_BLUE_1_Msk
	Output BLUE Value.
#define	DMA2D_OCOLR_GREEN_1_Pos   (8U)
#define	DMA2D_OCOLR_GREEN_1_Msk   (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos) /*0x0000FF00U)*/
#define	DMA2D_OCOLR_GREEN_1   DMA2D_OCOLR_GREEN_1_Msk
	Output GREEN Value.
#define	DMA2D_OCOLR_RED_1_Pos   (16U)
#define	DMA2D_OCOLR_RED_1_Msk   (0xFFUL << DMA2D_OCOLR_RED_1_Pos) /*0x00FF0000U */
#define	DMA2D_OCOLR_RED_1   DMA2D_OCOLR_RED_1_Msk
	Output Red Value.
#define	DMA2D_OCOLR_ALPHA_1_Pos   (24U)
#define	DMA2D_OCOLR_ALPHA_1_Msk   (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos) /*0xFF000000U*/
#define	DMA2D_OCOLR_ALPHA_1   DMA2D_OCOLR_ALPHA_1_Msk
	Output Alpha Channel Value.
#define	DMA2D_OCOLR_BLUE_2_Pos   (0U)
#define	DMA2D_OCOLR_BLUE_2_Msk   (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos) /*0x0000001FU*/
#define	DMA2D_OCOLR_BLUE_2   DMA2D_OCOLR_BLUE_2_Msk
	Output BLUE Value.
#define	DMA2D_OCOLR_GREEN_2_Pos   (5U)
#define	DMA2D_OCOLR_GREEN_2_Msk   (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos) /* 0x000007E0U */
#define	DMA2D_OCOLR_GREEN_2   DMA2D_OCOLR_GREEN_2_Msk
	Output GREEN Value.
#define	DMA2D_OCOLR_RED_2_Pos   (11U)
#define	DMA2D_OCOLR_RED_2_Msk   (0xF8UL<<DMA2D_OCOLR_RED_2_Pos) /*0x0000F800U*/
#define	DMA2D_OCOLR_RED_2   DMA2D_OCOLR_RED_2_Msk
	Output Red Value.
#define	DMA2D_OCOLR_BLUE_3_Pos   (0U)
#define	DMA2D_OCOLR_BLUE_3_Msk   (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos) /*0x0000001FU*/
#define	DMA2D_OCOLR_BLUE_3   DMA2D_OCOLR_BLUE_3_Msk
	Output BLUE Value.
#define	DMA2D_OCOLR_GREEN_3_Pos   (5U)
#define	DMA2D_OCOLR_GREEN_3_Msk   (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos) /*0x000003E0U*/
#define	DMA2D_OCOLR_GREEN_3   DMA2D_OCOLR_GREEN_3_Msk
	Output GREEN Value.
#define	DMA2D_OCOLR_RED_3_Pos   (10U)
#define	DMA2D_OCOLR_RED_3_Msk   (0x7CUL << DMA2D_OCOLR_RED_3_Pos) /* 0x00007C00U*/
#define	DMA2D_OCOLR_RED_3   DMA2D_OCOLR_RED_3_Msk
	Output Red Value.
#define	DMA2D_OCOLR_ALPHA_3_Pos   (15U)
#define	DMA2D_OCOLR_ALPHA_3_Msk   (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos) /*0x00008000U*/
#define	DMA2D_OCOLR_ALPHA_3   DMA2D_OCOLR_ALPHA_3_Msk
	Output Alpha Channel Value.
#define	DMA2D_OCOLR_BLUE_4_Pos   (0U)
#define	DMA2D_OCOLR_BLUE_4_Msk   (0xFUL << DMA2D_OCOLR_BLUE_4_Pos) /*0x0000000FU*/
#define	DMA2D_OCOLR_BLUE_4   DMA2D_OCOLR_BLUE_4_Msk
	Output BLUE Value.
#define	DMA2D_OCOLR_GREEN_4_Pos   (4U)
#define	DMA2D_OCOLR_GREEN_4_Msk   (0xFUL << DMA2D_OCOLR_GREEN_4_Pos) /*0x000000F0U*/
#define	DMA2D_OCOLR_GREEN_4   DMA2D_OCOLR_GREEN_4_Msk
	Output GREEN Value.
#define	DMA2D_OCOLR_RED_4_Pos   (8U)
#define	DMA2D_OCOLR_RED_4_Msk   (0xFUL << DMA2D_OCOLR_RED_4_Pos) /*0x00000F00U*/
#define	DMA2D_OCOLR_RED_4   DMA2D_OCOLR_RED_4_Msk
	Output Red Value.
#define	DMA2D_OCOLR_ALPHA_4_Pos   (12U)
#define	DMA2D_OCOLR_ALPHA_4_Msk   (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos) /*0x0000F000U*/
#define	DMA2D_OCOLR_ALPHA_4   DMA2D_OCOLR_ALPHA_4_Msk
	Output Alpha Channel Value.
#define	DMA2D_OMAR_MA_Pos   (0U)
#define	DMA2D_OMAR_MA_Msk   (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)
	0xFFFFFFFF
#define	DMA2D_OMAR_MA   DMA2D_OMAR_MA_Msk
	Output Memory Address.
#define	DMA2D_OOR_LO_Pos   (0U)
#define	DMA2D_OOR_LO_Msk   (0xFFFFUL << DMA2D_OOR_LO_Pos)
	0x0000FFFF
#define	DMA2D_OOR_LO   DMA2D_OOR_LO_Msk
	Output Line Offset.
#define	DMA2D_NLR_NL_Pos   (0U)
#define	DMA2D_NLR_NL_Msk   (0xFFFFUL << DMA2D_NLR_NL_Pos)
	0x0000FFFF
#define	DMA2D_NLR_NL   DMA2D_NLR_NL_Msk
	Number of Lines.
#define	DMA2D_NLR_PL_Pos   (16U)
#define	DMA2D_NLR_PL_Msk   (0x3FFFUL << DMA2D_NLR_PL_Pos)
	0x3FFF0000
#define	DMA2D_NLR_PL   DMA2D_NLR_PL_Msk
	Pixel per Lines.
#define	DMA2D_LWR_LW_Pos   (0U)
#define	DMA2D_LWR_LW_Msk   (0xFFFFUL << DMA2D_LWR_LW_Pos)
	0x0000FFFF
#define	DMA2D_LWR_LW   DMA2D_LWR_LW_Msk
	Line Watermark.
#define	DMA2D_AMTCR_EN_Pos   (0U)
#define	DMA2D_AMTCR_EN_Msk   (0x1UL << DMA2D_AMTCR_EN_Pos)
	0x00000001
#define	DMA2D_AMTCR_EN   DMA2D_AMTCR_EN_Msk
	Enable.
#define	DMA2D_AMTCR_DT_Pos   (8U)
#define	DMA2D_AMTCR_DT_Msk   (0xFFUL << DMA2D_AMTCR_DT_Pos)
	0x0000FF00
#define	DMA2D_AMTCR_DT   DMA2D_AMTCR_DT_Msk
	Dead Time.
#define	EXTI_RTSR1_TR_Pos   (0U)
#define	EXTI_RTSR1_TR_Msk   (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)
	0x003FFFFF
#define	EXTI_RTSR1_TR   EXTI_RTSR1_TR_Msk
	Rising trigger event configuration bit.
#define	EXTI_RTSR1_TR0_Pos   (0U)
#define	EXTI_RTSR1_TR0_Msk   (0x1UL << EXTI_RTSR1_TR0_Pos)
	0x00000001
#define	EXTI_RTSR1_TR0   EXTI_RTSR1_TR0_Msk
	Rising trigger event configuration bit of line 0.
#define	EXTI_RTSR1_TR1_Pos   (1U)
#define	EXTI_RTSR1_TR1_Msk   (0x1UL << EXTI_RTSR1_TR1_Pos)
	0x00000002
#define	EXTI_RTSR1_TR1   EXTI_RTSR1_TR1_Msk
	Rising trigger event configuration bit of line 1.
#define	EXTI_RTSR1_TR2_Pos   (2U)
#define	EXTI_RTSR1_TR2_Msk   (0x1UL << EXTI_RTSR1_TR2_Pos)
	0x00000004
#define	EXTI_RTSR1_TR2   EXTI_RTSR1_TR2_Msk
	Rising trigger event configuration bit of line 2.
#define	EXTI_RTSR1_TR3_Pos   (3U)
#define	EXTI_RTSR1_TR3_Msk   (0x1UL << EXTI_RTSR1_TR3_Pos)
	0x00000008
#define	EXTI_RTSR1_TR3   EXTI_RTSR1_TR3_Msk
	Rising trigger event configuration bit of line 3.
#define	EXTI_RTSR1_TR4_Pos   (4U)
#define	EXTI_RTSR1_TR4_Msk   (0x1UL << EXTI_RTSR1_TR4_Pos)
	0x00000010
#define	EXTI_RTSR1_TR4   EXTI_RTSR1_TR4_Msk
	Rising trigger event configuration bit of line 4.
#define	EXTI_RTSR1_TR5_Pos   (5U)
#define	EXTI_RTSR1_TR5_Msk   (0x1UL << EXTI_RTSR1_TR5_Pos)
	0x00000020
#define	EXTI_RTSR1_TR5   EXTI_RTSR1_TR5_Msk
	Rising trigger event configuration bit of line 5.
#define	EXTI_RTSR1_TR6_Pos   (6U)
#define	EXTI_RTSR1_TR6_Msk   (0x1UL << EXTI_RTSR1_TR6_Pos)
	0x00000040
#define	EXTI_RTSR1_TR6   EXTI_RTSR1_TR6_Msk
	Rising trigger event configuration bit of line 6.
#define	EXTI_RTSR1_TR7_Pos   (7U)
#define	EXTI_RTSR1_TR7_Msk   (0x1UL << EXTI_RTSR1_TR7_Pos)
	0x00000080
#define	EXTI_RTSR1_TR7   EXTI_RTSR1_TR7_Msk
	Rising trigger event configuration bit of line 7.
#define	EXTI_RTSR1_TR8_Pos   (8U)
#define	EXTI_RTSR1_TR8_Msk   (0x1UL << EXTI_RTSR1_TR8_Pos)
	0x00000100
#define	EXTI_RTSR1_TR8   EXTI_RTSR1_TR8_Msk
	Rising trigger event configuration bit of line 8.
#define	EXTI_RTSR1_TR9_Pos   (9U)
#define	EXTI_RTSR1_TR9_Msk   (0x1UL << EXTI_RTSR1_TR9_Pos)
	0x00000200
#define	EXTI_RTSR1_TR9   EXTI_RTSR1_TR9_Msk
	Rising trigger event configuration bit of line 9.
#define	EXTI_RTSR1_TR10_Pos   (10U)
#define	EXTI_RTSR1_TR10_Msk   (0x1UL << EXTI_RTSR1_TR10_Pos)
	0x00000400
#define	EXTI_RTSR1_TR10   EXTI_RTSR1_TR10_Msk
	Rising trigger event configuration bit of line 10.
#define	EXTI_RTSR1_TR11_Pos   (11U)
#define	EXTI_RTSR1_TR11_Msk   (0x1UL << EXTI_RTSR1_TR11_Pos)
	0x00000800
#define	EXTI_RTSR1_TR11   EXTI_RTSR1_TR11_Msk
	Rising trigger event configuration bit of line 11.
#define	EXTI_RTSR1_TR12_Pos   (12U)
#define	EXTI_RTSR1_TR12_Msk   (0x1UL << EXTI_RTSR1_TR12_Pos)
	0x00001000
#define	EXTI_RTSR1_TR12   EXTI_RTSR1_TR12_Msk
	Rising trigger event configuration bit of line 12.
#define	EXTI_RTSR1_TR13_Pos   (13U)
#define	EXTI_RTSR1_TR13_Msk   (0x1UL << EXTI_RTSR1_TR13_Pos)
	0x00002000
#define	EXTI_RTSR1_TR13   EXTI_RTSR1_TR13_Msk
	Rising trigger event configuration bit of line 13.
#define	EXTI_RTSR1_TR14_Pos   (14U)
#define	EXTI_RTSR1_TR14_Msk   (0x1UL << EXTI_RTSR1_TR14_Pos)
	0x00004000
#define	EXTI_RTSR1_TR14   EXTI_RTSR1_TR14_Msk
	Rising trigger event configuration bit of line 14.
#define	EXTI_RTSR1_TR15_Pos   (15U)
#define	EXTI_RTSR1_TR15_Msk   (0x1UL << EXTI_RTSR1_TR15_Pos)
	0x00008000
#define	EXTI_RTSR1_TR15   EXTI_RTSR1_TR15_Msk
	Rising trigger event configuration bit of line 15.
#define	EXTI_RTSR1_TR16_Pos   (16U)
#define	EXTI_RTSR1_TR16_Msk   (0x1UL << EXTI_RTSR1_TR16_Pos)
	0x00010000
#define	EXTI_RTSR1_TR16   EXTI_RTSR1_TR16_Msk
	Rising trigger event configuration bit of line 16.
#define	EXTI_RTSR1_TR17_Pos   (17U)
#define	EXTI_RTSR1_TR17_Msk   (0x1UL << EXTI_RTSR1_TR17_Pos)
	0x00020000
#define	EXTI_RTSR1_TR17   EXTI_RTSR1_TR17_Msk
	Rising trigger event configuration bit of line 17.
#define	EXTI_RTSR1_TR18_Pos   (18U)
#define	EXTI_RTSR1_TR18_Msk   (0x1UL << EXTI_RTSR1_TR18_Pos)
	0x00040000
#define	EXTI_RTSR1_TR18   EXTI_RTSR1_TR18_Msk
	Rising trigger event configuration bit of line 18.
#define	EXTI_RTSR1_TR19_Pos   (19U)
#define	EXTI_RTSR1_TR19_Msk   (0x1UL << EXTI_RTSR1_TR19_Pos)
	0x00080000
#define	EXTI_RTSR1_TR19   EXTI_RTSR1_TR19_Msk
	Rising trigger event configuration bit of line 19.
#define	EXTI_RTSR1_TR20_Pos   (20U)
#define	EXTI_RTSR1_TR20_Msk   (0x1UL << EXTI_RTSR1_TR20_Pos)
	0x00100000
#define	EXTI_RTSR1_TR20   EXTI_RTSR1_TR20_Msk
	Rising trigger event configuration bit of line 20.
#define	EXTI_RTSR1_TR21_Pos   (21U)
#define	EXTI_RTSR1_TR21_Msk   (0x1UL << EXTI_RTSR1_TR21_Pos)
	0x00200000
#define	EXTI_RTSR1_TR21   EXTI_RTSR1_TR21_Msk
	Rising trigger event configuration bit of line 21.
#define	EXTI_FTSR1_TR_Pos   (0U)
#define	EXTI_FTSR1_TR_Msk   (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)
	0x003FFFFF
#define	EXTI_FTSR1_TR   EXTI_FTSR1_TR_Msk
	Falling trigger event configuration bit.
#define	EXTI_FTSR1_TR0_Pos   (0U)
#define	EXTI_FTSR1_TR0_Msk   (0x1UL << EXTI_FTSR1_TR0_Pos)
	0x00000001
#define	EXTI_FTSR1_TR0   EXTI_FTSR1_TR0_Msk
	Falling trigger event configuration bit of line 0.
#define	EXTI_FTSR1_TR1_Pos   (1U)
#define	EXTI_FTSR1_TR1_Msk   (0x1UL << EXTI_FTSR1_TR1_Pos)
	0x00000002
#define	EXTI_FTSR1_TR1   EXTI_FTSR1_TR1_Msk
	Falling trigger event configuration bit of line 1.
#define	EXTI_FTSR1_TR2_Pos   (2U)
#define	EXTI_FTSR1_TR2_Msk   (0x1UL << EXTI_FTSR1_TR2_Pos)
	0x00000004
#define	EXTI_FTSR1_TR2   EXTI_FTSR1_TR2_Msk
	Falling trigger event configuration bit of line 2.
#define	EXTI_FTSR1_TR3_Pos   (3U)
#define	EXTI_FTSR1_TR3_Msk   (0x1UL << EXTI_FTSR1_TR3_Pos)
	0x00000008
#define	EXTI_FTSR1_TR3   EXTI_FTSR1_TR3_Msk
	Falling trigger event configuration bit of line 3.
#define	EXTI_FTSR1_TR4_Pos   (4U)
#define	EXTI_FTSR1_TR4_Msk   (0x1UL << EXTI_FTSR1_TR4_Pos)
	0x00000010
#define	EXTI_FTSR1_TR4   EXTI_FTSR1_TR4_Msk
	Falling trigger event configuration bit of line 4.
#define	EXTI_FTSR1_TR5_Pos   (5U)
#define	EXTI_FTSR1_TR5_Msk   (0x1UL << EXTI_FTSR1_TR5_Pos)
	0x00000020
#define	EXTI_FTSR1_TR5   EXTI_FTSR1_TR5_Msk
	Falling trigger event configuration bit of line 5.
#define	EXTI_FTSR1_TR6_Pos   (6U)
#define	EXTI_FTSR1_TR6_Msk   (0x1UL << EXTI_FTSR1_TR6_Pos)
	0x00000040
#define	EXTI_FTSR1_TR6   EXTI_FTSR1_TR6_Msk
	Falling trigger event configuration bit of line 6.
#define	EXTI_FTSR1_TR7_Pos   (7U)
#define	EXTI_FTSR1_TR7_Msk   (0x1UL << EXTI_FTSR1_TR7_Pos)
	0x00000080
#define	EXTI_FTSR1_TR7   EXTI_FTSR1_TR7_Msk
	Falling trigger event configuration bit of line 7.
#define	EXTI_FTSR1_TR8_Pos   (8U)
#define	EXTI_FTSR1_TR8_Msk   (0x1UL << EXTI_FTSR1_TR8_Pos)
	0x00000100
#define	EXTI_FTSR1_TR8   EXTI_FTSR1_TR8_Msk
	Falling trigger event configuration bit of line 8.
#define	EXTI_FTSR1_TR9_Pos   (9U)
#define	EXTI_FTSR1_TR9_Msk   (0x1UL << EXTI_FTSR1_TR9_Pos)
	0x00000200
#define	EXTI_FTSR1_TR9   EXTI_FTSR1_TR9_Msk
	Falling trigger event configuration bit of line 9.
#define	EXTI_FTSR1_TR10_Pos   (10U)
#define	EXTI_FTSR1_TR10_Msk   (0x1UL << EXTI_FTSR1_TR10_Pos)
	0x00000400
#define	EXTI_FTSR1_TR10   EXTI_FTSR1_TR10_Msk
	Falling trigger event configuration bit of line 10.
#define	EXTI_FTSR1_TR11_Pos   (11U)
#define	EXTI_FTSR1_TR11_Msk   (0x1UL << EXTI_FTSR1_TR11_Pos)
	0x00000800
#define	EXTI_FTSR1_TR11   EXTI_FTSR1_TR11_Msk
	Falling trigger event configuration bit of line 11.
#define	EXTI_FTSR1_TR12_Pos   (12U)
#define	EXTI_FTSR1_TR12_Msk   (0x1UL << EXTI_FTSR1_TR12_Pos)
	0x00001000
#define	EXTI_FTSR1_TR12   EXTI_FTSR1_TR12_Msk
	Falling trigger event configuration bit of line 12.
#define	EXTI_FTSR1_TR13_Pos   (13U)
#define	EXTI_FTSR1_TR13_Msk   (0x1UL << EXTI_FTSR1_TR13_Pos)
	0x00002000
#define	EXTI_FTSR1_TR13   EXTI_FTSR1_TR13_Msk
	Falling trigger event configuration bit of line 13.
#define	EXTI_FTSR1_TR14_Pos   (14U)
#define	EXTI_FTSR1_TR14_Msk   (0x1UL << EXTI_FTSR1_TR14_Pos)
	0x00004000
#define	EXTI_FTSR1_TR14   EXTI_FTSR1_TR14_Msk
	Falling trigger event configuration bit of line 14.
#define	EXTI_FTSR1_TR15_Pos   (15U)
#define	EXTI_FTSR1_TR15_Msk   (0x1UL << EXTI_FTSR1_TR15_Pos)
	0x00008000
#define	EXTI_FTSR1_TR15   EXTI_FTSR1_TR15_Msk
	Falling trigger event configuration bit of line 15.
#define	EXTI_FTSR1_TR16_Pos   (16U)
#define	EXTI_FTSR1_TR16_Msk   (0x1UL << EXTI_FTSR1_TR16_Pos)
	0x00010000
#define	EXTI_FTSR1_TR16   EXTI_FTSR1_TR16_Msk
	Falling trigger event configuration bit of line 16.
#define	EXTI_FTSR1_TR17_Pos   (17U)
#define	EXTI_FTSR1_TR17_Msk   (0x1UL << EXTI_FTSR1_TR17_Pos)
	0x00020000
#define	EXTI_FTSR1_TR17   EXTI_FTSR1_TR17_Msk
	Falling trigger event configuration bit of line 17.
#define	EXTI_FTSR1_TR18_Pos   (18U)
#define	EXTI_FTSR1_TR18_Msk   (0x1UL << EXTI_FTSR1_TR18_Pos)
	0x00040000
#define	EXTI_FTSR1_TR18   EXTI_FTSR1_TR18_Msk
	Falling trigger event configuration bit of line 18.
#define	EXTI_FTSR1_TR19_Pos   (19U)
#define	EXTI_FTSR1_TR19_Msk   (0x1UL << EXTI_FTSR1_TR19_Pos)
	0x00080000
#define	EXTI_FTSR1_TR19   EXTI_FTSR1_TR19_Msk
	Falling trigger event configuration bit of line 19.
#define	EXTI_FTSR1_TR20_Pos   (20U)
#define	EXTI_FTSR1_TR20_Msk   (0x1UL << EXTI_FTSR1_TR20_Pos)
	0x00100000
#define	EXTI_FTSR1_TR20   EXTI_FTSR1_TR20_Msk
	Falling trigger event configuration bit of line 20.
#define	EXTI_FTSR1_TR21_Pos   (21U)
#define	EXTI_FTSR1_TR21_Msk   (0x1UL << EXTI_FTSR1_TR21_Pos)
	0x00200000
#define	EXTI_FTSR1_TR21   EXTI_FTSR1_TR21_Msk
	Falling trigger event configuration bit of line 21.
#define	EXTI_SWIER1_SWIER0_Pos   (0U)
#define	EXTI_SWIER1_SWIER0_Msk   (0x1UL << EXTI_SWIER1_SWIER0_Pos)
	0x00000001
#define	EXTI_SWIER1_SWIER0   EXTI_SWIER1_SWIER0_Msk
	Software Interrupt on line 0.
#define	EXTI_SWIER1_SWIER1_Pos   (1U)
#define	EXTI_SWIER1_SWIER1_Msk   (0x1UL << EXTI_SWIER1_SWIER1_Pos)
	0x00000002
#define	EXTI_SWIER1_SWIER1   EXTI_SWIER1_SWIER1_Msk
	Software Interrupt on line 1.
#define	EXTI_SWIER1_SWIER2_Pos   (2U)
#define	EXTI_SWIER1_SWIER2_Msk   (0x1UL << EXTI_SWIER1_SWIER2_Pos)
	0x00000004
#define	EXTI_SWIER1_SWIER2   EXTI_SWIER1_SWIER2_Msk
	Software Interrupt on line 2.
#define	EXTI_SWIER1_SWIER3_Pos   (3U)
#define	EXTI_SWIER1_SWIER3_Msk   (0x1UL << EXTI_SWIER1_SWIER3_Pos)
	0x00000008
#define	EXTI_SWIER1_SWIER3   EXTI_SWIER1_SWIER3_Msk
	Software Interrupt on line 3.
#define	EXTI_SWIER1_SWIER4_Pos   (4U)
#define	EXTI_SWIER1_SWIER4_Msk   (0x1UL << EXTI_SWIER1_SWIER4_Pos)
	0x00000010
#define	EXTI_SWIER1_SWIER4   EXTI_SWIER1_SWIER4_Msk
	Software Interrupt on line 4.
#define	EXTI_SWIER1_SWIER5_Pos   (5U)
#define	EXTI_SWIER1_SWIER5_Msk   (0x1UL << EXTI_SWIER1_SWIER5_Pos)
	0x00000020
#define	EXTI_SWIER1_SWIER5   EXTI_SWIER1_SWIER5_Msk
	Software Interrupt on line 5.
#define	EXTI_SWIER1_SWIER6_Pos   (6U)
#define	EXTI_SWIER1_SWIER6_Msk   (0x1UL << EXTI_SWIER1_SWIER6_Pos)
	0x00000040
#define	EXTI_SWIER1_SWIER6   EXTI_SWIER1_SWIER6_Msk
	Software Interrupt on line 6.
#define	EXTI_SWIER1_SWIER7_Pos   (7U)
#define	EXTI_SWIER1_SWIER7_Msk   (0x1UL << EXTI_SWIER1_SWIER7_Pos)
	0x00000080
#define	EXTI_SWIER1_SWIER7   EXTI_SWIER1_SWIER7_Msk
	Software Interrupt on line 7.
#define	EXTI_SWIER1_SWIER8_Pos   (8U)
#define	EXTI_SWIER1_SWIER8_Msk   (0x1UL << EXTI_SWIER1_SWIER8_Pos)
	0x00000100
#define	EXTI_SWIER1_SWIER8   EXTI_SWIER1_SWIER8_Msk
	Software Interrupt on line 8.
#define	EXTI_SWIER1_SWIER9_Pos   (9U)
#define	EXTI_SWIER1_SWIER9_Msk   (0x1UL << EXTI_SWIER1_SWIER9_Pos)
	0x00000200
#define	EXTI_SWIER1_SWIER9   EXTI_SWIER1_SWIER9_Msk
	Software Interrupt on line 9.
#define	EXTI_SWIER1_SWIER10_Pos   (10U)
#define	EXTI_SWIER1_SWIER10_Msk   (0x1UL << EXTI_SWIER1_SWIER10_Pos)
	0x00000400
#define	EXTI_SWIER1_SWIER10   EXTI_SWIER1_SWIER10_Msk
	Software Interrupt on line 10.
#define	EXTI_SWIER1_SWIER11_Pos   (11U)
#define	EXTI_SWIER1_SWIER11_Msk   (0x1UL << EXTI_SWIER1_SWIER11_Pos)
	0x00000800
#define	EXTI_SWIER1_SWIER11   EXTI_SWIER1_SWIER11_Msk
	Software Interrupt on line 11.
#define	EXTI_SWIER1_SWIER12_Pos   (12U)
#define	EXTI_SWIER1_SWIER12_Msk   (0x1UL << EXTI_SWIER1_SWIER12_Pos)
	0x00001000
#define	EXTI_SWIER1_SWIER12   EXTI_SWIER1_SWIER12_Msk
	Software Interrupt on line 12.
#define	EXTI_SWIER1_SWIER13_Pos   (13U)
#define	EXTI_SWIER1_SWIER13_Msk   (0x1UL << EXTI_SWIER1_SWIER13_Pos)
	0x00002000
#define	EXTI_SWIER1_SWIER13   EXTI_SWIER1_SWIER13_Msk
	Software Interrupt on line 13.
#define	EXTI_SWIER1_SWIER14_Pos   (14U)
#define	EXTI_SWIER1_SWIER14_Msk   (0x1UL << EXTI_SWIER1_SWIER14_Pos)
	0x00004000
#define	EXTI_SWIER1_SWIER14   EXTI_SWIER1_SWIER14_Msk
	Software Interrupt on line 14.
#define	EXTI_SWIER1_SWIER15_Pos   (15U)
#define	EXTI_SWIER1_SWIER15_Msk   (0x1UL << EXTI_SWIER1_SWIER15_Pos)
	0x00008000
#define	EXTI_SWIER1_SWIER15   EXTI_SWIER1_SWIER15_Msk
	Software Interrupt on line 15.
#define	EXTI_SWIER1_SWIER16_Pos   (16U)
#define	EXTI_SWIER1_SWIER16_Msk   (0x1UL << EXTI_SWIER1_SWIER16_Pos)
	0x00010000
#define	EXTI_SWIER1_SWIER16   EXTI_SWIER1_SWIER16_Msk
	Software Interrupt on line 16.
#define	EXTI_SWIER1_SWIER17_Pos   (17U)
#define	EXTI_SWIER1_SWIER17_Msk   (0x1UL << EXTI_SWIER1_SWIER17_Pos)
	0x00020000
#define	EXTI_SWIER1_SWIER17   EXTI_SWIER1_SWIER17_Msk
	Software Interrupt on line 17.
#define	EXTI_SWIER1_SWIER18_Pos   (18U)
#define	EXTI_SWIER1_SWIER18_Msk   (0x1UL << EXTI_SWIER1_SWIER18_Pos)
	0x00040000
#define	EXTI_SWIER1_SWIER18   EXTI_SWIER1_SWIER18_Msk
	Software Interrupt on line 18.
#define	EXTI_SWIER1_SWIER19_Pos   (19U)
#define	EXTI_SWIER1_SWIER19_Msk   (0x1UL << EXTI_SWIER1_SWIER19_Pos)
	0x00080000
#define	EXTI_SWIER1_SWIER19   EXTI_SWIER1_SWIER19_Msk
	Software Interrupt on line 19.
#define	EXTI_SWIER1_SWIER20_Pos   (20U)
#define	EXTI_SWIER1_SWIER20_Msk   (0x1UL << EXTI_SWIER1_SWIER20_Pos)
	0x00100000
#define	EXTI_SWIER1_SWIER20   EXTI_SWIER1_SWIER20_Msk
	Software Interrupt on line 20.
#define	EXTI_SWIER1_SWIER21_Pos   (21U)
#define	EXTI_SWIER1_SWIER21_Msk   (0x1UL << EXTI_SWIER1_SWIER21_Pos)
	0x00200000
#define	EXTI_SWIER1_SWIER21   EXTI_SWIER1_SWIER21_Msk
	Software Interrupt on line 21.
#define	EXTI_D3PMR1_MR0_Pos   (0U)
#define	EXTI_D3PMR1_MR0_Msk   (0x1UL << EXTI_D3PMR1_MR0_Pos)
	0x00000001
#define	EXTI_D3PMR1_MR0   EXTI_D3PMR1_MR0_Msk
	Pending Mask Event for line 0.
#define	EXTI_D3PMR1_MR1_Pos   (1U)
#define	EXTI_D3PMR1_MR1_Msk   (0x1UL << EXTI_D3PMR1_MR1_Pos)
	0x00000002
#define	EXTI_D3PMR1_MR1   EXTI_D3PMR1_MR1_Msk
	Pending Mask Event for line 1.
#define	EXTI_D3PMR1_MR2_Pos   (2U)
#define	EXTI_D3PMR1_MR2_Msk   (0x1UL << EXTI_D3PMR1_MR2_Pos)
	0x00000004
#define	EXTI_D3PMR1_MR2   EXTI_D3PMR1_MR2_Msk
	Pending Mask Event for line 2.
#define	EXTI_D3PMR1_MR3_Pos   (3U)
#define	EXTI_D3PMR1_MR3_Msk   (0x1UL << EXTI_D3PMR1_MR3_Pos)
	0x00000008
#define	EXTI_D3PMR1_MR3   EXTI_D3PMR1_MR3_Msk
	Pending Mask Event for line 3.
#define	EXTI_D3PMR1_MR4_Pos   (4U)
#define	EXTI_D3PMR1_MR4_Msk   (0x1UL << EXTI_D3PMR1_MR4_Pos)
	0x00000010
#define	EXTI_D3PMR1_MR4   EXTI_D3PMR1_MR4_Msk
	Pending Mask Event for line 4.
#define	EXTI_D3PMR1_MR5_Pos   (5U)
#define	EXTI_D3PMR1_MR5_Msk   (0x1UL << EXTI_D3PMR1_MR5_Pos)
	0x00000020
#define	EXTI_D3PMR1_MR5   EXTI_D3PMR1_MR5_Msk
	Pending Mask Event for line 5.
#define	EXTI_D3PMR1_MR6_Pos   (6U)
#define	EXTI_D3PMR1_MR6_Msk   (0x1UL << EXTI_D3PMR1_MR6_Pos)
	0x00000040
#define	EXTI_D3PMR1_MR6   EXTI_D3PMR1_MR6_Msk
	Pending Mask Event for line 6.
#define	EXTI_D3PMR1_MR7_Pos   (7U)
#define	EXTI_D3PMR1_MR7_Msk   (0x1UL << EXTI_D3PMR1_MR7_Pos)
	0x00000080
#define	EXTI_D3PMR1_MR7   EXTI_D3PMR1_MR7_Msk
	Pending Mask Event for line 7.
#define	EXTI_D3PMR1_MR8_Pos   (8U)
#define	EXTI_D3PMR1_MR8_Msk   (0x1UL << EXTI_D3PMR1_MR8_Pos)
	0x00000100
#define	EXTI_D3PMR1_MR8   EXTI_D3PMR1_MR8_Msk
	Pending Mask Event for line 8.
#define	EXTI_D3PMR1_MR9_Pos   (9U)
#define	EXTI_D3PMR1_MR9_Msk   (0x1UL << EXTI_D3PMR1_MR9_Pos)
	0x00000200
#define	EXTI_D3PMR1_MR9   EXTI_D3PMR1_MR9_Msk
	Pending Mask Event for line 9.
#define	EXTI_D3PMR1_MR10_Pos   (10U)
#define	EXTI_D3PMR1_MR10_Msk   (0x1UL << EXTI_D3PMR1_MR10_Pos)
	0x00000400
#define	EXTI_D3PMR1_MR10   EXTI_D3PMR1_MR10_Msk
	Pending Mask Event for line 10.
#define	EXTI_D3PMR1_MR11_Pos   (11U)
#define	EXTI_D3PMR1_MR11_Msk   (0x1UL << EXTI_D3PMR1_MR11_Pos)
	0x00000800
#define	EXTI_D3PMR1_MR11   EXTI_D3PMR1_MR11_Msk
	Pending Mask Event for line 11.
#define	EXTI_D3PMR1_MR12_Pos   (12U)
#define	EXTI_D3PMR1_MR12_Msk   (0x1UL << EXTI_D3PMR1_MR12_Pos)
	0x00001000
#define	EXTI_D3PMR1_MR12   EXTI_D3PMR1_MR12_Msk
	Pending Mask Event for line 12.
#define	EXTI_D3PMR1_MR13_Pos   (13U)
#define	EXTI_D3PMR1_MR13_Msk   (0x1UL << EXTI_D3PMR1_MR13_Pos)
	0x00002000
#define	EXTI_D3PMR1_MR13   EXTI_D3PMR1_MR13_Msk
	Pending Mask Event for line 13.
#define	EXTI_D3PMR1_MR14_Pos   (14U)
#define	EXTI_D3PMR1_MR14_Msk   (0x1UL << EXTI_D3PMR1_MR14_Pos)
	0x00004000
#define	EXTI_D3PMR1_MR14   EXTI_D3PMR1_MR14_Msk
	Pending Mask Event for line 14.
#define	EXTI_D3PMR1_MR15_Pos   (15U)
#define	EXTI_D3PMR1_MR15_Msk   (0x1UL << EXTI_D3PMR1_MR15_Pos)
	0x00008000
#define	EXTI_D3PMR1_MR15   EXTI_D3PMR1_MR15_Msk
	Pending Mask Event for line 15.
#define	EXTI_D3PMR1_MR19_Pos   (19U)
#define	EXTI_D3PMR1_MR19_Msk   (0x1UL << EXTI_D3PMR1_MR19_Pos)
	0x00080000
#define	EXTI_D3PMR1_MR19   EXTI_D3PMR1_MR19_Msk
	Pending Mask Event for line 19.
#define	EXTI_D3PMR1_MR20_Pos   (20U)
#define	EXTI_D3PMR1_MR20_Msk   (0x1UL << EXTI_D3PMR1_MR20_Pos)
	0x00100000
#define	EXTI_D3PMR1_MR20   EXTI_D3PMR1_MR20_Msk
	Pending Mask Event for line 20.
#define	EXTI_D3PMR1_MR21_Pos   (21U)
#define	EXTI_D3PMR1_MR21_Msk   (0x1UL << EXTI_D3PMR1_MR21_Pos)
	0x00200000
#define	EXTI_D3PMR1_MR21   EXTI_D3PMR1_MR21_Msk
	Pending Mask Event for line 21.
#define	EXTI_D3PMR1_MR25_Pos   (24U)
#define	EXTI_D3PMR1_MR25_Msk   (0x1UL << EXTI_D3PMR1_MR25_Pos)
	0x01000000
#define	EXTI_D3PMR1_MR25   EXTI_D3PMR1_MR25_Msk
	Pending Mask Event for line 25.
#define	EXTI_D3PCR1L_PCS0_Pos   (0U)
#define	EXTI_D3PCR1L_PCS0_Msk   (0x3UL << EXTI_D3PCR1L_PCS0_Pos)
	0x00000003
#define	EXTI_D3PCR1L_PCS0   EXTI_D3PCR1L_PCS0_Msk
	D3 Pending request clear input signal selection on line 0.
#define	EXTI_D3PCR1L_PCS1_Pos   (2U)
#define	EXTI_D3PCR1L_PCS1_Msk   (0x3UL << EXTI_D3PCR1L_PCS1_Pos)
	0x000000C0
#define	EXTI_D3PCR1L_PCS1   EXTI_D3PCR1L_PCS1_Msk
	D3 Pending request clear input signal selection on line 1.
#define	EXTI_D3PCR1L_PCS2_Pos   (4U)
#define	EXTI_D3PCR1L_PCS2_Msk   (0x3UL << EXTI_D3PCR1L_PCS2_Pos)
	0x00000030
#define	EXTI_D3PCR1L_PCS2   EXTI_D3PCR1L_PCS2_Msk
	D3 Pending request clear input signal selection on line 2.
#define	EXTI_D3PCR1L_PCS3_Pos   (6U)
#define	EXTI_D3PCR1L_PCS3_Msk   (0x3UL << EXTI_D3PCR1L_PCS3_Pos)
	0x000000C0
#define	EXTI_D3PCR1L_PCS3   EXTI_D3PCR1L_PCS3_Msk
	D3 Pending request clear input signal selection on line 3.
#define	EXTI_D3PCR1L_PCS4_Pos   (8U)
#define	EXTI_D3PCR1L_PCS4_Msk   (0x3UL << EXTI_D3PCR1L_PCS4_Pos)
	0x00000300
#define	EXTI_D3PCR1L_PCS4   EXTI_D3PCR1L_PCS4_Msk
	D3 Pending request clear input signal selection on line 4.
#define	EXTI_D3PCR1L_PCS5_Pos   (10U)
#define	EXTI_D3PCR1L_PCS5_Msk   (0x3UL << EXTI_D3PCR1L_PCS5_Pos)
	0x00000C00
#define	EXTI_D3PCR1L_PCS5   EXTI_D3PCR1L_PCS5_Msk
	D3 Pending request clear input signal selection on line 5.
#define	EXTI_D3PCR1L_PCS6_Pos   (12U)
#define	EXTI_D3PCR1L_PCS6_Msk   (0x3UL << EXTI_D3PCR1L_PCS6_Pos)
	0x00003000
#define	EXTI_D3PCR1L_PCS6   EXTI_D3PCR1L_PCS6_Msk
	D3 Pending request clear input signal selection on line 6.
#define	EXTI_D3PCR1L_PCS7_Pos   (14U)
#define	EXTI_D3PCR1L_PCS7_Msk   (0x3UL << EXTI_D3PCR1L_PCS7_Pos)
	0x0000C000
#define	EXTI_D3PCR1L_PCS7   EXTI_D3PCR1L_PCS7_Msk
	D3 Pending request clear input signal selection on line 7.
#define	EXTI_D3PCR1L_PCS8_Pos   (16U)
#define	EXTI_D3PCR1L_PCS8_Msk   (0x3UL << EXTI_D3PCR1L_PCS8_Pos)
	0x00030000
#define	EXTI_D3PCR1L_PCS8   EXTI_D3PCR1L_PCS8_Msk
	D3 Pending request clear input signal selection on line 8.
#define	EXTI_D3PCR1L_PCS9_Pos   (18U)
#define	EXTI_D3PCR1L_PCS9_Msk   (0x3UL << EXTI_D3PCR1L_PCS9_Pos)
	0x000C0000
#define	EXTI_D3PCR1L_PCS9   EXTI_D3PCR1L_PCS9_Msk
	D3 Pending request clear input signal selection on line 9.
#define	EXTI_D3PCR1L_PCS10_Pos   (20U)
#define	EXTI_D3PCR1L_PCS10_Msk   (0x3UL << EXTI_D3PCR1L_PCS10_Pos)
	0x00300000
#define	EXTI_D3PCR1L_PCS10   EXTI_D3PCR1L_PCS10_Msk
	D3 Pending request clear input signal selection on line 10.
#define	EXTI_D3PCR1L_PCS11_Pos   (22U)
#define	EXTI_D3PCR1L_PCS11_Msk   (0x3UL << EXTI_D3PCR1L_PCS11_Pos)
	0x00C00000
#define	EXTI_D3PCR1L_PCS11   EXTI_D3PCR1L_PCS11_Msk
	D3 Pending request clear input signal selection on line 11.
#define	EXTI_D3PCR1L_PCS12_Pos   (24U)
#define	EXTI_D3PCR1L_PCS12_Msk   (0x3UL << EXTI_D3PCR1L_PCS12_Pos)
	0x03000000
#define	EXTI_D3PCR1L_PCS12   EXTI_D3PCR1L_PCS12_Msk
	D3 Pending request clear input signal selection on line 12.
#define	EXTI_D3PCR1L_PCS13_Pos   (26U)
#define	EXTI_D3PCR1L_PCS13_Msk   (0x3UL << EXTI_D3PCR1L_PCS13_Pos)
	0x0C000000
#define	EXTI_D3PCR1L_PCS13   EXTI_D3PCR1L_PCS13_Msk
	D3 Pending request clear input signal selection on line 13.
#define	EXTI_D3PCR1L_PCS14_Pos   (28U)
#define	EXTI_D3PCR1L_PCS14_Msk   (0x3UL << EXTI_D3PCR1L_PCS14_Pos)
	0x30000000
#define	EXTI_D3PCR1L_PCS14   EXTI_D3PCR1L_PCS14_Msk
	D3 Pending request clear input signal selection on line 14.
#define	EXTI_D3PCR1L_PCS15_Pos   (30U)
#define	EXTI_D3PCR1L_PCS15_Msk   (0x3UL << EXTI_D3PCR1L_PCS15_Pos)
	0xC0000000
#define	EXTI_D3PCR1L_PCS15   EXTI_D3PCR1L_PCS15_Msk
	D3 Pending request clear input signal selection on line 15.
#define	EXTI_D3PCR1H_PCS19_Pos   (6U)
#define	EXTI_D3PCR1H_PCS19_Msk   (0x3UL << EXTI_D3PCR1H_PCS19_Pos)
	0x000000C0
#define	EXTI_D3PCR1H_PCS19   EXTI_D3PCR1H_PCS19_Msk
	D3 Pending request clear input signal selection on line 19.
#define	EXTI_D3PCR1H_PCS20_Pos   (8U)
#define	EXTI_D3PCR1H_PCS20_Msk   (0x3UL << EXTI_D3PCR1H_PCS20_Pos)
	0x00000300
#define	EXTI_D3PCR1H_PCS20   EXTI_D3PCR1H_PCS20_Msk
	D3 Pending request clear input signal selection on line 20.
#define	EXTI_D3PCR1H_PCS21_Pos   (10U)
#define	EXTI_D3PCR1H_PCS21_Msk   (0x3UL << EXTI_D3PCR1H_PCS21_Pos)
	0x00000C00
#define	EXTI_D3PCR1H_PCS21   EXTI_D3PCR1H_PCS21_Msk
	D3 Pending request clear input signal selection on line 21.
#define	EXTI_D3PCR1H_PCS25_Pos   (18U)
#define	EXTI_D3PCR1H_PCS25_Msk   (0x3UL << EXTI_D3PCR1H_PCS25_Pos)
	0x000C0000
#define	EXTI_D3PCR1H_PCS25   EXTI_D3PCR1H_PCS25_Msk
	D3 Pending request clear input signal selection on line 25.
#define	EXTI_RTSR2_TR_Pos   (17U)
#define	EXTI_RTSR2_TR_Msk   (0x5UL << EXTI_RTSR2_TR_Pos)
	0x000A0000
#define	EXTI_RTSR2_TR   EXTI_RTSR2_TR_Msk
	Rising trigger event configuration bit.
#define	EXTI_RTSR2_TR49_Pos   (17U)
#define	EXTI_RTSR2_TR49_Msk   (0x1UL << EXTI_RTSR2_TR49_Pos)
	0x00020000
#define	EXTI_RTSR2_TR49   EXTI_RTSR2_TR49_Msk
	Rising trigger event configuration bit of line 49.
#define	EXTI_RTSR2_TR51_Pos   (19U)
#define	EXTI_RTSR2_TR51_Msk   (0x1UL << EXTI_RTSR2_TR51_Pos)
	0x00080000
#define	EXTI_RTSR2_TR51   EXTI_RTSR2_TR51_Msk
	Rising trigger event configuration bit of line 51.
#define	EXTI_FTSR2_TR_Pos   (17U)
#define	EXTI_FTSR2_TR_Msk   (0x5UL << EXTI_FTSR2_TR_Pos)
	0x000A0000
#define	EXTI_FTSR2_TR   EXTI_FTSR2_TR_Msk
	Falling trigger event configuration bit.
#define	EXTI_FTSR2_TR49_Pos   (17U)
#define	EXTI_FTSR2_TR49_Msk   (0x1UL << EXTI_FTSR2_TR49_Pos)
	0x00020000
#define	EXTI_FTSR2_TR49   EXTI_FTSR2_TR49_Msk
	Falling trigger event configuration bit of line 49.
#define	EXTI_FTSR2_TR51_Pos   (19U)
#define	EXTI_FTSR2_TR51_Msk   (0x1UL << EXTI_FTSR2_TR51_Pos)
	0x00080000
#define	EXTI_FTSR2_TR51   EXTI_FTSR2_TR51_Msk
	Falling trigger event configuration bit of line 51.
#define	EXTI_SWIER2_SWIER49_Pos   (17U)
#define	EXTI_SWIER2_SWIER49_Msk   (0x1UL << EXTI_SWIER2_SWIER49_Pos)
	0x00020000
#define	EXTI_SWIER2_SWIER49   EXTI_SWIER2_SWIER49_Msk
	Software Interrupt on line 49.
#define	EXTI_SWIER2_SWIER51_Pos   (19U)
#define	EXTI_SWIER2_SWIER51_Msk   (0x1UL << EXTI_SWIER2_SWIER51_Pos)
	0x00080000
#define	EXTI_SWIER2_SWIER51   EXTI_SWIER2_SWIER51_Msk
	Software Interrupt on line 51.
#define	EXTI_D3PMR2_MR34_Pos   (2U)
#define	EXTI_D3PMR2_MR34_Msk   (0x1UL << EXTI_D3PMR2_MR34_Pos)
	0x00000004
#define	EXTI_D3PMR2_MR34   EXTI_D3PMR2_MR34_Msk
	Pending Mask Event for line 34.
#define	EXTI_D3PMR2_MR35_Pos   (3U)
#define	EXTI_D3PMR2_MR35_Msk   (0x1UL << EXTI_D3PMR2_MR35_Pos)
	0x00000008
#define	EXTI_D3PMR2_MR35   EXTI_D3PMR2_MR35_Msk
	Pending Mask Event for line 35.
#define	EXTI_D3PMR2_MR41_Pos   (9U)
#define	EXTI_D3PMR2_MR41_Msk   (0x1UL << EXTI_D3PMR2_MR41_Pos)
	0x00000200
#define	EXTI_D3PMR2_MR41   EXTI_D3PMR2_MR41_Msk
	Pending Mask Event for line 41.
#define	EXTI_D3PMR2_MR48_Pos   (16U)
#define	EXTI_D3PMR2_MR48_Msk   (0x1UL << EXTI_D3PMR2_MR48_Pos)
	0x00010000
#define	EXTI_D3PMR2_MR48   EXTI_D3PMR2_MR48_Msk
	Pending Mask Event for line 48.
#define	EXTI_D3PMR2_MR49_Pos   (17U)
#define	EXTI_D3PMR2_MR49_Msk   (0x1UL << EXTI_D3PMR2_MR49_Pos)
	0x00020000
#define	EXTI_D3PMR2_MR49   EXTI_D3PMR2_MR49_Msk
	Pending Mask Event for line 49.
#define	EXTI_D3PMR2_MR50_Pos   (18U)
#define	EXTI_D3PMR2_MR50_Msk   (0x1UL << EXTI_D3PMR2_MR50_Pos)
	0x00040000
#define	EXTI_D3PMR2_MR50   EXTI_D3PMR2_MR50_Msk
	Pending Mask Event for line 50.
#define	EXTI_D3PMR2_MR51_Pos   (19U)
#define	EXTI_D3PMR2_MR51_Msk   (0x1UL << EXTI_D3PMR2_MR51_Pos)
	0x00080000
#define	EXTI_D3PMR2_MR51   EXTI_D3PMR2_MR51_Msk
	Pending Mask Event for line 51.
#define	EXTI_D3PMR2_MR52_Pos   (20U)
#define	EXTI_D3PMR2_MR52_Msk   (0x1UL << EXTI_D3PMR2_MR52_Pos)
	0x00100000
#define	EXTI_D3PMR2_MR52   EXTI_D3PMR2_MR52_Msk
	Pending Mask Event for line 52.
#define	EXTI_D3PMR2_MR53_Pos   (21U)
#define	EXTI_D3PMR2_MR53_Msk   (0x1UL << EXTI_D3PMR2_MR53_Pos)
	0x00200000
#define	EXTI_D3PMR2_MR53   EXTI_D3PMR2_MR53_Msk
	Pending Mask Event for line 53.
#define	EXTI_D3PCR2L_PCS34_Pos   (4U)
#define	EXTI_D3PCR2L_PCS34_Msk   (0x3UL << EXTI_D3PCR2L_PCS34_Pos)
	0x00000030
#define	EXTI_D3PCR2L_PCS34   EXTI_D3PCR2L_PCS34_Msk
	D3 Pending request clear input signal selection on line 34.
#define	EXTI_D3PCR2L_PCS35_Pos   (6U)
#define	EXTI_D3PCR2L_PCS35_Msk   (0x3UL << EXTI_D3PCR2L_PCS35_Pos)
	0x000000C0
#define	EXTI_D3PCR2L_PCS35   EXTI_D3PCR2L_PCS35_Msk
	D3 Pending request clear input signal selection on line 35.
#define	EXTI_D3PCR2L_PCS41_Pos   (18U)
#define	EXTI_D3PCR2L_PCS41_Msk   (0x3UL << EXTI_D3PCR2L_PCS41_Pos)
	0x000C0000
#define	EXTI_D3PCR2L_PCS41   EXTI_D3PCR2L_PCS41_Msk
	D3 Pending request clear input signal selection on line 41.
#define	EXTI_D3PCR2H_PCS48_Pos   (0U)
#define	EXTI_D3PCR2H_PCS48_Msk   (0x3UL << EXTI_D3PCR2H_PCS48_Pos)
	0x00000003
#define	EXTI_D3PCR2H_PCS48   EXTI_D3PCR2H_PCS48_Msk
	D3 Pending request clear input signal selection on line 48.
#define	EXTI_D3PCR2H_PCS49_Pos   (2U)
#define	EXTI_D3PCR2H_PCS49_Msk   (0x3UL << EXTI_D3PCR2H_PCS49_Pos)
	0x0000000C
#define	EXTI_D3PCR2H_PCS49   EXTI_D3PCR2H_PCS49_Msk
	D3 Pending request clear input signal selection on line 49.
#define	EXTI_D3PCR2H_PCS50_Pos   (4U)
#define	EXTI_D3PCR2H_PCS50_Msk   (0x3UL << EXTI_D3PCR2H_PCS50_Pos)
	0x00000030
#define	EXTI_D3PCR2H_PCS50   EXTI_D3PCR2H_PCS50_Msk
	D3 Pending request clear input signal selection on line 50.
#define	EXTI_D3PCR2H_PCS51_Pos   (6U)
#define	EXTI_D3PCR2H_PCS51_Msk   (0x3UL << EXTI_D3PCR2H_PCS51_Pos)
	0x000000C0
#define	EXTI_D3PCR2H_PCS51   EXTI_D3PCR2H_PCS51_Msk
	D3 Pending request clear input signal selection on line 51.
#define	EXTI_D3PCR2H_PCS52_Pos   (8U)
#define	EXTI_D3PCR2H_PCS52_Msk   (0x3UL << EXTI_D3PCR2H_PCS52_Pos)
	0x00000300
#define	EXTI_D3PCR2H_PCS52   EXTI_D3PCR2H_PCS52_Msk
	D3 Pending request clear input signal selection on line 52.
#define	EXTI_D3PCR2H_PCS53_Pos   (10U)
#define	EXTI_D3PCR2H_PCS53_Msk   (0x3UL << EXTI_D3PCR2H_PCS53_Pos)
	0x00000C00
#define	EXTI_D3PCR2H_PCS53   EXTI_D3PCR2H_PCS53_Msk
	D3 Pending request clear input signal selection on line 53.
#define	EXTI_RTSR3_TR_Pos   (21U)
#define	EXTI_RTSR3_TR_Msk   (0x3UL << EXTI_RTSR3_TR_Pos)
	0x00600000
#define	EXTI_RTSR3_TR   EXTI_RTSR3_TR_Msk
	Rising trigger event configuration bit.
#define	EXTI_RTSR3_TR85_Pos   (21U)
#define	EXTI_RTSR3_TR85_Msk   (0x1UL << EXTI_RTSR3_TR85_Pos)
	0x00200000
#define	EXTI_RTSR3_TR85   EXTI_RTSR3_TR85_Msk
	Rising trigger event configuration bit of line 85.
#define	EXTI_RTSR3_TR86_Pos   (22U)
#define	EXTI_RTSR3_TR86_Msk   (0x1UL << EXTI_RTSR3_TR86_Pos)
	0x00400000
#define	EXTI_RTSR3_TR86   EXTI_RTSR3_TR86_Msk
	Rising trigger event configuration bit of line 86.
#define	EXTI_FTSR3_TR_Pos   (21U)
#define	EXTI_FTSR3_TR_Msk   (0x3UL << EXTI_FTSR3_TR_Pos)
	0x00600000
#define	EXTI_FTSR3_TR   EXTI_FTSR3_TR_Msk
	Falling trigger event configuration bit.
#define	EXTI_FTSR3_TR85_Pos   (21U)
#define	EXTI_FTSR3_TR85_Msk   (0x1UL << EXTI_FTSR3_TR85_Pos)
	0x00200000
#define	EXTI_FTSR3_TR85   EXTI_FTSR3_TR85_Msk
	Falling trigger event configuration bit of line 85.
#define	EXTI_FTSR3_TR86_Pos   (22U)
#define	EXTI_FTSR3_TR86_Msk   (0x1UL << EXTI_FTSR3_TR86_Pos)
	0x00400000
#define	EXTI_FTSR3_TR86   EXTI_FTSR3_TR86_Msk
	Falling trigger event configuration bit of line 86.
#define	EXTI_SWIER3_SWI_Pos   (21U)
#define	EXTI_SWIER3_SWI_Msk   (0x3UL << EXTI_SWIER3_SWI_Pos)
	0x00600000
#define	EXTI_SWIER3_SWI   EXTI_SWIER3_SWI_Msk
	Software Interrupt event bit.
#define	EXTI_SWIER3_SWIER85_Pos   (21U)
#define	EXTI_SWIER3_SWIER85_Msk   (0x1UL << EXTI_SWIER3_SWIER85_Pos)
	0x00200000
#define	EXTI_SWIER3_SWIER85   EXTI_SWIER3_SWIER85_Msk
	Software Interrupt on line 85.
#define	EXTI_SWIER3_SWIER86_Pos   (22U)
#define	EXTI_SWIER3_SWIER86_Msk   (0x1UL << EXTI_SWIER3_SWIER86_Pos)
	0x00400000
#define	EXTI_SWIER3_SWIER86   EXTI_SWIER3_SWIER86_Msk
	Software Interrupt on line 86.
#define	EXTI_D3PMR3_MR88_Pos   (24U)
#define	EXTI_D3PMR3_MR88_Msk   (0x1UL << EXTI_D3PMR3_MR88_Pos)
	0x01000000
#define	EXTI_D3PMR3_MR88   EXTI_D3PMR3_MR88_Msk
	Pending Mask Event for line 88.
#define	EXTI_D3PCR3H_PCS88_Pos   (16U)
#define	EXTI_D3PCR3H_PCS88_Msk   (0x3UL << EXTI_D3PCR3H_PCS88_Pos)
	0x00030000
#define	EXTI_D3PCR3H_PCS88   EXTI_D3PCR3H_PCS88_Msk
	D3 Pending request clear input signal selection on line 88.
#define	EXTI_IMR1_IM_Pos   (0U)
#define	EXTI_IMR1_IM_Msk   (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)
	0xFFFFFFFF
#define	EXTI_IMR1_IM   EXTI_IMR1_IM_Msk
	Interrupt Mask.
#define	EXTI_IMR1_IM0_Pos   (0U)
#define	EXTI_IMR1_IM0_Msk   (0x1UL << EXTI_IMR1_IM0_Pos)
	0x00000001
#define	EXTI_IMR1_IM0   EXTI_IMR1_IM0_Msk
	Interrupt Mask on line 0.
#define	EXTI_IMR1_IM1_Pos   (1U)
#define	EXTI_IMR1_IM1_Msk   (0x1UL << EXTI_IMR1_IM1_Pos)
	0x00000002
#define	EXTI_IMR1_IM1   EXTI_IMR1_IM1_Msk
	Interrupt Mask on line 1.
#define	EXTI_IMR1_IM2_Pos   (2U)
#define	EXTI_IMR1_IM2_Msk   (0x1UL << EXTI_IMR1_IM2_Pos)
	0x00000004
#define	EXTI_IMR1_IM2   EXTI_IMR1_IM2_Msk
	Interrupt Mask on line 2.
#define	EXTI_IMR1_IM3_Pos   (3U)
#define	EXTI_IMR1_IM3_Msk   (0x1UL << EXTI_IMR1_IM3_Pos)
	0x00000008
#define	EXTI_IMR1_IM3   EXTI_IMR1_IM3_Msk
	Interrupt Mask on line 3.
#define	EXTI_IMR1_IM4_Pos   (4U)
#define	EXTI_IMR1_IM4_Msk   (0x1UL << EXTI_IMR1_IM4_Pos)
	0x00000010
#define	EXTI_IMR1_IM4   EXTI_IMR1_IM4_Msk
	Interrupt Mask on line 4.
#define	EXTI_IMR1_IM5_Pos   (5U)
#define	EXTI_IMR1_IM5_Msk   (0x1UL << EXTI_IMR1_IM5_Pos)
	0x00000020
#define	EXTI_IMR1_IM5   EXTI_IMR1_IM5_Msk
	Interrupt Mask on line 5.
#define	EXTI_IMR1_IM6_Pos   (6U)
#define	EXTI_IMR1_IM6_Msk   (0x1UL << EXTI_IMR1_IM6_Pos)
	0x00000040
#define	EXTI_IMR1_IM6   EXTI_IMR1_IM6_Msk
	Interrupt Mask on line 6.
#define	EXTI_IMR1_IM7_Pos   (7U)
#define	EXTI_IMR1_IM7_Msk   (0x1UL << EXTI_IMR1_IM7_Pos)
	0x00000080
#define	EXTI_IMR1_IM7   EXTI_IMR1_IM7_Msk
	Interrupt Mask on line 7.
#define	EXTI_IMR1_IM8_Pos   (8U)
#define	EXTI_IMR1_IM8_Msk   (0x1UL << EXTI_IMR1_IM8_Pos)
	0x00000100
#define	EXTI_IMR1_IM8   EXTI_IMR1_IM8_Msk
	Interrupt Mask on line 8.
#define	EXTI_IMR1_IM9_Pos   (9U)
#define	EXTI_IMR1_IM9_Msk   (0x1UL << EXTI_IMR1_IM9_Pos)
	0x00000200
#define	EXTI_IMR1_IM9   EXTI_IMR1_IM9_Msk
	Interrupt Mask on line 9.
#define	EXTI_IMR1_IM10_Pos   (10U)
#define	EXTI_IMR1_IM10_Msk   (0x1UL << EXTI_IMR1_IM10_Pos)
	0x00000400
#define	EXTI_IMR1_IM10   EXTI_IMR1_IM10_Msk
	Interrupt Mask on line 10.
#define	EXTI_IMR1_IM11_Pos   (11U)
#define	EXTI_IMR1_IM11_Msk   (0x1UL << EXTI_IMR1_IM11_Pos)
	0x00000800
#define	EXTI_IMR1_IM11   EXTI_IMR1_IM11_Msk
	Interrupt Mask on line 11.
#define	EXTI_IMR1_IM12_Pos   (12U)
#define	EXTI_IMR1_IM12_Msk   (0x1UL << EXTI_IMR1_IM12_Pos)
	0x00001000
#define	EXTI_IMR1_IM12   EXTI_IMR1_IM12_Msk
	Interrupt Mask on line 12.
#define	EXTI_IMR1_IM13_Pos   (13U)
#define	EXTI_IMR1_IM13_Msk   (0x1UL << EXTI_IMR1_IM13_Pos)
	0x00002000
#define	EXTI_IMR1_IM13   EXTI_IMR1_IM13_Msk
	Interrupt Mask on line 13.
#define	EXTI_IMR1_IM14_Pos   (14U)
#define	EXTI_IMR1_IM14_Msk   (0x1UL << EXTI_IMR1_IM14_Pos)
	0x00004000
#define	EXTI_IMR1_IM14   EXTI_IMR1_IM14_Msk
	Interrupt Mask on line 14.
#define	EXTI_IMR1_IM15_Pos   (15U)
#define	EXTI_IMR1_IM15_Msk   (0x1UL << EXTI_IMR1_IM15_Pos)
	0x00008000
#define	EXTI_IMR1_IM15   EXTI_IMR1_IM15_Msk
	Interrupt Mask on line 15.
#define	EXTI_IMR1_IM16_Pos   (16U)
#define	EXTI_IMR1_IM16_Msk   (0x1UL << EXTI_IMR1_IM16_Pos)
	0x00010000
#define	EXTI_IMR1_IM16   EXTI_IMR1_IM16_Msk
	Interrupt Mask on line 16.
#define	EXTI_IMR1_IM17_Pos   (17U)
#define	EXTI_IMR1_IM17_Msk   (0x1UL << EXTI_IMR1_IM17_Pos)
	0x00020000
#define	EXTI_IMR1_IM17   EXTI_IMR1_IM17_Msk
	Interrupt Mask on line 17.
#define	EXTI_IMR1_IM18_Pos   (18U)
#define	EXTI_IMR1_IM18_Msk   (0x1UL << EXTI_IMR1_IM18_Pos)
	0x00040000
#define	EXTI_IMR1_IM18   EXTI_IMR1_IM18_Msk
	Interrupt Mask on line 18.
#define	EXTI_IMR1_IM19_Pos   (19U)
#define	EXTI_IMR1_IM19_Msk   (0x1UL << EXTI_IMR1_IM19_Pos)
	0x00080000
#define	EXTI_IMR1_IM19   EXTI_IMR1_IM19_Msk
	Interrupt Mask on line 19.
#define	EXTI_IMR1_IM20_Pos   (20U)
#define	EXTI_IMR1_IM20_Msk   (0x1UL << EXTI_IMR1_IM20_Pos)
	0x00100000
#define	EXTI_IMR1_IM20   EXTI_IMR1_IM20_Msk
	Interrupt Mask on line 20.
#define	EXTI_IMR1_IM21_Pos   (21U)
#define	EXTI_IMR1_IM21_Msk   (0x1UL << EXTI_IMR1_IM21_Pos)
	0x00200000
#define	EXTI_IMR1_IM21   EXTI_IMR1_IM21_Msk
	Interrupt Mask on line 21.
#define	EXTI_IMR1_IM22_Pos   (22U)
#define	EXTI_IMR1_IM22_Msk   (0x1UL << EXTI_IMR1_IM22_Pos)
	0x00400000
#define	EXTI_IMR1_IM22   EXTI_IMR1_IM22_Msk
	Interrupt Mask on line 22.
#define	EXTI_IMR1_IM23_Pos   (23U)
#define	EXTI_IMR1_IM23_Msk   (0x1UL << EXTI_IMR1_IM23_Pos)
	0x00800000
#define	EXTI_IMR1_IM23   EXTI_IMR1_IM23_Msk
	Interrupt Mask on line 23.
#define	EXTI_IMR1_IM24_Pos   (24U)
#define	EXTI_IMR1_IM24_Msk   (0x1UL << EXTI_IMR1_IM24_Pos)
	0x01000000
#define	EXTI_IMR1_IM24   EXTI_IMR1_IM24_Msk
	Interrupt Mask on line 24.
#define	EXTI_IMR1_IM25_Pos   (25U)
#define	EXTI_IMR1_IM25_Msk   (0x1UL << EXTI_IMR1_IM25_Pos)
	0x02000000
#define	EXTI_IMR1_IM25   EXTI_IMR1_IM25_Msk
	Interrupt Mask on line 25.
#define	EXTI_IMR1_IM26_Pos   (26U)
#define	EXTI_IMR1_IM26_Msk   (0x1UL << EXTI_IMR1_IM26_Pos)
	0x04000000
#define	EXTI_IMR1_IM26   EXTI_IMR1_IM26_Msk
	Interrupt Mask on line 26.
#define	EXTI_IMR1_IM27_Pos   (27U)
#define	EXTI_IMR1_IM27_Msk   (0x1UL << EXTI_IMR1_IM27_Pos)
	0x08000000
#define	EXTI_IMR1_IM27   EXTI_IMR1_IM27_Msk
	Interrupt Mask on line 27.
#define	EXTI_IMR1_IM28_Pos   (28U)
#define	EXTI_IMR1_IM28_Msk   (0x1UL << EXTI_IMR1_IM28_Pos)
	0x10000000
#define	EXTI_IMR1_IM28   EXTI_IMR1_IM28_Msk
	Interrupt Mask on line 28.
#define	EXTI_IMR1_IM29_Pos   (29U)
#define	EXTI_IMR1_IM29_Msk   (0x1UL << EXTI_IMR1_IM29_Pos)
	0x20000000
#define	EXTI_IMR1_IM29   EXTI_IMR1_IM29_Msk
	Interrupt Mask on line 29.
#define	EXTI_IMR1_IM30_Pos   (30U)
#define	EXTI_IMR1_IM30_Msk   (0x1UL << EXTI_IMR1_IM30_Pos)
	0x40000000
#define	EXTI_IMR1_IM30   EXTI_IMR1_IM30_Msk
	Interrupt Mask on line 30.
#define	EXTI_IMR1_IM31_Pos   (31U)
#define	EXTI_IMR1_IM31_Msk   (0x1UL << EXTI_IMR1_IM31_Pos)
	0x80000000
#define	EXTI_IMR1_IM31   EXTI_IMR1_IM31_Msk
	Interrupt Mask on line 31.
#define	EXTI_EMR1_EM_Pos   (0U)
#define	EXTI_EMR1_EM_Msk   (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)
	0xFFFFFFFF
#define	EXTI_EMR1_EM   EXTI_EMR1_EM_Msk
	Event Mask.
#define	EXTI_EMR1_EM0_Pos   (0U)
#define	EXTI_EMR1_EM0_Msk   (0x1UL << EXTI_EMR1_EM0_Pos)
	0x00000001
#define	EXTI_EMR1_EM0   EXTI_EMR1_EM0_Msk
	Event Mask on line 0.
#define	EXTI_EMR1_EM1_Pos   (1U)
#define	EXTI_EMR1_EM1_Msk   (0x1UL << EXTI_EMR1_EM1_Pos)
	0x00000002
#define	EXTI_EMR1_EM1   EXTI_EMR1_EM1_Msk
	Event Mask on line 1.
#define	EXTI_EMR1_EM2_Pos   (2U)
#define	EXTI_EMR1_EM2_Msk   (0x1UL << EXTI_EMR1_EM2_Pos)
	0x00000004
#define	EXTI_EMR1_EM2   EXTI_EMR1_EM2_Msk
	Event Mask on line 2.
#define	EXTI_EMR1_EM3_Pos   (3U)
#define	EXTI_EMR1_EM3_Msk   (0x1UL << EXTI_EMR1_EM3_Pos)
	0x00000008
#define	EXTI_EMR1_EM3   EXTI_EMR1_EM3_Msk
	Event Mask on line 3.
#define	EXTI_EMR1_EM4_Pos   (4U)
#define	EXTI_EMR1_EM4_Msk   (0x1UL << EXTI_EMR1_EM4_Pos)
	0x00000010
#define	EXTI_EMR1_EM4   EXTI_EMR1_EM4_Msk
	Event Mask on line 4.
#define	EXTI_EMR1_EM5_Pos   (5U)
#define	EXTI_EMR1_EM5_Msk   (0x1UL << EXTI_EMR1_EM5_Pos)
	0x00000020
#define	EXTI_EMR1_EM5   EXTI_EMR1_EM5_Msk
	Event Mask on line 5.
#define	EXTI_EMR1_EM6_Pos   (6U)
#define	EXTI_EMR1_EM6_Msk   (0x1UL << EXTI_EMR1_EM6_Pos)
	0x00000040
#define	EXTI_EMR1_EM6   EXTI_EMR1_EM6_Msk
	Event Mask on line 6.
#define	EXTI_EMR1_EM7_Pos   (7U)
#define	EXTI_EMR1_EM7_Msk   (0x1UL << EXTI_EMR1_EM7_Pos)
	0x00000080
#define	EXTI_EMR1_EM7   EXTI_EMR1_EM7_Msk
	Event Mask on line 7.
#define	EXTI_EMR1_EM8_Pos   (8U)
#define	EXTI_EMR1_EM8_Msk   (0x1UL << EXTI_EMR1_EM8_Pos)
	0x00000100
#define	EXTI_EMR1_EM8   EXTI_EMR1_EM8_Msk
	Event Mask on line 8.
#define	EXTI_EMR1_EM9_Pos   (9U)
#define	EXTI_EMR1_EM9_Msk   (0x1UL << EXTI_EMR1_EM9_Pos)
	0x00000200
#define	EXTI_EMR1_EM9   EXTI_EMR1_EM9_Msk
	Event Mask on line 9.
#define	EXTI_EMR1_EM10_Pos   (10U)
#define	EXTI_EMR1_EM10_Msk   (0x1UL << EXTI_EMR1_EM10_Pos)
	0x00000400
#define	EXTI_EMR1_EM10   EXTI_EMR1_EM10_Msk
	Event Mask on line 10.
#define	EXTI_EMR1_EM11_Pos   (11U)
#define	EXTI_EMR1_EM11_Msk   (0x1UL << EXTI_EMR1_EM11_Pos)
	0x00000800
#define	EXTI_EMR1_EM11   EXTI_EMR1_EM11_Msk
	Event Mask on line 11.
#define	EXTI_EMR1_EM12_Pos   (12U)
#define	EXTI_EMR1_EM12_Msk   (0x1UL << EXTI_EMR1_EM12_Pos)
	0x00001000
#define	EXTI_EMR1_EM12   EXTI_EMR1_EM12_Msk
	Event Mask on line 12.
#define	EXTI_EMR1_EM13_Pos   (13U)
#define	EXTI_EMR1_EM13_Msk   (0x1UL << EXTI_EMR1_EM13_Pos)
	0x00002000
#define	EXTI_EMR1_EM13   EXTI_EMR1_EM13_Msk
	Event Mask on line 13.
#define	EXTI_EMR1_EM14_Pos   (14U)
#define	EXTI_EMR1_EM14_Msk   (0x1UL << EXTI_EMR1_EM14_Pos)
	0x00004000
#define	EXTI_EMR1_EM14   EXTI_EMR1_EM14_Msk
	Event Mask on line 14.
#define	EXTI_EMR1_EM15_Pos   (15U)
#define	EXTI_EMR1_EM15_Msk   (0x1UL << EXTI_EMR1_EM15_Pos)
	0x00008000
#define	EXTI_EMR1_EM15   EXTI_EMR1_EM15_Msk
	Event Mask on line 15.
#define	EXTI_EMR1_EM16_Pos   (16U)
#define	EXTI_EMR1_EM16_Msk   (0x1UL << EXTI_EMR1_EM16_Pos)
	0x00010000
#define	EXTI_EMR1_EM16   EXTI_EMR1_EM16_Msk
	Event Mask on line 16.
#define	EXTI_EMR1_EM17_Pos   (17U)
#define	EXTI_EMR1_EM17_Msk   (0x1UL << EXTI_EMR1_EM17_Pos)
	0x00020000
#define	EXTI_EMR1_EM17   EXTI_EMR1_EM17_Msk
	Event Mask on line 17.
#define	EXTI_EMR1_EM18_Pos   (18U)
#define	EXTI_EMR1_EM18_Msk   (0x1UL << EXTI_EMR1_EM18_Pos)
	0x00040000
#define	EXTI_EMR1_EM18   EXTI_EMR1_EM18_Msk
	Event Mask on line 18.
#define	EXTI_EMR1_EM20_Pos   (20U)
#define	EXTI_EMR1_EM20_Msk   (0x1UL << EXTI_EMR1_EM20_Pos)
	0x00100000
#define	EXTI_EMR1_EM20   EXTI_EMR1_EM20_Msk
	Event Mask on line 20.
#define	EXTI_EMR1_EM21_Pos   (21U)
#define	EXTI_EMR1_EM21_Msk   (0x1UL << EXTI_EMR1_EM21_Pos)
	0x00200000
#define	EXTI_EMR1_EM21   EXTI_EMR1_EM21_Msk
	Event Mask on line 21.
#define	EXTI_EMR1_EM22_Pos   (22U)
#define	EXTI_EMR1_EM22_Msk   (0x1UL << EXTI_EMR1_EM22_Pos)
	0x00400000
#define	EXTI_EMR1_EM22   EXTI_EMR1_EM22_Msk
	Event Mask on line 22.
#define	EXTI_EMR1_EM23_Pos   (23U)
#define	EXTI_EMR1_EM23_Msk   (0x1UL << EXTI_EMR1_EM23_Pos)
	0x00800000
#define	EXTI_EMR1_EM23   EXTI_EMR1_EM23_Msk
	Event Mask on line 23.
#define	EXTI_EMR1_EM24_Pos   (24U)
#define	EXTI_EMR1_EM24_Msk   (0x1UL << EXTI_EMR1_EM24_Pos)
	0x01000000
#define	EXTI_EMR1_EM24   EXTI_EMR1_EM24_Msk
	Event Mask on line 24.
#define	EXTI_EMR1_EM25_Pos   (25U)
#define	EXTI_EMR1_EM25_Msk   (0x1UL << EXTI_EMR1_EM25_Pos)
	0x02000000
#define	EXTI_EMR1_EM25   EXTI_EMR1_EM25_Msk
	Event Mask on line 25.
#define	EXTI_EMR1_EM26_Pos   (26U)
#define	EXTI_EMR1_EM26_Msk   (0x1UL << EXTI_EMR1_EM26_Pos)
	0x04000000
#define	EXTI_EMR1_EM26   EXTI_EMR1_EM26_Msk
	Event Mask on line 26.
#define	EXTI_EMR1_EM27_Pos   (27U)
#define	EXTI_EMR1_EM27_Msk   (0x1UL << EXTI_EMR1_EM27_Pos)
	0x08000000
#define	EXTI_EMR1_EM27   EXTI_EMR1_EM27_Msk
	Event Mask on line 27.
#define	EXTI_EMR1_EM28_Pos   (28U)
#define	EXTI_EMR1_EM28_Msk   (0x1UL << EXTI_EMR1_EM28_Pos)
	0x10000000
#define	EXTI_EMR1_EM28   EXTI_EMR1_EM28_Msk
	Event Mask on line 28.
#define	EXTI_EMR1_EM29_Pos   (29U)
#define	EXTI_EMR1_EM29_Msk   (0x1UL << EXTI_EMR1_EM29_Pos)
	0x20000000
#define	EXTI_EMR1_EM29   EXTI_EMR1_EM29_Msk
	Event Mask on line 29.
#define	EXTI_EMR1_EM30_Pos   (30U)
#define	EXTI_EMR1_EM30_Msk   (0x1UL << EXTI_EMR1_EM30_Pos)
	0x40000000
#define	EXTI_EMR1_EM30   EXTI_EMR1_EM30_Msk
	Event Mask on line 30.
#define	EXTI_EMR1_EM31_Pos   (31U)
#define	EXTI_EMR1_EM31_Msk   (0x1UL << EXTI_EMR1_EM31_Pos)
	0x80000000
#define	EXTI_EMR1_EM31   EXTI_EMR1_EM31_Msk
	Event Mask on line 31.
#define	EXTI_PR1_PR_Pos   (0U)
#define	EXTI_PR1_PR_Msk   (0x3FFFFFUL << EXTI_PR1_PR_Pos)
	0x003FFFFF
#define	EXTI_PR1_PR   EXTI_PR1_PR_Msk
	Pending bit.
#define	EXTI_PR1_PR0_Pos   (0U)
#define	EXTI_PR1_PR0_Msk   (0x1UL << EXTI_PR1_PR0_Pos)
	0x00000001
#define	EXTI_PR1_PR0   EXTI_PR1_PR0_Msk
	Pending bit for line 0.
#define	EXTI_PR1_PR1_Pos   (1U)
#define	EXTI_PR1_PR1_Msk   (0x1UL << EXTI_PR1_PR1_Pos)
	0x00000002
#define	EXTI_PR1_PR1   EXTI_PR1_PR1_Msk
	Pending bit for line 1.
#define	EXTI_PR1_PR2_Pos   (2U)
#define	EXTI_PR1_PR2_Msk   (0x1UL << EXTI_PR1_PR2_Pos)
	0x00000004
#define	EXTI_PR1_PR2   EXTI_PR1_PR2_Msk
	Pending bit for line 2.
#define	EXTI_PR1_PR3_Pos   (3U)
#define	EXTI_PR1_PR3_Msk   (0x1UL << EXTI_PR1_PR3_Pos)
	0x00000008
#define	EXTI_PR1_PR3   EXTI_PR1_PR3_Msk
	Pending bit for line 3.
#define	EXTI_PR1_PR4_Pos   (4U)
#define	EXTI_PR1_PR4_Msk   (0x1UL << EXTI_PR1_PR4_Pos)
	0x00000010
#define	EXTI_PR1_PR4   EXTI_PR1_PR4_Msk
	Pending bit for line 4.
#define	EXTI_PR1_PR5_Pos   (5U)
#define	EXTI_PR1_PR5_Msk   (0x1UL << EXTI_PR1_PR5_Pos)
	0x00000020
#define	EXTI_PR1_PR5   EXTI_PR1_PR5_Msk
	Pending bit for line 5.
#define	EXTI_PR1_PR6_Pos   (6U)
#define	EXTI_PR1_PR6_Msk   (0x1UL << EXTI_PR1_PR6_Pos)
	0x00000040
#define	EXTI_PR1_PR6   EXTI_PR1_PR6_Msk
	Pending bit for line 6.
#define	EXTI_PR1_PR7_Pos   (7U)
#define	EXTI_PR1_PR7_Msk   (0x1UL << EXTI_PR1_PR7_Pos)
	0x00000080
#define	EXTI_PR1_PR7   EXTI_PR1_PR7_Msk
	Pending bit for line 7.
#define	EXTI_PR1_PR8_Pos   (8U)
#define	EXTI_PR1_PR8_Msk   (0x1UL << EXTI_PR1_PR8_Pos)
	0x00000100
#define	EXTI_PR1_PR8   EXTI_PR1_PR8_Msk
	Pending bit for line 8.
#define	EXTI_PR1_PR9_Pos   (9U)
#define	EXTI_PR1_PR9_Msk   (0x1UL << EXTI_PR1_PR9_Pos)
	0x00000200
#define	EXTI_PR1_PR9   EXTI_PR1_PR9_Msk
	Pending bit for line 9.
#define	EXTI_PR1_PR10_Pos   (10U)
#define	EXTI_PR1_PR10_Msk   (0x1UL << EXTI_PR1_PR10_Pos)
	0x00000400
#define	EXTI_PR1_PR10   EXTI_PR1_PR10_Msk
	Pending bit for line 10.
#define	EXTI_PR1_PR11_Pos   (11U)
#define	EXTI_PR1_PR11_Msk   (0x1UL << EXTI_PR1_PR11_Pos)
	0x00000800
#define	EXTI_PR1_PR11   EXTI_PR1_PR11_Msk
	Pending bit for line 11.
#define	EXTI_PR1_PR12_Pos   (12U)
#define	EXTI_PR1_PR12_Msk   (0x1UL << EXTI_PR1_PR12_Pos)
	0x00001000
#define	EXTI_PR1_PR12   EXTI_PR1_PR12_Msk
	Pending bit for line 12.
#define	EXTI_PR1_PR13_Pos   (13U)
#define	EXTI_PR1_PR13_Msk   (0x1UL << EXTI_PR1_PR13_Pos)
	0x00002000
#define	EXTI_PR1_PR13   EXTI_PR1_PR13_Msk
	Pending bit for line 13.
#define	EXTI_PR1_PR14_Pos   (14U)
#define	EXTI_PR1_PR14_Msk   (0x1UL << EXTI_PR1_PR14_Pos)
	0x00004000
#define	EXTI_PR1_PR14   EXTI_PR1_PR14_Msk
	Pending bit for line 14.
#define	EXTI_PR1_PR15_Pos   (15U)
#define	EXTI_PR1_PR15_Msk   (0x1UL << EXTI_PR1_PR15_Pos)
	0x00008000
#define	EXTI_PR1_PR15   EXTI_PR1_PR15_Msk
	Pending bit for line 15.
#define	EXTI_PR1_PR16_Pos   (16U)
#define	EXTI_PR1_PR16_Msk   (0x1UL << EXTI_PR1_PR16_Pos)
	0x00010000
#define	EXTI_PR1_PR16   EXTI_PR1_PR16_Msk
	Pending bit for line 16.
#define	EXTI_PR1_PR17_Pos   (17U)
#define	EXTI_PR1_PR17_Msk   (0x1UL << EXTI_PR1_PR17_Pos)
	0x00020000
#define	EXTI_PR1_PR17   EXTI_PR1_PR17_Msk
	Pending bit for line 17.
#define	EXTI_PR1_PR18_Pos   (18U)
#define	EXTI_PR1_PR18_Msk   (0x1UL << EXTI_PR1_PR18_Pos)
	0x00040000
#define	EXTI_PR1_PR18   EXTI_PR1_PR18_Msk
	Pending bit for line 18.
#define	EXTI_PR1_PR19_Pos   (19U)
#define	EXTI_PR1_PR19_Msk   (0x1UL << EXTI_PR1_PR19_Pos)
	0x00080000
#define	EXTI_PR1_PR19   EXTI_PR1_PR19_Msk
	Pending bit for line 19.
#define	EXTI_PR1_PR20_Pos   (20U)
#define	EXTI_PR1_PR20_Msk   (0x1UL << EXTI_PR1_PR20_Pos)
	0x00100000
#define	EXTI_PR1_PR20   EXTI_PR1_PR20_Msk
	Pending bit for line 20.
#define	EXTI_PR1_PR21_Pos   (21U)
#define	EXTI_PR1_PR21_Msk   (0x1UL << EXTI_PR1_PR21_Pos)
	0x00200000
#define	EXTI_PR1_PR21   EXTI_PR1_PR21_Msk
	Pending bit for line 21.
#define	EXTI_IMR2_IM_Pos   (0U)
#define	EXTI_IMR2_IM_Msk   (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos)
	0xFFFFDFFF
#define	EXTI_IMR2_IM   EXTI_IMR2_IM_Msk
	Interrupt Mask.
#define	EXTI_IMR2_IM32_Pos   (0U)
#define	EXTI_IMR2_IM32_Msk   (0x1UL << EXTI_IMR2_IM32_Pos)
	0x00000001
#define	EXTI_IMR2_IM32   EXTI_IMR2_IM32_Msk
	Interrupt Mask on line 32.
#define	EXTI_IMR2_IM33_Pos   (1U)
#define	EXTI_IMR2_IM33_Msk   (0x1UL << EXTI_IMR2_IM33_Pos)
	0x00000002
#define	EXTI_IMR2_IM33   EXTI_IMR2_IM33_Msk
	Interrupt Mask on line 33.
#define	EXTI_IMR2_IM34_Pos   (2U)
#define	EXTI_IMR2_IM34_Msk   (0x1UL << EXTI_IMR2_IM34_Pos)
	0x00000004
#define	EXTI_IMR2_IM34   EXTI_IMR2_IM34_Msk
	Interrupt Mask on line 34.
#define	EXTI_IMR2_IM35_Pos   (3U)
#define	EXTI_IMR2_IM35_Msk   (0x1UL << EXTI_IMR2_IM35_Pos)
	0x00000008
#define	EXTI_IMR2_IM35   EXTI_IMR2_IM35_Msk
	Interrupt Mask on line 35.
#define	EXTI_IMR2_IM36_Pos   (4U)
#define	EXTI_IMR2_IM36_Msk   (0x1UL << EXTI_IMR2_IM36_Pos)
	0x00000010
#define	EXTI_IMR2_IM36   EXTI_IMR2_IM36_Msk
	Interrupt Mask on line 36.
#define	EXTI_IMR2_IM37_Pos   (5U)
#define	EXTI_IMR2_IM37_Msk   (0x1UL << EXTI_IMR2_IM37_Pos)
	0x00000020
#define	EXTI_IMR2_IM37   EXTI_IMR2_IM37_Msk
	Interrupt Mask on line 37.
#define	EXTI_IMR2_IM38_Pos   (6U)
#define	EXTI_IMR2_IM38_Msk   (0x1UL << EXTI_IMR2_IM38_Pos)
	0x00000040
#define	EXTI_IMR2_IM38   EXTI_IMR2_IM38_Msk
	Interrupt Mask on line 38.
#define	EXTI_IMR2_IM39_Pos   (7U)
#define	EXTI_IMR2_IM39_Msk   (0x1UL << EXTI_IMR2_IM39_Pos)
	0x00000080
#define	EXTI_IMR2_IM39   EXTI_IMR2_IM39_Msk
	Interrupt Mask on line 39.
#define	EXTI_IMR2_IM40_Pos   (8U)
#define	EXTI_IMR2_IM40_Msk   (0x1UL << EXTI_IMR2_IM40_Pos)
	0x00000100
#define	EXTI_IMR2_IM40   EXTI_IMR2_IM40_Msk
	Interrupt Mask on line 40.
#define	EXTI_IMR2_IM41_Pos   (9U)
#define	EXTI_IMR2_IM41_Msk   (0x1UL << EXTI_IMR2_IM41_Pos)
	0x00000200
#define	EXTI_IMR2_IM41   EXTI_IMR2_IM41_Msk
	Interrupt Mask on line 41.
#define	EXTI_IMR2_IM42_Pos   (10U)
#define	EXTI_IMR2_IM42_Msk   (0x1UL << EXTI_IMR2_IM42_Pos)
	0x00000400
#define	EXTI_IMR2_IM42   EXTI_IMR2_IM42_Msk
	Interrupt Mask on line 42.
#define	EXTI_IMR2_IM43_Pos   (11U)
#define	EXTI_IMR2_IM43_Msk   (0x1UL << EXTI_IMR2_IM43_Pos)
	0x00000800
#define	EXTI_IMR2_IM43   EXTI_IMR2_IM43_Msk
	Interrupt Mask on line 43.
#define	EXTI_IMR2_IM47_Pos   (15U)
#define	EXTI_IMR2_IM47_Msk   (0x1UL << EXTI_IMR2_IM47_Pos)
	0x00008000
#define	EXTI_IMR2_IM47   EXTI_IMR2_IM47_Msk
	Interrupt Mask on line 47.
#define	EXTI_IMR2_IM48_Pos   (16U)
#define	EXTI_IMR2_IM48_Msk   (0x1UL << EXTI_IMR2_IM48_Pos)
	0x00010000
#define	EXTI_IMR2_IM48   EXTI_IMR2_IM48_Msk
	Interrupt Mask on line 48.
#define	EXTI_IMR2_IM49_Pos   (17U)
#define	EXTI_IMR2_IM49_Msk   (0x1UL << EXTI_IMR2_IM49_Pos)
	0x00020000
#define	EXTI_IMR2_IM49   EXTI_IMR2_IM49_Msk
	Interrupt Mask on line 49.
#define	EXTI_IMR2_IM50_Pos   (18U)
#define	EXTI_IMR2_IM50_Msk   (0x1UL << EXTI_IMR2_IM50_Pos)
	0x00040000
#define	EXTI_IMR2_IM50   EXTI_IMR2_IM50_Msk
	Interrupt Mask on line 50.
#define	EXTI_IMR2_IM51_Pos   (19U)
#define	EXTI_IMR2_IM51_Msk   (0x1UL << EXTI_IMR2_IM51_Pos)
	0x00080000
#define	EXTI_IMR2_IM51   EXTI_IMR2_IM51_Msk
	Interrupt Mask on line 51.
#define	EXTI_IMR2_IM52_Pos   (20U)
#define	EXTI_IMR2_IM52_Msk   (0x1UL << EXTI_IMR2_IM52_Pos)
	0x00100000
#define	EXTI_IMR2_IM52   EXTI_IMR2_IM52_Msk
	Interrupt Mask on line 52.
#define	EXTI_IMR2_IM53_Pos   (21U)
#define	EXTI_IMR2_IM53_Msk   (0x1UL << EXTI_IMR2_IM53_Pos)
	0x00200000
#define	EXTI_IMR2_IM53   EXTI_IMR2_IM53_Msk
	Interrupt Mask on line 53.
#define	EXTI_IMR2_IM54_Pos   (22U)
#define	EXTI_IMR2_IM54_Msk   (0x1UL << EXTI_IMR2_IM54_Pos)
	0x00400000
#define	EXTI_IMR2_IM54   EXTI_IMR2_IM54_Msk
	Interrupt Mask on line 54.
#define	EXTI_IMR2_IM55_Pos   (23U)
#define	EXTI_IMR2_IM55_Msk   (0x1UL << EXTI_IMR2_IM55_Pos)
	0x00800000
#define	EXTI_IMR2_IM55   EXTI_IMR2_IM55_Msk
	Interrupt Mask on line 55.
#define	EXTI_IMR2_IM56_Pos   (24U)
#define	EXTI_IMR2_IM56_Msk   (0x1UL << EXTI_IMR2_IM56_Pos)
	0x01000000
#define	EXTI_IMR2_IM56   EXTI_IMR2_IM56_Msk
	Interrupt Mask on line 56.
#define	EXTI_IMR2_IM58_Pos   (26U)
#define	EXTI_IMR2_IM58_Msk   (0x1UL << EXTI_IMR2_IM58_Pos)
	0x04000000
#define	EXTI_IMR2_IM58   EXTI_IMR2_IM58_Msk
	Interrupt Mask on line 58.
#define	EXTI_IMR2_IM60_Pos   (28U)
#define	EXTI_IMR2_IM60_Msk   (0x1UL << EXTI_IMR2_IM60_Pos)
	0x10000000
#define	EXTI_IMR2_IM60   EXTI_IMR2_IM60_Msk
	Interrupt Mask on line 60.
#define	EXTI_IMR2_IM61_Pos   (29U)
#define	EXTI_IMR2_IM61_Msk   (0x1UL << EXTI_IMR2_IM61_Pos)
	0x20000000
#define	EXTI_IMR2_IM61   EXTI_IMR2_IM61_Msk
	Interrupt Mask on line 61.
#define	EXTI_IMR2_IM62_Pos   (30U)
#define	EXTI_IMR2_IM62_Msk   (0x1UL << EXTI_IMR2_IM62_Pos)
	0x40000000
#define	EXTI_IMR2_IM62   EXTI_IMR2_IM62_Msk
	Interrupt Mask on line 62.
#define	EXTI_IMR2_IM63_Pos   (31U)
#define	EXTI_IMR2_IM63_Msk   (0x1UL << EXTI_IMR2_IM63_Pos)
	0x80000000
#define	EXTI_IMR2_IM63   EXTI_IMR2_IM63_Msk
	Interrupt Mask on line 63.
#define	EXTI_EMR2_EM_Pos   (0U)
#define	EXTI_EMR2_EM_Msk   (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos)
	0xFFFFDFFF
#define	EXTI_EMR2_EM   EXTI_EMR2_EM_Msk
	Event Mask.
#define	EXTI_EMR2_EM32_Pos   (0U)
#define	EXTI_EMR2_EM32_Msk   (0x1UL << EXTI_EMR2_EM32_Pos)
	0x00000001
#define	EXTI_EMR2_EM32   EXTI_EMR2_EM32_Msk
	Event Mask on line 32.
#define	EXTI_EMR2_EM33_Pos   (1U)
#define	EXTI_EMR2_EM33_Msk   (0x1UL << EXTI_EMR2_EM33_Pos)
	0x00000002
#define	EXTI_EMR2_EM33   EXTI_EMR2_EM33_Msk
	Event Mask on line 33.
#define	EXTI_EMR2_EM34_Pos   (2U)
#define	EXTI_EMR2_EM34_Msk   (0x1UL << EXTI_EMR2_EM34_Pos)
	0x00000004
#define	EXTI_EMR2_EM34   EXTI_EMR2_EM34_Msk
	Event Mask on line 34.
#define	EXTI_EMR2_EM35_Pos   (3U)
#define	EXTI_EMR2_EM35_Msk   (0x1UL << EXTI_EMR2_EM35_Pos)
	0x00000008
#define	EXTI_EMR2_EM35   EXTI_EMR2_EM35_Msk
	Event Mask on line 35.
#define	EXTI_EMR2_EM36_Pos   (4U)
#define	EXTI_EMR2_EM36_Msk   (0x1UL << EXTI_EMR2_EM36_Pos)
	0x00000010
#define	EXTI_EMR2_EM36   EXTI_EMR2_EM36_Msk
	Event Mask on line 36.
#define	EXTI_EMR2_EM37_Pos   (5U)
#define	EXTI_EMR2_EM37_Msk   (0x1UL << EXTI_EMR2_EM37_Pos)
	0x00000020
#define	EXTI_EMR2_EM37   EXTI_EMR2_EM37_Msk
	Event Mask on line 37.
#define	EXTI_EMR2_EM38_Pos   (6U)
#define	EXTI_EMR2_EM38_Msk   (0x1UL << EXTI_EMR2_EM38_Pos)
	0x00000040
#define	EXTI_EMR2_EM38   EXTI_EMR2_EM38_Msk
	Event Mask on line 38.
#define	EXTI_EMR2_EM39_Pos   (7U)
#define	EXTI_EMR2_EM39_Msk   (0x1UL << EXTI_EMR2_EM39_Pos)
	0x00000080
#define	EXTI_EMR2_EM39   EXTI_EMR2_EM39_Msk
	Event Mask on line 39.
#define	EXTI_EMR2_EM40_Pos   (8U)
#define	EXTI_EMR2_EM40_Msk   (0x1UL << EXTI_EMR2_EM40_Pos)
	0x00000100
#define	EXTI_EMR2_EM40   EXTI_EMR2_EM40_Msk
	Event Mask on line 40.
#define	EXTI_EMR2_EM41_Pos   (9U)
#define	EXTI_EMR2_EM41_Msk   (0x1UL << EXTI_EMR2_EM41_Pos)
	0x00000200
#define	EXTI_EMR2_EM41   EXTI_EMR2_EM41_Msk
	Event Mask on line 41.
#define	EXTI_EMR2_EM42_Pos   (10U)
#define	EXTI_EMR2_EM42_Msk   (0x1UL << EXTI_EMR2_EM42_Pos)
	0x00000400
#define	EXTI_EMR2_EM42   EXTI_EMR2_EM42_Msk
	Event Mask on line 42.
#define	EXTI_EMR2_EM43_Pos   (11U)
#define	EXTI_EMR2_EM43_Msk   (0x1UL << EXTI_EMR2_EM43_Pos)
	0x00000800
#define	EXTI_EMR2_EM43   EXTI_EMR2_EM43_Msk
	Event Mask on line 43.
#define	EXTI_EMR2_EM47_Pos   (15U)
#define	EXTI_EMR2_EM47_Msk   (0x1UL << EXTI_EMR2_EM47_Pos)
	0x00008000
#define	EXTI_EMR2_EM47   EXTI_EMR2_EM47_Msk
	Event Mask on line 47.
#define	EXTI_EMR2_EM48_Pos   (16U)
#define	EXTI_EMR2_EM48_Msk   (0x1UL << EXTI_EMR2_EM48_Pos)
	0x00010000
#define	EXTI_EMR2_EM48   EXTI_EMR2_EM48_Msk
	Event Mask on line 48.
#define	EXTI_EMR2_EM49_Pos   (17U)
#define	EXTI_EMR2_EM49_Msk   (0x1UL << EXTI_EMR2_EM49_Pos)
	0x00020000
#define	EXTI_EMR2_EM49   EXTI_EMR2_EM49_Msk
	Event Mask on line 49.
#define	EXTI_EMR2_EM50_Pos   (18U)
#define	EXTI_EMR2_EM50_Msk   (0x1UL << EXTI_EMR2_EM50_Pos)
	0x00040000
#define	EXTI_EMR2_EM50   EXTI_EMR2_EM50_Msk
	Event Mask on line 50.
#define	EXTI_EMR2_EM51_Pos   (19U)
#define	EXTI_EMR2_EM51_Msk   (0x1UL << EXTI_EMR2_EM51_Pos)
	0x00080000
#define	EXTI_EMR2_EM51   EXTI_EMR2_EM51_Msk
	Event Mask on line 51.
#define	EXTI_EMR2_EM52_Pos   (20U)
#define	EXTI_EMR2_EM52_Msk   (0x1UL << EXTI_EMR2_EM52_Pos)
	0x00100000
#define	EXTI_EMR2_EM52   EXTI_EMR2_EM52_Msk
	Event Mask on line 52.
#define	EXTI_EMR2_EM53_Pos   (21U)
#define	EXTI_EMR2_EM53_Msk   (0x1UL << EXTI_EMR2_EM53_Pos)
	0x00200000
#define	EXTI_EMR2_EM53   EXTI_EMR2_EM53_Msk
	Event Mask on line 53.
#define	EXTI_EMR2_EM54_Pos   (22U)
#define	EXTI_EMR2_EM54_Msk   (0x1UL << EXTI_EMR2_EM54_Pos)
	0x00400000
#define	EXTI_EMR2_EM54   EXTI_EMR2_EM54_Msk
	Event Mask on line 54.
#define	EXTI_EMR2_EM55_Pos   (23U)
#define	EXTI_EMR2_EM55_Msk   (0x1UL << EXTI_EMR2_EM55_Pos)
	0x00800000
#define	EXTI_EMR2_EM55   EXTI_EMR2_EM55_Msk
	Event Mask on line 55.
#define	EXTI_EMR2_EM56_Pos   (24U)
#define	EXTI_EMR2_EM56_Msk   (0x1UL << EXTI_EMR2_EM56_Pos)
	0x01000000
#define	EXTI_EMR2_EM56   EXTI_EMR2_EM56_Msk
	Event Mask on line 56.
#define	EXTI_EMR2_EM58_Pos   (26U)
#define	EXTI_EMR2_EM58_Msk   (0x1UL << EXTI_EMR2_EM58_Pos)
	0x04000000
#define	EXTI_EMR2_EM58   EXTI_EMR2_EM58_Msk
	Event Mask on line 58.
#define	EXTI_EMR2_EM60_Pos   (28U)
#define	EXTI_EMR2_EM60_Msk   (0x1UL << EXTI_EMR2_EM60_Pos)
	0x10000000
#define	EXTI_EMR2_EM60   EXTI_EMR2_EM60_Msk
	Event Mask on line 60.
#define	EXTI_EMR2_EM61_Pos   (29U)
#define	EXTI_EMR2_EM61_Msk   (0x1UL << EXTI_EMR2_EM61_Pos)
	0x20000000
#define	EXTI_EMR2_EM61   EXTI_EMR2_EM61_Msk
	Event Mask on line 61.
#define	EXTI_EMR2_EM62_Pos   (30U)
#define	EXTI_EMR2_EM62_Msk   (0x1UL << EXTI_EMR2_EM62_Pos)
	0x40000000
#define	EXTI_EMR2_EM62   EXTI_EMR2_EM62_Msk
	Event Mask on line 62.
#define	EXTI_EMR2_EM63_Pos   (31U)
#define	EXTI_EMR2_EM63_Msk   (0x1UL << EXTI_EMR2_EM63_Pos)
	0x80000000
#define	EXTI_EMR2_EM63   EXTI_EMR2_EM63_Msk
	Event Mask on line 63.
#define	EXTI_PR2_PR_Pos   (17U)
#define	EXTI_PR2_PR_Msk   (0x5UL << EXTI_PR2_PR_Pos)
	0x000A0000
#define	EXTI_PR2_PR   EXTI_PR2_PR_Msk
	Pending bit.
#define	EXTI_PR2_PR49_Pos   (17U)
#define	EXTI_PR2_PR49_Msk   (0x1UL << EXTI_PR2_PR49_Pos)
	0x00020000
#define	EXTI_PR2_PR49   EXTI_PR2_PR49_Msk
	Pending bit for line 49.
#define	EXTI_PR2_PR51_Pos   (19U)
#define	EXTI_PR2_PR51_Msk   (0x1UL << EXTI_PR2_PR51_Pos)
	0x00080000
#define	EXTI_PR2_PR51   EXTI_PR2_PR51_Msk
	Pending bit for line 51.
#define	EXTI_IMR3_IM_Pos   (0U)
#define	EXTI_IMR3_IM_Msk   (0x0FE17FFFUL << EXTI_IMR3_IM_Pos)
	0x0FE17FFF
#define	EXTI_IMR3_IM   EXTI_IMR3_IM_Msk
	Interrupt Mask.
#define	EXTI_IMR3_IM64_Pos   (0U)
#define	EXTI_IMR3_IM64_Msk   (0x1UL << EXTI_IMR3_IM64_Pos)
	0x00000001
#define	EXTI_IMR3_IM64   EXTI_IMR3_IM64_Msk
	Interrupt Mask on line 64.
#define	EXTI_IMR3_IM65_Pos   (1U)
#define	EXTI_IMR3_IM65_Msk   (0x1UL << EXTI_IMR3_IM65_Pos)
	0x00000002
#define	EXTI_IMR3_IM65   EXTI_IMR3_IM65_Msk
	Interrupt Mask on line 65.
#define	EXTI_IMR3_IM66_Pos   (2U)
#define	EXTI_IMR3_IM66_Msk   (0x1UL << EXTI_IMR3_IM66_Pos)
	0x00000004
#define	EXTI_IMR3_IM66   EXTI_IMR3_IM66_Msk
	Interrupt Mask on line 66.
#define	EXTI_IMR3_IM67_Pos   (3U)
#define	EXTI_IMR3_IM67_Msk   (0x1UL << EXTI_IMR3_IM67_Pos)
	0x00000008
#define	EXTI_IMR3_IM67   EXTI_IMR3_IM67_Msk
	Interrupt Mask on line 67.
#define	EXTI_IMR3_IM68_Pos   (4U)
#define	EXTI_IMR3_IM68_Msk   (0x1UL << EXTI_IMR3_IM68_Pos)
	0x00000010
#define	EXTI_IMR3_IM68   EXTI_IMR3_IM68_Msk
	Interrupt Mask on line 68.
#define	EXTI_IMR3_IM69_Pos   (5U)
#define	EXTI_IMR3_IM69_Msk   (0x1UL << EXTI_IMR3_IM69_Pos)
	0x00000020
#define	EXTI_IMR3_IM69   EXTI_IMR3_IM69_Msk
	Interrupt Mask on line 69.
#define	EXTI_IMR3_IM70_Pos   (6U)
#define	EXTI_IMR3_IM70_Msk   (0x1UL << EXTI_IMR3_IM70_Pos)
	0x00000040
#define	EXTI_IMR3_IM70   EXTI_IMR3_IM70_Msk
	Interrupt Mask on line 70.
#define	EXTI_IMR3_IM71_Pos   (7U)
#define	EXTI_IMR3_IM71_Msk   (0x1UL << EXTI_IMR3_IM71_Pos)
	0x00000080
#define	EXTI_IMR3_IM71   EXTI_IMR3_IM71_Msk
	Interrupt Mask on line 71.
#define	EXTI_IMR3_IM72_Pos   (8U)
#define	EXTI_IMR3_IM72_Msk   (0x1UL << EXTI_IMR3_IM72_Pos)
	0x00000100
#define	EXTI_IMR3_IM72   EXTI_IMR3_IM72_Msk
	Interrupt Mask on line 72.
#define	EXTI_IMR3_IM73_Pos   (9U)
#define	EXTI_IMR3_IM73_Msk   (0x1UL << EXTI_IMR3_IM73_Pos)
	0x00000200
#define	EXTI_IMR3_IM73   EXTI_IMR3_IM73_Msk
	Interrupt Mask on line 73.
#define	EXTI_IMR3_IM74_Pos   (10U)
#define	EXTI_IMR3_IM74_Msk   (0x1UL << EXTI_IMR3_IM74_Pos)
	0x00000400
#define	EXTI_IMR3_IM74   EXTI_IMR3_IM74_Msk
	Interrupt Mask on line 74.
#define	EXTI_IMR3_IM75_Pos   (11U)
#define	EXTI_IMR3_IM75_Msk   (0x1UL << EXTI_IMR3_IM75_Pos)
	0x00000800
#define	EXTI_IMR3_IM75   EXTI_IMR3_IM75_Msk
	Interrupt Mask on line 75.
#define	EXTI_IMR3_IM76_Pos   (12U)
#define	EXTI_IMR3_IM76_Msk   (0x1UL << EXTI_IMR3_IM76_Pos)
	0x00001000
#define	EXTI_IMR3_IM76   EXTI_IMR3_IM76_Msk
	Interrupt Mask on line 76.
#define	EXTI_IMR3_IM77_Pos   (13U)
#define	EXTI_IMR3_IM77_Msk   (0x1UL << EXTI_IMR3_IM77_Pos)
	0x00002000
#define	EXTI_IMR3_IM77   EXTI_IMR3_IM77_Msk
	Interrupt Mask on line 77.
#define	EXTI_IMR3_IM78_Pos   (14U)
#define	EXTI_IMR3_IM78_Msk   (0x1UL << EXTI_IMR3_IM78_Pos)
	0x00004000
#define	EXTI_IMR3_IM78   EXTI_IMR3_IM78_Msk
	Interrupt Mask on line 78.
#define	EXTI_IMR3_IM80_Pos   (16U)
#define	EXTI_IMR3_IM80_Msk   (0x1UL << EXTI_IMR3_IM80_Pos)
	0x00010000
#define	EXTI_IMR3_IM80   EXTI_IMR3_IM80_Msk
	Interrupt Mask on line 80.
#define	EXTI_IMR3_IM85_Pos   (21U)
#define	EXTI_IMR3_IM85_Msk   (0x1UL << EXTI_IMR3_IM85_Pos)
	0x00200000
#define	EXTI_IMR3_IM85   EXTI_IMR3_IM85_Msk
	Interrupt Mask on line 85.
#define	EXTI_IMR3_IM86_Pos   (22U)
#define	EXTI_IMR3_IM86_Msk   (0x1UL << EXTI_IMR3_IM86_Pos)
	0x00400000
#define	EXTI_IMR3_IM86   EXTI_IMR3_IM86_Msk
	Interrupt Mask on line 86.
#define	EXTI_IMR3_IM87_Pos   (23U)
#define	EXTI_IMR3_IM87_Msk   (0x1UL << EXTI_IMR3_IM87_Pos)
	0x00800000
#define	EXTI_IMR3_IM87   EXTI_IMR3_IM87_Msk
	Interrupt Mask on line 87.
#define	EXTI_IMR3_IM88_Pos   (24U)
#define	EXTI_IMR3_IM88_Msk   (0x1UL << EXTI_IMR3_IM88_Pos)
	0x01000000
#define	EXTI_IMR3_IM88   EXTI_IMR3_IM88_Msk
	Interrupt Mask on line 88.
#define	EXTI_IMR3_IM89_Pos   (25U)
#define	EXTI_IMR3_IM89_Msk   (0x1UL << EXTI_IMR3_IM89_Pos)
	0x0200000
#define	EXTI_IMR3_IM89   EXTI_IMR3_IM89_Msk
	Interrupt Mask on line 89.
#define	EXTI_IMR3_IM90_Pos   (26U)
#define	EXTI_IMR3_IM90_Msk   (0x1UL << EXTI_IMR3_IM90_Pos)
	0x0400000
#define	EXTI_IMR3_IM90   EXTI_IMR3_IM90_Msk
	Interrupt Mask on line 90.
#define	EXTI_IMR3_IM91_Pos   (27U)
#define	EXTI_IMR3_IM91_Msk   (0x1UL << EXTI_IMR3_IM91_Pos)
	0x0800000
#define	EXTI_IMR3_IM91   EXTI_IMR3_IM91_Msk
	Interrupt Mask on line 91.
#define	EXTI_EMR3_EM_Pos   (0U)
#define	EXTI_EMR3_EM_Msk   (0x0FE17FFFUL << EXTI_EMR3_EM_Pos)
	0x0FE17FFF
#define	EXTI_EMR3_EM   EXTI_EMR3_EM_Msk
	Interrupt Mask.
#define	EXTI_EMR3_EM64_Pos   (0U)
#define	EXTI_EMR3_EM64_Msk   (0x1UL << EXTI_EMR3_EM64_Pos)
	0x00000001
#define	EXTI_EMR3_EM64   EXTI_EMR3_EM64_Msk
	Event Mask on line 64.
#define	EXTI_EMR3_EM65_Pos   (1U)
#define	EXTI_EMR3_EM65_Msk   (0x1UL << EXTI_EMR3_EM65_Pos)
	0x00000002
#define	EXTI_EMR3_EM65   EXTI_EMR3_EM65_Msk
	Event Mask on line 65.
#define	EXTI_EMR3_EM66_Pos   (2U)
#define	EXTI_EMR3_EM66_Msk   (0x1UL << EXTI_EMR3_EM66_Pos)
	0x00000004
#define	EXTI_EMR3_EM66   EXTI_EMR3_EM66_Msk
	Event Mask on line 66.
#define	EXTI_EMR3_EM67_Pos   (3U)
#define	EXTI_EMR3_EM67_Msk   (0x1UL << EXTI_EMR3_EM67_Pos)
	0x00000008
#define	EXTI_EMR3_EM67   EXTI_EMR3_EM67_Msk
	Event Mask on line 67.
#define	EXTI_EMR3_EM68_Pos   (4U)
#define	EXTI_EMR3_EM68_Msk   (0x1UL << EXTI_EMR3_EM68_Pos)
	0x00000010
#define	EXTI_EMR3_EM68   EXTI_EMR3_EM68_Msk
	Event Mask on line 68.
#define	EXTI_EMR3_EM69_Pos   (5U)
#define	EXTI_EMR3_EM69_Msk   (0x1UL << EXTI_EMR3_EM69_Pos)
	0x00000020
#define	EXTI_EMR3_EM69   EXTI_EMR3_EM69_Msk
	Event Mask on line 69.
#define	EXTI_EMR3_EM70_Pos   (6U)
#define	EXTI_EMR3_EM70_Msk   (0x1UL << EXTI_EMR3_EM70_Pos)
	0x00000040
#define	EXTI_EMR3_EM70   EXTI_EMR3_EM70_Msk
	Event Mask on line 70.
#define	EXTI_EMR3_EM71_Pos   (7U)
#define	EXTI_EMR3_EM71_Msk   (0x1UL << EXTI_EMR3_EM71_Pos)
	0x00000080
#define	EXTI_EMR3_EM71   EXTI_EMR3_EM71_Msk
	Event Mask on line 71.
#define	EXTI_EMR3_EM72_Pos   (8U)
#define	EXTI_EMR3_EM72_Msk   (0x1UL << EXTI_EMR3_EM72_Pos)
	0x00000100
#define	EXTI_EMR3_EM72   EXTI_EMR3_EM72_Msk
	Event Mask on line 72.
#define	EXTI_EMR3_EM73_Pos   (9U)
#define	EXTI_EMR3_EM73_Msk   (0x1UL << EXTI_EMR3_EM73_Pos)
	0x00000200
#define	EXTI_EMR3_EM73   EXTI_EMR3_EM73_Msk
	Event Mask on line 73.
#define	EXTI_EMR3_EM74_Pos   (10U)
#define	EXTI_EMR3_EM74_Msk   (0x1UL << EXTI_EMR3_EM74_Pos)
	0x00000400
#define	EXTI_EMR3_EM74   EXTI_EMR3_EM74_Msk
	Event Mask on line 74.
#define	EXTI_EMR3_EM75_Pos   (11U)
#define	EXTI_EMR3_EM75_Msk   (0x1UL << EXTI_EMR3_EM75_Pos)
	0x00000800
#define	EXTI_EMR3_EM75   EXTI_EMR3_EM75_Msk
	Event Mask on line 75.
#define	EXTI_EMR3_EM76_Pos   (12U)
#define	EXTI_EMR3_EM76_Msk   (0x1UL << EXTI_EMR3_EM76_Pos)
	0x00001000
#define	EXTI_EMR3_EM76   EXTI_EMR3_EM76_Msk
	Event Mask on line 76.
#define	EXTI_EMR3_EM77_Pos   (13U)
#define	EXTI_EMR3_EM77_Msk   (0x1UL << EXTI_EMR3_EM77_Pos)
	0x00002000
#define	EXTI_EMR3_EM77   EXTI_EMR3_EM77_Msk
	Event Mask on line 77.
#define	EXTI_EMR3_EM78_Pos   (14U)
#define	EXTI_EMR3_EM78_Msk   (0x1UL << EXTI_EMR3_EM78_Pos)
	0x00004000
#define	EXTI_EMR3_EM78   EXTI_EMR3_EM78_Msk
	Event Mask on line 78.
#define	EXTI_EMR3_EM80_Pos   (16U)
#define	EXTI_EMR3_EM80_Msk   (0x1UL << EXTI_EMR3_EM80_Pos)
	0x00010000
#define	EXTI_EMR3_EM80   EXTI_EMR3_EM80_Msk
	Event Mask on line 80.
#define	EXTI_EMR3_EM85_Pos   (21U)
#define	EXTI_EMR3_EM85_Msk   (0x1UL << EXTI_EMR3_EM85_Pos)
	0x00200000
#define	EXTI_EMR3_EM85   EXTI_EMR3_EM85_Msk
	Event Mask on line 85.
#define	EXTI_EMR3_EM86_Pos   (22U)
#define	EXTI_EMR3_EM86_Msk   (0x1UL << EXTI_EMR3_EM86_Pos)
	0x00400000
#define	EXTI_EMR3_EM86   EXTI_EMR3_EM86_Msk
	Event Mask on line 86.
#define	EXTI_EMR3_EM87_Pos   (23U)
#define	EXTI_EMR3_EM87_Msk   (0x1UL << EXTI_EMR3_EM87_Pos)
	0x00800000
#define	EXTI_EMR3_EM87   EXTI_EMR3_EM87_Msk
	Event Mask on line 87.
#define	EXTI_EMR3_EM88_Pos   (24U)
#define	EXTI_EMR3_EM88_Msk   (0x1UL << EXTI_EMR3_EM88_Pos)
	0x01000000
#define	EXTI_EMR3_EM88   EXTI_EMR3_EM88_Msk
	Event Mask on line 88.
#define	EXTI_EMR3_EM89_Pos   (25U)
#define	EXTI_EMR3_EM89_Msk   (0x1UL << EXTI_EMR3_EM89_Pos)
	0x0200000
#define	EXTI_EMR3_EM89   EXTI_EMR3_EM89_Msk
	Interrupt Mask on line 89.
#define	EXTI_EMR3_EM90_Pos   (26U)
#define	EXTI_EMR3_EM90_Msk   (0x1UL << EXTI_EMR3_EM90_Pos)
	0x0400000
#define	EXTI_EMR3_EM90   EXTI_EMR3_EM90_Msk
	Interrupt Mask on line 90.
#define	EXTI_EMR3_EM91_Pos   (27U)
#define	EXTI_EMR3_EM91_Msk   (0x1UL << EXTI_EMR3_EM91_Pos)
	0x0800000
#define	EXTI_EMR3_EM91   EXTI_EMR3_EM91_Msk
	Interrupt Mask on line 91.
#define	EXTI_PR3_PR_Pos   (20U)
#define	EXTI_PR3_PR_Msk   (0x7UL << EXTI_PR3_PR_Pos)
	0x00700000
#define	EXTI_PR3_PR   EXTI_PR3_PR_Msk
	Pending bit.
#define	EXTI_PR3_PR84_Pos   (20U)
#define	EXTI_PR3_PR84_Msk   (0x1UL << EXTI_PR3_PR84_Pos)
	0x00100000
#define	EXTI_PR3_PR84   EXTI_PR3_PR84_Msk
	Pending bit for line 84.
#define	EXTI_PR3_PR85_Pos   (21U)
#define	EXTI_PR3_PR85_Msk   (0x1UL << EXTI_PR3_PR85_Pos)
	0x00200000
#define	EXTI_PR3_PR85   EXTI_PR3_PR85_Msk
	Pending bit for line 85.
#define	EXTI_PR3_PR86_Pos   (22U)
#define	EXTI_PR3_PR86_Msk   (0x1UL << EXTI_PR3_PR86_Pos)
	0x00400000
#define	EXTI_PR3_PR86   EXTI_PR3_PR86_Msk
	Pending bit for line 86.
#define	FLASH_SIZE_DATA_REGISTER   0x1FF1E880U
#define	FLASH_SECTOR_TOTAL   8U /* 8 sectors */
#define	FLASH_SIZE
#define	FLASH_BANK_SIZE   FLASH_SIZE /* 1 MB */
#define	FLASH_SECTOR_SIZE   0x00020000UL /* 128 KB */
#define	FLASH_LATENCY_DEFAULT   FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
#define	FLASH_NB_32BITWORD_IN_FLASHWORD   8U /* 256 bits */
#define	FLASH_ACR_LATENCY_Pos   (0U)
#define	FLASH_ACR_LATENCY_Msk   (0xFUL << FLASH_ACR_LATENCY_Pos)
	0x0000000F: bit4 is kept only for legacy purpose
#define	FLASH_ACR_LATENCY   FLASH_ACR_LATENCY_Msk
	Read Latency.
#define	FLASH_ACR_LATENCY_0WS   (0x00000000UL)
#define	FLASH_ACR_LATENCY_1WS   (0x00000001UL)
#define	FLASH_ACR_LATENCY_2WS   (0x00000002UL)
#define	FLASH_ACR_LATENCY_3WS   (0x00000003UL)
#define	FLASH_ACR_LATENCY_4WS   (0x00000004UL)
#define	FLASH_ACR_LATENCY_5WS   (0x00000005UL)
#define	FLASH_ACR_LATENCY_6WS   (0x00000006UL)
#define	FLASH_ACR_LATENCY_7WS   (0x00000007UL)
#define	FLASH_ACR_WRHIGHFREQ_Pos   (4U)
#define	FLASH_ACR_WRHIGHFREQ_Msk   (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)
	0x00000030
#define	FLASH_ACR_WRHIGHFREQ   FLASH_ACR_WRHIGHFREQ_Msk
	Flash signal delay.
#define	FLASH_ACR_WRHIGHFREQ_0   (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)
	0x00000010
#define	FLASH_ACR_WRHIGHFREQ_1   (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)
	0x00000020
#define	FLASH_ACR_LATENCY_8WS   (0x00000008UL)
#define	FLASH_ACR_LATENCY_9WS   (0x00000009UL)
#define	FLASH_ACR_LATENCY_10WS   (0x0000000AUL)
#define	FLASH_ACR_LATENCY_11WS   (0x0000000BUL)
#define	FLASH_ACR_LATENCY_12WS   (0x0000000CUL)
#define	FLASH_ACR_LATENCY_13WS   (0x0000000DUL)
#define	FLASH_ACR_LATENCY_14WS   (0x0000000EUL)
#define	FLASH_ACR_LATENCY_15WS   (0x0000000FUL)
#define	FLASH_CR_LOCK_Pos   (0U)
#define	FLASH_CR_LOCK_Msk   (0x1UL << FLASH_CR_LOCK_Pos)
	0x00000001
#define	FLASH_CR_LOCK   FLASH_CR_LOCK_Msk
	Configuration lock bit.
#define	FLASH_CR_PG_Pos   (1U)
#define	FLASH_CR_PG_Msk   (0x1UL << FLASH_CR_PG_Pos)
	0x00000002
#define	FLASH_CR_PG   FLASH_CR_PG_Msk
	Internal buffer control bit.
#define	FLASH_CR_SER_Pos   (2U)
#define	FLASH_CR_SER_Msk   (0x1UL << FLASH_CR_SER_Pos)
	0x00000004
#define	FLASH_CR_SER   FLASH_CR_SER_Msk
	Sector erase request.
#define	FLASH_CR_BER_Pos   (3U)
#define	FLASH_CR_BER_Msk   (0x1UL << FLASH_CR_BER_Pos)
	0x00000008
#define	FLASH_CR_BER   FLASH_CR_BER_Msk
	Bank erase request.
#define	FLASH_CR_PSIZE_Pos   (4U)
#define	FLASH_CR_PSIZE_Msk   (0x3UL << FLASH_CR_PSIZE_Pos)
	0x00000030
#define	FLASH_CR_PSIZE   FLASH_CR_PSIZE_Msk
	Program size.
#define	FLASH_CR_PSIZE_0   (0x1UL << FLASH_CR_PSIZE_Pos)
	0x00000010
#define	FLASH_CR_PSIZE_1   (0x2UL << FLASH_CR_PSIZE_Pos)
	0x00000020
#define	FLASH_CR_FW_Pos   (6U)
#define	FLASH_CR_FW_Msk   (0x1UL << FLASH_CR_FW_Pos)
	0x00000040
#define	FLASH_CR_FW   FLASH_CR_FW_Msk
	Write forcing control bit.
#define	FLASH_CR_START_Pos   (7U)
#define	FLASH_CR_START_Msk   (0x1UL << FLASH_CR_START_Pos)
	0x00000080
#define	FLASH_CR_START   FLASH_CR_START_Msk
	Erase start control bit.
#define	FLASH_CR_SNB_Pos   (8U)
#define	FLASH_CR_SNB_Msk   (0x7UL << FLASH_CR_SNB_Pos)
	0x00000700
#define	FLASH_CR_SNB   FLASH_CR_SNB_Msk
	Sector erase selection number.
#define	FLASH_CR_SNB_0   (0x1UL << FLASH_CR_SNB_Pos)
	0x00000100
#define	FLASH_CR_SNB_1   (0x2UL << FLASH_CR_SNB_Pos)
	0x00000200
#define	FLASH_CR_SNB_2   (0x4UL << FLASH_CR_SNB_Pos)
	0x00000400
#define	FLASH_CR_CRC_EN_Pos   (15U)
#define	FLASH_CR_CRC_EN_Msk   (0x1UL << FLASH_CR_CRC_EN_Pos)
	0x00008000
#define	FLASH_CR_CRC_EN   FLASH_CR_CRC_EN_Msk
	CRC control bit.
#define	FLASH_CR_EOPIE_Pos   (16U)
#define	FLASH_CR_EOPIE_Msk   (0x1UL << FLASH_CR_EOPIE_Pos)
	0x00010000
#define	FLASH_CR_EOPIE   FLASH_CR_EOPIE_Msk
	End-of-program interrupt control bit.
#define	FLASH_CR_WRPERRIE_Pos   (17U)
#define	FLASH_CR_WRPERRIE_Msk   (0x1UL << FLASH_CR_WRPERRIE_Pos)
	0x00020000
#define	FLASH_CR_WRPERRIE   FLASH_CR_WRPERRIE_Msk
	Write protection error interrupt enable bit.
#define	FLASH_CR_PGSERRIE_Pos   (18U)
#define	FLASH_CR_PGSERRIE_Msk   (0x1UL << FLASH_CR_PGSERRIE_Pos)
	0x00040000
#define	FLASH_CR_PGSERRIE   FLASH_CR_PGSERRIE_Msk
	Programming sequence error interrupt enable bit.
#define	FLASH_CR_STRBERRIE_Pos   (19U)
#define	FLASH_CR_STRBERRIE_Msk   (0x1UL << FLASH_CR_STRBERRIE_Pos)
	0x00080000
#define	FLASH_CR_STRBERRIE   FLASH_CR_STRBERRIE_Msk
	Strobe error interrupt enable bit.
#define	FLASH_CR_INCERRIE_Pos   (21U)
#define	FLASH_CR_INCERRIE_Msk   (0x1UL << FLASH_CR_INCERRIE_Pos)
	0x00200000
#define	FLASH_CR_INCERRIE   FLASH_CR_INCERRIE_Msk
	Inconsistency error interrupt enable bit.
#define	FLASH_CR_OPERRIE_Pos   (22U)
#define	FLASH_CR_OPERRIE_Msk   (0x1UL << FLASH_CR_OPERRIE_Pos)
	0x00400000
#define	FLASH_CR_OPERRIE   FLASH_CR_OPERRIE_Msk
	Write/erase error interrupt enable bit.
#define	FLASH_CR_RDPERRIE_Pos   (23U)
#define	FLASH_CR_RDPERRIE_Msk   (0x1UL << FLASH_CR_RDPERRIE_Pos)
	0x00800000
#define	FLASH_CR_RDPERRIE   FLASH_CR_RDPERRIE_Msk
	Read protection error interrupt enable bit.
#define	FLASH_CR_RDSERRIE_Pos   (24U)
#define	FLASH_CR_RDSERRIE_Msk   (0x1UL << FLASH_CR_RDSERRIE_Pos)
	0x01000000
#define	FLASH_CR_RDSERRIE   FLASH_CR_RDSERRIE_Msk
	Secure error interrupt enable bit.
#define	FLASH_CR_SNECCERRIE_Pos   (25U)
#define	FLASH_CR_SNECCERRIE_Msk   (0x1UL << FLASH_CR_SNECCERRIE_Pos)
	0x02000000
#define	FLASH_CR_SNECCERRIE   FLASH_CR_SNECCERRIE_Msk
	ECC single correction error interrupt enable bit.
#define	FLASH_CR_DBECCERRIE_Pos   (26U)
#define	FLASH_CR_DBECCERRIE_Msk   (0x1UL << FLASH_CR_DBECCERRIE_Pos)
	0x04000000
#define	FLASH_CR_DBECCERRIE   FLASH_CR_DBECCERRIE_Msk
	ECC double detection error interrupt enable bit.
#define	FLASH_CR_CRCENDIE_Pos   (27U)
#define	FLASH_CR_CRCENDIE_Msk   (0x1UL << FLASH_CR_CRCENDIE_Pos)
	0x08000000
#define	FLASH_CR_CRCENDIE   FLASH_CR_CRCENDIE_Msk
	CRC end of calculation interrupt enable bit.
#define	FLASH_CR_CRCRDERRIE_Pos   (28U)
#define	FLASH_CR_CRCRDERRIE_Msk   (0x1UL << FLASH_CR_CRCRDERRIE_Pos)
	0x10000000
#define	FLASH_CR_CRCRDERRIE   FLASH_CR_CRCRDERRIE_Msk
	CRC read error interrupt enable bit.
#define	FLASH_SR_BSY_Pos   (0U)
#define	FLASH_SR_BSY_Msk   (0x1UL << FLASH_SR_BSY_Pos)
	0x00000001
#define	FLASH_SR_BSY   FLASH_SR_BSY_Msk
	Busy flag.
#define	FLASH_SR_WBNE_Pos   (1U)
#define	FLASH_SR_WBNE_Msk   (0x1UL << FLASH_SR_WBNE_Pos)
	0x00000002
#define	FLASH_SR_WBNE   FLASH_SR_WBNE_Msk
	Write buffer not empty flag.
#define	FLASH_SR_QW_Pos   (2U)
#define	FLASH_SR_QW_Msk   (0x1UL << FLASH_SR_QW_Pos)
	0x00000004
#define	FLASH_SR_QW   FLASH_SR_QW_Msk
	Wait queue flag.
#define	FLASH_SR_CRC_BUSY_Pos   (3U)
#define	FLASH_SR_CRC_BUSY_Msk   (0x1UL << FLASH_SR_CRC_BUSY_Pos)
	0x00000008
#define	FLASH_SR_CRC_BUSY   FLASH_SR_CRC_BUSY_Msk
	CRC busy flag.
#define	FLASH_SR_EOP_Pos   (16U)
#define	FLASH_SR_EOP_Msk   (0x1UL << FLASH_SR_EOP_Pos)
	0x00010000
#define	FLASH_SR_EOP   FLASH_SR_EOP_Msk
	End-of-program flag.
#define	FLASH_SR_WRPERR_Pos   (17U)
#define	FLASH_SR_WRPERR_Msk   (0x1UL << FLASH_SR_WRPERR_Pos)
	0x00020000
#define	FLASH_SR_WRPERR   FLASH_SR_WRPERR_Msk
	Write protection error flag.
#define	FLASH_SR_PGSERR_Pos   (18U)
#define	FLASH_SR_PGSERR_Msk   (0x1UL << FLASH_SR_PGSERR_Pos)
	0x00040000
#define	FLASH_SR_PGSERR   FLASH_SR_PGSERR_Msk
	Programming sequence error flag.
#define	FLASH_SR_STRBERR_Pos   (19U)
#define	FLASH_SR_STRBERR_Msk   (0x1UL << FLASH_SR_STRBERR_Pos)
	0x00080000
#define	FLASH_SR_STRBERR   FLASH_SR_STRBERR_Msk
	Strobe error flag.
#define	FLASH_SR_INCERR_Pos   (21U)
#define	FLASH_SR_INCERR_Msk   (0x1UL << FLASH_SR_INCERR_Pos)
	0x00200000
#define	FLASH_SR_INCERR   FLASH_SR_INCERR_Msk
	Inconsistency error flag.
#define	FLASH_SR_OPERR_Pos   (22U)
#define	FLASH_SR_OPERR_Msk   (0x1UL << FLASH_SR_OPERR_Pos)
	0x00400000
#define	FLASH_SR_OPERR   FLASH_SR_OPERR_Msk
	Write/erase error flag.
#define	FLASH_SR_RDPERR_Pos   (23U)
#define	FLASH_SR_RDPERR_Msk   (0x1UL << FLASH_SR_RDPERR_Pos)
	0x00800000
#define	FLASH_SR_RDPERR   FLASH_SR_RDPERR_Msk
	Read protection error flag.
#define	FLASH_SR_RDSERR_Pos   (24U)
#define	FLASH_SR_RDSERR_Msk   (0x1UL << FLASH_SR_RDSERR_Pos)
	0x01000000
#define	FLASH_SR_RDSERR   FLASH_SR_RDSERR_Msk
	Secure error flag.
#define	FLASH_SR_SNECCERR_Pos   (25U)
#define	FLASH_SR_SNECCERR_Msk   (0x1UL << FLASH_SR_SNECCERR_Pos)
	0x02000000
#define	FLASH_SR_SNECCERR   FLASH_SR_SNECCERR_Msk
	Single correction error flag.
#define	FLASH_SR_DBECCERR_Pos   (26U)
#define	FLASH_SR_DBECCERR_Msk   (0x1UL << FLASH_SR_DBECCERR_Pos)
	0x04000000
#define	FLASH_SR_DBECCERR   FLASH_SR_DBECCERR_Msk
	ECC double detection error flag.
#define	FLASH_SR_CRCEND_Pos   (27U)
#define	FLASH_SR_CRCEND_Msk   (0x1UL << FLASH_SR_CRCEND_Pos)
	0x08000000
#define	FLASH_SR_CRCEND   FLASH_SR_CRCEND_Msk
	CRC end of calculation flag.
#define	FLASH_SR_CRCRDERR_Pos   (28U)
#define	FLASH_SR_CRCRDERR_Msk   (0x1UL << FLASH_SR_CRCRDERR_Pos)
	0x10000000
#define	FLASH_SR_CRCRDERR   FLASH_SR_CRCRDERR_Msk
	CRC read error flag.
#define	FLASH_CCR_CLR_EOP_Pos   (16U)
#define	FLASH_CCR_CLR_EOP_Msk   (0x1UL << FLASH_CCR_CLR_EOP_Pos)
	0x00010000
#define	FLASH_CCR_CLR_EOP   FLASH_CCR_CLR_EOP_Msk
	EOP flag clear bit.
#define	FLASH_CCR_CLR_WRPERR_Pos   (17U)
#define	FLASH_CCR_CLR_WRPERR_Msk   (0x1UL << FLASH_CCR_CLR_WRPERR_Pos)
	0x00020000
#define	FLASH_CCR_CLR_WRPERR   FLASH_CCR_CLR_WRPERR_Msk
	WRPERR flag clear bit.
#define	FLASH_CCR_CLR_PGSERR_Pos   (18U)
#define	FLASH_CCR_CLR_PGSERR_Msk   (0x1UL << FLASH_CCR_CLR_PGSERR_Pos)
	0x00040000
#define	FLASH_CCR_CLR_PGSERR   FLASH_CCR_CLR_PGSERR_Msk
	PGSERR flag clear bit.
#define	FLASH_CCR_CLR_STRBERR_Pos   (19U)
#define	FLASH_CCR_CLR_STRBERR_Msk   (0x1UL << FLASH_CCR_CLR_STRBERR_Pos)
	0x00080000
#define	FLASH_CCR_CLR_STRBERR   FLASH_CCR_CLR_STRBERR_Msk
	STRBERR flag clear bit.
#define	FLASH_CCR_CLR_INCERR_Pos   (21U)
#define	FLASH_CCR_CLR_INCERR_Msk   (0x1UL << FLASH_CCR_CLR_INCERR_Pos)
	0x00200000
#define	FLASH_CCR_CLR_INCERR   FLASH_CCR_CLR_INCERR_Msk
	INCERR flag clear bit.
#define	FLASH_CCR_CLR_OPERR_Pos   (22U)
#define	FLASH_CCR_CLR_OPERR_Msk   (0x1UL << FLASH_CCR_CLR_OPERR_Pos)
	0x00400000
#define	FLASH_CCR_CLR_OPERR   FLASH_CCR_CLR_OPERR_Msk
	OPERR flag clear bit.
#define	FLASH_CCR_CLR_RDPERR_Pos   (23U)
#define	FLASH_CCR_CLR_RDPERR_Msk   (0x1UL << FLASH_CCR_CLR_RDPERR_Pos)
	0x00800000
#define	FLASH_CCR_CLR_RDPERR   FLASH_CCR_CLR_RDPERR_Msk
	RDPERR flag clear bit.
#define	FLASH_CCR_CLR_RDSERR_Pos   (24U)
#define	FLASH_CCR_CLR_RDSERR_Msk   (0x1UL << FLASH_CCR_CLR_RDSERR_Pos)
	0x01000000
#define	FLASH_CCR_CLR_RDSERR   FLASH_CCR_CLR_RDSERR_Msk
	RDSERR flag clear bit.
#define	FLASH_CCR_CLR_SNECCERR_Pos   (25U)
#define	FLASH_CCR_CLR_SNECCERR_Msk   (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos)
	0x02000000
#define	FLASH_CCR_CLR_SNECCERR   FLASH_CCR_CLR_SNECCERR_Msk
	SNECCERR flag clear bit.
#define	FLASH_CCR_CLR_DBECCERR_Pos   (26U)
#define	FLASH_CCR_CLR_DBECCERR_Msk   (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos)
	0x04000000
#define	FLASH_CCR_CLR_DBECCERR   FLASH_CCR_CLR_DBECCERR_Msk
	DBECCERR flag clear bit.
#define	FLASH_CCR_CLR_CRCEND_Pos   (27U)
#define	FLASH_CCR_CLR_CRCEND_Msk   (0x1UL << FLASH_CCR_CLR_CRCEND_Pos)
	0x08000000
#define	FLASH_CCR_CLR_CRCEND   FLASH_CCR_CLR_CRCEND_Msk
	CRCEND flag clear bit.
#define	FLASH_CCR_CLR_CRCRDERR_Pos   (28U)
#define	FLASH_CCR_CLR_CRCRDERR_Msk   (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos)
	0x10000000
#define	FLASH_CCR_CLR_CRCRDERR   FLASH_CCR_CLR_CRCRDERR_Msk
	CRCRDERR flag clear bit.
#define	FLASH_OPTCR_OPTLOCK_Pos   (0U)
#define	FLASH_OPTCR_OPTLOCK_Msk   (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
	0x00000001
#define	FLASH_OPTCR_OPTLOCK   FLASH_OPTCR_OPTLOCK_Msk
	FLASH_OPTCR lock option configuration bit.
#define	FLASH_OPTCR_OPTSTART_Pos   (1U)
#define	FLASH_OPTCR_OPTSTART_Msk   (0x1UL << FLASH_OPTCR_OPTSTART_Pos)
	0x00000002
#define	FLASH_OPTCR_OPTSTART   FLASH_OPTCR_OPTSTART_Msk
	Option byte start change option configuration bit.
#define	FLASH_OPTCR_OPTCHANGEERRIE_Pos   (30U)
#define	FLASH_OPTCR_OPTCHANGEERRIE_Msk   (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos)
	0x40000000
#define	FLASH_OPTCR_OPTCHANGEERRIE   FLASH_OPTCR_OPTCHANGEERRIE_Msk
	Option byte change error interrupt enable bit.
#define	FLASH_OPTSR_OPT_BUSY_Pos   (0U)
#define	FLASH_OPTSR_OPT_BUSY_Msk   (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos)
	0x00000001
#define	FLASH_OPTSR_OPT_BUSY   FLASH_OPTSR_OPT_BUSY_Msk
	Option byte change ongoing flag.
#define	FLASH_OPTSR_BOR_LEV_Pos   (2U)
#define	FLASH_OPTSR_BOR_LEV_Msk   (0x3UL << FLASH_OPTSR_BOR_LEV_Pos)
	0x0000000C
#define	FLASH_OPTSR_BOR_LEV   FLASH_OPTSR_BOR_LEV_Msk
	Brownout level option status bit.
#define	FLASH_OPTSR_BOR_LEV_0   (0x1UL << FLASH_OPTSR_BOR_LEV_Pos)
	0x00000004
#define	FLASH_OPTSR_BOR_LEV_1   (0x2UL << FLASH_OPTSR_BOR_LEV_Pos)
	0x00000008
#define	FLASH_OPTSR_IWDG1_SW_Pos   (4U)
#define	FLASH_OPTSR_IWDG1_SW_Msk   (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos)
	0x00000010
#define	FLASH_OPTSR_IWDG1_SW   FLASH_OPTSR_IWDG1_SW_Msk
	IWDG1 control mode option status bit.
#define	FLASH_OPTSR_NRST_STOP_D1_Pos   (6U)
#define	FLASH_OPTSR_NRST_STOP_D1_Msk   (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos)
	0x00000040
#define	FLASH_OPTSR_NRST_STOP_D1   FLASH_OPTSR_NRST_STOP_D1_Msk
	D1 domain DStop entry reset option status bit.
#define	FLASH_OPTSR_NRST_STBY_D1_Pos   (7U)
#define	FLASH_OPTSR_NRST_STBY_D1_Msk   (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos)
	0x00000080
#define	FLASH_OPTSR_NRST_STBY_D1   FLASH_OPTSR_NRST_STBY_D1_Msk
	D1 domain DStandby entry reset option status bit.
#define	FLASH_OPTSR_RDP_Pos   (8U)
#define	FLASH_OPTSR_RDP_Msk   (0xFFUL << FLASH_OPTSR_RDP_Pos)
	0x0000FF00
#define	FLASH_OPTSR_RDP   FLASH_OPTSR_RDP_Msk
	Readout protection level option status byte.
#define	FLASH_OPTSR_FZ_IWDG_STOP_Pos   (17U)
#define	FLASH_OPTSR_FZ_IWDG_STOP_Msk   (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos)
	0x00020000
#define	FLASH_OPTSR_FZ_IWDG_STOP   FLASH_OPTSR_FZ_IWDG_STOP_Msk
	IWDG Stop mode freeze option status bit.
#define	FLASH_OPTSR_FZ_IWDG_SDBY_Pos   (18U)
#define	FLASH_OPTSR_FZ_IWDG_SDBY_Msk   (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos)
	0x00040000
#define	FLASH_OPTSR_FZ_IWDG_SDBY   FLASH_OPTSR_FZ_IWDG_SDBY_Msk
	IWDG Standby mode freeze option status bit.
#define	FLASH_OPTSR_ST_RAM_SIZE_Pos   (19U)
#define	FLASH_OPTSR_ST_RAM_SIZE_Msk   (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos)
	0x00180000
#define	FLASH_OPTSR_ST_RAM_SIZE   FLASH_OPTSR_ST_RAM_SIZE_Msk
	ST RAM size option status.
#define	FLASH_OPTSR_ST_RAM_SIZE_0   (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos)
	0x00080000
#define	FLASH_OPTSR_ST_RAM_SIZE_1   (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos)
	0x00100000
#define	FLASH_OPTSR_SECURITY_Pos   (21U)
#define	FLASH_OPTSR_SECURITY_Msk   (0x1UL << FLASH_OPTSR_SECURITY_Pos)
	0x00200000
#define	FLASH_OPTSR_SECURITY   FLASH_OPTSR_SECURITY_Msk
	Security enable option status bit.
#define	FLASH_OPTSR_NRST_STOP_D2_Pos   (24U)
#define	FLASH_OPTSR_NRST_STOP_D2_Msk   (0x1UL << FLASH_OPTSR_NRST_STOP_D2_Pos)
	0x01000000
#define	FLASH_OPTSR_NRST_STOP_D2   FLASH_OPTSR_NRST_STOP_D2_Msk
	D2 domain DStop entry reset option status bit.
#define	FLASH_OPTSR_NRST_STBY_D2_Pos   (25U)
#define	FLASH_OPTSR_NRST_STBY_D2_Msk   (0x1UL << FLASH_OPTSR_NRST_STBY_D2_Pos)
	0x02000000
#define	FLASH_OPTSR_NRST_STBY_D2   FLASH_OPTSR_NRST_STBY_D2_Msk
	D2 domain DStandby entry reset option status bit.
#define	FLASH_OPTSR_IO_HSLV_Pos   (29U)
#define	FLASH_OPTSR_IO_HSLV_Msk   (0x1UL << FLASH_OPTSR_IO_HSLV_Pos)
	0x20000000
#define	FLASH_OPTSR_IO_HSLV   FLASH_OPTSR_IO_HSLV_Msk
	I/O high-speed at low-voltage status bit.
#define	FLASH_OPTSR_OPTCHANGEERR_Pos   (30U)
#define	FLASH_OPTSR_OPTCHANGEERR_Msk   (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos)
	0x40000000
#define	FLASH_OPTSR_OPTCHANGEERR   FLASH_OPTSR_OPTCHANGEERR_Msk
	Option byte change error flag.
#define	FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos   (30U)
#define	FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk   (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos)
	0x40000000
#define	FLASH_OPTCCR_CLR_OPTCHANGEERR   FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk
	OPTCHANGEERR reset bit.
#define	FLASH_PRAR_PROT_AREA_START_Pos   (0U)
#define	FLASH_PRAR_PROT_AREA_START_Msk   (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos)
	0x00000FFF
#define	FLASH_PRAR_PROT_AREA_START   FLASH_PRAR_PROT_AREA_START_Msk
	PCROP area start status bits.
#define	FLASH_PRAR_PROT_AREA_END_Pos   (16U)
#define	FLASH_PRAR_PROT_AREA_END_Msk   (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos)
	0x0FFF0000
#define	FLASH_PRAR_PROT_AREA_END   FLASH_PRAR_PROT_AREA_END_Msk
	PCROP area end status bits.
#define	FLASH_PRAR_DMEP_Pos   (31U)
#define	FLASH_PRAR_DMEP_Msk   (0x1UL << FLASH_PRAR_DMEP_Pos)
	0x80000000
#define	FLASH_PRAR_DMEP   FLASH_PRAR_DMEP_Msk
	PCROP protected erase enable option status bit.
#define	FLASH_SCAR_SEC_AREA_START_Pos   (0U)
#define	FLASH_SCAR_SEC_AREA_START_Msk   (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos)
	0x00000FFF
#define	FLASH_SCAR_SEC_AREA_START   FLASH_SCAR_SEC_AREA_START_Msk
	Secure-only area start status bits.
#define	FLASH_SCAR_SEC_AREA_END_Pos   (16U)
#define	FLASH_SCAR_SEC_AREA_END_Msk   (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos)
	0x0FFF0000
#define	FLASH_SCAR_SEC_AREA_END   FLASH_SCAR_SEC_AREA_END_Msk
	Secure-only area end status bits.
#define	FLASH_SCAR_DMES_Pos   (31U)
#define	FLASH_SCAR_DMES_Msk   (0x1UL << FLASH_SCAR_DMES_Pos)
	0x80000000
#define	FLASH_SCAR_DMES   FLASH_SCAR_DMES_Msk
	Secure access protected erase enable option status bit.
#define	FLASH_WPSN_WRPSN_Pos   (0U)
#define	FLASH_WPSN_WRPSN_Msk   (0xFFUL << FLASH_WPSN_WRPSN_Pos)
	0x000000FF
#define	FLASH_WPSN_WRPSN   FLASH_WPSN_WRPSN_Msk
	Sector write protection option status byte.
#define	FLASH_BOOT_ADD0_Pos   (0U)
#define	FLASH_BOOT_ADD0_Msk   (0xFFFFUL << FLASH_BOOT_ADD0_Pos)
	0x0000FFFF
#define	FLASH_BOOT_ADD0   FLASH_BOOT_ADD0_Msk
	Arm Cortex-M7 boot address 0.
#define	FLASH_BOOT_ADD1_Pos   (16U)
#define	FLASH_BOOT_ADD1_Msk   (0xFFFFUL << FLASH_BOOT_ADD1_Pos)
	0xFFFF0000
#define	FLASH_BOOT_ADD1   FLASH_BOOT_ADD1_Msk
	Arm Cortex-M7 boot address 1.
#define	FLASH_CRCCR_CRC_SECT_Pos   (0U)
#define	FLASH_CRCCR_CRC_SECT_Msk   (0x7UL << FLASH_CRCCR_CRC_SECT_Pos)
	0x00000007
#define	FLASH_CRCCR_CRC_SECT   FLASH_CRCCR_CRC_SECT_Msk
	CRC sector number.
#define	FLASH_CRCCR_CRC_BY_SECT_Pos   (8U)
#define	FLASH_CRCCR_CRC_BY_SECT_Msk   (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos)
	0x00000100
#define	FLASH_CRCCR_CRC_BY_SECT   FLASH_CRCCR_CRC_BY_SECT_Msk
	CRC sector mode select bit.
#define	FLASH_CRCCR_ADD_SECT_Pos   (9U)
#define	FLASH_CRCCR_ADD_SECT_Msk   (0x1UL << FLASH_CRCCR_ADD_SECT_Pos)
	0x00000200
#define	FLASH_CRCCR_ADD_SECT   FLASH_CRCCR_ADD_SECT_Msk
	CRC sector select bit.
#define	FLASH_CRCCR_CLEAN_SECT_Pos   (10U)
#define	FLASH_CRCCR_CLEAN_SECT_Msk   (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos)
	0x00000400
#define	FLASH_CRCCR_CLEAN_SECT   FLASH_CRCCR_CLEAN_SECT_Msk
	CRC sector list clear bit.
#define	FLASH_CRCCR_START_CRC_Pos   (16U)
#define	FLASH_CRCCR_START_CRC_Msk   (0x1UL << FLASH_CRCCR_START_CRC_Pos)
	0x00010000
#define	FLASH_CRCCR_START_CRC   FLASH_CRCCR_START_CRC_Msk
	CRC start bit.
#define	FLASH_CRCCR_CLEAN_CRC_Pos   (17U)
#define	FLASH_CRCCR_CLEAN_CRC_Msk   (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos)
	0x00020000
#define	FLASH_CRCCR_CLEAN_CRC   FLASH_CRCCR_CLEAN_CRC_Msk
	CRC clear bit.
#define	FLASH_CRCCR_CRC_BURST_Pos   (20U)
#define	FLASH_CRCCR_CRC_BURST_Msk   (0x3UL << FLASH_CRCCR_CRC_BURST_Pos)
	0x00300000
#define	FLASH_CRCCR_CRC_BURST   FLASH_CRCCR_CRC_BURST_Msk
	CRC burst size.
#define	FLASH_CRCCR_CRC_BURST_0   (0x1UL << FLASH_CRCCR_CRC_BURST_Pos)
	0x00100000
#define	FLASH_CRCCR_CRC_BURST_1   (0x2UL << FLASH_CRCCR_CRC_BURST_Pos)
	0x00200000
#define	FLASH_CRCCR_ALL_BANK_Pos   (22U)
#define	FLASH_CRCCR_ALL_BANK_Msk   (0x1UL << FLASH_CRCCR_ALL_BANK_Pos)
	0x00400000
#define	FLASH_CRCCR_ALL_BANK   FLASH_CRCCR_ALL_BANK_Msk
	CRC select bit.
#define	FLASH_CRCSADD_CRC_START_ADDR_Pos   (0U)
#define	FLASH_CRCSADD_CRC_START_ADDR_Msk   (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos)
	0xFFFFFFFF
#define	FLASH_CRCSADD_CRC_START_ADDR   FLASH_CRCSADD_CRC_START_ADDR_Msk
	CRC start address.
#define	FLASH_CRCEADD_CRC_END_ADDR_Pos   (0U)
#define	FLASH_CRCEADD_CRC_END_ADDR_Msk   (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos)
	0xFFFFFFFF
#define	FLASH_CRCEADD_CRC_END_ADDR   FLASH_CRCEADD_CRC_END_ADDR_Msk
	CRC end address.
#define	FLASH_CRCDATA_CRC_DATA_Pos   (0U)
#define	FLASH_CRCDATA_CRC_DATA_Msk   (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos)
	0xFFFFFFFF
#define	FLASH_CRCDATA_CRC_DATA   FLASH_CRCDATA_CRC_DATA_Msk
	CRC result.
#define	FLASH_ECC_FA_FAIL_ECC_ADDR_Pos   (0U)
#define	FLASH_ECC_FA_FAIL_ECC_ADDR_Msk   (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos)
	0x00007FFF
#define	FLASH_ECC_FA_FAIL_ECC_ADDR   FLASH_ECC_FA_FAIL_ECC_ADDR_Msk
	ECC error address.
#define	FLASH_OPTSR2_TCM_AXI_SHARED_Pos   (0U)
#define	FLASH_OPTSR2_TCM_AXI_SHARED_Msk   (0x3UL << FLASH_OPTSR2_TCM_AXI_SHARED_Pos)
	0x00000003
#define	FLASH_OPTSR2_TCM_AXI_SHARED   FLASH_OPTSR2_TCM_AXI_SHARED_Msk
	TCM RAM shared.
#define	FLASH_OPTSR2_TCM_AXI_SHARED_0   (0x1UL << FLASH_OPTSR2_TCM_AXI_SHARED_Pos)
	0x00000001
#define	FLASH_OPTSR2_TCM_AXI_SHARED_1   (0x2UL << FLASH_OPTSR2_TCM_AXI_SHARED_Pos)
	0x00000002
#define	FLASH_OPTSR2_CPUFREQ_BOOST_Pos   (2U)
#define	FLASH_OPTSR2_CPUFREQ_BOOST_Msk   (0x1UL << FLASH_OPTSR2_CPUFREQ_BOOST_Pos)
	0x00000004
#define	FLASH_OPTSR2_CPUFREQ_BOOST   FLASH_OPTSR2_CPUFREQ_BOOST_Msk
	CPU frequency boost.
#define	FMAC_X1BUFCFG_X1_BASE_Pos   (0U)
#define	FMAC_X1BUFCFG_X1_BASE_Msk   (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos)
	0x000000FF
#define	FMAC_X1BUFCFG_X1_BASE   FMAC_X1BUFCFG_X1_BASE_Msk
	Base address of X1 buffer.
#define	FMAC_X1BUFCFG_X1_BUF_SIZE_Pos   (8U)
#define	FMAC_X1BUFCFG_X1_BUF_SIZE_Msk   (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos
	0x0000FF00
#define	FMAC_X1BUFCFG_X1_BUF_SIZE   FMAC_X1BUFCFG_X1_BUF_SIZE_Msk
	Allocated size of X1 buffer in 16-bit words.
#define	FMAC_X1BUFCFG_FULL_WM_Pos   (24U)
#define	FMAC_X1BUFCFG_FULL_WM_Msk   (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos)
	0x03000000
#define	FMAC_X1BUFCFG_FULL_WM   FMAC_X1BUFCFG_FULL_WM_Msk
	Watermark for buffer full flag.
#define	FMAC_X2BUFCFG_X2_BASE_Pos   (0U)
#define	FMAC_X2BUFCFG_X2_BASE_Msk   (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos)
	0x000000FF
#define	FMAC_X2BUFCFG_X2_BASE   FMAC_X2BUFCFG_X2_BASE_Msk
	Base address of X2 buffer.
#define	FMAC_X2BUFCFG_X2_BUF_SIZE_Pos   (8U)
#define	FMAC_X2BUFCFG_X2_BUF_SIZE_Msk   (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos
	0x0000FF00
#define	FMAC_X2BUFCFG_X2_BUF_SIZE   FMAC_X2BUFCFG_X2_BUF_SIZE_Msk
	Size of X2 buffer in 16-bit words.
#define	FMAC_YBUFCFG_Y_BASE_Pos   (0U)
#define	FMAC_YBUFCFG_Y_BASE_Msk   (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos)
	0x000000FF
#define	FMAC_YBUFCFG_Y_BASE   FMAC_YBUFCFG_Y_BASE_Msk
	Base address of Y buffer.
#define	FMAC_YBUFCFG_Y_BUF_SIZE_Pos   (8U)
#define	FMAC_YBUFCFG_Y_BUF_SIZE_Msk   (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos)
	0x0000FF00
#define	FMAC_YBUFCFG_Y_BUF_SIZE   FMAC_YBUFCFG_Y_BUF_SIZE_Msk
	Size of Y buffer in 16-bit words.
#define	FMAC_YBUFCFG_EMPTY_WM_Pos   (24U)
#define	FMAC_YBUFCFG_EMPTY_WM_Msk   (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos)
	0x03000000
#define	FMAC_YBUFCFG_EMPTY_WM   FMAC_YBUFCFG_EMPTY_WM_Msk
	Watermark for buffer empty flag.
#define	FMAC_PARAM_P_Pos   (0U)
#define	FMAC_PARAM_P_Msk   (0xFFUL << FMAC_PARAM_P_Pos)
	0x000000FF
#define	FMAC_PARAM_P   FMAC_PARAM_P_Msk
	Input parameter P.
#define	FMAC_PARAM_Q_Pos   (8U)
#define	FMAC_PARAM_Q_Msk   (0xFFUL << FMAC_PARAM_Q_Pos)
	0x0000FF00
#define	FMAC_PARAM_Q   FMAC_PARAM_Q_Msk
	Input parameter Q.
#define	FMAC_PARAM_R_Pos   (16U)
#define	FMAC_PARAM_R_Msk   (0xFFUL << FMAC_PARAM_R_Pos)
	0x00FF0000
#define	FMAC_PARAM_R   FMAC_PARAM_R_Msk
	Input parameter R.
#define	FMAC_PARAM_FUNC_Pos   (24U)
#define	FMAC_PARAM_FUNC_Msk   (0x7FUL << FMAC_PARAM_FUNC_Pos)
	0x7F000000
#define	FMAC_PARAM_FUNC   FMAC_PARAM_FUNC_Msk
	Function.
#define	FMAC_PARAM_FUNC_0   (0x1UL << FMAC_PARAM_FUNC_Pos)
	0x01000000
#define	FMAC_PARAM_FUNC_1   (0x2UL << FMAC_PARAM_FUNC_Pos)
	0x02000000
#define	FMAC_PARAM_FUNC_2   (0x4UL << FMAC_PARAM_FUNC_Pos)
	0x04000000
#define	FMAC_PARAM_FUNC_3   (0x8UL << FMAC_PARAM_FUNC_Pos)
	0x08000000
#define	FMAC_PARAM_FUNC_4   (0x10UL << FMAC_PARAM_FUNC_Pos)
	0x10000000
#define	FMAC_PARAM_FUNC_5   (0x20UL << FMAC_PARAM_FUNC_Pos)
	0x20000000
#define	FMAC_PARAM_FUNC_6   (0x40UL << FMAC_PARAM_FUNC_Pos)
	0x40000000
#define	FMAC_PARAM_START_Pos   (31U)
#define	FMAC_PARAM_START_Msk   (0x1UL << FMAC_PARAM_START_Pos)
	0x80000000
#define	FMAC_PARAM_START   FMAC_PARAM_START_Msk
	Enable execution.
#define	FMAC_CR_RIEN_Pos   (0U)
#define	FMAC_CR_RIEN_Msk   (0x1UL << FMAC_CR_RIEN_Pos)
	0x00000001
#define	FMAC_CR_RIEN   FMAC_CR_RIEN_Msk
	Enable read interrupt.
#define	FMAC_CR_WIEN_Pos   (1U)
#define	FMAC_CR_WIEN_Msk   (0x1UL << FMAC_CR_WIEN_Pos)
	0x00000002
#define	FMAC_CR_WIEN   FMAC_CR_WIEN_Msk
	Enable write interrupt.
#define	FMAC_CR_OVFLIEN_Pos   (2U)
#define	FMAC_CR_OVFLIEN_Msk   (0x1UL << FMAC_CR_OVFLIEN_Pos)
	0x00000004
#define	FMAC_CR_OVFLIEN   FMAC_CR_OVFLIEN_Msk
	Enable overflow error interrupts.
#define	FMAC_CR_UNFLIEN_Pos   (3U)
#define	FMAC_CR_UNFLIEN_Msk   (0x1UL << FMAC_CR_UNFLIEN_Pos)
	0x00000008
#define	FMAC_CR_UNFLIEN   FMAC_CR_UNFLIEN_Msk
	Enable underflow error interrupts.
#define	FMAC_CR_SATIEN_Pos   (4U)
#define	FMAC_CR_SATIEN_Msk   (0x1UL << FMAC_CR_SATIEN_Pos)
	0x00000010
#define	FMAC_CR_SATIEN   FMAC_CR_SATIEN_Msk
	Enable saturation error interrupts.
#define	FMAC_CR_DMAREN_Pos   (8U)
#define	FMAC_CR_DMAREN_Msk   (0x1UL << FMAC_CR_DMAREN_Pos)
	0x00000100
#define	FMAC_CR_DMAREN   FMAC_CR_DMAREN_Msk
	Enable DMA read channel requests.
#define	FMAC_CR_DMAWEN_Pos   (9U)
#define	FMAC_CR_DMAWEN_Msk   (0x1UL << FMAC_CR_DMAWEN_Pos)
	0x00000200
#define	FMAC_CR_DMAWEN   FMAC_CR_DMAWEN_Msk
	Enable DMA write channel requests.
#define	FMAC_CR_CLIPEN_Pos   (15U)
#define	FMAC_CR_CLIPEN_Msk   (0x1UL << FMAC_CR_CLIPEN_Pos)
	0x00008000
#define	FMAC_CR_CLIPEN   FMAC_CR_CLIPEN_Msk
	Enable clipping.
#define	FMAC_CR_RESET_Pos   (16U)
#define	FMAC_CR_RESET_Msk   (0x1UL << FMAC_CR_RESET_Pos)
	0x00010000
#define	FMAC_CR_RESET   FMAC_CR_RESET_Msk
	Reset filter mathematical accelerator unit.
#define	FMAC_SR_YEMPTY_Pos   (0U)
#define	FMAC_SR_YEMPTY_Msk   (0x1UL << FMAC_SR_YEMPTY_Pos)
	0x00000001
#define	FMAC_SR_YEMPTY   FMAC_SR_YEMPTY_Msk
	Y buffer empty flag.
#define	FMAC_SR_X1FULL_Pos   (1U)
#define	FMAC_SR_X1FULL_Msk   (0x1UL << FMAC_SR_X1FULL_Pos)
	0x00000002
#define	FMAC_SR_X1FULL   FMAC_SR_X1FULL_Msk
	X1 buffer full flag.
#define	FMAC_SR_OVFL_Pos   (8U)
#define	FMAC_SR_OVFL_Msk   (0x1UL << FMAC_SR_OVFL_Pos)
	0x00000100
#define	FMAC_SR_OVFL   FMAC_SR_OVFL_Msk
	Overflow error flag.
#define	FMAC_SR_UNFL_Pos   (9U)
#define	FMAC_SR_UNFL_Msk   (0x1UL << FMAC_SR_UNFL_Pos)
	0x00000200
#define	FMAC_SR_UNFL   FMAC_SR_UNFL_Msk
	Underflow error flag.
#define	FMAC_SR_SAT_Pos   (10U)
#define	FMAC_SR_SAT_Msk   (0x1UL << FMAC_SR_SAT_Pos)
	0x00000400
#define	FMAC_SR_SAT   FMAC_SR_SAT_Msk
	Saturation error flag.
#define	FMAC_WDATA_WDATA_Pos   (0U)
#define	FMAC_WDATA_WDATA_Msk   (0xFFFFUL << FMAC_WDATA_WDATA_Pos)
	0x0000FFFF
#define	FMAC_WDATA_WDATA   FMAC_WDATA_WDATA_Msk
	Write data.
#define	FMAC_RDATA_RDATA_Pos   (0U)
#define	FMAC_RDATA_RDATA_Msk   (0xFFFFUL << FMAC_RDATA_RDATA_Pos)
	0x0000FFFF
#define	FMAC_RDATA_RDATA   FMAC_RDATA_RDATA_Msk
	Read data.
#define	FMC_BCR1_CCLKEN_Pos   (20U)
#define	FMC_BCR1_CCLKEN_Msk   (0x1UL << FMC_BCR1_CCLKEN_Pos)
	0x00100000
#define	FMC_BCR1_CCLKEN   FMC_BCR1_CCLKEN_Msk
	Continuous clock enable.
#define	FMC_BCR1_WFDIS_Pos   (21U)
#define	FMC_BCR1_WFDIS_Msk   (0x1UL << FMC_BCR1_WFDIS_Pos)
	0x00200000
#define	FMC_BCR1_WFDIS   FMC_BCR1_WFDIS_Msk
	Write FIFO Disable.
#define	FMC_BCR1_BMAP_Pos   (24U)
#define	FMC_BCR1_BMAP_Msk   (0x3UL << FMC_BCR1_BMAP_Pos)
	0x03000000
#define	FMC_BCR1_BMAP   FMC_BCR1_BMAP_Msk
	BMAP[1:0] FMC bank mapping.
#define	FMC_BCR1_BMAP_0   (0x1UL << FMC_BCR1_BMAP_Pos)
	0x01000000
#define	FMC_BCR1_BMAP_1   (0x2UL << FMC_BCR1_BMAP_Pos)
	0x02000000
#define	FMC_BCR1_FMCEN_Pos   (31U)
#define	FMC_BCR1_FMCEN_Msk   (0x1UL << FMC_BCR1_FMCEN_Pos)
	0x80000000
#define	FMC_BCR1_FMCEN   FMC_BCR1_FMCEN_Msk
	FMC controller Enable.
#define	FMC_BCRx_MBKEN_Pos   (0U)
#define	FMC_BCRx_MBKEN_Msk   (0x1UL << FMC_BCRx_MBKEN_Pos)
	0x00000001
#define	FMC_BCRx_MBKEN   FMC_BCRx_MBKEN_Msk
	Memory bank enable bit.
#define	FMC_BCRx_MUXEN_Pos   (1U)
#define	FMC_BCRx_MUXEN_Msk   (0x1UL << FMC_BCRx_MUXEN_Pos)
	0x00000002
#define	FMC_BCRx_MUXEN   FMC_BCRx_MUXEN_Msk
	Address/data multiplexing enable bit.
#define	FMC_BCRx_MTYP_Pos   (2U)
#define	FMC_BCRx_MTYP_Msk   (0x3UL << FMC_BCRx_MTYP_Pos)
	0x0000000C
#define	FMC_BCRx_MTYP   FMC_BCRx_MTYP_Msk
	MTYP[1:0] bits (Memory type).
#define	FMC_BCRx_MTYP_0   (0x1UL << FMC_BCRx_MTYP_Pos)
	0x00000004
#define	FMC_BCRx_MTYP_1   (0x2UL << FMC_BCRx_MTYP_Pos)
	0x00000008
#define	FMC_BCRx_MWID_Pos   (4U)
#define	FMC_BCRx_MWID_Msk   (0x3UL << FMC_BCRx_MWID_Pos)
	0x00000030
#define	FMC_BCRx_MWID   FMC_BCRx_MWID_Msk
	MWID[1:0] bits (Memory data bus width).
#define	FMC_BCRx_MWID_0   (0x1UL << FMC_BCRx_MWID_Pos)
	0x00000010
#define	FMC_BCRx_MWID_1   (0x2UL << FMC_BCRx_MWID_Pos)
	0x00000020
#define	FMC_BCRx_FACCEN_Pos   (6U)
#define	FMC_BCRx_FACCEN_Msk   (0x1UL << FMC_BCRx_FACCEN_Pos)
	0x00000040
#define	FMC_BCRx_FACCEN   FMC_BCRx_FACCEN_Msk
	Flash access enable.
#define	FMC_BCRx_BURSTEN_Pos   (8U)
#define	FMC_BCRx_BURSTEN_Msk   (0x1UL << FMC_BCRx_BURSTEN_Pos)
	0x00000100
#define	FMC_BCRx_BURSTEN   FMC_BCRx_BURSTEN_Msk
	Burst enable bit.
#define	FMC_BCRx_WAITPOL_Pos   (9U)
#define	FMC_BCRx_WAITPOL_Msk   (0x1UL << FMC_BCRx_WAITPOL_Pos)
	0x00000200
#define	FMC_BCRx_WAITPOL   FMC_BCRx_WAITPOL_Msk
	Wait signal polarity bit.
#define	FMC_BCRx_WAITCFG_Pos   (11U)
#define	FMC_BCRx_WAITCFG_Msk   (0x1UL << FMC_BCRx_WAITCFG_Pos)
	0x00000800
#define	FMC_BCRx_WAITCFG   FMC_BCRx_WAITCFG_Msk
	Wait timing configuration.
#define	FMC_BCRx_WREN_Pos   (12U)
#define	FMC_BCRx_WREN_Msk   (0x1UL << FMC_BCRx_WREN_Pos)
	0x00001000
#define	FMC_BCRx_WREN   FMC_BCRx_WREN_Msk
	Write enable bit.
#define	FMC_BCRx_WAITEN_Pos   (13U)
#define	FMC_BCRx_WAITEN_Msk   (0x1UL << FMC_BCRx_WAITEN_Pos)
	0x00002000
#define	FMC_BCRx_WAITEN   FMC_BCRx_WAITEN_Msk
	Wait enable bit.
#define	FMC_BCRx_EXTMOD_Pos   (14U)
#define	FMC_BCRx_EXTMOD_Msk   (0x1UL << FMC_BCRx_EXTMOD_Pos)
	0x00004000
#define	FMC_BCRx_EXTMOD   FMC_BCRx_EXTMOD_Msk
	Extended mode enable.
#define	FMC_BCRx_ASYNCWAIT_Pos   (15U)
#define	FMC_BCRx_ASYNCWAIT_Msk   (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)
	0x00008000
#define	FMC_BCRx_ASYNCWAIT   FMC_BCRx_ASYNCWAIT_Msk
	Asynchronous wait.
#define	FMC_BCRx_CPSIZE_Pos   (16U)
#define	FMC_BCRx_CPSIZE_Msk   (0x7UL << FMC_BCRx_CPSIZE_Pos)
	0x00070000
#define	FMC_BCRx_CPSIZE   FMC_BCRx_CPSIZE_Msk
	PSIZE[2:0] bits CRAM Page Size.
#define	FMC_BCRx_CPSIZE_0   (0x1UL << FMC_BCRx_CPSIZE_Pos)
	0x00010000
#define	FMC_BCRx_CPSIZE_1   (0x2UL << FMC_BCRx_CPSIZE_Pos)
	0x00020000
#define	FMC_BCRx_CPSIZE_2   (0x4UL << FMC_BCRx_CPSIZE_Pos)
	0x00040000
#define	FMC_BCRx_CBURSTRW_Pos   (19U)
#define	FMC_BCRx_CBURSTRW_Msk   (0x1UL << FMC_BCRx_CBURSTRW_Pos)
	0x00080000
#define	FMC_BCRx_CBURSTRW   FMC_BCRx_CBURSTRW_Msk
	Write burst enable.
#define	FMC_BTRx_ADDSET_Pos   (0U)
#define	FMC_BTRx_ADDSET_Msk   (0xFUL << FMC_BTRx_ADDSET_Pos)
	0x0000000F
#define	FMC_BTRx_ADDSET   FMC_BTRx_ADDSET_Msk
	ADDSET[3:0] bits (Address setup phase duration).
#define	FMC_BTRx_ADDSET_0   (0x1UL << FMC_BTRx_ADDSET_Pos)
	0x00000001
#define	FMC_BTRx_ADDSET_1   (0x2UL << FMC_BTRx_ADDSET_Pos)
	0x00000002
#define	FMC_BTRx_ADDSET_2   (0x4UL << FMC_BTRx_ADDSET_Pos)
	0x00000004
#define	FMC_BTRx_ADDSET_3   (0x8UL << FMC_BTRx_ADDSET_Pos)
	0x00000008
#define	FMC_BTRx_ADDHLD_Pos   (4U)
#define	FMC_BTRx_ADDHLD_Msk   (0xFUL << FMC_BTRx_ADDHLD_Pos)
	0x000000F0
#define	FMC_BTRx_ADDHLD   FMC_BTRx_ADDHLD_Msk
	ADDHLD[3:0] bits (Address-hold phase duration).
#define	FMC_BTRx_ADDHLD_0   (0x1UL << FMC_BTRx_ADDHLD_Pos)
	0x00000010
#define	FMC_BTRx_ADDHLD_1   (0x2UL << FMC_BTRx_ADDHLD_Pos)
	0x00000020
#define	FMC_BTRx_ADDHLD_2   (0x4UL << FMC_BTRx_ADDHLD_Pos)
	0x00000040
#define	FMC_BTRx_ADDHLD_3   (0x8UL << FMC_BTRx_ADDHLD_Pos)
	0x00000080
#define	FMC_BTRx_DATAST_Pos   (8U)
#define	FMC_BTRx_DATAST_Msk   (0xFFUL << FMC_BTRx_DATAST_Pos)
	0x0000FF00
#define	FMC_BTRx_DATAST   FMC_BTRx_DATAST_Msk
	DATAST [3:0] bits (Data-phase duration).
#define	FMC_BTRx_DATAST_0   (0x01UL << FMC_BTRx_DATAST_Pos)
	0x00000100
#define	FMC_BTRx_DATAST_1   (0x02UL << FMC_BTRx_DATAST_Pos)
	0x00000200
#define	FMC_BTRx_DATAST_2   (0x04UL << FMC_BTRx_DATAST_Pos)
	0x00000400
#define	FMC_BTRx_DATAST_3   (0x08UL << FMC_BTRx_DATAST_Pos)
	0x00000800
#define	FMC_BTRx_DATAST_4   (0x10UL << FMC_BTRx_DATAST_Pos)
	0x00001000
#define	FMC_BTRx_DATAST_5   (0x20UL << FMC_BTRx_DATAST_Pos)
	0x00002000
#define	FMC_BTRx_DATAST_6   (0x40UL << FMC_BTRx_DATAST_Pos)
	0x00004000
#define	FMC_BTRx_DATAST_7   (0x80UL << FMC_BTRx_DATAST_Pos)
	0x00008000
#define	FMC_BTRx_BUSTURN_Pos   (16U)
#define	FMC_BTRx_BUSTURN_Msk   (0xFUL << FMC_BTRx_BUSTURN_Pos)
	0x000F0000
#define	FMC_BTRx_BUSTURN   FMC_BTRx_BUSTURN_Msk
	BUSTURN[3:0] bits (Bus turnaround phase duration).
#define	FMC_BTRx_BUSTURN_0   (0x1UL << FMC_BTRx_BUSTURN_Pos)
	0x00010000
#define	FMC_BTRx_BUSTURN_1   (0x2UL << FMC_BTRx_BUSTURN_Pos)
	0x00020000
#define	FMC_BTRx_BUSTURN_2   (0x4UL << FMC_BTRx_BUSTURN_Pos)
	0x00040000
#define	FMC_BTRx_BUSTURN_3   (0x8UL << FMC_BTRx_BUSTURN_Pos)
	0x00080000
#define	FMC_BTRx_CLKDIV_Pos   (20U)
#define	FMC_BTRx_CLKDIV_Msk   (0xFUL << FMC_BTRx_CLKDIV_Pos)
	0x00F00000
#define	FMC_BTRx_CLKDIV   FMC_BTRx_CLKDIV_Msk
	CLKDIV[3:0] bits (Clock divide ratio).
#define	FMC_BTRx_CLKDIV_0   (0x1UL << FMC_BTRx_CLKDIV_Pos)
	0x00100000
#define	FMC_BTRx_CLKDIV_1   (0x2UL << FMC_BTRx_CLKDIV_Pos)
	0x00200000
#define	FMC_BTRx_CLKDIV_2   (0x4UL << FMC_BTRx_CLKDIV_Pos)
	0x00400000
#define	FMC_BTRx_CLKDIV_3   (0x8UL << FMC_BTRx_CLKDIV_Pos)
	0x00800000
#define	FMC_BTRx_DATLAT_Pos   (24U)
#define	FMC_BTRx_DATLAT_Msk   (0xFUL << FMC_BTRx_DATLAT_Pos)
	0x0F000000
#define	FMC_BTRx_DATLAT   FMC_BTRx_DATLAT_Msk
	DATLA[3:0] bits (Data latency).
#define	FMC_BTRx_DATLAT_0   (0x1UL << FMC_BTRx_DATLAT_Pos)
	0x01000000
#define	FMC_BTRx_DATLAT_1   (0x2UL << FMC_BTRx_DATLAT_Pos)
	0x02000000
#define	FMC_BTRx_DATLAT_2   (0x4UL << FMC_BTRx_DATLAT_Pos)
	0x04000000
#define	FMC_BTRx_DATLAT_3   (0x8UL << FMC_BTRx_DATLAT_Pos)
	0x08000000
#define	FMC_BTRx_ACCMOD_Pos   (28U)
#define	FMC_BTRx_ACCMOD_Msk   (0x3UL << FMC_BTRx_ACCMOD_Pos)
	0x30000000
#define	FMC_BTRx_ACCMOD   FMC_BTRx_ACCMOD_Msk
	ACCMOD[1:0] bits (Access mode).
#define	FMC_BTRx_ACCMOD_0   (0x1UL << FMC_BTRx_ACCMOD_Pos)
	0x10000000
#define	FMC_BTRx_ACCMOD_1   (0x2UL << FMC_BTRx_ACCMOD_Pos)
	0x20000000
#define	FMC_BWTRx_ADDSET_Pos   (0U)
#define	FMC_BWTRx_ADDSET_Msk   (0xFUL << FMC_BWTRx_ADDSET_Pos)
	0x0000000F
#define	FMC_BWTRx_ADDSET   FMC_BWTRx_ADDSET_Msk
	ADDSET[3:0] bits (Address setup phase duration).
#define	FMC_BWTRx_ADDSET_0   (0x1UL << FMC_BWTRx_ADDSET_Pos)
	0x00000001
#define	FMC_BWTRx_ADDSET_1   (0x2UL << FMC_BWTRx_ADDSET_Pos)
	0x00000002
#define	FMC_BWTRx_ADDSET_2   (0x4UL << FMC_BWTRx_ADDSET_Pos)
	0x00000004
#define	FMC_BWTRx_ADDSET_3   (0x8UL << FMC_BWTRx_ADDSET_Pos)
	0x00000008
#define	FMC_BWTRx_ADDHLD_Pos   (4U)
#define	FMC_BWTRx_ADDHLD_Msk   (0xFUL << FMC_BWTRx_ADDHLD_Pos)
	0x000000F0
#define	FMC_BWTRx_ADDHLD   FMC_BWTRx_ADDHLD_Msk
	ADDHLD[3:0] bits (Address-hold phase duration).
#define	FMC_BWTRx_ADDHLD_0   (0x1UL << FMC_BWTRx_ADDHLD_Pos)
	0x00000010
#define	FMC_BWTRx_ADDHLD_1   (0x2UL << FMC_BWTRx_ADDHLD_Pos)
	0x00000020
#define	FMC_BWTRx_ADDHLD_2   (0x4UL << FMC_BWTRx_ADDHLD_Pos)
	0x00000040
#define	FMC_BWTRx_ADDHLD_3   (0x8UL << FMC_BWTRx_ADDHLD_Pos)
	0x00000080
#define	FMC_BWTRx_DATAST_Pos   (8U)
#define	FMC_BWTRx_DATAST_Msk   (0xFFUL << FMC_BWTRx_DATAST_Pos)
	0x0000FF00
#define	FMC_BWTRx_DATAST   FMC_BWTRx_DATAST_Msk
	DATAST [3:0] bits (Data-phase duration).
#define	FMC_BWTRx_DATAST_0   (0x01UL << FMC_BWTRx_DATAST_Pos)
	0x00000100
#define	FMC_BWTRx_DATAST_1   (0x02UL << FMC_BWTRx_DATAST_Pos)
	0x00000200
#define	FMC_BWTRx_DATAST_2   (0x04UL << FMC_BWTRx_DATAST_Pos)
	0x00000400
#define	FMC_BWTRx_DATAST_3   (0x08UL << FMC_BWTRx_DATAST_Pos)
	0x00000800
#define	FMC_BWTRx_DATAST_4   (0x10UL << FMC_BWTRx_DATAST_Pos)
	0x00001000
#define	FMC_BWTRx_DATAST_5   (0x20UL << FMC_BWTRx_DATAST_Pos)
	0x00002000
#define	FMC_BWTRx_DATAST_6   (0x40UL << FMC_BWTRx_DATAST_Pos)
	0x00004000
#define	FMC_BWTRx_DATAST_7   (0x80UL << FMC_BWTRx_DATAST_Pos)
	0x00008000
#define	FMC_BWTRx_BUSTURN_Pos   (16U)
#define	FMC_BWTRx_BUSTURN_Msk   (0xFUL << FMC_BWTRx_BUSTURN_Pos)
	0x000F0000
#define	FMC_BWTRx_BUSTURN   FMC_BWTRx_BUSTURN_Msk
	BUSTURN[3:0] bits (Bus turnaround phase duration).
#define	FMC_BWTRx_BUSTURN_0   (0x1UL << FMC_BWTRx_BUSTURN_Pos)
	0x00010000
#define	FMC_BWTRx_BUSTURN_1   (0x2UL << FMC_BWTRx_BUSTURN_Pos)
	0x00020000
#define	FMC_BWTRx_BUSTURN_2   (0x4UL << FMC_BWTRx_BUSTURN_Pos)
	0x00040000
#define	FMC_BWTRx_BUSTURN_3   (0x8UL << FMC_BWTRx_BUSTURN_Pos)
	0x00080000
#define	FMC_BWTRx_ACCMOD_Pos   (28U)
#define	FMC_BWTRx_ACCMOD_Msk   (0x3UL << FMC_BWTRx_ACCMOD_Pos)
	0x30000000
#define	FMC_BWTRx_ACCMOD   FMC_BWTRx_ACCMOD_Msk
	ACCMOD[1:0] bits (Access mode).
#define	FMC_BWTRx_ACCMOD_0   (0x1UL << FMC_BWTRx_ACCMOD_Pos)
	0x10000000
#define	FMC_BWTRx_ACCMOD_1   (0x2UL << FMC_BWTRx_ACCMOD_Pos)
	0x20000000
#define	FMC_PCR_PWAITEN_Pos   (1U)
#define	FMC_PCR_PWAITEN_Msk   (0x1UL << FMC_PCR_PWAITEN_Pos)
	0x00000002
#define	FMC_PCR_PWAITEN   FMC_PCR_PWAITEN_Msk
	Wait feature enable bit.
#define	FMC_PCR_PBKEN_Pos   (2U)
#define	FMC_PCR_PBKEN_Msk   (0x1UL << FMC_PCR_PBKEN_Pos)
	0x00000004
#define	FMC_PCR_PBKEN   FMC_PCR_PBKEN_Msk
	NAND Flash memory bank enable bit.
#define	FMC_PCR_PWID_Pos   (4U)
#define	FMC_PCR_PWID_Msk   (0x3UL << FMC_PCR_PWID_Pos)
	0x00000030
#define	FMC_PCR_PWID   FMC_PCR_PWID_Msk
	PWID[1:0] bits (NAND Flash databus width).
#define	FMC_PCR_PWID_0   (0x1UL << FMC_PCR_PWID_Pos)
	0x00000010
#define	FMC_PCR_PWID_1   (0x2UL << FMC_PCR_PWID_Pos)
	0x00000020
#define	FMC_PCR_ECCEN_Pos   (6U)
#define	FMC_PCR_ECCEN_Msk   (0x1UL << FMC_PCR_ECCEN_Pos)
	0x00000040
#define	FMC_PCR_ECCEN   FMC_PCR_ECCEN_Msk
	ECC computation logic enable bit.
#define	FMC_PCR_TCLR_Pos   (9U)
#define	FMC_PCR_TCLR_Msk   (0xFUL << FMC_PCR_TCLR_Pos)
	0x00001E00
#define	FMC_PCR_TCLR   FMC_PCR_TCLR_Msk
	TCLR[3:0] bits (CLE to RE delay).
#define	FMC_PCR_TCLR_0   (0x1UL << FMC_PCR_TCLR_Pos)
	0x00000200
#define	FMC_PCR_TCLR_1   (0x2UL << FMC_PCR_TCLR_Pos)
	0x00000400
#define	FMC_PCR_TCLR_2   (0x4UL << FMC_PCR_TCLR_Pos)
	0x00000800
#define	FMC_PCR_TCLR_3   (0x8UL << FMC_PCR_TCLR_Pos)
	0x00001000
#define	FMC_PCR_TAR_Pos   (13U)
#define	FMC_PCR_TAR_Msk   (0xFUL << FMC_PCR_TAR_Pos)
	0x0001E000
#define	FMC_PCR_TAR   FMC_PCR_TAR_Msk
	TAR[3:0] bits (ALE to RE delay).
#define	FMC_PCR_TAR_0   (0x1UL << FMC_PCR_TAR_Pos)
	0x00002000
#define	FMC_PCR_TAR_1   (0x2UL << FMC_PCR_TAR_Pos)
	0x00004000
#define	FMC_PCR_TAR_2   (0x4UL << FMC_PCR_TAR_Pos)
	0x00008000
#define	FMC_PCR_TAR_3   (0x8UL << FMC_PCR_TAR_Pos)
	0x00010000
#define	FMC_PCR_ECCPS_Pos   (17U)
#define	FMC_PCR_ECCPS_Msk   (0x7UL << FMC_PCR_ECCPS_Pos)
	0x000E0000
#define	FMC_PCR_ECCPS   FMC_PCR_ECCPS_Msk
	ECCPS[1:0] bits (ECC page size).
#define	FMC_PCR_ECCPS_0   (0x1UL << FMC_PCR_ECCPS_Pos)
	0x00020000
#define	FMC_PCR_ECCPS_1   (0x2UL << FMC_PCR_ECCPS_Pos)
	0x00040000
#define	FMC_PCR_ECCPS_2   (0x4UL << FMC_PCR_ECCPS_Pos)
	0x00080000
#define	FMC_SR_IRS_Pos   (0U)
#define	FMC_SR_IRS_Msk   (0x1UL << FMC_SR_IRS_Pos)
	0x00000001
#define	FMC_SR_IRS   FMC_SR_IRS_Msk
	Interrupt Rising Edge status.
#define	FMC_SR_ILS_Pos   (1U)
#define	FMC_SR_ILS_Msk   (0x1UL << FMC_SR_ILS_Pos)
	0x00000002
#define	FMC_SR_ILS   FMC_SR_ILS_Msk
	Interrupt Level status.
#define	FMC_SR_IFS_Pos   (2U)
#define	FMC_SR_IFS_Msk   (0x1UL << FMC_SR_IFS_Pos)
	0x00000004
#define	FMC_SR_IFS   FMC_SR_IFS_Msk
	Interrupt Falling Edge status.
#define	FMC_SR_IREN_Pos   (3U)
#define	FMC_SR_IREN_Msk   (0x1UL << FMC_SR_IREN_Pos)
	0x00000008
#define	FMC_SR_IREN   FMC_SR_IREN_Msk
	Interrupt Rising Edge detection Enable bit.
#define	FMC_SR_ILEN_Pos   (4U)
#define	FMC_SR_ILEN_Msk   (0x1UL << FMC_SR_ILEN_Pos)
	0x00000010
#define	FMC_SR_ILEN   FMC_SR_ILEN_Msk
	Interrupt Level detection Enable bit.
#define	FMC_SR_IFEN_Pos   (5U)
#define	FMC_SR_IFEN_Msk   (0x1UL << FMC_SR_IFEN_Pos)
	0x00000020
#define	FMC_SR_IFEN   FMC_SR_IFEN_Msk
	Interrupt Falling Edge detection Enable bit.
#define	FMC_SR_FEMPT_Pos   (6U)
#define	FMC_SR_FEMPT_Msk   (0x1UL << FMC_SR_FEMPT_Pos)
	0x00000040
#define	FMC_SR_FEMPT   FMC_SR_FEMPT_Msk
	FIFO empty.
#define	FMC_PMEM_MEMSET_Pos   (0U)
#define	FMC_PMEM_MEMSET_Msk   (0xFFUL << FMC_PMEM_MEMSET_Pos)
	0x000000FF
#define	FMC_PMEM_MEMSET   FMC_PMEM_MEMSET_Msk
	MEMSET[7:0] bits (Common memory setup time).
#define	FMC_PMEM_MEMSET_0   (0x01UL << FMC_PMEM_MEMSET_Pos)
	0x00000001
#define	FMC_PMEM_MEMSET_1   (0x02UL << FMC_PMEM_MEMSET_Pos)
	0x00000002
#define	FMC_PMEM_MEMSET_2   (0x04UL << FMC_PMEM_MEMSET_Pos)
	0x00000004
#define	FMC_PMEM_MEMSET_3   (0x08UL << FMC_PMEM_MEMSET_Pos)
	0x00000008
#define	FMC_PMEM_MEMSET_4   (0x10UL << FMC_PMEM_MEMSET_Pos)
	0x00000010
#define	FMC_PMEM_MEMSET_5   (0x20UL << FMC_PMEM_MEMSET_Pos)
	0x00000020
#define	FMC_PMEM_MEMSET_6   (0x40UL << FMC_PMEM_MEMSET_Pos)
	0x00000040
#define	FMC_PMEM_MEMSET_7   (0x80UL << FMC_PMEM_MEMSET_Pos)
	0x00000080
#define	FMC_PMEM_MEMWAIT_Pos   (8U)
#define	FMC_PMEM_MEMWAIT_Msk   (0xFFUL << FMC_PMEM_MEMWAIT_Pos)
	0x0000FF00
#define	FMC_PMEM_MEMWAIT   FMC_PMEM_MEMWAIT_Msk
	MEMWAIT[7:0] bits (Common memory wait time).
#define	FMC_PMEM_MEMWAIT_0   (0x01UL << FMC_PMEM_MEMWAIT_Pos)
	0x00000100
#define	FMC_PMEM_MEMWAIT_1   (0x02UL << FMC_PMEM_MEMWAIT_Pos)
	0x00000200
#define	FMC_PMEM_MEMWAIT_2   (0x04UL << FMC_PMEM_MEMWAIT_Pos)
	0x00000400
#define	FMC_PMEM_MEMWAIT_3   (0x08UL << FMC_PMEM_MEMWAIT_Pos)
	0x00000800
#define	FMC_PMEM_MEMWAIT_4   (0x10UL << FMC_PMEM_MEMWAIT_Pos)
	0x00001000
#define	FMC_PMEM_MEMWAIT_5   (0x20UL << FMC_PMEM_MEMWAIT_Pos)
	0x00002000
#define	FMC_PMEM_MEMWAIT_6   (0x40UL << FMC_PMEM_MEMWAIT_Pos)
	0x00004000
#define	FMC_PMEM_MEMWAIT_7   (0x80UL << FMC_PMEM_MEMWAIT_Pos)
	0x00008000
#define	FMC_PMEM_MEMHOLD_Pos   (16U)
#define	FMC_PMEM_MEMHOLD_Msk   (0xFFUL << FMC_PMEM_MEMHOLD_Pos)
	0x00FF0000
#define	FMC_PMEM_MEMHOLD   FMC_PMEM_MEMHOLD_Msk
	MEMHOLD[7:0] bits (Common memory hold time).
#define	FMC_PMEM_MEMHOLD_0   (0x01UL << FMC_PMEM_MEMHOLD_Pos)
	0x00010000
#define	FMC_PMEM_MEMHOLD_1   (0x02UL << FMC_PMEM_MEMHOLD_Pos)
	0x00020000
#define	FMC_PMEM_MEMHOLD_2   (0x04UL << FMC_PMEM_MEMHOLD_Pos)
	0x00040000
#define	FMC_PMEM_MEMHOLD_3   (0x08UL << FMC_PMEM_MEMHOLD_Pos)
	0x00080000
#define	FMC_PMEM_MEMHOLD_4   (0x10UL << FMC_PMEM_MEMHOLD_Pos)
	0x00100000
#define	FMC_PMEM_MEMHOLD_5   (0x20UL << FMC_PMEM_MEMHOLD_Pos)
	0x00200000
#define	FMC_PMEM_MEMHOLD_6   (0x40UL << FMC_PMEM_MEMHOLD_Pos)
	0x00400000
#define	FMC_PMEM_MEMHOLD_7   (0x80UL << FMC_PMEM_MEMHOLD_Pos)
	0x00800000
#define	FMC_PMEM_MEMHIZ_Pos   (24U)
#define	FMC_PMEM_MEMHIZ_Msk   (0xFFUL << FMC_PMEM_MEMHIZ_Pos)
	0xFF000000
#define	FMC_PMEM_MEMHIZ   FMC_PMEM_MEMHIZ_Msk
	MEMHIZ[7:0] bits (Common memory databus HiZ time).
#define	FMC_PMEM_MEMHIZ_0   (0x01UL << FMC_PMEM_MEMHIZ_Pos)
	0x01000000
#define	FMC_PMEM_MEMHIZ_1   (0x02UL << FMC_PMEM_MEMHIZ_Pos)
	0x02000000
#define	FMC_PMEM_MEMHIZ_2   (0x04UL << FMC_PMEM_MEMHIZ_Pos)
	0x04000000
#define	FMC_PMEM_MEMHIZ_3   (0x08UL << FMC_PMEM_MEMHIZ_Pos)
	0x08000000
#define	FMC_PMEM_MEMHIZ_4   (0x10UL << FMC_PMEM_MEMHIZ_Pos)
	0x10000000
#define	FMC_PMEM_MEMHIZ_5   (0x20UL << FMC_PMEM_MEMHIZ_Pos)
	0x20000000
#define	FMC_PMEM_MEMHIZ_6   (0x40UL << FMC_PMEM_MEMHIZ_Pos)
	0x40000000
#define	FMC_PMEM_MEMHIZ_7   (0x80UL << FMC_PMEM_MEMHIZ_Pos)
	0x80000000
#define	FMC_PATT_ATTSET_Pos   (0U)
#define	FMC_PATT_ATTSET_Msk   (0xFFUL << FMC_PATT_ATTSET_Pos)
	0x000000FF
#define	FMC_PATT_ATTSET   FMC_PATT_ATTSET_Msk
	ATTSET[7:0] bits (Attribute memory setup time).
#define	FMC_PATT_ATTSET_0   (0x01UL << FMC_PATT_ATTSET_Pos)
	0x00000001
#define	FMC_PATT_ATTSET_1   (0x02UL << FMC_PATT_ATTSET_Pos)
	0x00000002
#define	FMC_PATT_ATTSET_2   (0x04UL << FMC_PATT_ATTSET_Pos)
	0x00000004
#define	FMC_PATT_ATTSET_3   (0x08UL << FMC_PATT_ATTSET_Pos)
	0x00000008
#define	FMC_PATT_ATTSET_4   (0x10UL << FMC_PATT_ATTSET_Pos)
	0x00000010
#define	FMC_PATT_ATTSET_5   (0x20UL << FMC_PATT_ATTSET_Pos)
	0x00000020
#define	FMC_PATT_ATTSET_6   (0x40UL << FMC_PATT_ATTSET_Pos)
	0x00000040
#define	FMC_PATT_ATTSET_7   (0x80UL << FMC_PATT_ATTSET_Pos)
	0x00000080
#define	FMC_PATT_ATTWAIT_Pos   (8U)
#define	FMC_PATT_ATTWAIT_Msk   (0xFFUL << FMC_PATT_ATTWAIT_Pos)
	0x0000FF00
#define	FMC_PATT_ATTWAIT   FMC_PATT_ATTWAIT_Msk
	ATTWAIT[7:0] bits (Attribute memory wait time).
#define	FMC_PATT_ATTWAIT_0   (0x01UL << FMC_PATT_ATTWAIT_Pos)
	0x00000100
#define	FMC_PATT_ATTWAIT_1   (0x02UL << FMC_PATT_ATTWAIT_Pos)
	0x00000200
#define	FMC_PATT_ATTWAIT_2   (0x04UL << FMC_PATT_ATTWAIT_Pos)
	0x00000400
#define	FMC_PATT_ATTWAIT_3   (0x08UL << FMC_PATT_ATTWAIT_Pos)
	0x00000800
#define	FMC_PATT_ATTWAIT_4   (0x10UL << FMC_PATT_ATTWAIT_Pos)
	0x00001000
#define	FMC_PATT_ATTWAIT_5   (0x20UL << FMC_PATT_ATTWAIT_Pos)
	0x00002000
#define	FMC_PATT_ATTWAIT_6   (0x40UL << FMC_PATT_ATTWAIT_Pos)
	0x00004000
#define	FMC_PATT_ATTWAIT_7   (0x80UL << FMC_PATT_ATTWAIT_Pos)
	0x00008000
#define	FMC_PATT_ATTHOLD_Pos   (16U)
#define	FMC_PATT_ATTHOLD_Msk   (0xFFUL << FMC_PATT_ATTHOLD_Pos)
	0x00FF0000
#define	FMC_PATT_ATTHOLD   FMC_PATT_ATTHOLD_Msk
	ATTHOLD[7:0] bits (Attribute memory hold time).
#define	FMC_PATT_ATTHOLD_0   (0x01UL << FMC_PATT_ATTHOLD_Pos)
	0x00010000
#define	FMC_PATT_ATTHOLD_1   (0x02UL << FMC_PATT_ATTHOLD_Pos)
	0x00020000
#define	FMC_PATT_ATTHOLD_2   (0x04UL << FMC_PATT_ATTHOLD_Pos)
	0x00040000
#define	FMC_PATT_ATTHOLD_3   (0x08UL << FMC_PATT_ATTHOLD_Pos)
	0x00080000
#define	FMC_PATT_ATTHOLD_4   (0x10UL << FMC_PATT_ATTHOLD_Pos)
	0x00100000
#define	FMC_PATT_ATTHOLD_5   (0x20UL << FMC_PATT_ATTHOLD_Pos)
	0x00200000
#define	FMC_PATT_ATTHOLD_6   (0x40UL << FMC_PATT_ATTHOLD_Pos)
	0x00400000
#define	FMC_PATT_ATTHOLD_7   (0x80UL << FMC_PATT_ATTHOLD_Pos)
	0x00800000
#define	FMC_PATT_ATTHIZ_Pos   (24U)
#define	FMC_PATT_ATTHIZ_Msk   (0xFFUL << FMC_PATT_ATTHIZ_Pos)
	0xFF000000
#define	FMC_PATT_ATTHIZ   FMC_PATT_ATTHIZ_Msk
	ATTHIZ[7:0] bits (Attribute memory databus HiZ time).
#define	FMC_PATT_ATTHIZ_0   (0x01UL << FMC_PATT_ATTHIZ_Pos)
	0x01000000
#define	FMC_PATT_ATTHIZ_1   (0x02UL << FMC_PATT_ATTHIZ_Pos)
	0x02000000
#define	FMC_PATT_ATTHIZ_2   (0x04UL << FMC_PATT_ATTHIZ_Pos)
	0x04000000
#define	FMC_PATT_ATTHIZ_3   (0x08UL << FMC_PATT_ATTHIZ_Pos)
	0x08000000
#define	FMC_PATT_ATTHIZ_4   (0x10UL << FMC_PATT_ATTHIZ_Pos)
	0x10000000
#define	FMC_PATT_ATTHIZ_5   (0x20UL << FMC_PATT_ATTHIZ_Pos)
	0x20000000
#define	FMC_PATT_ATTHIZ_6   (0x40UL << FMC_PATT_ATTHIZ_Pos)
	0x40000000
#define	FMC_PATT_ATTHIZ_7   (0x80UL << FMC_PATT_ATTHIZ_Pos)
	0x80000000
#define	FMC_ECCR3_ECC3_Pos   (0U)
#define	FMC_ECCR3_ECC3_Msk   (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)
	0xFFFFFFFF
#define	FMC_ECCR3_ECC3   FMC_ECCR3_ECC3_Msk
	ECC result.
#define	FMC_SDCRx_NC_Pos   (0U)
#define	FMC_SDCRx_NC_Msk   (0x3UL << FMC_SDCRx_NC_Pos)
	0x00000003
#define	FMC_SDCRx_NC   FMC_SDCRx_NC_Msk
	NC[1:0] bits (Number of column bits).
#define	FMC_SDCRx_NC_0   (0x1UL << FMC_SDCRx_NC_Pos)
	0x00000001
#define	FMC_SDCRx_NC_1   (0x2UL << FMC_SDCRx_NC_Pos)
	0x00000002
#define	FMC_SDCRx_NR_Pos   (2U)
#define	FMC_SDCRx_NR_Msk   (0x3UL << FMC_SDCRx_NR_Pos)
	0x0000000C
#define	FMC_SDCRx_NR   FMC_SDCRx_NR_Msk
	NR[1:0] bits (Number of row bits).
#define	FMC_SDCRx_NR_0   (0x1UL << FMC_SDCRx_NR_Pos)
	0x00000004
#define	FMC_SDCRx_NR_1   (0x2UL << FMC_SDCRx_NR_Pos)
	0x00000008
#define	FMC_SDCRx_MWID_Pos   (4U)
#define	FMC_SDCRx_MWID_Msk   (0x3UL << FMC_SDCRx_MWID_Pos)
	0x00000030
#define	FMC_SDCRx_MWID   FMC_SDCRx_MWID_Msk
	NR[1:0] bits (Number of row bits).
#define	FMC_SDCRx_MWID_0   (0x1UL << FMC_SDCRx_MWID_Pos)
	0x00000010
#define	FMC_SDCRx_MWID_1   (0x2UL << FMC_SDCRx_MWID_Pos)
	0x00000020
#define	FMC_SDCRx_NB_Pos   (6U)
#define	FMC_SDCRx_NB_Msk   (0x1UL << FMC_SDCRx_NB_Pos)
	0x00000040
#define	FMC_SDCRx_NB   FMC_SDCRx_NB_Msk
	Number of internal bank.
#define	FMC_SDCRx_CAS_Pos   (7U)
#define	FMC_SDCRx_CAS_Msk   (0x3UL << FMC_SDCRx_CAS_Pos)
	0x00000180
#define	FMC_SDCRx_CAS   FMC_SDCRx_CAS_Msk
	CAS[1:0] bits (CAS latency).
#define	FMC_SDCRx_CAS_0   (0x1UL << FMC_SDCRx_CAS_Pos)
	0x00000080
#define	FMC_SDCRx_CAS_1   (0x2UL << FMC_SDCRx_CAS_Pos)
	0x00000100
#define	FMC_SDCRx_WP_Pos   (9U)
#define	FMC_SDCRx_WP_Msk   (0x1UL << FMC_SDCRx_WP_Pos)
	0x00000200
#define	FMC_SDCRx_WP   FMC_SDCRx_WP_Msk
	Write protection.
#define	FMC_SDCRx_SDCLK_Pos   (10U)
#define	FMC_SDCRx_SDCLK_Msk   (0x3UL << FMC_SDCRx_SDCLK_Pos)
	0x00000C00
#define	FMC_SDCRx_SDCLK   FMC_SDCRx_SDCLK_Msk
	SDRAM clock configuration.
#define	FMC_SDCRx_SDCLK_0   (0x1UL << FMC_SDCRx_SDCLK_Pos)
	0x00000400
#define	FMC_SDCRx_SDCLK_1   (0x2UL << FMC_SDCRx_SDCLK_Pos)
	0x00000800
#define	FMC_SDCRx_RBURST_Pos   (12U)
#define	FMC_SDCRx_RBURST_Msk   (0x1UL << FMC_SDCRx_RBURST_Pos)
	0x00001000
#define	FMC_SDCRx_RBURST   FMC_SDCRx_RBURST_Msk
	Read burst.
#define	FMC_SDCRx_RPIPE_Pos   (13U)
#define	FMC_SDCRx_RPIPE_Msk   (0x3UL << FMC_SDCRx_RPIPE_Pos)
	0x00006000
#define	FMC_SDCRx_RPIPE   FMC_SDCRx_RPIPE_Msk
	Write protection.
#define	FMC_SDCRx_RPIPE_0   (0x1UL << FMC_SDCRx_RPIPE_Pos)
	0x00002000
#define	FMC_SDCRx_RPIPE_1   (0x2UL << FMC_SDCRx_RPIPE_Pos)
	0x00004000
#define	FMC_SDTRx_TMRD_Pos   (0U)
#define	FMC_SDTRx_TMRD_Msk   (0xFUL << FMC_SDTRx_TMRD_Pos)
	0x0000000F
#define	FMC_SDTRx_TMRD   FMC_SDTRx_TMRD_Msk
	TMRD[3:0] bits (Load mode register to active).
#define	FMC_SDTRx_TMRD_0   (0x1UL << FMC_SDTRx_TMRD_Pos)
	0x00000001
#define	FMC_SDTRx_TMRD_1   (0x2UL << FMC_SDTRx_TMRD_Pos)
	0x00000002
#define	FMC_SDTRx_TMRD_2   (0x4UL << FMC_SDTRx_TMRD_Pos)
	0x00000004
#define	FMC_SDTRx_TMRD_3   (0x8UL << FMC_SDTRx_TMRD_Pos)
	0x00000008
#define	FMC_SDTRx_TXSR_Pos   (4U)
#define	FMC_SDTRx_TXSR_Msk   (0xFUL << FMC_SDTRx_TXSR_Pos)
	0x000000F0
#define	FMC_SDTRx_TXSR   FMC_SDTRx_TXSR_Msk
	TXSR[3:0] bits (Exit self refresh).
#define	FMC_SDTRx_TXSR_0   (0x1UL << FMC_SDTRx_TXSR_Pos)
	0x00000010
#define	FMC_SDTRx_TXSR_1   (0x2UL << FMC_SDTRx_TXSR_Pos)
	0x00000020
#define	FMC_SDTRx_TXSR_2   (0x4UL << FMC_SDTRx_TXSR_Pos)
	0x00000040
#define	FMC_SDTRx_TXSR_3   (0x8UL << FMC_SDTRx_TXSR_Pos)
	0x00000080
#define	FMC_SDTRx_TRAS_Pos   (8U)
#define	FMC_SDTRx_TRAS_Msk   (0xFUL << FMC_SDTRx_TRAS_Pos)
	0x00000F00
#define	FMC_SDTRx_TRAS   FMC_SDTRx_TRAS_Msk
	TRAS[3:0] bits (Self refresh time).
#define	FMC_SDTRx_TRAS_0   (0x1UL << FMC_SDTRx_TRAS_Pos)
	0x00000100
#define	FMC_SDTRx_TRAS_1   (0x2UL << FMC_SDTRx_TRAS_Pos)
	0x00000200
#define	FMC_SDTRx_TRAS_2   (0x4UL << FMC_SDTRx_TRAS_Pos)
	0x00000400
#define	FMC_SDTRx_TRAS_3   (0x8UL << FMC_SDTRx_TRAS_Pos)
	0x00000800
#define	FMC_SDTRx_TRC_Pos   (12U)
#define	FMC_SDTRx_TRC_Msk   (0xFUL << FMC_SDTRx_TRC_Pos)
	0x0000F000
#define	FMC_SDTRx_TRC   FMC_SDTRx_TRC_Msk
	TRC[2:0] bits (Row cycle delay).
#define	FMC_SDTRx_TRC_0   (0x1UL << FMC_SDTRx_TRC_Pos)
	0x00001000
#define	FMC_SDTRx_TRC_1   (0x2UL << FMC_SDTRx_TRC_Pos)
	0x00002000
#define	FMC_SDTRx_TRC_2   (0x4UL << FMC_SDTRx_TRC_Pos)
	0x00004000
#define	FMC_SDTRx_TWR_Pos   (16U)
#define	FMC_SDTRx_TWR_Msk   (0xFUL << FMC_SDTRx_TWR_Pos)
	0x000F0000
#define	FMC_SDTRx_TWR   FMC_SDTRx_TWR_Msk
	TRC[2:0] bits (Write recovery delay).
#define	FMC_SDTRx_TWR_0   (0x1UL << FMC_SDTRx_TWR_Pos)
	0x00010000
#define	FMC_SDTRx_TWR_1   (0x2UL << FMC_SDTRx_TWR_Pos)
	0x00020000
#define	FMC_SDTRx_TWR_2   (0x4UL << FMC_SDTRx_TWR_Pos)
	0x00040000
#define	FMC_SDTRx_TRP_Pos   (20U)
#define	FMC_SDTRx_TRP_Msk   (0xFUL << FMC_SDTRx_TRP_Pos)
	0x00F00000
#define	FMC_SDTRx_TRP   FMC_SDTRx_TRP_Msk
	TRP[2:0] bits (Row precharge delay).
#define	FMC_SDTRx_TRP_0   (0x1UL << FMC_SDTRx_TRP_Pos)
	0x00100000
#define	FMC_SDTRx_TRP_1   (0x2UL << FMC_SDTRx_TRP_Pos)
	0x00200000
#define	FMC_SDTRx_TRP_2   (0x4UL << FMC_SDTRx_TRP_Pos)
	0x00400000
#define	FMC_SDTRx_TRCD_Pos   (24U)
#define	FMC_SDTRx_TRCD_Msk   (0xFUL << FMC_SDTRx_TRCD_Pos)
	0x0F000000
#define	FMC_SDTRx_TRCD   FMC_SDTRx_TRCD_Msk
	TRP[2:0] bits (Row to column delay).
#define	FMC_SDTRx_TRCD_0   (0x1UL << FMC_SDTRx_TRCD_Pos)
	0x01000000
#define	FMC_SDTRx_TRCD_1   (0x2UL << FMC_SDTRx_TRCD_Pos)
	0x02000000
#define	FMC_SDTRx_TRCD_2   (0x4UL << FMC_SDTRx_TRCD_Pos)
	0x04000000
#define	FMC_SDCMR_MODE_Pos   (0U)
#define	FMC_SDCMR_MODE_Msk   (0x7UL << FMC_SDCMR_MODE_Pos)
	0x00000007
#define	FMC_SDCMR_MODE   FMC_SDCMR_MODE_Msk
	MODE[2:0] bits (Command mode).
#define	FMC_SDCMR_MODE_0   (0x1UL << FMC_SDCMR_MODE_Pos)
	0x00000001
#define	FMC_SDCMR_MODE_1   (0x2UL << FMC_SDCMR_MODE_Pos)
	0x00000002
#define	FMC_SDCMR_MODE_2   (0x4UL << FMC_SDCMR_MODE_Pos)
	0x00000004
#define	FMC_SDCMR_CTB2_Pos   (3U)
#define	FMC_SDCMR_CTB2_Msk   (0x1UL << FMC_SDCMR_CTB2_Pos)
	0x00000008
#define	FMC_SDCMR_CTB2   FMC_SDCMR_CTB2_Msk
	Command target 2.
#define	FMC_SDCMR_CTB1_Pos   (4U)
#define	FMC_SDCMR_CTB1_Msk   (0x1UL << FMC_SDCMR_CTB1_Pos)
	0x00000010
#define	FMC_SDCMR_CTB1   FMC_SDCMR_CTB1_Msk
	Command target 1.
#define	FMC_SDCMR_NRFS_Pos   (5U)
#define	FMC_SDCMR_NRFS_Msk   (0xFUL << FMC_SDCMR_NRFS_Pos)
	0x000001E0
#define	FMC_SDCMR_NRFS   FMC_SDCMR_NRFS_Msk
	NRFS[3:0] bits (Number of auto-refresh).
#define	FMC_SDCMR_NRFS_0   (0x1UL << FMC_SDCMR_NRFS_Pos)
	0x00000020
#define	FMC_SDCMR_NRFS_1   (0x2UL << FMC_SDCMR_NRFS_Pos)
	0x00000040
#define	FMC_SDCMR_NRFS_2   (0x4UL << FMC_SDCMR_NRFS_Pos)
	0x00000080
#define	FMC_SDCMR_NRFS_3   (0x8UL << FMC_SDCMR_NRFS_Pos)
	0x00000100
#define	FMC_SDCMR_MRD_Pos   (9U)
#define	FMC_SDCMR_MRD_Msk   (0x1FFFUL << FMC_SDCMR_MRD_Pos)
	0x003FFE00
#define	FMC_SDCMR_MRD   FMC_SDCMR_MRD_Msk
	MRD[12:0] bits (Mode register definition).
#define	FMC_SDRTR_CRE_Pos   (0U)
#define	FMC_SDRTR_CRE_Msk   (0x1UL << FMC_SDRTR_CRE_Pos)
	0x00000001
#define	FMC_SDRTR_CRE   FMC_SDRTR_CRE_Msk
	Clear refresh error flag.
#define	FMC_SDRTR_COUNT_Pos   (1U)
#define	FMC_SDRTR_COUNT_Msk   (0x1FFFUL << FMC_SDRTR_COUNT_Pos)
	0x00003FFE
#define	FMC_SDRTR_COUNT   FMC_SDRTR_COUNT_Msk
	COUNT[12:0] bits (Refresh timer count).
#define	FMC_SDRTR_REIE_Pos   (14U)
#define	FMC_SDRTR_REIE_Msk   (0x1UL << FMC_SDRTR_REIE_Pos)
	0x00004000
#define	FMC_SDRTR_REIE   FMC_SDRTR_REIE_Msk
	RES interrupt enable.
#define	FMC_SDSR_RE_Pos   (0U)
#define	FMC_SDSR_RE_Msk   (0x1UL << FMC_SDSR_RE_Pos)
	0x00000001
#define	FMC_SDSR_RE   FMC_SDSR_RE_Msk
	Refresh error flag.
#define	FMC_SDSR_MODES1_Pos   (1U)
#define	FMC_SDSR_MODES1_Msk   (0x3UL << FMC_SDSR_MODES1_Pos)
	0x00000006
#define	FMC_SDSR_MODES1   FMC_SDSR_MODES1_Msk
	MODES1[1:0]bits (Status mode for bank 1).
#define	FMC_SDSR_MODES1_0   (0x1UL << FMC_SDSR_MODES1_Pos)
	0x00000002
#define	FMC_SDSR_MODES1_1   (0x2UL << FMC_SDSR_MODES1_Pos)
	0x00000004
#define	FMC_SDSR_MODES2_Pos   (3U)
#define	FMC_SDSR_MODES2_Msk   (0x3UL << FMC_SDSR_MODES2_Pos)
	0x00000018
#define	FMC_SDSR_MODES2   FMC_SDSR_MODES2_Msk
	MODES2[1:0]bits (Status mode for bank 2).
#define	FMC_SDSR_MODES2_0   (0x1UL << FMC_SDSR_MODES2_Pos)
	0x00000008
#define	FMC_SDSR_MODES2_1   (0x2UL << FMC_SDSR_MODES2_Pos)
	0x00000010
#define	GPIO_MODER_MODER0_Pos   (0U)
#define	GPIO_MODER_MODER0_Msk   (0x3UL << GPIO_MODER_MODER0_Pos)
	0x00000003
#define	GPIO_MODER_MODER0   GPIO_MODER_MODER0_Msk
#define	GPIO_MODER_MODER0_0   (0x1UL << GPIO_MODER_MODER0_Pos)
	0x00000001
#define	GPIO_MODER_MODER0_1   (0x2UL << GPIO_MODER_MODER0_Pos)
	0x00000002
#define	GPIO_MODER_MODER1_Pos   (2U)
#define	GPIO_MODER_MODER1_Msk   (0x3UL << GPIO_MODER_MODER1_Pos)
	0x0000000C
#define	GPIO_MODER_MODER1   GPIO_MODER_MODER1_Msk
#define	GPIO_MODER_MODER1_0   (0x1UL << GPIO_MODER_MODER1_Pos)
	0x00000004
#define	GPIO_MODER_MODER1_1   (0x2UL << GPIO_MODER_MODER1_Pos)
	0x00000008
#define	GPIO_MODER_MODER2_Pos   (4U)
#define	GPIO_MODER_MODER2_Msk   (0x3UL << GPIO_MODER_MODER2_Pos)
	0x00000030
#define	GPIO_MODER_MODER2   GPIO_MODER_MODER2_Msk
#define	GPIO_MODER_MODER2_0   (0x1UL << GPIO_MODER_MODER2_Pos)
	0x00000010
#define	GPIO_MODER_MODER2_1   (0x2UL << GPIO_MODER_MODER2_Pos)
	0x00000020
#define	GPIO_MODER_MODER3_Pos   (6U)
#define	GPIO_MODER_MODER3_Msk   (0x3UL << GPIO_MODER_MODER3_Pos)
	0x000000C0
#define	GPIO_MODER_MODER3   GPIO_MODER_MODER3_Msk
#define	GPIO_MODER_MODER3_0   (0x1UL << GPIO_MODER_MODER3_Pos)
	0x00000040
#define	GPIO_MODER_MODER3_1   (0x2UL << GPIO_MODER_MODER3_Pos)
	0x00000080
#define	GPIO_MODER_MODER4_Pos   (8U)
#define	GPIO_MODER_MODER4_Msk   (0x3UL << GPIO_MODER_MODER4_Pos)
	0x00000300
#define	GPIO_MODER_MODER4   GPIO_MODER_MODER4_Msk
#define	GPIO_MODER_MODER4_0   (0x1UL << GPIO_MODER_MODER4_Pos)
	0x00000100
#define	GPIO_MODER_MODER4_1   (0x2UL << GPIO_MODER_MODER4_Pos)
	0x00000200
#define	GPIO_MODER_MODER5_Pos   (10U)
#define	GPIO_MODER_MODER5_Msk   (0x3UL << GPIO_MODER_MODER5_Pos)
	0x00000C00
#define	GPIO_MODER_MODER5   GPIO_MODER_MODER5_Msk
#define	GPIO_MODER_MODER5_0   (0x1UL << GPIO_MODER_MODER5_Pos)
	0x00000400
#define	GPIO_MODER_MODER5_1   (0x2UL << GPIO_MODER_MODER5_Pos)
	0x00000800
#define	GPIO_MODER_MODER6_Pos   (12U)
#define	GPIO_MODER_MODER6_Msk   (0x3UL << GPIO_MODER_MODER6_Pos)
	0x00003000
#define	GPIO_MODER_MODER6   GPIO_MODER_MODER6_Msk
#define	GPIO_MODER_MODER6_0   (0x1UL << GPIO_MODER_MODER6_Pos)
	0x00001000
#define	GPIO_MODER_MODER6_1   (0x2UL << GPIO_MODER_MODER6_Pos)
	0x00002000
#define	GPIO_MODER_MODER7_Pos   (14U)
#define	GPIO_MODER_MODER7_Msk   (0x3UL << GPIO_MODER_MODER7_Pos)
	0x0000C000
#define	GPIO_MODER_MODER7   GPIO_MODER_MODER7_Msk
#define	GPIO_MODER_MODER7_0   (0x1UL << GPIO_MODER_MODER7_Pos)
	0x00004000
#define	GPIO_MODER_MODER7_1   (0x2UL << GPIO_MODER_MODER7_Pos)
	0x00008000
#define	GPIO_MODER_MODER8_Pos   (16U)
#define	GPIO_MODER_MODER8_Msk   (0x3UL << GPIO_MODER_MODER8_Pos)
	0x00030000
#define	GPIO_MODER_MODER8   GPIO_MODER_MODER8_Msk
#define	GPIO_MODER_MODER8_0   (0x1UL << GPIO_MODER_MODER8_Pos)
	0x00010000
#define	GPIO_MODER_MODER8_1   (0x2UL << GPIO_MODER_MODER8_Pos)
	0x00020000
#define	GPIO_MODER_MODER9_Pos   (18U)
#define	GPIO_MODER_MODER9_Msk   (0x3UL << GPIO_MODER_MODER9_Pos)
	0x000C0000
#define	GPIO_MODER_MODER9   GPIO_MODER_MODER9_Msk
#define	GPIO_MODER_MODER9_0   (0x1UL << GPIO_MODER_MODER9_Pos)
	0x00040000
#define	GPIO_MODER_MODER9_1   (0x2UL << GPIO_MODER_MODER9_Pos)
	0x00080000
#define	GPIO_MODER_MODER10_Pos   (20U)
#define	GPIO_MODER_MODER10_Msk   (0x3UL << GPIO_MODER_MODER10_Pos)
	0x00300000
#define	GPIO_MODER_MODER10   GPIO_MODER_MODER10_Msk
#define	GPIO_MODER_MODER10_0   (0x1UL << GPIO_MODER_MODER10_Pos)
	0x00100000
#define	GPIO_MODER_MODER10_1   (0x2UL << GPIO_MODER_MODER10_Pos)
	0x00200000
#define	GPIO_MODER_MODER11_Pos   (22U)
#define	GPIO_MODER_MODER11_Msk   (0x3UL << GPIO_MODER_MODER11_Pos)
	0x00C00000
#define	GPIO_MODER_MODER11   GPIO_MODER_MODER11_Msk
#define	GPIO_MODER_MODER11_0   (0x1UL << GPIO_MODER_MODER11_Pos)
	0x00400000
#define	GPIO_MODER_MODER11_1   (0x2UL << GPIO_MODER_MODER11_Pos)
	0x00800000
#define	GPIO_MODER_MODER12_Pos   (24U)
#define	GPIO_MODER_MODER12_Msk   (0x3UL << GPIO_MODER_MODER12_Pos)
	0x03000000
#define	GPIO_MODER_MODER12   GPIO_MODER_MODER12_Msk
#define	GPIO_MODER_MODER12_0   (0x1UL << GPIO_MODER_MODER12_Pos)
	0x01000000
#define	GPIO_MODER_MODER12_1   (0x2UL << GPIO_MODER_MODER12_Pos)
	0x02000000
#define	GPIO_MODER_MODER13_Pos   (26U)
#define	GPIO_MODER_MODER13_Msk   (0x3UL << GPIO_MODER_MODER13_Pos)
	0x0C000000
#define	GPIO_MODER_MODER13   GPIO_MODER_MODER13_Msk
#define	GPIO_MODER_MODER13_0   (0x1UL << GPIO_MODER_MODER13_Pos)
	0x04000000
#define	GPIO_MODER_MODER13_1   (0x2UL << GPIO_MODER_MODER13_Pos)
	0x08000000
#define	GPIO_MODER_MODER14_Pos   (28U)
#define	GPIO_MODER_MODER14_Msk   (0x3UL << GPIO_MODER_MODER14_Pos)
	0x30000000
#define	GPIO_MODER_MODER14   GPIO_MODER_MODER14_Msk
#define	GPIO_MODER_MODER14_0   (0x1UL << GPIO_MODER_MODER14_Pos)
	0x10000000
#define	GPIO_MODER_MODER14_1   (0x2UL << GPIO_MODER_MODER14_Pos)
	0x20000000
#define	GPIO_MODER_MODER15_Pos   (30U)
#define	GPIO_MODER_MODER15_Msk   (0x3UL << GPIO_MODER_MODER15_Pos)
	0xC0000000
#define	GPIO_MODER_MODER15   GPIO_MODER_MODER15_Msk
#define	GPIO_MODER_MODER15_0   (0x1UL << GPIO_MODER_MODER15_Pos)
	0x40000000
#define	GPIO_MODER_MODER15_1   (0x2UL << GPIO_MODER_MODER15_Pos)
	0x80000000
#define	GPIO_MODER_MODE0_Pos   GPIO_MODER_MODER0_Pos
#define	GPIO_MODER_MODE0_Msk   GPIO_MODER_MODER0_Msk
#define	GPIO_MODER_MODE0   GPIO_MODER_MODER0
#define	GPIO_MODER_MODE0_0   GPIO_MODER_MODER0_0
#define	GPIO_MODER_MODE0_1   GPIO_MODER_MODER0_1
#define	GPIO_MODER_MODE1_Pos   GPIO_MODER_MODER1_Pos
#define	GPIO_MODER_MODE1_Msk   GPIO_MODER_MODER1_Msk
#define	GPIO_MODER_MODE1   GPIO_MODER_MODER1
#define	GPIO_MODER_MODE1_0   GPIO_MODER_MODER1_0
#define	GPIO_MODER_MODE1_1   GPIO_MODER_MODER1_1
#define	GPIO_MODER_MODE2_Pos   GPIO_MODER_MODER2_Pos
#define	GPIO_MODER_MODE2_Msk   GPIO_MODER_MODER2_Msk
#define	GPIO_MODER_MODE2   GPIO_MODER_MODER2
#define	GPIO_MODER_MODE2_0   GPIO_MODER_MODER2_0
#define	GPIO_MODER_MODE2_1   GPIO_MODER_MODER2_1
#define	GPIO_MODER_MODE3_Pos   GPIO_MODER_MODER3_Pos
#define	GPIO_MODER_MODE3_Msk   GPIO_MODER_MODER3_Msk
#define	GPIO_MODER_MODE3   GPIO_MODER_MODER3
#define	GPIO_MODER_MODE3_0   GPIO_MODER_MODER3_0
#define	GPIO_MODER_MODE3_1   GPIO_MODER_MODER3_1
#define	GPIO_MODER_MODE4_Pos   GPIO_MODER_MODER4_Pos
#define	GPIO_MODER_MODE4_Msk   GPIO_MODER_MODER4_Msk
#define	GPIO_MODER_MODE4   GPIO_MODER_MODER4
#define	GPIO_MODER_MODE4_0   GPIO_MODER_MODER4_0
#define	GPIO_MODER_MODE4_1   GPIO_MODER_MODER4_1
#define	GPIO_MODER_MODE5_Pos   GPIO_MODER_MODER5_Pos
#define	GPIO_MODER_MODE5_Msk   GPIO_MODER_MODER5_Msk
#define	GPIO_MODER_MODE5   GPIO_MODER_MODER5
#define	GPIO_MODER_MODE5_0   GPIO_MODER_MODER5_0
#define	GPIO_MODER_MODE5_1   GPIO_MODER_MODER5_1
#define	GPIO_MODER_MODE6_Pos   GPIO_MODER_MODER6_Pos
#define	GPIO_MODER_MODE6_Msk   GPIO_MODER_MODER6_Msk
#define	GPIO_MODER_MODE6   GPIO_MODER_MODER6
#define	GPIO_MODER_MODE6_0   GPIO_MODER_MODER6_0
#define	GPIO_MODER_MODE6_1   GPIO_MODER_MODER6_1
#define	GPIO_MODER_MODE7_Pos   GPIO_MODER_MODER7_Pos
#define	GPIO_MODER_MODE7_Msk   GPIO_MODER_MODER7_Msk
#define	GPIO_MODER_MODE7   GPIO_MODER_MODER7
#define	GPIO_MODER_MODE7_0   GPIO_MODER_MODER7_0
#define	GPIO_MODER_MODE7_1   GPIO_MODER_MODER7_1
#define	GPIO_MODER_MODE8_Pos   GPIO_MODER_MODER8_Pos
#define	GPIO_MODER_MODE8_Msk   GPIO_MODER_MODER8_Msk
#define	GPIO_MODER_MODE8   GPIO_MODER_MODER8
#define	GPIO_MODER_MODE8_0   GPIO_MODER_MODER8_0
#define	GPIO_MODER_MODE8_1   GPIO_MODER_MODER8_1
#define	GPIO_MODER_MODE9_Pos   GPIO_MODER_MODER9_Pos
#define	GPIO_MODER_MODE9_Msk   GPIO_MODER_MODER9_Msk
#define	GPIO_MODER_MODE9   GPIO_MODER_MODER9
#define	GPIO_MODER_MODE9_0   GPIO_MODER_MODER9_0
#define	GPIO_MODER_MODE9_1   GPIO_MODER_MODER9_1
#define	GPIO_MODER_MODE10_Pos   GPIO_MODER_MODER10_Pos
#define	GPIO_MODER_MODE10_Msk   GPIO_MODER_MODER10_Msk
#define	GPIO_MODER_MODE10   GPIO_MODER_MODER10
#define	GPIO_MODER_MODE10_0   GPIO_MODER_MODER10_0
#define	GPIO_MODER_MODE10_1   GPIO_MODER_MODER10_1
#define	GPIO_MODER_MODE11_Pos   GPIO_MODER_MODER11_Pos
#define	GPIO_MODER_MODE11_Msk   GPIO_MODER_MODER11_Msk
#define	GPIO_MODER_MODE11   GPIO_MODER_MODER11
#define	GPIO_MODER_MODE11_0   GPIO_MODER_MODER11_0
#define	GPIO_MODER_MODE11_1   GPIO_MODER_MODER11_1
#define	GPIO_MODER_MODE12_Pos   GPIO_MODER_MODER12_Pos
#define	GPIO_MODER_MODE12_Msk   GPIO_MODER_MODER12_Msk
#define	GPIO_MODER_MODE12   GPIO_MODER_MODER12
#define	GPIO_MODER_MODE12_0   GPIO_MODER_MODER12_0
#define	GPIO_MODER_MODE12_1   GPIO_MODER_MODER12_1
#define	GPIO_MODER_MODE13_Pos   GPIO_MODER_MODER13_Pos
#define	GPIO_MODER_MODE13_Msk   GPIO_MODER_MODER13_Msk
#define	GPIO_MODER_MODE13   GPIO_MODER_MODER13
#define	GPIO_MODER_MODE13_0   GPIO_MODER_MODER13_0
#define	GPIO_MODER_MODE13_1   GPIO_MODER_MODER13_1
#define	GPIO_MODER_MODE14_Pos   GPIO_MODER_MODER14_Pos
#define	GPIO_MODER_MODE14_Msk   GPIO_MODER_MODER14_Msk
#define	GPIO_MODER_MODE14   GPIO_MODER_MODER14
#define	GPIO_MODER_MODE14_0   GPIO_MODER_MODER14_0
#define	GPIO_MODER_MODE14_1   GPIO_MODER_MODER14_1
#define	GPIO_MODER_MODE15_Pos   GPIO_MODER_MODER15_Pos
#define	GPIO_MODER_MODE15_Msk   GPIO_MODER_MODER15_Msk
#define	GPIO_MODER_MODE15   GPIO_MODER_MODER15
#define	GPIO_MODER_MODE15_0   GPIO_MODER_MODER15_0
#define	GPIO_MODER_MODE15_1   GPIO_MODER_MODER15_1
#define	GPIO_OTYPER_OT0_Pos   (0U)
#define	GPIO_OTYPER_OT0_Msk   (0x1UL << GPIO_OTYPER_OT0_Pos)
	0x00000001
#define	GPIO_OTYPER_OT0   GPIO_OTYPER_OT0_Msk
#define	GPIO_OTYPER_OT1_Pos   (1U)
#define	GPIO_OTYPER_OT1_Msk   (0x1UL << GPIO_OTYPER_OT1_Pos)
	0x00000002
#define	GPIO_OTYPER_OT1   GPIO_OTYPER_OT1_Msk
#define	GPIO_OTYPER_OT2_Pos   (2U)
#define	GPIO_OTYPER_OT2_Msk   (0x1UL << GPIO_OTYPER_OT2_Pos)
	0x00000004
#define	GPIO_OTYPER_OT2   GPIO_OTYPER_OT2_Msk
#define	GPIO_OTYPER_OT3_Pos   (3U)
#define	GPIO_OTYPER_OT3_Msk   (0x1UL << GPIO_OTYPER_OT3_Pos)
	0x00000008
#define	GPIO_OTYPER_OT3   GPIO_OTYPER_OT3_Msk
#define	GPIO_OTYPER_OT4_Pos   (4U)
#define	GPIO_OTYPER_OT4_Msk   (0x1UL << GPIO_OTYPER_OT4_Pos)
	0x00000010
#define	GPIO_OTYPER_OT4   GPIO_OTYPER_OT4_Msk
#define	GPIO_OTYPER_OT5_Pos   (5U)
#define	GPIO_OTYPER_OT5_Msk   (0x1UL << GPIO_OTYPER_OT5_Pos)
	0x00000020
#define	GPIO_OTYPER_OT5   GPIO_OTYPER_OT5_Msk
#define	GPIO_OTYPER_OT6_Pos   (6U)
#define	GPIO_OTYPER_OT6_Msk   (0x1UL << GPIO_OTYPER_OT6_Pos)
	0x00000040
#define	GPIO_OTYPER_OT6   GPIO_OTYPER_OT6_Msk
#define	GPIO_OTYPER_OT7_Pos   (7U)
#define	GPIO_OTYPER_OT7_Msk   (0x1UL << GPIO_OTYPER_OT7_Pos)
	0x00000080
#define	GPIO_OTYPER_OT7   GPIO_OTYPER_OT7_Msk
#define	GPIO_OTYPER_OT8_Pos   (8U)
#define	GPIO_OTYPER_OT8_Msk   (0x1UL << GPIO_OTYPER_OT8_Pos)
	0x00000100
#define	GPIO_OTYPER_OT8   GPIO_OTYPER_OT8_Msk
#define	GPIO_OTYPER_OT9_Pos   (9U)
#define	GPIO_OTYPER_OT9_Msk   (0x1UL << GPIO_OTYPER_OT9_Pos)
	0x00000200
#define	GPIO_OTYPER_OT9   GPIO_OTYPER_OT9_Msk
#define	GPIO_OTYPER_OT10_Pos   (10U)
#define	GPIO_OTYPER_OT10_Msk   (0x1UL << GPIO_OTYPER_OT10_Pos)
	0x00000400
#define	GPIO_OTYPER_OT10   GPIO_OTYPER_OT10_Msk
#define	GPIO_OTYPER_OT11_Pos   (11U)
#define	GPIO_OTYPER_OT11_Msk   (0x1UL << GPIO_OTYPER_OT11_Pos)
	0x00000800
#define	GPIO_OTYPER_OT11   GPIO_OTYPER_OT11_Msk
#define	GPIO_OTYPER_OT12_Pos   (12U)
#define	GPIO_OTYPER_OT12_Msk   (0x1UL << GPIO_OTYPER_OT12_Pos)
	0x00001000
#define	GPIO_OTYPER_OT12   GPIO_OTYPER_OT12_Msk
#define	GPIO_OTYPER_OT13_Pos   (13U)
#define	GPIO_OTYPER_OT13_Msk   (0x1UL << GPIO_OTYPER_OT13_Pos)
	0x00002000
#define	GPIO_OTYPER_OT13   GPIO_OTYPER_OT13_Msk
#define	GPIO_OTYPER_OT14_Pos   (14U)
#define	GPIO_OTYPER_OT14_Msk   (0x1UL << GPIO_OTYPER_OT14_Pos)
	0x00004000
#define	GPIO_OTYPER_OT14   GPIO_OTYPER_OT14_Msk
#define	GPIO_OTYPER_OT15_Pos   (15U)
#define	GPIO_OTYPER_OT15_Msk   (0x1UL << GPIO_OTYPER_OT15_Pos)
	0x00008000
#define	GPIO_OTYPER_OT15   GPIO_OTYPER_OT15_Msk
#define	GPIO_OSPEEDR_OSPEED0_Pos   (0U)
#define	GPIO_OSPEEDR_OSPEED0_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
	0x00000003
#define	GPIO_OSPEEDR_OSPEED0   GPIO_OSPEEDR_OSPEED0_Msk
#define	GPIO_OSPEEDR_OSPEED0_0   (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
	0x00000001
#define	GPIO_OSPEEDR_OSPEED0_1   (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
	0x00000002
#define	GPIO_OSPEEDR_OSPEED1_Pos   (2U)
#define	GPIO_OSPEEDR_OSPEED1_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
	0x0000000C
#define	GPIO_OSPEEDR_OSPEED1   GPIO_OSPEEDR_OSPEED1_Msk
#define	GPIO_OSPEEDR_OSPEED1_0   (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
	0x00000004
#define	GPIO_OSPEEDR_OSPEED1_1   (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
	0x00000008
#define	GPIO_OSPEEDR_OSPEED2_Pos   (4U)
#define	GPIO_OSPEEDR_OSPEED2_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
	0x00000030
#define	GPIO_OSPEEDR_OSPEED2   GPIO_OSPEEDR_OSPEED2_Msk
#define	GPIO_OSPEEDR_OSPEED2_0   (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
	0x00000010
#define	GPIO_OSPEEDR_OSPEED2_1   (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
	0x00000020
#define	GPIO_OSPEEDR_OSPEED3_Pos   (6U)
#define	GPIO_OSPEEDR_OSPEED3_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
	0x000000C0
#define	GPIO_OSPEEDR_OSPEED3   GPIO_OSPEEDR_OSPEED3_Msk
#define	GPIO_OSPEEDR_OSPEED3_0   (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
	0x00000040
#define	GPIO_OSPEEDR_OSPEED3_1   (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
	0x00000080
#define	GPIO_OSPEEDR_OSPEED4_Pos   (8U)
#define	GPIO_OSPEEDR_OSPEED4_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
	0x00000300
#define	GPIO_OSPEEDR_OSPEED4   GPIO_OSPEEDR_OSPEED4_Msk
#define	GPIO_OSPEEDR_OSPEED4_0   (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
	0x00000100
#define	GPIO_OSPEEDR_OSPEED4_1   (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
	0x00000200
#define	GPIO_OSPEEDR_OSPEED5_Pos   (10U)
#define	GPIO_OSPEEDR_OSPEED5_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
	0x00000C00
#define	GPIO_OSPEEDR_OSPEED5   GPIO_OSPEEDR_OSPEED5_Msk
#define	GPIO_OSPEEDR_OSPEED5_0   (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
	0x00000400
#define	GPIO_OSPEEDR_OSPEED5_1   (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
	0x00000800
#define	GPIO_OSPEEDR_OSPEED6_Pos   (12U)
#define	GPIO_OSPEEDR_OSPEED6_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
	0x00003000
#define	GPIO_OSPEEDR_OSPEED6   GPIO_OSPEEDR_OSPEED6_Msk
#define	GPIO_OSPEEDR_OSPEED6_0   (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
	0x00001000
#define	GPIO_OSPEEDR_OSPEED6_1   (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
	0x00002000
#define	GPIO_OSPEEDR_OSPEED7_Pos   (14U)
#define	GPIO_OSPEEDR_OSPEED7_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
	0x0000C000
#define	GPIO_OSPEEDR_OSPEED7   GPIO_OSPEEDR_OSPEED7_Msk
#define	GPIO_OSPEEDR_OSPEED7_0   (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
	0x00004000
#define	GPIO_OSPEEDR_OSPEED7_1   (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
	0x00008000
#define	GPIO_OSPEEDR_OSPEED8_Pos   (16U)
#define	GPIO_OSPEEDR_OSPEED8_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
	0x00030000
#define	GPIO_OSPEEDR_OSPEED8   GPIO_OSPEEDR_OSPEED8_Msk
#define	GPIO_OSPEEDR_OSPEED8_0   (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
	0x00010000
#define	GPIO_OSPEEDR_OSPEED8_1   (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
	0x00020000
#define	GPIO_OSPEEDR_OSPEED9_Pos   (18U)
#define	GPIO_OSPEEDR_OSPEED9_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
	0x000C0000
#define	GPIO_OSPEEDR_OSPEED9   GPIO_OSPEEDR_OSPEED9_Msk
#define	GPIO_OSPEEDR_OSPEED9_0   (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
	0x00040000
#define	GPIO_OSPEEDR_OSPEED9_1   (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
	0x00080000
#define	GPIO_OSPEEDR_OSPEED10_Pos   (20U)
#define	GPIO_OSPEEDR_OSPEED10_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
	0x00300000
#define	GPIO_OSPEEDR_OSPEED10   GPIO_OSPEEDR_OSPEED10_Msk
#define	GPIO_OSPEEDR_OSPEED10_0   (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
	0x00100000
#define	GPIO_OSPEEDR_OSPEED10_1   (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
	0x00200000
#define	GPIO_OSPEEDR_OSPEED11_Pos   (22U)
#define	GPIO_OSPEEDR_OSPEED11_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
	0x00C00000
#define	GPIO_OSPEEDR_OSPEED11   GPIO_OSPEEDR_OSPEED11_Msk
#define	GPIO_OSPEEDR_OSPEED11_0   (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
	0x00400000
#define	GPIO_OSPEEDR_OSPEED11_1   (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
	0x00800000
#define	GPIO_OSPEEDR_OSPEED12_Pos   (24U)
#define	GPIO_OSPEEDR_OSPEED12_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
	0x03000000
#define	GPIO_OSPEEDR_OSPEED12   GPIO_OSPEEDR_OSPEED12_Msk
#define	GPIO_OSPEEDR_OSPEED12_0   (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
	0x01000000
#define	GPIO_OSPEEDR_OSPEED12_1   (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
	0x02000000
#define	GPIO_OSPEEDR_OSPEED13_Pos   (26U)
#define	GPIO_OSPEEDR_OSPEED13_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
	0x0C000000
#define	GPIO_OSPEEDR_OSPEED13   GPIO_OSPEEDR_OSPEED13_Msk
#define	GPIO_OSPEEDR_OSPEED13_0   (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
	0x04000000
#define	GPIO_OSPEEDR_OSPEED13_1   (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
	0x08000000
#define	GPIO_OSPEEDR_OSPEED14_Pos   (28U)
#define	GPIO_OSPEEDR_OSPEED14_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
	0x30000000
#define	GPIO_OSPEEDR_OSPEED14   GPIO_OSPEEDR_OSPEED14_Msk
#define	GPIO_OSPEEDR_OSPEED14_0   (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
	0x10000000
#define	GPIO_OSPEEDR_OSPEED14_1   (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
	0x20000000
#define	GPIO_OSPEEDR_OSPEED15_Pos   (30U)
#define	GPIO_OSPEEDR_OSPEED15_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
	0xC0000000
#define	GPIO_OSPEEDR_OSPEED15   GPIO_OSPEEDR_OSPEED15_Msk
#define	GPIO_OSPEEDR_OSPEED15_0   (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
	0x40000000
#define	GPIO_OSPEEDR_OSPEED15_1   (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
	0x80000000
#define	GPIO_PUPDR_PUPD0_Pos   (0U)
#define	GPIO_PUPDR_PUPD0_Msk   (0x3UL << GPIO_PUPDR_PUPD0_Pos)
	0x00000003
#define	GPIO_PUPDR_PUPD0   GPIO_PUPDR_PUPD0_Msk
#define	GPIO_PUPDR_PUPD0_0   (0x1UL << GPIO_PUPDR_PUPD0_Pos)
	0x00000001
#define	GPIO_PUPDR_PUPD0_1   (0x2UL << GPIO_PUPDR_PUPD0_Pos)
	0x00000002
#define	GPIO_PUPDR_PUPD1_Pos   (2U)
#define	GPIO_PUPDR_PUPD1_Msk   (0x3UL << GPIO_PUPDR_PUPD1_Pos)
	0x0000000C
#define	GPIO_PUPDR_PUPD1   GPIO_PUPDR_PUPD1_Msk
#define	GPIO_PUPDR_PUPD1_0   (0x1UL << GPIO_PUPDR_PUPD1_Pos)
	0x00000004
#define	GPIO_PUPDR_PUPD1_1   (0x2UL << GPIO_PUPDR_PUPD1_Pos)
	0x00000008
#define	GPIO_PUPDR_PUPD2_Pos   (4U)
#define	GPIO_PUPDR_PUPD2_Msk   (0x3UL << GPIO_PUPDR_PUPD2_Pos)
	0x00000030
#define	GPIO_PUPDR_PUPD2   GPIO_PUPDR_PUPD2_Msk
#define	GPIO_PUPDR_PUPD2_0   (0x1UL << GPIO_PUPDR_PUPD2_Pos)
	0x00000010
#define	GPIO_PUPDR_PUPD2_1   (0x2UL << GPIO_PUPDR_PUPD2_Pos)
	0x00000020
#define	GPIO_PUPDR_PUPD3_Pos   (6U)
#define	GPIO_PUPDR_PUPD3_Msk   (0x3UL << GPIO_PUPDR_PUPD3_Pos)
	0x000000C0
#define	GPIO_PUPDR_PUPD3   GPIO_PUPDR_PUPD3_Msk
#define	GPIO_PUPDR_PUPD3_0   (0x1UL << GPIO_PUPDR_PUPD3_Pos)
	0x00000040
#define	GPIO_PUPDR_PUPD3_1   (0x2UL << GPIO_PUPDR_PUPD3_Pos)
	0x00000080
#define	GPIO_PUPDR_PUPD4_Pos   (8U)
#define	GPIO_PUPDR_PUPD4_Msk   (0x3UL << GPIO_PUPDR_PUPD4_Pos)
	0x00000300
#define	GPIO_PUPDR_PUPD4   GPIO_PUPDR_PUPD4_Msk
#define	GPIO_PUPDR_PUPD4_0   (0x1UL << GPIO_PUPDR_PUPD4_Pos)
	0x00000100
#define	GPIO_PUPDR_PUPD4_1   (0x2UL << GPIO_PUPDR_PUPD4_Pos)
	0x00000200
#define	GPIO_PUPDR_PUPD5_Pos   (10U)
#define	GPIO_PUPDR_PUPD5_Msk   (0x3UL << GPIO_PUPDR_PUPD5_Pos)
	0x00000C00
#define	GPIO_PUPDR_PUPD5   GPIO_PUPDR_PUPD5_Msk
#define	GPIO_PUPDR_PUPD5_0   (0x1UL << GPIO_PUPDR_PUPD5_Pos)
	0x00000400
#define	GPIO_PUPDR_PUPD5_1   (0x2UL << GPIO_PUPDR_PUPD5_Pos)
	0x00000800
#define	GPIO_PUPDR_PUPD6_Pos   (12U)
#define	GPIO_PUPDR_PUPD6_Msk   (0x3UL << GPIO_PUPDR_PUPD6_Pos)
	0x00003000
#define	GPIO_PUPDR_PUPD6   GPIO_PUPDR_PUPD6_Msk
#define	GPIO_PUPDR_PUPD6_0   (0x1UL << GPIO_PUPDR_PUPD6_Pos)
	0x00001000
#define	GPIO_PUPDR_PUPD6_1   (0x2UL << GPIO_PUPDR_PUPD6_Pos)
	0x00002000
#define	GPIO_PUPDR_PUPD7_Pos   (14U)
#define	GPIO_PUPDR_PUPD7_Msk   (0x3UL << GPIO_PUPDR_PUPD7_Pos)
	0x0000C000
#define	GPIO_PUPDR_PUPD7   GPIO_PUPDR_PUPD7_Msk
#define	GPIO_PUPDR_PUPD7_0   (0x1UL << GPIO_PUPDR_PUPD7_Pos)
	0x00004000
#define	GPIO_PUPDR_PUPD7_1   (0x2UL << GPIO_PUPDR_PUPD7_Pos)
	0x00008000
#define	GPIO_PUPDR_PUPD8_Pos   (16U)
#define	GPIO_PUPDR_PUPD8_Msk   (0x3UL << GPIO_PUPDR_PUPD8_Pos)
	0x00030000
#define	GPIO_PUPDR_PUPD8   GPIO_PUPDR_PUPD8_Msk
#define	GPIO_PUPDR_PUPD8_0   (0x1UL << GPIO_PUPDR_PUPD8_Pos)
	0x00010000
#define	GPIO_PUPDR_PUPD8_1   (0x2UL << GPIO_PUPDR_PUPD8_Pos)
	0x00020000
#define	GPIO_PUPDR_PUPD9_Pos   (18U)
#define	GPIO_PUPDR_PUPD9_Msk   (0x3UL << GPIO_PUPDR_PUPD9_Pos)
	0x000C0000
#define	GPIO_PUPDR_PUPD9   GPIO_PUPDR_PUPD9_Msk
#define	GPIO_PUPDR_PUPD9_0   (0x1UL << GPIO_PUPDR_PUPD9_Pos)
	0x00040000
#define	GPIO_PUPDR_PUPD9_1   (0x2UL << GPIO_PUPDR_PUPD9_Pos)
	0x00080000
#define	GPIO_PUPDR_PUPD10_Pos   (20U)
#define	GPIO_PUPDR_PUPD10_Msk   (0x3UL << GPIO_PUPDR_PUPD10_Pos)
	0x00300000
#define	GPIO_PUPDR_PUPD10   GPIO_PUPDR_PUPD10_Msk
#define	GPIO_PUPDR_PUPD10_0   (0x1UL << GPIO_PUPDR_PUPD10_Pos)
	0x00100000
#define	GPIO_PUPDR_PUPD10_1   (0x2UL << GPIO_PUPDR_PUPD10_Pos)
	0x00200000
#define	GPIO_PUPDR_PUPD11_Pos   (22U)
#define	GPIO_PUPDR_PUPD11_Msk   (0x3UL << GPIO_PUPDR_PUPD11_Pos)
	0x00C00000
#define	GPIO_PUPDR_PUPD11   GPIO_PUPDR_PUPD11_Msk
#define	GPIO_PUPDR_PUPD11_0   (0x1UL << GPIO_PUPDR_PUPD11_Pos)
	0x00400000
#define	GPIO_PUPDR_PUPD11_1   (0x2UL << GPIO_PUPDR_PUPD11_Pos)
	0x00800000
#define	GPIO_PUPDR_PUPD12_Pos   (24U)
#define	GPIO_PUPDR_PUPD12_Msk   (0x3UL << GPIO_PUPDR_PUPD12_Pos)
	0x03000000
#define	GPIO_PUPDR_PUPD12   GPIO_PUPDR_PUPD12_Msk
#define	GPIO_PUPDR_PUPD12_0   (0x1UL << GPIO_PUPDR_PUPD12_Pos)
	0x01000000
#define	GPIO_PUPDR_PUPD12_1   (0x2UL << GPIO_PUPDR_PUPD12_Pos)
	0x02000000
#define	GPIO_PUPDR_PUPD13_Pos   (26U)
#define	GPIO_PUPDR_PUPD13_Msk   (0x3UL << GPIO_PUPDR_PUPD13_Pos)
	0x0C000000
#define	GPIO_PUPDR_PUPD13   GPIO_PUPDR_PUPD13_Msk
#define	GPIO_PUPDR_PUPD13_0   (0x1UL << GPIO_PUPDR_PUPD13_Pos)
	0x04000000
#define	GPIO_PUPDR_PUPD13_1   (0x2UL << GPIO_PUPDR_PUPD13_Pos)
	0x08000000
#define	GPIO_PUPDR_PUPD14_Pos   (28U)
#define	GPIO_PUPDR_PUPD14_Msk   (0x3UL << GPIO_PUPDR_PUPD14_Pos)
	0x30000000
#define	GPIO_PUPDR_PUPD14   GPIO_PUPDR_PUPD14_Msk
#define	GPIO_PUPDR_PUPD14_0   (0x1UL << GPIO_PUPDR_PUPD14_Pos)
	0x10000000
#define	GPIO_PUPDR_PUPD14_1   (0x2UL << GPIO_PUPDR_PUPD14_Pos)
	0x20000000
#define	GPIO_PUPDR_PUPD15_Pos   (30U)
#define	GPIO_PUPDR_PUPD15_Msk   (0x3UL << GPIO_PUPDR_PUPD15_Pos)
	0xC0000000
#define	GPIO_PUPDR_PUPD15   GPIO_PUPDR_PUPD15_Msk
#define	GPIO_PUPDR_PUPD15_0   (0x1UL << GPIO_PUPDR_PUPD15_Pos)
	0x40000000
#define	GPIO_PUPDR_PUPD15_1   (0x2UL << GPIO_PUPDR_PUPD15_Pos)
	0x80000000
#define	GPIO_IDR_ID0_Pos   (0U)
#define	GPIO_IDR_ID0_Msk   (0x1UL << GPIO_IDR_ID0_Pos)
	0x00000001
#define	GPIO_IDR_ID0   GPIO_IDR_ID0_Msk
#define	GPIO_IDR_ID1_Pos   (1U)
#define	GPIO_IDR_ID1_Msk   (0x1UL << GPIO_IDR_ID1_Pos)
	0x00000002
#define	GPIO_IDR_ID1   GPIO_IDR_ID1_Msk
#define	GPIO_IDR_ID2_Pos   (2U)
#define	GPIO_IDR_ID2_Msk   (0x1UL << GPIO_IDR_ID2_Pos)
	0x00000004
#define	GPIO_IDR_ID2   GPIO_IDR_ID2_Msk
#define	GPIO_IDR_ID3_Pos   (3U)
#define	GPIO_IDR_ID3_Msk   (0x1UL << GPIO_IDR_ID3_Pos)
	0x00000008
#define	GPIO_IDR_ID3   GPIO_IDR_ID3_Msk
#define	GPIO_IDR_ID4_Pos   (4U)
#define	GPIO_IDR_ID4_Msk   (0x1UL << GPIO_IDR_ID4_Pos)
	0x00000010
#define	GPIO_IDR_ID4   GPIO_IDR_ID4_Msk
#define	GPIO_IDR_ID5_Pos   (5U)
#define	GPIO_IDR_ID5_Msk   (0x1UL << GPIO_IDR_ID5_Pos)
	0x00000020
#define	GPIO_IDR_ID5   GPIO_IDR_ID5_Msk
#define	GPIO_IDR_ID6_Pos   (6U)
#define	GPIO_IDR_ID6_Msk   (0x1UL << GPIO_IDR_ID6_Pos)
	0x00000040
#define	GPIO_IDR_ID6   GPIO_IDR_ID6_Msk
#define	GPIO_IDR_ID7_Pos   (7U)
#define	GPIO_IDR_ID7_Msk   (0x1UL << GPIO_IDR_ID7_Pos)
	0x00000080
#define	GPIO_IDR_ID7   GPIO_IDR_ID7_Msk
#define	GPIO_IDR_ID8_Pos   (8U)
#define	GPIO_IDR_ID8_Msk   (0x1UL << GPIO_IDR_ID8_Pos)
	0x00000100
#define	GPIO_IDR_ID8   GPIO_IDR_ID8_Msk
#define	GPIO_IDR_ID9_Pos   (9U)
#define	GPIO_IDR_ID9_Msk   (0x1UL << GPIO_IDR_ID9_Pos)
	0x00000200
#define	GPIO_IDR_ID9   GPIO_IDR_ID9_Msk
#define	GPIO_IDR_ID10_Pos   (10U)
#define	GPIO_IDR_ID10_Msk   (0x1UL << GPIO_IDR_ID10_Pos)
	0x00000400
#define	GPIO_IDR_ID10   GPIO_IDR_ID10_Msk
#define	GPIO_IDR_ID11_Pos   (11U)
#define	GPIO_IDR_ID11_Msk   (0x1UL << GPIO_IDR_ID11_Pos)
	0x00000800
#define	GPIO_IDR_ID11   GPIO_IDR_ID11_Msk
#define	GPIO_IDR_ID12_Pos   (12U)
#define	GPIO_IDR_ID12_Msk   (0x1UL << GPIO_IDR_ID12_Pos)
	0x00001000
#define	GPIO_IDR_ID12   GPIO_IDR_ID12_Msk
#define	GPIO_IDR_ID13_Pos   (13U)
#define	GPIO_IDR_ID13_Msk   (0x1UL << GPIO_IDR_ID13_Pos)
	0x00002000
#define	GPIO_IDR_ID13   GPIO_IDR_ID13_Msk
#define	GPIO_IDR_ID14_Pos   (14U)
#define	GPIO_IDR_ID14_Msk   (0x1UL << GPIO_IDR_ID14_Pos)
	0x00004000
#define	GPIO_IDR_ID14   GPIO_IDR_ID14_Msk
#define	GPIO_IDR_ID15_Pos   (15U)
#define	GPIO_IDR_ID15_Msk   (0x1UL << GPIO_IDR_ID15_Pos)
	0x00008000
#define	GPIO_IDR_ID15   GPIO_IDR_ID15_Msk
#define	GPIO_ODR_OD0_Pos   (0U)
#define	GPIO_ODR_OD0_Msk   (0x1UL << GPIO_ODR_OD0_Pos)
	0x00000001
#define	GPIO_ODR_OD0   GPIO_ODR_OD0_Msk
#define	GPIO_ODR_OD1_Pos   (1U)
#define	GPIO_ODR_OD1_Msk   (0x1UL << GPIO_ODR_OD1_Pos)
	0x00000002
#define	GPIO_ODR_OD1   GPIO_ODR_OD1_Msk
#define	GPIO_ODR_OD2_Pos   (2U)
#define	GPIO_ODR_OD2_Msk   (0x1UL << GPIO_ODR_OD2_Pos)
	0x00000004
#define	GPIO_ODR_OD2   GPIO_ODR_OD2_Msk
#define	GPIO_ODR_OD3_Pos   (3U)
#define	GPIO_ODR_OD3_Msk   (0x1UL << GPIO_ODR_OD3_Pos)
	0x00000008
#define	GPIO_ODR_OD3   GPIO_ODR_OD3_Msk
#define	GPIO_ODR_OD4_Pos   (4U)
#define	GPIO_ODR_OD4_Msk   (0x1UL << GPIO_ODR_OD4_Pos)
	0x00000010
#define	GPIO_ODR_OD4   GPIO_ODR_OD4_Msk
#define	GPIO_ODR_OD5_Pos   (5U)
#define	GPIO_ODR_OD5_Msk   (0x1UL << GPIO_ODR_OD5_Pos)
	0x00000020
#define	GPIO_ODR_OD5   GPIO_ODR_OD5_Msk
#define	GPIO_ODR_OD6_Pos   (6U)
#define	GPIO_ODR_OD6_Msk   (0x1UL << GPIO_ODR_OD6_Pos)
	0x00000040
#define	GPIO_ODR_OD6   GPIO_ODR_OD6_Msk
#define	GPIO_ODR_OD7_Pos   (7U)
#define	GPIO_ODR_OD7_Msk   (0x1UL << GPIO_ODR_OD7_Pos)
	0x00000080
#define	GPIO_ODR_OD7   GPIO_ODR_OD7_Msk
#define	GPIO_ODR_OD8_Pos   (8U)
#define	GPIO_ODR_OD8_Msk   (0x1UL << GPIO_ODR_OD8_Pos)
	0x00000100
#define	GPIO_ODR_OD8   GPIO_ODR_OD8_Msk
#define	GPIO_ODR_OD9_Pos   (9U)
#define	GPIO_ODR_OD9_Msk   (0x1UL << GPIO_ODR_OD9_Pos)
	0x00000200
#define	GPIO_ODR_OD9   GPIO_ODR_OD9_Msk
#define	GPIO_ODR_OD10_Pos   (10U)
#define	GPIO_ODR_OD10_Msk   (0x1UL << GPIO_ODR_OD10_Pos)
	0x00000400
#define	GPIO_ODR_OD10   GPIO_ODR_OD10_Msk
#define	GPIO_ODR_OD11_Pos   (11U)
#define	GPIO_ODR_OD11_Msk   (0x1UL << GPIO_ODR_OD11_Pos)
	0x00000800
#define	GPIO_ODR_OD11   GPIO_ODR_OD11_Msk
#define	GPIO_ODR_OD12_Pos   (12U)
#define	GPIO_ODR_OD12_Msk   (0x1UL << GPIO_ODR_OD12_Pos)
	0x00001000
#define	GPIO_ODR_OD12   GPIO_ODR_OD12_Msk
#define	GPIO_ODR_OD13_Pos   (13U)
#define	GPIO_ODR_OD13_Msk   (0x1UL << GPIO_ODR_OD13_Pos)
	0x00002000
#define	GPIO_ODR_OD13   GPIO_ODR_OD13_Msk
#define	GPIO_ODR_OD14_Pos   (14U)
#define	GPIO_ODR_OD14_Msk   (0x1UL << GPIO_ODR_OD14_Pos)
	0x00004000
#define	GPIO_ODR_OD14   GPIO_ODR_OD14_Msk
#define	GPIO_ODR_OD15_Pos   (15U)
#define	GPIO_ODR_OD15_Msk   (0x1UL << GPIO_ODR_OD15_Pos)
	0x00008000
#define	GPIO_ODR_OD15   GPIO_ODR_OD15_Msk
#define	GPIO_BSRR_BS0_Pos   (0U)
#define	GPIO_BSRR_BS0_Msk   (0x1UL << GPIO_BSRR_BS0_Pos)
	0x00000001
#define	GPIO_BSRR_BS0   GPIO_BSRR_BS0_Msk
#define	GPIO_BSRR_BS1_Pos   (1U)
#define	GPIO_BSRR_BS1_Msk   (0x1UL << GPIO_BSRR_BS1_Pos)
	0x00000002
#define	GPIO_BSRR_BS1   GPIO_BSRR_BS1_Msk
#define	GPIO_BSRR_BS2_Pos   (2U)
#define	GPIO_BSRR_BS2_Msk   (0x1UL << GPIO_BSRR_BS2_Pos)
	0x00000004
#define	GPIO_BSRR_BS2   GPIO_BSRR_BS2_Msk
#define	GPIO_BSRR_BS3_Pos   (3U)
#define	GPIO_BSRR_BS3_Msk   (0x1UL << GPIO_BSRR_BS3_Pos)
	0x00000008
#define	GPIO_BSRR_BS3   GPIO_BSRR_BS3_Msk
#define	GPIO_BSRR_BS4_Pos   (4U)
#define	GPIO_BSRR_BS4_Msk   (0x1UL << GPIO_BSRR_BS4_Pos)
	0x00000010
#define	GPIO_BSRR_BS4   GPIO_BSRR_BS4_Msk
#define	GPIO_BSRR_BS5_Pos   (5U)
#define	GPIO_BSRR_BS5_Msk   (0x1UL << GPIO_BSRR_BS5_Pos)
	0x00000020
#define	GPIO_BSRR_BS5   GPIO_BSRR_BS5_Msk
#define	GPIO_BSRR_BS6_Pos   (6U)
#define	GPIO_BSRR_BS6_Msk   (0x1UL << GPIO_BSRR_BS6_Pos)
	0x00000040
#define	GPIO_BSRR_BS6   GPIO_BSRR_BS6_Msk
#define	GPIO_BSRR_BS7_Pos   (7U)
#define	GPIO_BSRR_BS7_Msk   (0x1UL << GPIO_BSRR_BS7_Pos)
	0x00000080
#define	GPIO_BSRR_BS7   GPIO_BSRR_BS7_Msk
#define	GPIO_BSRR_BS8_Pos   (8U)
#define	GPIO_BSRR_BS8_Msk   (0x1UL << GPIO_BSRR_BS8_Pos)
	0x00000100
#define	GPIO_BSRR_BS8   GPIO_BSRR_BS8_Msk
#define	GPIO_BSRR_BS9_Pos   (9U)
#define	GPIO_BSRR_BS9_Msk   (0x1UL << GPIO_BSRR_BS9_Pos)
	0x00000200
#define	GPIO_BSRR_BS9   GPIO_BSRR_BS9_Msk
#define	GPIO_BSRR_BS10_Pos   (10U)
#define	GPIO_BSRR_BS10_Msk   (0x1UL << GPIO_BSRR_BS10_Pos)
	0x00000400
#define	GPIO_BSRR_BS10   GPIO_BSRR_BS10_Msk
#define	GPIO_BSRR_BS11_Pos   (11U)
#define	GPIO_BSRR_BS11_Msk   (0x1UL << GPIO_BSRR_BS11_Pos)
	0x00000800
#define	GPIO_BSRR_BS11   GPIO_BSRR_BS11_Msk
#define	GPIO_BSRR_BS12_Pos   (12U)
#define	GPIO_BSRR_BS12_Msk   (0x1UL << GPIO_BSRR_BS12_Pos)
	0x00001000
#define	GPIO_BSRR_BS12   GPIO_BSRR_BS12_Msk
#define	GPIO_BSRR_BS13_Pos   (13U)
#define	GPIO_BSRR_BS13_Msk   (0x1UL << GPIO_BSRR_BS13_Pos)
	0x00002000
#define	GPIO_BSRR_BS13   GPIO_BSRR_BS13_Msk
#define	GPIO_BSRR_BS14_Pos   (14U)
#define	GPIO_BSRR_BS14_Msk   (0x1UL << GPIO_BSRR_BS14_Pos)
	0x00004000
#define	GPIO_BSRR_BS14   GPIO_BSRR_BS14_Msk
#define	GPIO_BSRR_BS15_Pos   (15U)
#define	GPIO_BSRR_BS15_Msk   (0x1UL << GPIO_BSRR_BS15_Pos)
	0x00008000
#define	GPIO_BSRR_BS15   GPIO_BSRR_BS15_Msk
#define	GPIO_BSRR_BR0_Pos   (16U)
#define	GPIO_BSRR_BR0_Msk   (0x1UL << GPIO_BSRR_BR0_Pos)
	0x00010000
#define	GPIO_BSRR_BR0   GPIO_BSRR_BR0_Msk
#define	GPIO_BSRR_BR1_Pos   (17U)
#define	GPIO_BSRR_BR1_Msk   (0x1UL << GPIO_BSRR_BR1_Pos)
	0x00020000
#define	GPIO_BSRR_BR1   GPIO_BSRR_BR1_Msk
#define	GPIO_BSRR_BR2_Pos   (18U)
#define	GPIO_BSRR_BR2_Msk   (0x1UL << GPIO_BSRR_BR2_Pos)
	0x00040000
#define	GPIO_BSRR_BR2   GPIO_BSRR_BR2_Msk
#define	GPIO_BSRR_BR3_Pos   (19U)
#define	GPIO_BSRR_BR3_Msk   (0x1UL << GPIO_BSRR_BR3_Pos)
	0x00080000
#define	GPIO_BSRR_BR3   GPIO_BSRR_BR3_Msk
#define	GPIO_BSRR_BR4_Pos   (20U)
#define	GPIO_BSRR_BR4_Msk   (0x1UL << GPIO_BSRR_BR4_Pos)
	0x00100000
#define	GPIO_BSRR_BR4   GPIO_BSRR_BR4_Msk
#define	GPIO_BSRR_BR5_Pos   (21U)
#define	GPIO_BSRR_BR5_Msk   (0x1UL << GPIO_BSRR_BR5_Pos)
	0x00200000
#define	GPIO_BSRR_BR5   GPIO_BSRR_BR5_Msk
#define	GPIO_BSRR_BR6_Pos   (22U)
#define	GPIO_BSRR_BR6_Msk   (0x1UL << GPIO_BSRR_BR6_Pos)
	0x00400000
#define	GPIO_BSRR_BR6   GPIO_BSRR_BR6_Msk
#define	GPIO_BSRR_BR7_Pos   (23U)
#define	GPIO_BSRR_BR7_Msk   (0x1UL << GPIO_BSRR_BR7_Pos)
	0x00800000
#define	GPIO_BSRR_BR7   GPIO_BSRR_BR7_Msk
#define	GPIO_BSRR_BR8_Pos   (24U)
#define	GPIO_BSRR_BR8_Msk   (0x1UL << GPIO_BSRR_BR8_Pos)
	0x01000000
#define	GPIO_BSRR_BR8   GPIO_BSRR_BR8_Msk
#define	GPIO_BSRR_BR9_Pos   (25U)
#define	GPIO_BSRR_BR9_Msk   (0x1UL << GPIO_BSRR_BR9_Pos)
	0x02000000
#define	GPIO_BSRR_BR9   GPIO_BSRR_BR9_Msk
#define	GPIO_BSRR_BR10_Pos   (26U)
#define	GPIO_BSRR_BR10_Msk   (0x1UL << GPIO_BSRR_BR10_Pos)
	0x04000000
#define	GPIO_BSRR_BR10   GPIO_BSRR_BR10_Msk
#define	GPIO_BSRR_BR11_Pos   (27U)
#define	GPIO_BSRR_BR11_Msk   (0x1UL << GPIO_BSRR_BR11_Pos)
	0x08000000
#define	GPIO_BSRR_BR11   GPIO_BSRR_BR11_Msk
#define	GPIO_BSRR_BR12_Pos   (28U)
#define	GPIO_BSRR_BR12_Msk   (0x1UL << GPIO_BSRR_BR12_Pos)
	0x10000000
#define	GPIO_BSRR_BR12   GPIO_BSRR_BR12_Msk
#define	GPIO_BSRR_BR13_Pos   (29U)
#define	GPIO_BSRR_BR13_Msk   (0x1UL << GPIO_BSRR_BR13_Pos)
	0x20000000
#define	GPIO_BSRR_BR13   GPIO_BSRR_BR13_Msk
#define	GPIO_BSRR_BR14_Pos   (30U)
#define	GPIO_BSRR_BR14_Msk   (0x1UL << GPIO_BSRR_BR14_Pos)
	0x40000000
#define	GPIO_BSRR_BR14   GPIO_BSRR_BR14_Msk
#define	GPIO_BSRR_BR15_Pos   (31U)
#define	GPIO_BSRR_BR15_Msk   (0x1UL << GPIO_BSRR_BR15_Pos)
	0x80000000
#define	GPIO_BSRR_BR15   GPIO_BSRR_BR15_Msk
#define	GPIO_LCKR_LCK0_Pos   (0U)
#define	GPIO_LCKR_LCK0_Msk   (0x1UL << GPIO_LCKR_LCK0_Pos)
	0x00000001
#define	GPIO_LCKR_LCK0   GPIO_LCKR_LCK0_Msk
#define	GPIO_LCKR_LCK1_Pos   (1U)
#define	GPIO_LCKR_LCK1_Msk   (0x1UL << GPIO_LCKR_LCK1_Pos)
	0x00000002
#define	GPIO_LCKR_LCK1   GPIO_LCKR_LCK1_Msk
#define	GPIO_LCKR_LCK2_Pos   (2U)
#define	GPIO_LCKR_LCK2_Msk   (0x1UL << GPIO_LCKR_LCK2_Pos)
	0x00000004
#define	GPIO_LCKR_LCK2   GPIO_LCKR_LCK2_Msk
#define	GPIO_LCKR_LCK3_Pos   (3U)
#define	GPIO_LCKR_LCK3_Msk   (0x1UL << GPIO_LCKR_LCK3_Pos)
	0x00000008
#define	GPIO_LCKR_LCK3   GPIO_LCKR_LCK3_Msk
#define	GPIO_LCKR_LCK4_Pos   (4U)
#define	GPIO_LCKR_LCK4_Msk   (0x1UL << GPIO_LCKR_LCK4_Pos)
	0x00000010
#define	GPIO_LCKR_LCK4   GPIO_LCKR_LCK4_Msk
#define	GPIO_LCKR_LCK5_Pos   (5U)
#define	GPIO_LCKR_LCK5_Msk   (0x1UL << GPIO_LCKR_LCK5_Pos)
	0x00000020
#define	GPIO_LCKR_LCK5   GPIO_LCKR_LCK5_Msk
#define	GPIO_LCKR_LCK6_Pos   (6U)
#define	GPIO_LCKR_LCK6_Msk   (0x1UL << GPIO_LCKR_LCK6_Pos)
	0x00000040
#define	GPIO_LCKR_LCK6   GPIO_LCKR_LCK6_Msk
#define	GPIO_LCKR_LCK7_Pos   (7U)
#define	GPIO_LCKR_LCK7_Msk   (0x1UL << GPIO_LCKR_LCK7_Pos)
	0x00000080
#define	GPIO_LCKR_LCK7   GPIO_LCKR_LCK7_Msk
#define	GPIO_LCKR_LCK8_Pos   (8U)
#define	GPIO_LCKR_LCK8_Msk   (0x1UL << GPIO_LCKR_LCK8_Pos)
	0x00000100
#define	GPIO_LCKR_LCK8   GPIO_LCKR_LCK8_Msk
#define	GPIO_LCKR_LCK9_Pos   (9U)
#define	GPIO_LCKR_LCK9_Msk   (0x1UL << GPIO_LCKR_LCK9_Pos)
	0x00000200
#define	GPIO_LCKR_LCK9   GPIO_LCKR_LCK9_Msk
#define	GPIO_LCKR_LCK10_Pos   (10U)
#define	GPIO_LCKR_LCK10_Msk   (0x1UL << GPIO_LCKR_LCK10_Pos)
	0x00000400
#define	GPIO_LCKR_LCK10   GPIO_LCKR_LCK10_Msk
#define	GPIO_LCKR_LCK11_Pos   (11U)
#define	GPIO_LCKR_LCK11_Msk   (0x1UL << GPIO_LCKR_LCK11_Pos)
	0x00000800
#define	GPIO_LCKR_LCK11   GPIO_LCKR_LCK11_Msk
#define	GPIO_LCKR_LCK12_Pos   (12U)
#define	GPIO_LCKR_LCK12_Msk   (0x1UL << GPIO_LCKR_LCK12_Pos)
	0x00001000
#define	GPIO_LCKR_LCK12   GPIO_LCKR_LCK12_Msk
#define	GPIO_LCKR_LCK13_Pos   (13U)
#define	GPIO_LCKR_LCK13_Msk   (0x1UL << GPIO_LCKR_LCK13_Pos)
	0x00002000
#define	GPIO_LCKR_LCK13   GPIO_LCKR_LCK13_Msk
#define	GPIO_LCKR_LCK14_Pos   (14U)
#define	GPIO_LCKR_LCK14_Msk   (0x1UL << GPIO_LCKR_LCK14_Pos)
	0x00004000
#define	GPIO_LCKR_LCK14   GPIO_LCKR_LCK14_Msk
#define	GPIO_LCKR_LCK15_Pos   (15U)
#define	GPIO_LCKR_LCK15_Msk   (0x1UL << GPIO_LCKR_LCK15_Pos)
	0x00008000
#define	GPIO_LCKR_LCK15   GPIO_LCKR_LCK15_Msk
#define	GPIO_LCKR_LCKK_Pos   (16U)
#define	GPIO_LCKR_LCKK_Msk   (0x1UL << GPIO_LCKR_LCKK_Pos)
	0x00010000
#define	GPIO_LCKR_LCKK   GPIO_LCKR_LCKK_Msk
#define	GPIO_AFRL_AFSEL0_Pos   (0U)
#define	GPIO_AFRL_AFSEL0_Msk   (0xFUL << GPIO_AFRL_AFSEL0_Pos)
	0x0000000F
#define	GPIO_AFRL_AFSEL0   GPIO_AFRL_AFSEL0_Msk
#define	GPIO_AFRL_AFSEL0_0   (0x1UL << GPIO_AFRL_AFSEL0_Pos)
	0x00000001
#define	GPIO_AFRL_AFSEL0_1   (0x2UL << GPIO_AFRL_AFSEL0_Pos)
	0x00000002
#define	GPIO_AFRL_AFSEL0_2   (0x4UL << GPIO_AFRL_AFSEL0_Pos)
	0x00000004
#define	GPIO_AFRL_AFSEL0_3   (0x8UL << GPIO_AFRL_AFSEL0_Pos)
	0x00000008
#define	GPIO_AFRL_AFSEL1_Pos   (4U)
#define	GPIO_AFRL_AFSEL1_Msk   (0xFUL << GPIO_AFRL_AFSEL1_Pos)
	0x000000F0
#define	GPIO_AFRL_AFSEL1   GPIO_AFRL_AFSEL1_Msk
#define	GPIO_AFRL_AFSEL1_0   (0x1UL << GPIO_AFRL_AFSEL1_Pos)
	0x00000010
#define	GPIO_AFRL_AFSEL1_1   (0x2UL << GPIO_AFRL_AFSEL1_Pos)
	0x00000020
#define	GPIO_AFRL_AFSEL1_2   (0x4UL << GPIO_AFRL_AFSEL1_Pos)
	0x00000040
#define	GPIO_AFRL_AFSEL1_3   (0x8UL << GPIO_AFRL_AFSEL1_Pos)
	0x00000080
#define	GPIO_AFRL_AFSEL2_Pos   (8U)
#define	GPIO_AFRL_AFSEL2_Msk   (0xFUL << GPIO_AFRL_AFSEL2_Pos)
	0x00000F00
#define	GPIO_AFRL_AFSEL2   GPIO_AFRL_AFSEL2_Msk
#define	GPIO_AFRL_AFSEL2_0   (0x1UL << GPIO_AFRL_AFSEL2_Pos)
	0x00000100
#define	GPIO_AFRL_AFSEL2_1   (0x2UL << GPIO_AFRL_AFSEL2_Pos)
	0x00000200
#define	GPIO_AFRL_AFSEL2_2   (0x4UL << GPIO_AFRL_AFSEL2_Pos)
	0x00000400
#define	GPIO_AFRL_AFSEL2_3   (0x8UL << GPIO_AFRL_AFSEL2_Pos)
	0x00000800
#define	GPIO_AFRL_AFSEL3_Pos   (12U)
#define	GPIO_AFRL_AFSEL3_Msk   (0xFUL << GPIO_AFRL_AFSEL3_Pos)
	0x0000F000
#define	GPIO_AFRL_AFSEL3   GPIO_AFRL_AFSEL3_Msk
#define	GPIO_AFRL_AFSEL3_0   (0x1UL << GPIO_AFRL_AFSEL3_Pos)
	0x00001000
#define	GPIO_AFRL_AFSEL3_1   (0x2UL << GPIO_AFRL_AFSEL3_Pos)
	0x00002000
#define	GPIO_AFRL_AFSEL3_2   (0x4UL << GPIO_AFRL_AFSEL3_Pos)
	0x00004000
#define	GPIO_AFRL_AFSEL3_3   (0x8UL << GPIO_AFRL_AFSEL3_Pos)
	0x00008000
#define	GPIO_AFRL_AFSEL4_Pos   (16U)
#define	GPIO_AFRL_AFSEL4_Msk   (0xFUL << GPIO_AFRL_AFSEL4_Pos)
	0x000F0000
#define	GPIO_AFRL_AFSEL4   GPIO_AFRL_AFSEL4_Msk
#define	GPIO_AFRL_AFSEL4_0   (0x1UL << GPIO_AFRL_AFSEL4_Pos)
	0x00010000
#define	GPIO_AFRL_AFSEL4_1   (0x2UL << GPIO_AFRL_AFSEL4_Pos)
	0x00020000
#define	GPIO_AFRL_AFSEL4_2   (0x4UL << GPIO_AFRL_AFSEL4_Pos)
	0x00040000
#define	GPIO_AFRL_AFSEL4_3   (0x8UL << GPIO_AFRL_AFSEL4_Pos)
	0x00080000
#define	GPIO_AFRL_AFSEL5_Pos   (20U)
#define	GPIO_AFRL_AFSEL5_Msk   (0xFUL << GPIO_AFRL_AFSEL5_Pos)
	0x00F00000
#define	GPIO_AFRL_AFSEL5   GPIO_AFRL_AFSEL5_Msk
#define	GPIO_AFRL_AFSEL5_0   (0x1UL << GPIO_AFRL_AFSEL5_Pos)
	0x00100000
#define	GPIO_AFRL_AFSEL5_1   (0x2UL << GPIO_AFRL_AFSEL5_Pos)
	0x00200000
#define	GPIO_AFRL_AFSEL5_2   (0x4UL << GPIO_AFRL_AFSEL5_Pos)
	0x00400000
#define	GPIO_AFRL_AFSEL5_3   (0x8UL << GPIO_AFRL_AFSEL5_Pos)
	0x00800000
#define	GPIO_AFRL_AFSEL6_Pos   (24U)
#define	GPIO_AFRL_AFSEL6_Msk   (0xFUL << GPIO_AFRL_AFSEL6_Pos)
	0x0F000000
#define	GPIO_AFRL_AFSEL6   GPIO_AFRL_AFSEL6_Msk
#define	GPIO_AFRL_AFSEL6_0   (0x1UL << GPIO_AFRL_AFSEL6_Pos)
	0x01000000
#define	GPIO_AFRL_AFSEL6_1   (0x2UL << GPIO_AFRL_AFSEL6_Pos)
	0x02000000
#define	GPIO_AFRL_AFSEL6_2   (0x4UL << GPIO_AFRL_AFSEL6_Pos)
	0x04000000
#define	GPIO_AFRL_AFSEL6_3   (0x8UL << GPIO_AFRL_AFSEL6_Pos)
	0x08000000
#define	GPIO_AFRL_AFSEL7_Pos   (28U)
#define	GPIO_AFRL_AFSEL7_Msk   (0xFUL << GPIO_AFRL_AFSEL7_Pos)
	0xF0000000
#define	GPIO_AFRL_AFSEL7   GPIO_AFRL_AFSEL7_Msk
#define	GPIO_AFRL_AFSEL7_0   (0x1UL << GPIO_AFRL_AFSEL7_Pos)
	0x10000000
#define	GPIO_AFRL_AFSEL7_1   (0x2UL << GPIO_AFRL_AFSEL7_Pos)
	0x20000000
#define	GPIO_AFRL_AFSEL7_2   (0x4UL << GPIO_AFRL_AFSEL7_Pos)
	0x40000000
#define	GPIO_AFRL_AFSEL7_3   (0x8UL << GPIO_AFRL_AFSEL7_Pos)
	0x80000000
#define	GPIO_AFRL_AFRL0   GPIO_AFRL_AFSEL0
#define	GPIO_AFRL_AFRL1   GPIO_AFRL_AFSEL1
#define	GPIO_AFRL_AFRL2   GPIO_AFRL_AFSEL2
#define	GPIO_AFRL_AFRL3   GPIO_AFRL_AFSEL3
#define	GPIO_AFRL_AFRL4   GPIO_AFRL_AFSEL4
#define	GPIO_AFRL_AFRL5   GPIO_AFRL_AFSEL5
#define	GPIO_AFRL_AFRL6   GPIO_AFRL_AFSEL6
#define	GPIO_AFRL_AFRL7   GPIO_AFRL_AFSEL7
#define	GPIO_AFRH_AFSEL8_Pos   (0U)
#define	GPIO_AFRH_AFSEL8_Msk   (0xFUL << GPIO_AFRH_AFSEL8_Pos)
	0x0000000F
#define	GPIO_AFRH_AFSEL8   GPIO_AFRH_AFSEL8_Msk
#define	GPIO_AFRH_AFSEL8_0   (0x1UL << GPIO_AFRH_AFSEL8_Pos)
	0x00000001
#define	GPIO_AFRH_AFSEL8_1   (0x2UL << GPIO_AFRH_AFSEL8_Pos)
	0x00000002
#define	GPIO_AFRH_AFSEL8_2   (0x4UL << GPIO_AFRH_AFSEL8_Pos)
	0x00000004
#define	GPIO_AFRH_AFSEL8_3   (0x8UL << GPIO_AFRH_AFSEL8_Pos)
	0x00000008
#define	GPIO_AFRH_AFSEL9_Pos   (4U)
#define	GPIO_AFRH_AFSEL9_Msk   (0xFUL << GPIO_AFRH_AFSEL9_Pos)
	0x000000F0
#define	GPIO_AFRH_AFSEL9   GPIO_AFRH_AFSEL9_Msk
#define	GPIO_AFRH_AFSEL9_0   (0x1UL << GPIO_AFRH_AFSEL9_Pos)
	0x00000010
#define	GPIO_AFRH_AFSEL9_1   (0x2UL << GPIO_AFRH_AFSEL9_Pos)
	0x00000020
#define	GPIO_AFRH_AFSEL9_2   (0x4UL << GPIO_AFRH_AFSEL9_Pos)
	0x00000040
#define	GPIO_AFRH_AFSEL9_3   (0x8UL << GPIO_AFRH_AFSEL9_Pos)
	0x00000080
#define	GPIO_AFRH_AFSEL10_Pos   (8U)
#define	GPIO_AFRH_AFSEL10_Msk   (0xFUL << GPIO_AFRH_AFSEL10_Pos)
	0x00000F00
#define	GPIO_AFRH_AFSEL10   GPIO_AFRH_AFSEL10_Msk
#define	GPIO_AFRH_AFSEL10_0   (0x1UL << GPIO_AFRH_AFSEL10_Pos)
	0x00000100
#define	GPIO_AFRH_AFSEL10_1   (0x2UL << GPIO_AFRH_AFSEL10_Pos)
	0x00000200
#define	GPIO_AFRH_AFSEL10_2   (0x4UL << GPIO_AFRH_AFSEL10_Pos)
	0x00000400
#define	GPIO_AFRH_AFSEL10_3   (0x8UL << GPIO_AFRH_AFSEL10_Pos)
	0x00000800
#define	GPIO_AFRH_AFSEL11_Pos   (12U)
#define	GPIO_AFRH_AFSEL11_Msk   (0xFUL << GPIO_AFRH_AFSEL11_Pos)
	0x0000F000
#define	GPIO_AFRH_AFSEL11   GPIO_AFRH_AFSEL11_Msk
#define	GPIO_AFRH_AFSEL11_0   (0x1UL << GPIO_AFRH_AFSEL11_Pos)
	0x00001000
#define	GPIO_AFRH_AFSEL11_1   (0x2UL << GPIO_AFRH_AFSEL11_Pos)
	0x00002000
#define	GPIO_AFRH_AFSEL11_2   (0x4UL << GPIO_AFRH_AFSEL11_Pos)
	0x00004000
#define	GPIO_AFRH_AFSEL11_3   (0x8UL << GPIO_AFRH_AFSEL11_Pos)
	0x00008000
#define	GPIO_AFRH_AFSEL12_Pos   (16U)
#define	GPIO_AFRH_AFSEL12_Msk   (0xFUL << GPIO_AFRH_AFSEL12_Pos)
	0x000F0000
#define	GPIO_AFRH_AFSEL12   GPIO_AFRH_AFSEL12_Msk
#define	GPIO_AFRH_AFSEL12_0   (0x1UL << GPIO_AFRH_AFSEL12_Pos)
	0x00010000
#define	GPIO_AFRH_AFSEL12_1   (0x2UL << GPIO_AFRH_AFSEL12_Pos)
	0x00020000
#define	GPIO_AFRH_AFSEL12_2   (0x4UL << GPIO_AFRH_AFSEL12_Pos)
	0x00040000
#define	GPIO_AFRH_AFSEL12_3   (0x8UL << GPIO_AFRH_AFSEL12_Pos)
	0x00080000
#define	GPIO_AFRH_AFSEL13_Pos   (20U)
#define	GPIO_AFRH_AFSEL13_Msk   (0xFUL << GPIO_AFRH_AFSEL13_Pos)
	0x00F00000
#define	GPIO_AFRH_AFSEL13   GPIO_AFRH_AFSEL13_Msk
#define	GPIO_AFRH_AFSEL13_0   (0x1UL << GPIO_AFRH_AFSEL13_Pos)
	0x00100000
#define	GPIO_AFRH_AFSEL13_1   (0x2UL << GPIO_AFRH_AFSEL13_Pos)
	0x00200000
#define	GPIO_AFRH_AFSEL13_2   (0x4UL << GPIO_AFRH_AFSEL13_Pos)
	0x00400000
#define	GPIO_AFRH_AFSEL13_3   (0x8UL << GPIO_AFRH_AFSEL13_Pos)
	0x00800000
#define	GPIO_AFRH_AFSEL14_Pos   (24U)
#define	GPIO_AFRH_AFSEL14_Msk   (0xFUL << GPIO_AFRH_AFSEL14_Pos)
	0x0F000000
#define	GPIO_AFRH_AFSEL14   GPIO_AFRH_AFSEL14_Msk
#define	GPIO_AFRH_AFSEL14_0   (0x1UL << GPIO_AFRH_AFSEL14_Pos)
	0x01000000
#define	GPIO_AFRH_AFSEL14_1   (0x2UL << GPIO_AFRH_AFSEL14_Pos)
	0x02000000
#define	GPIO_AFRH_AFSEL14_2   (0x4UL << GPIO_AFRH_AFSEL14_Pos)
	0x04000000
#define	GPIO_AFRH_AFSEL14_3   (0x8UL << GPIO_AFRH_AFSEL14_Pos)
	0x08000000
#define	GPIO_AFRH_AFSEL15_Pos   (28U)
#define	GPIO_AFRH_AFSEL15_Msk   (0xFUL << GPIO_AFRH_AFSEL15_Pos)
	0xF0000000
#define	GPIO_AFRH_AFSEL15   GPIO_AFRH_AFSEL15_Msk
#define	GPIO_AFRH_AFSEL15_0   (0x1UL << GPIO_AFRH_AFSEL15_Pos)
	0x10000000
#define	GPIO_AFRH_AFSEL15_1   (0x2UL << GPIO_AFRH_AFSEL15_Pos)
	0x20000000
#define	GPIO_AFRH_AFSEL15_2   (0x4UL << GPIO_AFRH_AFSEL15_Pos)
	0x40000000
#define	GPIO_AFRH_AFSEL15_3   (0x8UL << GPIO_AFRH_AFSEL15_Pos)
	0x80000000
#define	GPIO_AFRH_AFRH0   GPIO_AFRH_AFSEL8
#define	GPIO_AFRH_AFRH1   GPIO_AFRH_AFSEL9
#define	GPIO_AFRH_AFRH2   GPIO_AFRH_AFSEL10
#define	GPIO_AFRH_AFRH3   GPIO_AFRH_AFSEL11
#define	GPIO_AFRH_AFRH4   GPIO_AFRH_AFSEL12
#define	GPIO_AFRH_AFRH5   GPIO_AFRH_AFSEL13
#define	GPIO_AFRH_AFRH6   GPIO_AFRH_AFSEL14
#define	GPIO_AFRH_AFRH7   GPIO_AFRH_AFSEL15
#define	HSEM_R_PROCID_Pos   (0U)
#define	HSEM_R_PROCID_Msk   (0xFFUL << HSEM_R_PROCID_Pos)
	0x000000FF
#define	HSEM_R_PROCID   HSEM_R_PROCID_Msk
	Semaphore ProcessID.
#define	HSEM_R_COREID_Pos   (8U)
#define	HSEM_R_COREID_Msk   (0xFFUL << HSEM_R_COREID_Pos)
	0x0000FF00
#define	HSEM_R_COREID   HSEM_R_COREID_Msk
	Semaphore CoreID.
#define	HSEM_R_LOCK_Pos   (31U)
#define	HSEM_R_LOCK_Msk   (0x1UL << HSEM_R_LOCK_Pos)
	0x80000000
#define	HSEM_R_LOCK   HSEM_R_LOCK_Msk
	Lock indication.
#define	HSEM_RLR_PROCID_Pos   (0U)
#define	HSEM_RLR_PROCID_Msk   (0xFFUL << HSEM_RLR_PROCID_Pos)
	0x000000FF
#define	HSEM_RLR_PROCID   HSEM_RLR_PROCID_Msk
	Semaphore ProcessID.
#define	HSEM_RLR_COREID_Pos   (8U)
#define	HSEM_RLR_COREID_Msk   (0xFFUL << HSEM_RLR_COREID_Pos)
	0x0000FF00
#define	HSEM_RLR_COREID   HSEM_RLR_COREID_Msk
	Semaphore CoreID.
#define	HSEM_RLR_LOCK_Pos   (31U)
#define	HSEM_RLR_LOCK_Msk   (0x1UL << HSEM_RLR_LOCK_Pos)
	0x80000000
#define	HSEM_RLR_LOCK   HSEM_RLR_LOCK_Msk
	Lock indication.
#define	HSEM_C1IER_ISE0_Pos   (0U)
#define	HSEM_C1IER_ISE0_Msk   (0x1UL << HSEM_C1IER_ISE0_Pos)
	0x00000001
#define	HSEM_C1IER_ISE0   HSEM_C1IER_ISE0_Msk
	semaphore 0 , interrupt 0 enable bit.
#define	HSEM_C1IER_ISE1_Pos   (1U)
#define	HSEM_C1IER_ISE1_Msk   (0x1UL << HSEM_C1IER_ISE1_Pos)
	0x00000002
#define	HSEM_C1IER_ISE1   HSEM_C1IER_ISE1_Msk
	semaphore 1 , interrupt 0 enable bit.
#define	HSEM_C1IER_ISE2_Pos   (2U)
#define	HSEM_C1IER_ISE2_Msk   (0x1UL << HSEM_C1IER_ISE2_Pos)
	0x00000004
#define	HSEM_C1IER_ISE2   HSEM_C1IER_ISE2_Msk
	semaphore 2 , interrupt 0 enable bit.
#define	HSEM_C1IER_ISE3_Pos   (3U)
#define	HSEM_C1IER_ISE3_Msk   (0x1UL << HSEM_C1IER_ISE3_Pos)
	0x00000008
#define	HSEM_C1IER_ISE3   HSEM_C1IER_ISE3_Msk
	semaphore 3 , interrupt 0 enable bit.
#define	HSEM_C1IER_ISE4_Pos   (4U)
#define	HSEM_C1IER_ISE4_Msk   (0x1UL << HSEM_C1IER_ISE4_Pos)
	0x00000010
#define	HSEM_C1IER_ISE4   HSEM_C1IER_ISE4_Msk
	semaphore 4 , interrupt 0 enable bit.
#define	HSEM_C1IER_ISE5_Pos   (5U)
#define	HSEM_C1IER_ISE5_Msk   (0x1UL << HSEM_C1IER_ISE5_Pos)
	0x00000020
#define	HSEM_C1IER_ISE5   HSEM_C1IER_ISE5_Msk
	semaphore 5 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE6_Pos   (6U)
#define	HSEM_C1IER_ISE6_Msk   (0x1UL << HSEM_C1IER_ISE6_Pos)
	0x00000040
#define	HSEM_C1IER_ISE6   HSEM_C1IER_ISE6_Msk
	semaphore 6 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE7_Pos   (7U)
#define	HSEM_C1IER_ISE7_Msk   (0x1UL << HSEM_C1IER_ISE7_Pos)
	0x00000080
#define	HSEM_C1IER_ISE7   HSEM_C1IER_ISE7_Msk
	semaphore 7 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE8_Pos   (8U)
#define	HSEM_C1IER_ISE8_Msk   (0x1UL << HSEM_C1IER_ISE8_Pos)
	0x00000100
#define	HSEM_C1IER_ISE8   HSEM_C1IER_ISE8_Msk
	semaphore 8 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE9_Pos   (9U)
#define	HSEM_C1IER_ISE9_Msk   (0x1UL << HSEM_C1IER_ISE9_Pos)
	0x00000200
#define	HSEM_C1IER_ISE9   HSEM_C1IER_ISE9_Msk
	semaphore 9 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE10_Pos   (10U)
#define	HSEM_C1IER_ISE10_Msk   (0x1UL << HSEM_C1IER_ISE10_Pos)
	0x00000400
#define	HSEM_C1IER_ISE10   HSEM_C1IER_ISE10_Msk
	semaphore 10 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE11_Pos   (11U)
#define	HSEM_C1IER_ISE11_Msk   (0x1UL << HSEM_C1IER_ISE11_Pos)
	0x00000800
#define	HSEM_C1IER_ISE11   HSEM_C1IER_ISE11_Msk
	semaphore 11 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE12_Pos   (12U)
#define	HSEM_C1IER_ISE12_Msk   (0x1UL << HSEM_C1IER_ISE12_Pos)
	0x00001000
#define	HSEM_C1IER_ISE12   HSEM_C1IER_ISE12_Msk
	semaphore 12 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE13_Pos   (13U)
#define	HSEM_C1IER_ISE13_Msk   (0x1UL << HSEM_C1IER_ISE13_Pos)
	0x00002000
#define	HSEM_C1IER_ISE13   HSEM_C1IER_ISE13_Msk
	semaphore 13 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE14_Pos   (14U)
#define	HSEM_C1IER_ISE14_Msk   (0x1UL << HSEM_C1IER_ISE14_Pos)
	0x00004000
#define	HSEM_C1IER_ISE14   HSEM_C1IER_ISE14_Msk
	semaphore 14 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE15_Pos   (15U)
#define	HSEM_C1IER_ISE15_Msk   (0x1UL << HSEM_C1IER_ISE15_Pos)
	0x00008000
#define	HSEM_C1IER_ISE15   HSEM_C1IER_ISE15_Msk
	semaphore 15 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE16_Pos   (16U)
#define	HSEM_C1IER_ISE16_Msk   (0x1UL << HSEM_C1IER_ISE16_Pos)
	0x00010000
#define	HSEM_C1IER_ISE16   HSEM_C1IER_ISE16_Msk
	semaphore 16 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE17_Pos   (17U)
#define	HSEM_C1IER_ISE17_Msk   (0x1UL << HSEM_C1IER_ISE17_Pos)
	0x00020000
#define	HSEM_C1IER_ISE17   HSEM_C1IER_ISE17_Msk
	semaphore 17 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE18_Pos   (18U)
#define	HSEM_C1IER_ISE18_Msk   (0x1UL << HSEM_C1IER_ISE18_Pos)
	0x00040000
#define	HSEM_C1IER_ISE18   HSEM_C1IER_ISE18_Msk
	semaphore 18 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE19_Pos   (19U)
#define	HSEM_C1IER_ISE19_Msk   (0x1UL << HSEM_C1IER_ISE19_Pos)
	0x00080000
#define	HSEM_C1IER_ISE19   HSEM_C1IER_ISE19_Msk
	semaphore 19 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE20_Pos   (20U)
#define	HSEM_C1IER_ISE20_Msk   (0x1UL << HSEM_C1IER_ISE20_Pos)
	0x00100000
#define	HSEM_C1IER_ISE20   HSEM_C1IER_ISE20_Msk
	semaphore 20 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE21_Pos   (21U)
#define	HSEM_C1IER_ISE21_Msk   (0x1UL << HSEM_C1IER_ISE21_Pos)
	0x00200000
#define	HSEM_C1IER_ISE21   HSEM_C1IER_ISE21_Msk
	semaphore 21 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE22_Pos   (22U)
#define	HSEM_C1IER_ISE22_Msk   (0x1UL << HSEM_C1IER_ISE22_Pos)
	0x00400000
#define	HSEM_C1IER_ISE22   HSEM_C1IER_ISE22_Msk
	semaphore 22 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE23_Pos   (23U)
#define	HSEM_C1IER_ISE23_Msk   (0x1UL << HSEM_C1IER_ISE23_Pos)
	0x00800000
#define	HSEM_C1IER_ISE23   HSEM_C1IER_ISE23_Msk
	semaphore 23 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE24_Pos   (24U)
#define	HSEM_C1IER_ISE24_Msk   (0x1UL << HSEM_C1IER_ISE24_Pos)
	0x01000000
#define	HSEM_C1IER_ISE24   HSEM_C1IER_ISE24_Msk
	semaphore 24 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE25_Pos   (25U)
#define	HSEM_C1IER_ISE25_Msk   (0x1UL << HSEM_C1IER_ISE25_Pos)
	0x02000000
#define	HSEM_C1IER_ISE25   HSEM_C1IER_ISE25_Msk
	semaphore 25 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE26_Pos   (26U)
#define	HSEM_C1IER_ISE26_Msk   (0x1UL << HSEM_C1IER_ISE26_Pos)
	0x04000000
#define	HSEM_C1IER_ISE26   HSEM_C1IER_ISE26_Msk
	semaphore 26 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE27_Pos   (27U)
#define	HSEM_C1IER_ISE27_Msk   (0x1UL << HSEM_C1IER_ISE27_Pos)
	0x08000000
#define	HSEM_C1IER_ISE27   HSEM_C1IER_ISE27_Msk
	semaphore 27 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE28_Pos   (28U)
#define	HSEM_C1IER_ISE28_Msk   (0x1UL << HSEM_C1IER_ISE28_Pos)
	0x10000000
#define	HSEM_C1IER_ISE28   HSEM_C1IER_ISE28_Msk
	semaphore 28 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE29_Pos   (29U)
#define	HSEM_C1IER_ISE29_Msk   (0x1UL << HSEM_C1IER_ISE29_Pos)
	0x20000000
#define	HSEM_C1IER_ISE29   HSEM_C1IER_ISE29_Msk
	semaphore 29 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE30_Pos   (30U)
#define	HSEM_C1IER_ISE30_Msk   (0x1UL << HSEM_C1IER_ISE30_Pos)
	0x40000000
#define	HSEM_C1IER_ISE30   HSEM_C1IER_ISE30_Msk
	semaphore 30 interrupt 0 enable bit.
#define	HSEM_C1IER_ISE31_Pos   (31U)
#define	HSEM_C1IER_ISE31_Msk   (0x1UL << HSEM_C1IER_ISE31_Pos)
	0x80000000
#define	HSEM_C1IER_ISE31   HSEM_C1IER_ISE31_Msk
	semaphore 31 interrupt 0 enable bit.
#define	HSEM_C1ICR_ISC0_Pos   (0U)
#define	HSEM_C1ICR_ISC0_Msk   (0x1UL << HSEM_C1ICR_ISC0_Pos)
	0x00000001
#define	HSEM_C1ICR_ISC0   HSEM_C1ICR_ISC0_Msk
	semaphore 0 , interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC1_Pos   (1U)
#define	HSEM_C1ICR_ISC1_Msk   (0x1UL << HSEM_C1ICR_ISC1_Pos)
	0x00000002
#define	HSEM_C1ICR_ISC1   HSEM_C1ICR_ISC1_Msk
	semaphore 1 , interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC2_Pos   (2U)
#define	HSEM_C1ICR_ISC2_Msk   (0x1UL << HSEM_C1ICR_ISC2_Pos)
	0x00000004
#define	HSEM_C1ICR_ISC2   HSEM_C1ICR_ISC2_Msk
	semaphore 2 , interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC3_Pos   (3U)
#define	HSEM_C1ICR_ISC3_Msk   (0x1UL << HSEM_C1ICR_ISC3_Pos)
	0x00000008
#define	HSEM_C1ICR_ISC3   HSEM_C1ICR_ISC3_Msk
	semaphore 3 , interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC4_Pos   (4U)
#define	HSEM_C1ICR_ISC4_Msk   (0x1UL << HSEM_C1ICR_ISC4_Pos)
	0x00000010
#define	HSEM_C1ICR_ISC4   HSEM_C1ICR_ISC4_Msk
	semaphore 4 , interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC5_Pos   (5U)
#define	HSEM_C1ICR_ISC5_Msk   (0x1UL << HSEM_C1ICR_ISC5_Pos)
	0x00000020
#define	HSEM_C1ICR_ISC5   HSEM_C1ICR_ISC5_Msk
	semaphore 5 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC6_Pos   (6U)
#define	HSEM_C1ICR_ISC6_Msk   (0x1UL << HSEM_C1ICR_ISC6_Pos)
	0x00000040
#define	HSEM_C1ICR_ISC6   HSEM_C1ICR_ISC6_Msk
	semaphore 6 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC7_Pos   (7U)
#define	HSEM_C1ICR_ISC7_Msk   (0x1UL << HSEM_C1ICR_ISC7_Pos)
	0x00000080
#define	HSEM_C1ICR_ISC7   HSEM_C1ICR_ISC7_Msk
	semaphore 7 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC8_Pos   (8U)
#define	HSEM_C1ICR_ISC8_Msk   (0x1UL << HSEM_C1ICR_ISC8_Pos)
	0x00000100
#define	HSEM_C1ICR_ISC8   HSEM_C1ICR_ISC8_Msk
	semaphore 8 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC9_Pos   (9U)
#define	HSEM_C1ICR_ISC9_Msk   (0x1UL << HSEM_C1ICR_ISC9_Pos)
	0x00000200
#define	HSEM_C1ICR_ISC9   HSEM_C1ICR_ISC9_Msk
	semaphore 9 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC10_Pos   (10U)
#define	HSEM_C1ICR_ISC10_Msk   (0x1UL << HSEM_C1ICR_ISC10_Pos)
	0x00000400
#define	HSEM_C1ICR_ISC10   HSEM_C1ICR_ISC10_Msk
	semaphore 10 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC11_Pos   (11U)
#define	HSEM_C1ICR_ISC11_Msk   (0x1UL << HSEM_C1ICR_ISC11_Pos)
	0x00000800
#define	HSEM_C1ICR_ISC11   HSEM_C1ICR_ISC11_Msk
	semaphore 11 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC12_Pos   (12U)
#define	HSEM_C1ICR_ISC12_Msk   (0x1UL << HSEM_C1ICR_ISC12_Pos)
	0x00001000
#define	HSEM_C1ICR_ISC12   HSEM_C1ICR_ISC12_Msk
	semaphore 12 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC13_Pos   (13U)
#define	HSEM_C1ICR_ISC13_Msk   (0x1UL << HSEM_C1ICR_ISC13_Pos)
	0x00002000
#define	HSEM_C1ICR_ISC13   HSEM_C1ICR_ISC13_Msk
	semaphore 13 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC14_Pos   (14U)
#define	HSEM_C1ICR_ISC14_Msk   (0x1UL << HSEM_C1ICR_ISC14_Pos)
	0x00004000
#define	HSEM_C1ICR_ISC14   HSEM_C1ICR_ISC14_Msk
	semaphore 14 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC15_Pos   (15U)
#define	HSEM_C1ICR_ISC15_Msk   (0x1UL << HSEM_C1ICR_ISC15_Pos)
	0x00008000
#define	HSEM_C1ICR_ISC15   HSEM_C1ICR_ISC15_Msk
	semaphore 15 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC16_Pos   (16U)
#define	HSEM_C1ICR_ISC16_Msk   (0x1UL << HSEM_C1ICR_ISC16_Pos)
	0x00010000
#define	HSEM_C1ICR_ISC16   HSEM_C1ICR_ISC16_Msk
	semaphore 16 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC17_Pos   (17U)
#define	HSEM_C1ICR_ISC17_Msk   (0x1UL << HSEM_C1ICR_ISC17_Pos)
	0x00020000
#define	HSEM_C1ICR_ISC17   HSEM_C1ICR_ISC17_Msk
	semaphore 17 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC18_Pos   (18U)
#define	HSEM_C1ICR_ISC18_Msk   (0x1UL << HSEM_C1ICR_ISC18_Pos)
	0x00040000
#define	HSEM_C1ICR_ISC18   HSEM_C1ICR_ISC18_Msk
	semaphore 18 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC19_Pos   (19U)
#define	HSEM_C1ICR_ISC19_Msk   (0x1UL << HSEM_C1ICR_ISC19_Pos)
	0x00080000
#define	HSEM_C1ICR_ISC19   HSEM_C1ICR_ISC19_Msk
	semaphore 19 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC20_Pos   (20U)
#define	HSEM_C1ICR_ISC20_Msk   (0x1UL << HSEM_C1ICR_ISC20_Pos)
	0x00100000
#define	HSEM_C1ICR_ISC20   HSEM_C1ICR_ISC20_Msk
	semaphore 20 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC21_Pos   (21U)
#define	HSEM_C1ICR_ISC21_Msk   (0x1UL << HSEM_C1ICR_ISC21_Pos)
	0x00200000
#define	HSEM_C1ICR_ISC21   HSEM_C1ICR_ISC21_Msk
	semaphore 21 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC22_Pos   (22U)
#define	HSEM_C1ICR_ISC22_Msk   (0x1UL << HSEM_C1ICR_ISC22_Pos)
	0x00400000
#define	HSEM_C1ICR_ISC22   HSEM_C1ICR_ISC22_Msk
	semaphore 22 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC23_Pos   (23U)
#define	HSEM_C1ICR_ISC23_Msk   (0x1UL << HSEM_C1ICR_ISC23_Pos)
	0x00800000
#define	HSEM_C1ICR_ISC23   HSEM_C1ICR_ISC23_Msk
	semaphore 23 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC24_Pos   (24U)
#define	HSEM_C1ICR_ISC24_Msk   (0x1UL << HSEM_C1ICR_ISC24_Pos)
	0x01000000
#define	HSEM_C1ICR_ISC24   HSEM_C1ICR_ISC24_Msk
	semaphore 24 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC25_Pos   (25U)
#define	HSEM_C1ICR_ISC25_Msk   (0x1UL << HSEM_C1ICR_ISC25_Pos)
	0x02000000
#define	HSEM_C1ICR_ISC25   HSEM_C1ICR_ISC25_Msk
	semaphore 25 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC26_Pos   (26U)
#define	HSEM_C1ICR_ISC26_Msk   (0x1UL << HSEM_C1ICR_ISC26_Pos)
	0x04000000
#define	HSEM_C1ICR_ISC26   HSEM_C1ICR_ISC26_Msk
	semaphore 26 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC27_Pos   (27U)
#define	HSEM_C1ICR_ISC27_Msk   (0x1UL << HSEM_C1ICR_ISC27_Pos)
	0x08000000
#define	HSEM_C1ICR_ISC27   HSEM_C1ICR_ISC27_Msk
	semaphore 27 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC28_Pos   (28U)
#define	HSEM_C1ICR_ISC28_Msk   (0x1UL << HSEM_C1ICR_ISC28_Pos)
	0x10000000
#define	HSEM_C1ICR_ISC28   HSEM_C1ICR_ISC28_Msk
	semaphore 28 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC29_Pos   (29U)
#define	HSEM_C1ICR_ISC29_Msk   (0x1UL << HSEM_C1ICR_ISC29_Pos)
	0x20000000
#define	HSEM_C1ICR_ISC29   HSEM_C1ICR_ISC29_Msk
	semaphore 29 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC30_Pos   (30U)
#define	HSEM_C1ICR_ISC30_Msk   (0x1UL << HSEM_C1ICR_ISC30_Pos)
	0x40000000
#define	HSEM_C1ICR_ISC30   HSEM_C1ICR_ISC30_Msk
	semaphore 30 interrupt 0 clear bit.
#define	HSEM_C1ICR_ISC31_Pos   (31U)
#define	HSEM_C1ICR_ISC31_Msk   (0x1UL << HSEM_C1ICR_ISC31_Pos)
	0x80000000
#define	HSEM_C1ICR_ISC31   HSEM_C1ICR_ISC31_Msk
	semaphore 31 interrupt 0 clear bit.
#define	HSEM_C1ISR_ISF0_Pos   (0U)
#define	HSEM_C1ISR_ISF0_Msk   (0x1UL << HSEM_C1ISR_ISF0_Pos)
	0x00000001
#define	HSEM_C1ISR_ISF0   HSEM_C1ISR_ISF0_Msk
	semaphore 0 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF1_Pos   (1U)
#define	HSEM_C1ISR_ISF1_Msk   (0x1UL << HSEM_C1ISR_ISF1_Pos)
	0x00000002
#define	HSEM_C1ISR_ISF1   HSEM_C1ISR_ISF1_Msk
	semaphore 1 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF2_Pos   (2U)
#define	HSEM_C1ISR_ISF2_Msk   (0x1UL << HSEM_C1ISR_ISF2_Pos)
	0x00000004
#define	HSEM_C1ISR_ISF2   HSEM_C1ISR_ISF2_Msk
	semaphore 2 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF3_Pos   (3U)
#define	HSEM_C1ISR_ISF3_Msk   (0x1UL << HSEM_C1ISR_ISF3_Pos)
	0x00000008
#define	HSEM_C1ISR_ISF3   HSEM_C1ISR_ISF3_Msk
	semaphore 3 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF4_Pos   (4U)
#define	HSEM_C1ISR_ISF4_Msk   (0x1UL << HSEM_C1ISR_ISF4_Pos)
	0x00000010
#define	HSEM_C1ISR_ISF4   HSEM_C1ISR_ISF4_Msk
	semaphore 4 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF5_Pos   (5U)
#define	HSEM_C1ISR_ISF5_Msk   (0x1UL << HSEM_C1ISR_ISF5_Pos)
	0x00000020
#define	HSEM_C1ISR_ISF5   HSEM_C1ISR_ISF5_Msk
	semaphore 5 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF6_Pos   (6U)
#define	HSEM_C1ISR_ISF6_Msk   (0x1UL << HSEM_C1ISR_ISF6_Pos)
	0x00000040
#define	HSEM_C1ISR_ISF6   HSEM_C1ISR_ISF6_Msk
	semaphore 6 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF7_Pos   (7U)
#define	HSEM_C1ISR_ISF7_Msk   (0x1UL << HSEM_C1ISR_ISF7_Pos)
	0x00000080
#define	HSEM_C1ISR_ISF7   HSEM_C1ISR_ISF7_Msk
	semaphore 7 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF8_Pos   (8U)
#define	HSEM_C1ISR_ISF8_Msk   (0x1UL << HSEM_C1ISR_ISF8_Pos)
	0x00000100
#define	HSEM_C1ISR_ISF8   HSEM_C1ISR_ISF8_Msk
	semaphore 8 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF9_Pos   (9U)
#define	HSEM_C1ISR_ISF9_Msk   (0x1UL << HSEM_C1ISR_ISF9_Pos)
	0x00000200
#define	HSEM_C1ISR_ISF9   HSEM_C1ISR_ISF9_Msk
	semaphore 9 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF10_Pos   (10U)
#define	HSEM_C1ISR_ISF10_Msk   (0x1UL << HSEM_C1ISR_ISF10_Pos)
	0x00000400
#define	HSEM_C1ISR_ISF10   HSEM_C1ISR_ISF10_Msk
	semaphore 10 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF11_Pos   (11U)
#define	HSEM_C1ISR_ISF11_Msk   (0x1UL << HSEM_C1ISR_ISF11_Pos)
	0x00000800
#define	HSEM_C1ISR_ISF11   HSEM_C1ISR_ISF11_Msk
	semaphore 11 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF12_Pos   (12U)
#define	HSEM_C1ISR_ISF12_Msk   (0x1UL << HSEM_C1ISR_ISF12_Pos)
	0x00001000
#define	HSEM_C1ISR_ISF12   HSEM_C1ISR_ISF12_Msk
	semaphore 12 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF13_Pos   (13U)
#define	HSEM_C1ISR_ISF13_Msk   (0x1UL << HSEM_C1ISR_ISF13_Pos)
	0x00002000
#define	HSEM_C1ISR_ISF13   HSEM_C1ISR_ISF13_Msk
	semaphore 13 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF14_Pos   (14U)
#define	HSEM_C1ISR_ISF14_Msk   (0x1UL << HSEM_C1ISR_ISF14_Pos)
	0x00004000
#define	HSEM_C1ISR_ISF14   HSEM_C1ISR_ISF14_Msk
	semaphore 14 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF15_Pos   (15U)
#define	HSEM_C1ISR_ISF15_Msk   (0x1UL << HSEM_C1ISR_ISF15_Pos)
	0x00008000
#define	HSEM_C1ISR_ISF15   HSEM_C1ISR_ISF15_Msk
	semaphore 15 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF16_Pos   (16U)
#define	HSEM_C1ISR_ISF16_Msk   (0x1UL << HSEM_C1ISR_ISF16_Pos)
	0x00010000
#define	HSEM_C1ISR_ISF16   HSEM_C1ISR_ISF16_Msk
	semaphore 16 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF17_Pos   (17U)
#define	HSEM_C1ISR_ISF17_Msk   (0x1UL << HSEM_C1ISR_ISF17_Pos)
	0x00020000
#define	HSEM_C1ISR_ISF17   HSEM_C1ISR_ISF17_Msk
	semaphore 17 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF18_Pos   (18U)
#define	HSEM_C1ISR_ISF18_Msk   (0x1UL << HSEM_C1ISR_ISF18_Pos)
	0x00040000
#define	HSEM_C1ISR_ISF18   HSEM_C1ISR_ISF18_Msk
	semaphore 18 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF19_Pos   (19U)
#define	HSEM_C1ISR_ISF19_Msk   (0x1UL << HSEM_C1ISR_ISF19_Pos)
	0x00080000
#define	HSEM_C1ISR_ISF19   HSEM_C1ISR_ISF19_Msk
	semaphore 19 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF20_Pos   (20U)
#define	HSEM_C1ISR_ISF20_Msk   (0x1UL << HSEM_C1ISR_ISF20_Pos)
	0x00100000
#define	HSEM_C1ISR_ISF20   HSEM_C1ISR_ISF20_Msk
	semaphore 20 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF21_Pos   (21U)
#define	HSEM_C1ISR_ISF21_Msk   (0x1UL << HSEM_C1ISR_ISF21_Pos)
	0x00200000
#define	HSEM_C1ISR_ISF21   HSEM_C1ISR_ISF21_Msk
	semaphore 21 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF22_Pos   (22U)
#define	HSEM_C1ISR_ISF22_Msk   (0x1UL << HSEM_C1ISR_ISF22_Pos)
	0x00400000
#define	HSEM_C1ISR_ISF22   HSEM_C1ISR_ISF22_Msk
	semaphore 22 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF23_Pos   (23U)
#define	HSEM_C1ISR_ISF23_Msk   (0x1UL << HSEM_C1ISR_ISF23_Pos)
	0x00800000
#define	HSEM_C1ISR_ISF23   HSEM_C1ISR_ISF23_Msk
	semaphore 23 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF24_Pos   (24U)
#define	HSEM_C1ISR_ISF24_Msk   (0x1UL << HSEM_C1ISR_ISF24_Pos)
	0x01000000
#define	HSEM_C1ISR_ISF24   HSEM_C1ISR_ISF24_Msk
	semaphore 24 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF25_Pos   (25U)
#define	HSEM_C1ISR_ISF25_Msk   (0x1UL << HSEM_C1ISR_ISF25_Pos)
	0x02000000
#define	HSEM_C1ISR_ISF25   HSEM_C1ISR_ISF25_Msk
	semaphore 25 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF26_Pos   (26U)
#define	HSEM_C1ISR_ISF26_Msk   (0x1UL << HSEM_C1ISR_ISF26_Pos)
	0x04000000
#define	HSEM_C1ISR_ISF26   HSEM_C1ISR_ISF26_Msk
	semaphore 26 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF27_Pos   (27U)
#define	HSEM_C1ISR_ISF27_Msk   (0x1UL << HSEM_C1ISR_ISF27_Pos)
	0x08000000
#define	HSEM_C1ISR_ISF27   HSEM_C1ISR_ISF27_Msk
	semaphore 27 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF28_Pos   (28U)
#define	HSEM_C1ISR_ISF28_Msk   (0x1UL << HSEM_C1ISR_ISF28_Pos)
	0x10000000
#define	HSEM_C1ISR_ISF28   HSEM_C1ISR_ISF28_Msk
	semaphore 28 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF29_Pos   (29U)
#define	HSEM_C1ISR_ISF29_Msk   (0x1UL << HSEM_C1ISR_ISF29_Pos)
	0x20000000
#define	HSEM_C1ISR_ISF29   HSEM_C1ISR_ISF29_Msk
	semaphore 29 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF30_Pos   (30U)
#define	HSEM_C1ISR_ISF30_Msk   (0x1UL << HSEM_C1ISR_ISF30_Pos)
	0x40000000
#define	HSEM_C1ISR_ISF30   HSEM_C1ISR_ISF30_Msk
	semaphore 30 interrupt 0 status bit.
#define	HSEM_C1ISR_ISF31_Pos   (31U)
#define	HSEM_C1ISR_ISF31_Msk   (0x1UL << HSEM_C1ISR_ISF31_Pos)
	0x80000000
#define	HSEM_C1ISR_ISF31   HSEM_C1ISR_ISF31_Msk
	semaphore 31 interrupt 0 status bit.
#define	HSEM_C1MISR_MISF0_Pos   (0U)
#define	HSEM_C1MISR_MISF0_Msk   (0x1UL << HSEM_C1MISR_MISF0_Pos)
	0x00000001
#define	HSEM_C1MISR_MISF0   HSEM_C1MISR_MISF0_Msk
	semaphore 0 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF1_Pos   (1U)
#define	HSEM_C1MISR_MISF1_Msk   (0x1UL << HSEM_C1MISR_MISF1_Pos)
	0x00000002
#define	HSEM_C1MISR_MISF1   HSEM_C1MISR_MISF1_Msk
	semaphore 1 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF2_Pos   (2U)
#define	HSEM_C1MISR_MISF2_Msk   (0x1UL << HSEM_C1MISR_MISF2_Pos)
	0x00000004
#define	HSEM_C1MISR_MISF2   HSEM_C1MISR_MISF2_Msk
	semaphore 2 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF3_Pos   (3U)
#define	HSEM_C1MISR_MISF3_Msk   (0x1UL << HSEM_C1MISR_MISF3_Pos)
	0x00000008
#define	HSEM_C1MISR_MISF3   HSEM_C1MISR_MISF3_Msk
	semaphore 3 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF4_Pos   (4U)
#define	HSEM_C1MISR_MISF4_Msk   (0x1UL << HSEM_C1MISR_MISF4_Pos)
	0x00000010
#define	HSEM_C1MISR_MISF4   HSEM_C1MISR_MISF4_Msk
	semaphore 4 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF5_Pos   (5U)
#define	HSEM_C1MISR_MISF5_Msk   (0x1UL << HSEM_C1MISR_MISF5_Pos)
	0x00000020
#define	HSEM_C1MISR_MISF5   HSEM_C1MISR_MISF5_Msk
	semaphore 5 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF6_Pos   (6U)
#define	HSEM_C1MISR_MISF6_Msk   (0x1UL << HSEM_C1MISR_MISF6_Pos)
	0x00000040
#define	HSEM_C1MISR_MISF6   HSEM_C1MISR_MISF6_Msk
	semaphore 6 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF7_Pos   (7U)
#define	HSEM_C1MISR_MISF7_Msk   (0x1UL << HSEM_C1MISR_MISF7_Pos)
	0x00000080
#define	HSEM_C1MISR_MISF7   HSEM_C1MISR_MISF7_Msk
	semaphore 7 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF8_Pos   (8U)
#define	HSEM_C1MISR_MISF8_Msk   (0x1UL << HSEM_C1MISR_MISF8_Pos)
	0x00000100
#define	HSEM_C1MISR_MISF8   HSEM_C1MISR_MISF8_Msk
	semaphore 8 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF9_Pos   (9U)
#define	HSEM_C1MISR_MISF9_Msk   (0x1UL << HSEM_C1MISR_MISF9_Pos)
	0x00000200
#define	HSEM_C1MISR_MISF9   HSEM_C1MISR_MISF9_Msk
	semaphore 9 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF10_Pos   (10U)
#define	HSEM_C1MISR_MISF10_Msk   (0x1UL << HSEM_C1MISR_MISF10_Pos)
	0x00000400
#define	HSEM_C1MISR_MISF10   HSEM_C1MISR_MISF10_Msk
	semaphore 10 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF11_Pos   (11U)
#define	HSEM_C1MISR_MISF11_Msk   (0x1UL << HSEM_C1MISR_MISF11_Pos)
	0x00000800
#define	HSEM_C1MISR_MISF11   HSEM_C1MISR_MISF11_Msk
	semaphore 11 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF12_Pos   (12U)
#define	HSEM_C1MISR_MISF12_Msk   (0x1UL << HSEM_C1MISR_MISF12_Pos)
	0x00001000
#define	HSEM_C1MISR_MISF12   HSEM_C1MISR_MISF12_Msk
	semaphore 12 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF13_Pos   (13U)
#define	HSEM_C1MISR_MISF13_Msk   (0x1UL << HSEM_C1MISR_MISF13_Pos)
	0x00002000
#define	HSEM_C1MISR_MISF13   HSEM_C1MISR_MISF13_Msk
	semaphore 13 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF14_Pos   (14U)
#define	HSEM_C1MISR_MISF14_Msk   (0x1UL << HSEM_C1MISR_MISF14_Pos)
	0x00004000
#define	HSEM_C1MISR_MISF14   HSEM_C1MISR_MISF14_Msk
	semaphore 14 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF15_Pos   (15U)
#define	HSEM_C1MISR_MISF15_Msk   (0x1UL << HSEM_C1MISR_MISF15_Pos)
	0x00008000
#define	HSEM_C1MISR_MISF15   HSEM_C1MISR_MISF15_Msk
	semaphore 15 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF16_Pos   (16U)
#define	HSEM_C1MISR_MISF16_Msk   (0x1UL << HSEM_C1MISR_MISF16_Pos)
	0x00010000
#define	HSEM_C1MISR_MISF16   HSEM_C1MISR_MISF16_Msk
	semaphore 16 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF17_Pos   (17U)
#define	HSEM_C1MISR_MISF17_Msk   (0x1UL << HSEM_C1MISR_MISF17_Pos)
	0x00020000
#define	HSEM_C1MISR_MISF17   HSEM_C1MISR_MISF17_Msk
	semaphore 17 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF18_Pos   (18U)
#define	HSEM_C1MISR_MISF18_Msk   (0x1UL << HSEM_C1MISR_MISF18_Pos)
	0x00040000
#define	HSEM_C1MISR_MISF18   HSEM_C1MISR_MISF18_Msk
	semaphore 18 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF19_Pos   (19U)
#define	HSEM_C1MISR_MISF19_Msk   (0x1UL << HSEM_C1MISR_MISF19_Pos)
	0x00080000
#define	HSEM_C1MISR_MISF19   HSEM_C1MISR_MISF19_Msk
	semaphore 19 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF20_Pos   (20U)
#define	HSEM_C1MISR_MISF20_Msk   (0x1UL << HSEM_C1MISR_MISF20_Pos)
	0x00100000
#define	HSEM_C1MISR_MISF20   HSEM_C1MISR_MISF20_Msk
	semaphore 20 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF21_Pos   (21U)
#define	HSEM_C1MISR_MISF21_Msk   (0x1UL << HSEM_C1MISR_MISF21_Pos)
	0x00200000
#define	HSEM_C1MISR_MISF21   HSEM_C1MISR_MISF21_Msk
	semaphore 21 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF22_Pos   (22U)
#define	HSEM_C1MISR_MISF22_Msk   (0x1UL << HSEM_C1MISR_MISF22_Pos)
	0x00400000
#define	HSEM_C1MISR_MISF22   HSEM_C1MISR_MISF22_Msk
	semaphore 22 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF23_Pos   (23U)
#define	HSEM_C1MISR_MISF23_Msk   (0x1UL << HSEM_C1MISR_MISF23_Pos)
	0x00800000
#define	HSEM_C1MISR_MISF23   HSEM_C1MISR_MISF23_Msk
	semaphore 23 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF24_Pos   (24U)
#define	HSEM_C1MISR_MISF24_Msk   (0x1UL << HSEM_C1MISR_MISF24_Pos)
	0x01000000
#define	HSEM_C1MISR_MISF24   HSEM_C1MISR_MISF24_Msk
	semaphore 24 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF25_Pos   (25U)
#define	HSEM_C1MISR_MISF25_Msk   (0x1UL << HSEM_C1MISR_MISF25_Pos)
	0x02000000
#define	HSEM_C1MISR_MISF25   HSEM_C1MISR_MISF25_Msk
	semaphore 25 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF26_Pos   (26U)
#define	HSEM_C1MISR_MISF26_Msk   (0x1UL << HSEM_C1MISR_MISF26_Pos)
	0x04000000
#define	HSEM_C1MISR_MISF26   HSEM_C1MISR_MISF26_Msk
	semaphore 26 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF27_Pos   (27U)
#define	HSEM_C1MISR_MISF27_Msk   (0x1UL << HSEM_C1MISR_MISF27_Pos)
	0x08000000
#define	HSEM_C1MISR_MISF27   HSEM_C1MISR_MISF27_Msk
	semaphore 27 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF28_Pos   (28U)
#define	HSEM_C1MISR_MISF28_Msk   (0x1UL << HSEM_C1MISR_MISF28_Pos)
	0x10000000
#define	HSEM_C1MISR_MISF28   HSEM_C1MISR_MISF28_Msk
	semaphore 28 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF29_Pos   (29U)
#define	HSEM_C1MISR_MISF29_Msk   (0x1UL << HSEM_C1MISR_MISF29_Pos)
	0x20000000
#define	HSEM_C1MISR_MISF29   HSEM_C1MISR_MISF29_Msk
	semaphore 29 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF30_Pos   (30U)
#define	HSEM_C1MISR_MISF30_Msk   (0x1UL << HSEM_C1MISR_MISF30_Pos)
	0x40000000
#define	HSEM_C1MISR_MISF30   HSEM_C1MISR_MISF30_Msk
	semaphore 30 interrupt 0 masked status bit.
#define	HSEM_C1MISR_MISF31_Pos   (31U)
#define	HSEM_C1MISR_MISF31_Msk   (0x1UL << HSEM_C1MISR_MISF31_Pos)
	0x80000000
#define	HSEM_C1MISR_MISF31   HSEM_C1MISR_MISF31_Msk
	semaphore 31 interrupt 0 masked status bit.
#define	HSEM_CR_COREID_Pos   (8U)
#define	HSEM_CR_COREID_Msk   (0xFFUL << HSEM_CR_COREID_Pos)
	0x0000FF00
#define	HSEM_CR_COREID   HSEM_CR_COREID_Msk
	CoreID of semaphores to be cleared.
#define	HSEM_CR_KEY_Pos   (16U)
#define	HSEM_CR_KEY_Msk   (0xFFFFUL << HSEM_CR_KEY_Pos)
	0xFFFF0000
#define	HSEM_CR_KEY   HSEM_CR_KEY_Msk
	semaphores clear key.
#define	HSEM_KEYR_KEY_Pos   (16U)
#define	HSEM_KEYR_KEY_Msk   (0xFFFFUL << HSEM_KEYR_KEY_Pos)
	0xFFFF0000
#define	HSEM_KEYR_KEY   HSEM_KEYR_KEY_Msk
	semaphores clear key.
#define	I2C_CR1_PE_Pos   (0U)
#define	I2C_CR1_PE_Msk   (0x1UL << I2C_CR1_PE_Pos)
	0x00000001
#define	I2C_CR1_PE   I2C_CR1_PE_Msk
	Peripheral enable.
#define	I2C_CR1_TXIE_Pos   (1U)
#define	I2C_CR1_TXIE_Msk   (0x1UL << I2C_CR1_TXIE_Pos)
	0x00000002
#define	I2C_CR1_TXIE   I2C_CR1_TXIE_Msk
	TX interrupt enable.
#define	I2C_CR1_RXIE_Pos   (2U)
#define	I2C_CR1_RXIE_Msk   (0x1UL << I2C_CR1_RXIE_Pos)
	0x00000004
#define	I2C_CR1_RXIE   I2C_CR1_RXIE_Msk
	RX interrupt enable.
#define	I2C_CR1_ADDRIE_Pos   (3U)
#define	I2C_CR1_ADDRIE_Msk   (0x1UL << I2C_CR1_ADDRIE_Pos)
	0x00000008
#define	I2C_CR1_ADDRIE   I2C_CR1_ADDRIE_Msk
	Address match interrupt enable.
#define	I2C_CR1_NACKIE_Pos   (4U)
#define	I2C_CR1_NACKIE_Msk   (0x1UL << I2C_CR1_NACKIE_Pos)
	0x00000010
#define	I2C_CR1_NACKIE   I2C_CR1_NACKIE_Msk
	NACK received interrupt enable.
#define	I2C_CR1_STOPIE_Pos   (5U)
#define	I2C_CR1_STOPIE_Msk   (0x1UL << I2C_CR1_STOPIE_Pos)
	0x00000020
#define	I2C_CR1_STOPIE   I2C_CR1_STOPIE_Msk
	STOP detection interrupt enable.
#define	I2C_CR1_TCIE_Pos   (6U)
#define	I2C_CR1_TCIE_Msk   (0x1UL << I2C_CR1_TCIE_Pos)
	0x00000040
#define	I2C_CR1_TCIE   I2C_CR1_TCIE_Msk
	Transfer complete interrupt enable.
#define	I2C_CR1_ERRIE_Pos   (7U)
#define	I2C_CR1_ERRIE_Msk   (0x1UL << I2C_CR1_ERRIE_Pos)
	0x00000080
#define	I2C_CR1_ERRIE   I2C_CR1_ERRIE_Msk
	Errors interrupt enable.
#define	I2C_CR1_DNF_Pos   (8U)
#define	I2C_CR1_DNF_Msk   (0xFUL << I2C_CR1_DNF_Pos)
	0x00000F00
#define	I2C_CR1_DNF   I2C_CR1_DNF_Msk
	Digital noise filter.
#define	I2C_CR1_ANFOFF_Pos   (12U)
#define	I2C_CR1_ANFOFF_Msk   (0x1UL << I2C_CR1_ANFOFF_Pos)
	0x00001000
#define	I2C_CR1_ANFOFF   I2C_CR1_ANFOFF_Msk
	Analog noise filter OFF.
#define	I2C_CR1_TXDMAEN_Pos   (14U)
#define	I2C_CR1_TXDMAEN_Msk   (0x1UL << I2C_CR1_TXDMAEN_Pos)
	0x00004000
#define	I2C_CR1_TXDMAEN   I2C_CR1_TXDMAEN_Msk
	DMA transmission requests enable.
#define	I2C_CR1_RXDMAEN_Pos   (15U)
#define	I2C_CR1_RXDMAEN_Msk   (0x1UL << I2C_CR1_RXDMAEN_Pos)
	0x00008000
#define	I2C_CR1_RXDMAEN   I2C_CR1_RXDMAEN_Msk
	DMA reception requests enable.
#define	I2C_CR1_SBC_Pos   (16U)
#define	I2C_CR1_SBC_Msk   (0x1UL << I2C_CR1_SBC_Pos)
	0x00010000
#define	I2C_CR1_SBC   I2C_CR1_SBC_Msk
	Slave byte control.
#define	I2C_CR1_NOSTRETCH_Pos   (17U)
#define	I2C_CR1_NOSTRETCH_Msk   (0x1UL << I2C_CR1_NOSTRETCH_Pos)
	0x00020000
#define	I2C_CR1_NOSTRETCH   I2C_CR1_NOSTRETCH_Msk
	Clock stretching disable.
#define	I2C_CR1_WUPEN_Pos   (18U)
#define	I2C_CR1_WUPEN_Msk   (0x1UL << I2C_CR1_WUPEN_Pos)
	0x00040000
#define	I2C_CR1_WUPEN   I2C_CR1_WUPEN_Msk
	Wakeup from STOP enable.
#define	I2C_CR1_GCEN_Pos   (19U)
#define	I2C_CR1_GCEN_Msk   (0x1UL << I2C_CR1_GCEN_Pos)
	0x00080000
#define	I2C_CR1_GCEN   I2C_CR1_GCEN_Msk
	General call enable.
#define	I2C_CR1_SMBHEN_Pos   (20U)
#define	I2C_CR1_SMBHEN_Msk   (0x1UL << I2C_CR1_SMBHEN_Pos)
	0x00100000
#define	I2C_CR1_SMBHEN   I2C_CR1_SMBHEN_Msk
	SMBus host address enable.
#define	I2C_CR1_SMBDEN_Pos   (21U)
#define	I2C_CR1_SMBDEN_Msk   (0x1UL << I2C_CR1_SMBDEN_Pos)
	0x00200000
#define	I2C_CR1_SMBDEN   I2C_CR1_SMBDEN_Msk
	SMBus device default address enable.
#define	I2C_CR1_ALERTEN_Pos   (22U)
#define	I2C_CR1_ALERTEN_Msk   (0x1UL << I2C_CR1_ALERTEN_Pos)
	0x00400000
#define	I2C_CR1_ALERTEN   I2C_CR1_ALERTEN_Msk
	SMBus alert enable.
#define	I2C_CR1_PECEN_Pos   (23U)
#define	I2C_CR1_PECEN_Msk   (0x1UL << I2C_CR1_PECEN_Pos)
	0x00800000
#define	I2C_CR1_PECEN   I2C_CR1_PECEN_Msk
	PEC enable.
#define	I2C_CR2_SADD_Pos   (0U)
#define	I2C_CR2_SADD_Msk   (0x3FFUL << I2C_CR2_SADD_Pos)
	0x000003FF
#define	I2C_CR2_SADD   I2C_CR2_SADD_Msk
	Slave address (master mode).
#define	I2C_CR2_RD_WRN_Pos   (10U)
#define	I2C_CR2_RD_WRN_Msk   (0x1UL << I2C_CR2_RD_WRN_Pos)
	0x00000400
#define	I2C_CR2_RD_WRN   I2C_CR2_RD_WRN_Msk
	Transfer direction (master mode).
#define	I2C_CR2_ADD10_Pos   (11U)
#define	I2C_CR2_ADD10_Msk   (0x1UL << I2C_CR2_ADD10_Pos)
	0x00000800
#define	I2C_CR2_ADD10   I2C_CR2_ADD10_Msk
	10-bit addressing mode (master mode)
#define	I2C_CR2_HEAD10R_Pos   (12U)
#define	I2C_CR2_HEAD10R_Msk   (0x1UL << I2C_CR2_HEAD10R_Pos)
	0x00001000
#define	I2C_CR2_HEAD10R   I2C_CR2_HEAD10R_Msk
	10-bit address header only read direction (master mode)
#define	I2C_CR2_START_Pos   (13U)
#define	I2C_CR2_START_Msk   (0x1UL << I2C_CR2_START_Pos)
	0x00002000
#define	I2C_CR2_START   I2C_CR2_START_Msk
	START generation.
#define	I2C_CR2_STOP_Pos   (14U)
#define	I2C_CR2_STOP_Msk   (0x1UL << I2C_CR2_STOP_Pos)
	0x00004000
#define	I2C_CR2_STOP   I2C_CR2_STOP_Msk
	STOP generation (master mode).
#define	I2C_CR2_NACK_Pos   (15U)
#define	I2C_CR2_NACK_Msk   (0x1UL << I2C_CR2_NACK_Pos)
	0x00008000
#define	I2C_CR2_NACK   I2C_CR2_NACK_Msk
	NACK generation (slave mode).
#define	I2C_CR2_NBYTES_Pos   (16U)
#define	I2C_CR2_NBYTES_Msk   (0xFFUL << I2C_CR2_NBYTES_Pos)
	0x00FF0000
#define	I2C_CR2_NBYTES   I2C_CR2_NBYTES_Msk
	Number of bytes.
#define	I2C_CR2_RELOAD_Pos   (24U)
#define	I2C_CR2_RELOAD_Msk   (0x1UL << I2C_CR2_RELOAD_Pos)
	0x01000000
#define	I2C_CR2_RELOAD   I2C_CR2_RELOAD_Msk
	NBYTES reload mode.
#define	I2C_CR2_AUTOEND_Pos   (25U)
#define	I2C_CR2_AUTOEND_Msk   (0x1UL << I2C_CR2_AUTOEND_Pos)
	0x02000000
#define	I2C_CR2_AUTOEND   I2C_CR2_AUTOEND_Msk
	Automatic end mode (master mode).
#define	I2C_CR2_PECBYTE_Pos   (26U)
#define	I2C_CR2_PECBYTE_Msk   (0x1UL << I2C_CR2_PECBYTE_Pos)
	0x04000000
#define	I2C_CR2_PECBYTE   I2C_CR2_PECBYTE_Msk
	Packet error checking byte.
#define	I2C_OAR1_OA1_Pos   (0U)
#define	I2C_OAR1_OA1_Msk   (0x3FFUL << I2C_OAR1_OA1_Pos)
	0x000003FF
#define	I2C_OAR1_OA1   I2C_OAR1_OA1_Msk
	Interface own address 1.
#define	I2C_OAR1_OA1MODE_Pos   (10U)
#define	I2C_OAR1_OA1MODE_Msk   (0x1UL << I2C_OAR1_OA1MODE_Pos)
	0x00000400
#define	I2C_OAR1_OA1MODE   I2C_OAR1_OA1MODE_Msk
	Own address 1 10-bit mode.
#define	I2C_OAR1_OA1EN_Pos   (15U)
#define	I2C_OAR1_OA1EN_Msk   (0x1UL << I2C_OAR1_OA1EN_Pos)
	0x00008000
#define	I2C_OAR1_OA1EN   I2C_OAR1_OA1EN_Msk
	Own address 1 enable.
#define	I2C_OAR2_OA2_Pos   (1U)
#define	I2C_OAR2_OA2_Msk   (0x7FUL << I2C_OAR2_OA2_Pos)
	0x000000FE
#define	I2C_OAR2_OA2   I2C_OAR2_OA2_Msk
	Interface own address 2.
#define	I2C_OAR2_OA2MSK_Pos   (8U)
#define	I2C_OAR2_OA2MSK_Msk   (0x7UL << I2C_OAR2_OA2MSK_Pos)
	0x00000700
#define	I2C_OAR2_OA2MSK   I2C_OAR2_OA2MSK_Msk
	Own address 2 masks.
#define	I2C_OAR2_OA2NOMASK   0x00000000UL
	No mask.
#define	I2C_OAR2_OA2MASK01_Pos   (8U)
#define	I2C_OAR2_OA2MASK01_Msk   (0x1UL << I2C_OAR2_OA2MASK01_Pos)
	0x00000100
#define	I2C_OAR2_OA2MASK01   I2C_OAR2_OA2MASK01_Msk
	OA2[1] is masked, Only OA2[7:2] are compared.
#define	I2C_OAR2_OA2MASK02_Pos   (9U)
#define	I2C_OAR2_OA2MASK02_Msk   (0x1UL << I2C_OAR2_OA2MASK02_Pos)
	0x00000200
#define	I2C_OAR2_OA2MASK02   I2C_OAR2_OA2MASK02_Msk
	OA2[2:1] is masked, Only OA2[7:3] are compared.
#define	I2C_OAR2_OA2MASK03_Pos   (8U)
#define	I2C_OAR2_OA2MASK03_Msk   (0x3UL << I2C_OAR2_OA2MASK03_Pos)
	0x00000300
#define	I2C_OAR2_OA2MASK03   I2C_OAR2_OA2MASK03_Msk
	OA2[3:1] is masked, Only OA2[7:4] are compared.
#define	I2C_OAR2_OA2MASK04_Pos   (10U)
#define	I2C_OAR2_OA2MASK04_Msk   (0x1UL << I2C_OAR2_OA2MASK04_Pos)
	0x00000400
#define	I2C_OAR2_OA2MASK04   I2C_OAR2_OA2MASK04_Msk
	OA2[4:1] is masked, Only OA2[7:5] are compared.
#define	I2C_OAR2_OA2MASK05_Pos   (8U)
#define	I2C_OAR2_OA2MASK05_Msk   (0x5UL << I2C_OAR2_OA2MASK05_Pos)
	0x00000500
#define	I2C_OAR2_OA2MASK05   I2C_OAR2_OA2MASK05_Msk
	OA2[5:1] is masked, Only OA2[7:6] are compared.
#define	I2C_OAR2_OA2MASK06_Pos   (9U)
#define	I2C_OAR2_OA2MASK06_Msk   (0x3UL << I2C_OAR2_OA2MASK06_Pos)
	0x00000600
#define	I2C_OAR2_OA2MASK06   I2C_OAR2_OA2MASK06_Msk
	OA2[6:1] is masked, Only OA2[7] are compared.
#define	I2C_OAR2_OA2MASK07_Pos   (8U)
#define	I2C_OAR2_OA2MASK07_Msk   (0x7UL << I2C_OAR2_OA2MASK07_Pos)
	0x00000700
#define	I2C_OAR2_OA2MASK07   I2C_OAR2_OA2MASK07_Msk
	OA2[7:1] is masked, No comparison is done.
#define	I2C_OAR2_OA2EN_Pos   (15U)
#define	I2C_OAR2_OA2EN_Msk   (0x1UL << I2C_OAR2_OA2EN_Pos)
	0x00008000
#define	I2C_OAR2_OA2EN   I2C_OAR2_OA2EN_Msk
	Own address 2 enable.
#define	I2C_TIMINGR_SCLL_Pos   (0U)
#define	I2C_TIMINGR_SCLL_Msk   (0xFFUL << I2C_TIMINGR_SCLL_Pos)
	0x000000FF
#define	I2C_TIMINGR_SCLL   I2C_TIMINGR_SCLL_Msk
	SCL low period (master mode).
#define	I2C_TIMINGR_SCLH_Pos   (8U)
#define	I2C_TIMINGR_SCLH_Msk   (0xFFUL << I2C_TIMINGR_SCLH_Pos)
	0x0000FF00
#define	I2C_TIMINGR_SCLH   I2C_TIMINGR_SCLH_Msk
	SCL high period (master mode).
#define	I2C_TIMINGR_SDADEL_Pos   (16U)
#define	I2C_TIMINGR_SDADEL_Msk   (0xFUL << I2C_TIMINGR_SDADEL_Pos)
	0x000F0000
#define	I2C_TIMINGR_SDADEL   I2C_TIMINGR_SDADEL_Msk
	Data hold time.
#define	I2C_TIMINGR_SCLDEL_Pos   (20U)
#define	I2C_TIMINGR_SCLDEL_Msk   (0xFUL << I2C_TIMINGR_SCLDEL_Pos)
	0x00F00000
#define	I2C_TIMINGR_SCLDEL   I2C_TIMINGR_SCLDEL_Msk
	Data setup time.
#define	I2C_TIMINGR_PRESC_Pos   (28U)
#define	I2C_TIMINGR_PRESC_Msk   (0xFUL << I2C_TIMINGR_PRESC_Pos)
	0xF0000000
#define	I2C_TIMINGR_PRESC   I2C_TIMINGR_PRESC_Msk
	Timings prescaler.
#define	I2C_TIMEOUTR_TIMEOUTA_Pos   (0U)
#define	I2C_TIMEOUTR_TIMEOUTA_Msk   (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)
	0x00000FFF
#define	I2C_TIMEOUTR_TIMEOUTA   I2C_TIMEOUTR_TIMEOUTA_Msk
	Bus timeout A.
#define	I2C_TIMEOUTR_TIDLE_Pos   (12U)
#define	I2C_TIMEOUTR_TIDLE_Msk   (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)
	0x00001000
#define	I2C_TIMEOUTR_TIDLE   I2C_TIMEOUTR_TIDLE_Msk
	Idle clock timeout detection.
#define	I2C_TIMEOUTR_TIMOUTEN_Pos   (15U)
#define	I2C_TIMEOUTR_TIMOUTEN_Msk   (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)
	0x00008000
#define	I2C_TIMEOUTR_TIMOUTEN   I2C_TIMEOUTR_TIMOUTEN_Msk
	Clock timeout enable.
#define	I2C_TIMEOUTR_TIMEOUTB_Pos   (16U)
#define	I2C_TIMEOUTR_TIMEOUTB_Msk   (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)
	0x0FFF0000
#define	I2C_TIMEOUTR_TIMEOUTB   I2C_TIMEOUTR_TIMEOUTB_Msk
	Bus timeout B.
#define	I2C_TIMEOUTR_TEXTEN_Pos   (31U)
#define	I2C_TIMEOUTR_TEXTEN_Msk   (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)
	0x80000000
#define	I2C_TIMEOUTR_TEXTEN   I2C_TIMEOUTR_TEXTEN_Msk
	Extended clock timeout enable.
#define	I2C_ISR_TXE_Pos   (0U)
#define	I2C_ISR_TXE_Msk   (0x1UL << I2C_ISR_TXE_Pos)
	0x00000001
#define	I2C_ISR_TXE   I2C_ISR_TXE_Msk
	Transmit data register empty.
#define	I2C_ISR_TXIS_Pos   (1U)
#define	I2C_ISR_TXIS_Msk   (0x1UL << I2C_ISR_TXIS_Pos)
	0x00000002
#define	I2C_ISR_TXIS   I2C_ISR_TXIS_Msk
	Transmit interrupt status.
#define	I2C_ISR_RXNE_Pos   (2U)
#define	I2C_ISR_RXNE_Msk   (0x1UL << I2C_ISR_RXNE_Pos)
	0x00000004
#define	I2C_ISR_RXNE   I2C_ISR_RXNE_Msk
	Receive data register not empty.
#define	I2C_ISR_ADDR_Pos   (3U)
#define	I2C_ISR_ADDR_Msk   (0x1UL << I2C_ISR_ADDR_Pos)
	0x00000008
#define	I2C_ISR_ADDR   I2C_ISR_ADDR_Msk
	Address matched (slave mode).
#define	I2C_ISR_NACKF_Pos   (4U)
#define	I2C_ISR_NACKF_Msk   (0x1UL << I2C_ISR_NACKF_Pos)
	0x00000010
#define	I2C_ISR_NACKF   I2C_ISR_NACKF_Msk
	NACK received flag.
#define	I2C_ISR_STOPF_Pos   (5U)
#define	I2C_ISR_STOPF_Msk   (0x1UL << I2C_ISR_STOPF_Pos)
	0x00000020
#define	I2C_ISR_STOPF   I2C_ISR_STOPF_Msk
	STOP detection flag.
#define	I2C_ISR_TC_Pos   (6U)
#define	I2C_ISR_TC_Msk   (0x1UL << I2C_ISR_TC_Pos)
	0x00000040
#define	I2C_ISR_TC   I2C_ISR_TC_Msk
	Transfer complete (master mode).
#define	I2C_ISR_TCR_Pos   (7U)
#define	I2C_ISR_TCR_Msk   (0x1UL << I2C_ISR_TCR_Pos)
	0x00000080
#define	I2C_ISR_TCR   I2C_ISR_TCR_Msk
	Transfer complete reload.
#define	I2C_ISR_BERR_Pos   (8U)
#define	I2C_ISR_BERR_Msk   (0x1UL << I2C_ISR_BERR_Pos)
	0x00000100
#define	I2C_ISR_BERR   I2C_ISR_BERR_Msk
	Bus error.
#define	I2C_ISR_ARLO_Pos   (9U)
#define	I2C_ISR_ARLO_Msk   (0x1UL << I2C_ISR_ARLO_Pos)
	0x00000200
#define	I2C_ISR_ARLO   I2C_ISR_ARLO_Msk
	Arbitration lost.
#define	I2C_ISR_OVR_Pos   (10U)
#define	I2C_ISR_OVR_Msk   (0x1UL << I2C_ISR_OVR_Pos)
	0x00000400
#define	I2C_ISR_OVR   I2C_ISR_OVR_Msk
	Overrun/Underrun.
#define	I2C_ISR_PECERR_Pos   (11U)
#define	I2C_ISR_PECERR_Msk   (0x1UL << I2C_ISR_PECERR_Pos)
	0x00000800
#define	I2C_ISR_PECERR   I2C_ISR_PECERR_Msk
	PEC error in reception.
#define	I2C_ISR_TIMEOUT_Pos   (12U)
#define	I2C_ISR_TIMEOUT_Msk   (0x1UL << I2C_ISR_TIMEOUT_Pos)
	0x00001000
#define	I2C_ISR_TIMEOUT   I2C_ISR_TIMEOUT_Msk
	Timeout or Tlow detection flag.
#define	I2C_ISR_ALERT_Pos   (13U)
#define	I2C_ISR_ALERT_Msk   (0x1UL << I2C_ISR_ALERT_Pos)
	0x00002000
#define	I2C_ISR_ALERT   I2C_ISR_ALERT_Msk
	SMBus alert.
#define	I2C_ISR_BUSY_Pos   (15U)
#define	I2C_ISR_BUSY_Msk   (0x1UL << I2C_ISR_BUSY_Pos)
	0x00008000
#define	I2C_ISR_BUSY   I2C_ISR_BUSY_Msk
	Bus busy.
#define	I2C_ISR_DIR_Pos   (16U)
#define	I2C_ISR_DIR_Msk   (0x1UL << I2C_ISR_DIR_Pos)
	0x00010000
#define	I2C_ISR_DIR   I2C_ISR_DIR_Msk
	Transfer direction (slave mode).
#define	I2C_ISR_ADDCODE_Pos   (17U)
#define	I2C_ISR_ADDCODE_Msk   (0x7FUL << I2C_ISR_ADDCODE_Pos)
	0x00FE0000
#define	I2C_ISR_ADDCODE   I2C_ISR_ADDCODE_Msk
	Address match code (slave mode).
#define	I2C_ICR_ADDRCF_Pos   (3U)
#define	I2C_ICR_ADDRCF_Msk   (0x1UL << I2C_ICR_ADDRCF_Pos)
	0x00000008
#define	I2C_ICR_ADDRCF   I2C_ICR_ADDRCF_Msk
	Address matched clear flag.
#define	I2C_ICR_NACKCF_Pos   (4U)
#define	I2C_ICR_NACKCF_Msk   (0x1UL << I2C_ICR_NACKCF_Pos)
	0x00000010
#define	I2C_ICR_NACKCF   I2C_ICR_NACKCF_Msk
	NACK clear flag.
#define	I2C_ICR_STOPCF_Pos   (5U)
#define	I2C_ICR_STOPCF_Msk   (0x1UL << I2C_ICR_STOPCF_Pos)
	0x00000020
#define	I2C_ICR_STOPCF   I2C_ICR_STOPCF_Msk
	STOP detection clear flag.
#define	I2C_ICR_BERRCF_Pos   (8U)
#define	I2C_ICR_BERRCF_Msk   (0x1UL << I2C_ICR_BERRCF_Pos)
	0x00000100
#define	I2C_ICR_BERRCF   I2C_ICR_BERRCF_Msk
	Bus error clear flag.
#define	I2C_ICR_ARLOCF_Pos   (9U)
#define	I2C_ICR_ARLOCF_Msk   (0x1UL << I2C_ICR_ARLOCF_Pos)
	0x00000200
#define	I2C_ICR_ARLOCF   I2C_ICR_ARLOCF_Msk
	Arbitration lost clear flag.
#define	I2C_ICR_OVRCF_Pos   (10U)
#define	I2C_ICR_OVRCF_Msk   (0x1UL << I2C_ICR_OVRCF_Pos)
	0x00000400
#define	I2C_ICR_OVRCF   I2C_ICR_OVRCF_Msk
	Overrun/Underrun clear flag.
#define	I2C_ICR_PECCF_Pos   (11U)
#define	I2C_ICR_PECCF_Msk   (0x1UL << I2C_ICR_PECCF_Pos)
	0x00000800
#define	I2C_ICR_PECCF   I2C_ICR_PECCF_Msk
	PAC error clear flag.
#define	I2C_ICR_TIMOUTCF_Pos   (12U)
#define	I2C_ICR_TIMOUTCF_Msk   (0x1UL << I2C_ICR_TIMOUTCF_Pos)
	0x00001000
#define	I2C_ICR_TIMOUTCF   I2C_ICR_TIMOUTCF_Msk
	Timeout clear flag.
#define	I2C_ICR_ALERTCF_Pos   (13U)
#define	I2C_ICR_ALERTCF_Msk   (0x1UL << I2C_ICR_ALERTCF_Pos)
	0x00002000
#define	I2C_ICR_ALERTCF   I2C_ICR_ALERTCF_Msk
	Alert clear flag.
#define	I2C_PECR_PEC_Pos   (0U)
#define	I2C_PECR_PEC_Msk   (0xFFUL << I2C_PECR_PEC_Pos)
	0x000000FF
#define	I2C_PECR_PEC   I2C_PECR_PEC_Msk
	PEC register.
#define	I2C_RXDR_RXDATA_Pos   (0U)
#define	I2C_RXDR_RXDATA_Msk   (0xFFUL << I2C_RXDR_RXDATA_Pos)
	0x000000FF
#define	I2C_RXDR_RXDATA   I2C_RXDR_RXDATA_Msk
	8-bit receive data
#define	I2C_TXDR_TXDATA_Pos   (0U)
#define	I2C_TXDR_TXDATA_Msk   (0xFFUL << I2C_TXDR_TXDATA_Pos)
	0x000000FF
#define	I2C_TXDR_TXDATA   I2C_TXDR_TXDATA_Msk
	8-bit transmit data
#define	IWDG_KR_KEY_Pos   (0U)
#define	IWDG_KR_KEY_Msk   (0xFFFFUL << IWDG_KR_KEY_Pos)
	0x0000FFFF
#define	IWDG_KR_KEY   IWDG_KR_KEY_Msk
	Key value (write only, read 0000h).
#define	IWDG_PR_PR_Pos   (0U)
#define	IWDG_PR_PR_Msk   (0x7UL << IWDG_PR_PR_Pos)
	0x00000007
#define	IWDG_PR_PR   IWDG_PR_PR_Msk
	PR[2:0] (Prescaler divider).
#define	IWDG_PR_PR_0   (0x1UL << IWDG_PR_PR_Pos)
	0x00000001
#define	IWDG_PR_PR_1   (0x2UL << IWDG_PR_PR_Pos)
	0x00000002
#define	IWDG_PR_PR_2   (0x4UL << IWDG_PR_PR_Pos)
	0x00000004
#define	IWDG_RLR_RL_Pos   (0U)
#define	IWDG_RLR_RL_Msk   (0xFFFUL << IWDG_RLR_RL_Pos)
	0x00000FFF
#define	IWDG_RLR_RL   IWDG_RLR_RL_Msk
	Watchdog counter reload value.
#define	IWDG_SR_PVU_Pos   (0U)
#define	IWDG_SR_PVU_Msk   (0x1UL << IWDG_SR_PVU_Pos)
	0x00000001
#define	IWDG_SR_PVU   IWDG_SR_PVU_Msk
	Watchdog prescaler value update.
#define	IWDG_SR_RVU_Pos   (1U)
#define	IWDG_SR_RVU_Msk   (0x1UL << IWDG_SR_RVU_Pos)
	0x00000002
#define	IWDG_SR_RVU   IWDG_SR_RVU_Msk
	Watchdog counter reload value update.
#define	IWDG_SR_WVU_Pos   (2U)
#define	IWDG_SR_WVU_Msk   (0x1UL << IWDG_SR_WVU_Pos)
	0x00000004
#define	IWDG_SR_WVU   IWDG_SR_WVU_Msk
	Watchdog counter window value update.
#define	IWDG_WINR_WIN_Pos   (0U)
#define	IWDG_WINR_WIN_Msk   (0xFFFUL << IWDG_WINR_WIN_Pos)
	0x00000FFF
#define	IWDG_WINR_WIN   IWDG_WINR_WIN_Msk
	Watchdog counter window value.
#define	LTDC_SSCR_VSH_Pos   (0U)
#define	LTDC_SSCR_VSH_Msk   (0x7FFUL << LTDC_SSCR_VSH_Pos)
	0x000007FF
#define	LTDC_SSCR_VSH   LTDC_SSCR_VSH_Msk
	Vertical Synchronization Height.
#define	LTDC_SSCR_HSW_Pos   (16U)
#define	LTDC_SSCR_HSW_Msk   (0xFFFUL << LTDC_SSCR_HSW_Pos)
	0x0FFF0000
#define	LTDC_SSCR_HSW   LTDC_SSCR_HSW_Msk
	Horizontal Synchronization Width.
#define	LTDC_BPCR_AVBP_Pos   (0U)
#define	LTDC_BPCR_AVBP_Msk   (0x7FFUL << LTDC_BPCR_AVBP_Pos)
	0x000007FF
#define	LTDC_BPCR_AVBP   LTDC_BPCR_AVBP_Msk
	Accumulated Vertical Back Porch.
#define	LTDC_BPCR_AHBP_Pos   (16U)
#define	LTDC_BPCR_AHBP_Msk   (0xFFFUL << LTDC_BPCR_AHBP_Pos)
	0x0FFF0000
#define	LTDC_BPCR_AHBP   LTDC_BPCR_AHBP_Msk
	Accumulated Horizontal Back Porch.
#define	LTDC_AWCR_AAH_Pos   (0U)
#define	LTDC_AWCR_AAH_Msk   (0x7FFUL << LTDC_AWCR_AAH_Pos)
	0x000007FF
#define	LTDC_AWCR_AAH   LTDC_AWCR_AAH_Msk
	Accumulated Active height.
#define	LTDC_AWCR_AAW_Pos   (16U)
#define	LTDC_AWCR_AAW_Msk   (0xFFFUL << LTDC_AWCR_AAW_Pos)
	0x0FFF0000
#define	LTDC_AWCR_AAW   LTDC_AWCR_AAW_Msk
	Accumulated Active Width.
#define	LTDC_TWCR_TOTALH_Pos   (0U)
#define	LTDC_TWCR_TOTALH_Msk   (0x7FFUL << LTDC_TWCR_TOTALH_Pos)
	0x000007FF
#define	LTDC_TWCR_TOTALH   LTDC_TWCR_TOTALH_Msk
	Total height.
#define	LTDC_TWCR_TOTALW_Pos   (16U)
#define	LTDC_TWCR_TOTALW_Msk   (0xFFFUL << LTDC_TWCR_TOTALW_Pos)
	0x0FFF0000
#define	LTDC_TWCR_TOTALW   LTDC_TWCR_TOTALW_Msk
	Total Width.
#define	LTDC_GCR_LTDCEN_Pos   (0U)
#define	LTDC_GCR_LTDCEN_Msk   (0x1UL << LTDC_GCR_LTDCEN_Pos)
	0x00000001
#define	LTDC_GCR_LTDCEN   LTDC_GCR_LTDCEN_Msk
	LCD-TFT controller enable bit.
#define	LTDC_GCR_DBW_Pos   (4U)
#define	LTDC_GCR_DBW_Msk   (0x7UL << LTDC_GCR_DBW_Pos)
	0x00000070
#define	LTDC_GCR_DBW   LTDC_GCR_DBW_Msk
	Dither Blue Width.
#define	LTDC_GCR_DGW_Pos   (8U)
#define	LTDC_GCR_DGW_Msk   (0x7UL << LTDC_GCR_DGW_Pos)
	0x00000700
#define	LTDC_GCR_DGW   LTDC_GCR_DGW_Msk
	Dither Green Width.
#define	LTDC_GCR_DRW_Pos   (12U)
#define	LTDC_GCR_DRW_Msk   (0x7UL << LTDC_GCR_DRW_Pos)
	0x00007000
#define	LTDC_GCR_DRW   LTDC_GCR_DRW_Msk
	Dither Red Width.
#define	LTDC_GCR_DEN_Pos   (16U)
#define	LTDC_GCR_DEN_Msk   (0x1UL << LTDC_GCR_DEN_Pos)
	0x00010000
#define	LTDC_GCR_DEN   LTDC_GCR_DEN_Msk
	Dither Enable.
#define	LTDC_GCR_PCPOL_Pos   (28U)
#define	LTDC_GCR_PCPOL_Msk   (0x1UL << LTDC_GCR_PCPOL_Pos)
	0x10000000
#define	LTDC_GCR_PCPOL   LTDC_GCR_PCPOL_Msk
	Pixel Clock Polarity.
#define	LTDC_GCR_DEPOL_Pos   (29U)
#define	LTDC_GCR_DEPOL_Msk   (0x1UL << LTDC_GCR_DEPOL_Pos)
	0x20000000
#define	LTDC_GCR_DEPOL   LTDC_GCR_DEPOL_Msk
	Data Enable Polarity.
#define	LTDC_GCR_VSPOL_Pos   (30U)
#define	LTDC_GCR_VSPOL_Msk   (0x1UL << LTDC_GCR_VSPOL_Pos)
	0x40000000
#define	LTDC_GCR_VSPOL   LTDC_GCR_VSPOL_Msk
	Vertical Synchronization Polarity.
#define	LTDC_GCR_HSPOL_Pos   (31U)
#define	LTDC_GCR_HSPOL_Msk   (0x1UL << LTDC_GCR_HSPOL_Pos)
	0x80000000
#define	LTDC_GCR_HSPOL   LTDC_GCR_HSPOL_Msk
	Horizontal Synchronization Polarity.
#define	LTDC_SRCR_IMR_Pos   (0U)
#define	LTDC_SRCR_IMR_Msk   (0x1UL << LTDC_SRCR_IMR_Pos)
	0x00000001
#define	LTDC_SRCR_IMR   LTDC_SRCR_IMR_Msk
	Immediate Reload.
#define	LTDC_SRCR_VBR_Pos   (1U)
#define	LTDC_SRCR_VBR_Msk   (0x1UL << LTDC_SRCR_VBR_Pos)
	0x00000002
#define	LTDC_SRCR_VBR   LTDC_SRCR_VBR_Msk
	Vertical Blanking Reload.
#define	LTDC_BCCR_BCBLUE_Pos   (0U)
#define	LTDC_BCCR_BCBLUE_Msk   (0xFFUL << LTDC_BCCR_BCBLUE_Pos)
	0x000000FF
#define	LTDC_BCCR_BCBLUE   LTDC_BCCR_BCBLUE_Msk
	Background Blue value.
#define	LTDC_BCCR_BCGREEN_Pos   (8U)
#define	LTDC_BCCR_BCGREEN_Msk   (0xFFUL << LTDC_BCCR_BCGREEN_Pos)
	0x0000FF00
#define	LTDC_BCCR_BCGREEN   LTDC_BCCR_BCGREEN_Msk
	Background Green value.
#define	LTDC_BCCR_BCRED_Pos   (16U)
#define	LTDC_BCCR_BCRED_Msk   (0xFFUL << LTDC_BCCR_BCRED_Pos)
	0x00FF0000
#define	LTDC_BCCR_BCRED   LTDC_BCCR_BCRED_Msk
	Background Red value.
#define	LTDC_IER_LIE_Pos   (0U)
#define	LTDC_IER_LIE_Msk   (0x1UL << LTDC_IER_LIE_Pos)
	0x00000001
#define	LTDC_IER_LIE   LTDC_IER_LIE_Msk
	Line Interrupt Enable.
#define	LTDC_IER_FUIE_Pos   (1U)
#define	LTDC_IER_FUIE_Msk   (0x1UL << LTDC_IER_FUIE_Pos)
	0x00000002
#define	LTDC_IER_FUIE   LTDC_IER_FUIE_Msk
	FIFO Underrun Interrupt Enable.
#define	LTDC_IER_TERRIE_Pos   (2U)
#define	LTDC_IER_TERRIE_Msk   (0x1UL << LTDC_IER_TERRIE_Pos)
	0x00000004
#define	LTDC_IER_TERRIE   LTDC_IER_TERRIE_Msk
	Transfer Error Interrupt Enable.
#define	LTDC_IER_RRIE_Pos   (3U)
#define	LTDC_IER_RRIE_Msk   (0x1UL << LTDC_IER_RRIE_Pos)
	0x00000008
#define	LTDC_IER_RRIE   LTDC_IER_RRIE_Msk
	Register Reload interrupt enable.
#define	LTDC_ISR_LIF_Pos   (0U)
#define	LTDC_ISR_LIF_Msk   (0x1UL << LTDC_ISR_LIF_Pos)
	0x00000001
#define	LTDC_ISR_LIF   LTDC_ISR_LIF_Msk
	Line Interrupt Flag.
#define	LTDC_ISR_FUIF_Pos   (1U)
#define	LTDC_ISR_FUIF_Msk   (0x1UL << LTDC_ISR_FUIF_Pos)
	0x00000002
#define	LTDC_ISR_FUIF   LTDC_ISR_FUIF_Msk
	FIFO Underrun Interrupt Flag.
#define	LTDC_ISR_TERRIF_Pos   (2U)
#define	LTDC_ISR_TERRIF_Msk   (0x1UL << LTDC_ISR_TERRIF_Pos)
	0x00000004
#define	LTDC_ISR_TERRIF   LTDC_ISR_TERRIF_Msk
	Transfer Error Interrupt Flag.
#define	LTDC_ISR_RRIF_Pos   (3U)
#define	LTDC_ISR_RRIF_Msk   (0x1UL << LTDC_ISR_RRIF_Pos)
	0x00000008
#define	LTDC_ISR_RRIF   LTDC_ISR_RRIF_Msk
	Register Reload interrupt Flag.
#define	LTDC_ICR_CLIF_Pos   (0U)
#define	LTDC_ICR_CLIF_Msk   (0x1UL << LTDC_ICR_CLIF_Pos)
	0x00000001
#define	LTDC_ICR_CLIF   LTDC_ICR_CLIF_Msk
	Clears the Line Interrupt Flag.
#define	LTDC_ICR_CFUIF_Pos   (1U)
#define	LTDC_ICR_CFUIF_Msk   (0x1UL << LTDC_ICR_CFUIF_Pos)
	0x00000002
#define	LTDC_ICR_CFUIF   LTDC_ICR_CFUIF_Msk
	Clears the FIFO Underrun Interrupt Flag.
#define	LTDC_ICR_CTERRIF_Pos   (2U)
#define	LTDC_ICR_CTERRIF_Msk   (0x1UL << LTDC_ICR_CTERRIF_Pos)
	0x00000004
#define	LTDC_ICR_CTERRIF   LTDC_ICR_CTERRIF_Msk
	Clears the Transfer Error Interrupt Flag.
#define	LTDC_ICR_CRRIF_Pos   (3U)
#define	LTDC_ICR_CRRIF_Msk   (0x1UL << LTDC_ICR_CRRIF_Pos)
	0x00000008
#define	LTDC_ICR_CRRIF   LTDC_ICR_CRRIF_Msk
	Clears Register Reload interrupt Flag.
#define	LTDC_LIPCR_LIPOS_Pos   (0U)
#define	LTDC_LIPCR_LIPOS_Msk   (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)
	0x000007FF
#define	LTDC_LIPCR_LIPOS   LTDC_LIPCR_LIPOS_Msk
	Line Interrupt Position.
#define	LTDC_CPSR_CYPOS_Pos   (0U)
#define	LTDC_CPSR_CYPOS_Msk   (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)
	0x0000FFFF
#define	LTDC_CPSR_CYPOS   LTDC_CPSR_CYPOS_Msk
	Current Y Position.
#define	LTDC_CPSR_CXPOS_Pos   (16U)
#define	LTDC_CPSR_CXPOS_Msk   (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)
	0xFFFF0000
#define	LTDC_CPSR_CXPOS   LTDC_CPSR_CXPOS_Msk
	Current X Position.
#define	LTDC_CDSR_VDES_Pos   (0U)
#define	LTDC_CDSR_VDES_Msk   (0x1UL << LTDC_CDSR_VDES_Pos)
	0x00000001
#define	LTDC_CDSR_VDES   LTDC_CDSR_VDES_Msk
	Vertical Data Enable Status.
#define	LTDC_CDSR_HDES_Pos   (1U)
#define	LTDC_CDSR_HDES_Msk   (0x1UL << LTDC_CDSR_HDES_Pos)
	0x00000002
#define	LTDC_CDSR_HDES   LTDC_CDSR_HDES_Msk
	Horizontal Data Enable Status.
#define	LTDC_CDSR_VSYNCS_Pos   (2U)
#define	LTDC_CDSR_VSYNCS_Msk   (0x1UL << LTDC_CDSR_VSYNCS_Pos)
	0x00000004
#define	LTDC_CDSR_VSYNCS   LTDC_CDSR_VSYNCS_Msk
	Vertical Synchronization Status.
#define	LTDC_CDSR_HSYNCS_Pos   (3U)
#define	LTDC_CDSR_HSYNCS_Msk   (0x1UL << LTDC_CDSR_HSYNCS_Pos)
	0x00000008
#define	LTDC_CDSR_HSYNCS   LTDC_CDSR_HSYNCS_Msk
	Horizontal Synchronization Status.
#define	LTDC_LxCR_LEN_Pos   (0U)
#define	LTDC_LxCR_LEN_Msk   (0x1UL << LTDC_LxCR_LEN_Pos)
	0x00000001
#define	LTDC_LxCR_LEN   LTDC_LxCR_LEN_Msk
	Layer Enable.
#define	LTDC_LxCR_COLKEN_Pos   (1U)
#define	LTDC_LxCR_COLKEN_Msk   (0x1UL << LTDC_LxCR_COLKEN_Pos)
	0x00000002
#define	LTDC_LxCR_COLKEN   LTDC_LxCR_COLKEN_Msk
	Color Keying Enable.
#define	LTDC_LxCR_CLUTEN_Pos   (4U)
#define	LTDC_LxCR_CLUTEN_Msk   (0x1UL << LTDC_LxCR_CLUTEN_Pos)
	0x00000010
#define	LTDC_LxCR_CLUTEN   LTDC_LxCR_CLUTEN_Msk
	Color Lockup Table Enable.
#define	LTDC_LxWHPCR_WHSTPOS_Pos   (0U)
#define	LTDC_LxWHPCR_WHSTPOS_Msk   (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)
	0x00000FFF
#define	LTDC_LxWHPCR_WHSTPOS   LTDC_LxWHPCR_WHSTPOS_Msk
	Window Horizontal Start Position.
#define	LTDC_LxWHPCR_WHSPPOS_Pos   (16U)
#define	LTDC_LxWHPCR_WHSPPOS_Msk   (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)
	0xFFFF0000
#define	LTDC_LxWHPCR_WHSPPOS   LTDC_LxWHPCR_WHSPPOS_Msk
	Window Horizontal Stop Position.
#define	LTDC_LxWVPCR_WVSTPOS_Pos   (0U)
#define	LTDC_LxWVPCR_WVSTPOS_Msk   (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)
	0x00000FFF
#define	LTDC_LxWVPCR_WVSTPOS   LTDC_LxWVPCR_WVSTPOS_Msk
	Window Vertical Start Position.
#define	LTDC_LxWVPCR_WVSPPOS_Pos   (16U)
#define	LTDC_LxWVPCR_WVSPPOS_Msk   (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)
	0xFFFF0000
#define	LTDC_LxWVPCR_WVSPPOS   LTDC_LxWVPCR_WVSPPOS_Msk
	Window Vertical Stop Position.
#define	LTDC_LxCKCR_CKBLUE_Pos   (0U)
#define	LTDC_LxCKCR_CKBLUE_Msk   (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)
	0x000000FF
#define	LTDC_LxCKCR_CKBLUE   LTDC_LxCKCR_CKBLUE_Msk
	Color Key Blue value.
#define	LTDC_LxCKCR_CKGREEN_Pos   (8U)
#define	LTDC_LxCKCR_CKGREEN_Msk   (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)
	0x0000FF00
#define	LTDC_LxCKCR_CKGREEN   LTDC_LxCKCR_CKGREEN_Msk
	Color Key Green value.
#define	LTDC_LxCKCR_CKRED_Pos   (16U)
#define	LTDC_LxCKCR_CKRED_Msk   (0xFFUL << LTDC_LxCKCR_CKRED_Pos)
	0x00FF0000
#define	LTDC_LxCKCR_CKRED   LTDC_LxCKCR_CKRED_Msk
	Color Key Red value.
#define	LTDC_LxPFCR_PF_Pos   (0U)
#define	LTDC_LxPFCR_PF_Msk   (0x7UL << LTDC_LxPFCR_PF_Pos)
	0x00000007
#define	LTDC_LxPFCR_PF   LTDC_LxPFCR_PF_Msk
	Pixel Format.
#define	LTDC_LxCACR_CONSTA_Pos   (0U)
#define	LTDC_LxCACR_CONSTA_Msk   (0xFFUL << LTDC_LxCACR_CONSTA_Pos)
	0x000000FF
#define	LTDC_LxCACR_CONSTA   LTDC_LxCACR_CONSTA_Msk
	Constant Alpha.
#define	LTDC_LxDCCR_DCBLUE_Pos   (0U)
#define	LTDC_LxDCCR_DCBLUE_Msk   (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)
	0x000000FF
#define	LTDC_LxDCCR_DCBLUE   LTDC_LxDCCR_DCBLUE_Msk
	Default Color Blue.
#define	LTDC_LxDCCR_DCGREEN_Pos   (8U)
#define	LTDC_LxDCCR_DCGREEN_Msk   (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)
	0x0000FF00
#define	LTDC_LxDCCR_DCGREEN   LTDC_LxDCCR_DCGREEN_Msk
	Default Color Green.
#define	LTDC_LxDCCR_DCRED_Pos   (16U)
#define	LTDC_LxDCCR_DCRED_Msk   (0xFFUL << LTDC_LxDCCR_DCRED_Pos)
	0x00FF0000
#define	LTDC_LxDCCR_DCRED   LTDC_LxDCCR_DCRED_Msk
	Default Color Red.
#define	LTDC_LxDCCR_DCALPHA_Pos   (24U)
#define	LTDC_LxDCCR_DCALPHA_Msk   (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)
	0xFF000000
#define	LTDC_LxDCCR_DCALPHA   LTDC_LxDCCR_DCALPHA_Msk
	Default Color Alpha.
#define	LTDC_LxBFCR_BF2_Pos   (0U)
#define	LTDC_LxBFCR_BF2_Msk   (0x7UL << LTDC_LxBFCR_BF2_Pos)
	0x00000007
#define	LTDC_LxBFCR_BF2   LTDC_LxBFCR_BF2_Msk
	Blending Factor 2.
#define	LTDC_LxBFCR_BF1_Pos   (8U)
#define	LTDC_LxBFCR_BF1_Msk   (0x7UL << LTDC_LxBFCR_BF1_Pos)
	0x00000700
#define	LTDC_LxBFCR_BF1   LTDC_LxBFCR_BF1_Msk
	Blending Factor 1.
#define	LTDC_LxCFBAR_CFBADD_Pos   (0U)
#define	LTDC_LxCFBAR_CFBADD_Msk   (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos)
	0xFFFFFFFF
#define	LTDC_LxCFBAR_CFBADD   LTDC_LxCFBAR_CFBADD_Msk
	Color Frame Buffer Start Address.
#define	LTDC_LxCFBLR_CFBLL_Pos   (0U)
#define	LTDC_LxCFBLR_CFBLL_Msk   (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)
	0x00001FFF
#define	LTDC_LxCFBLR_CFBLL   LTDC_LxCFBLR_CFBLL_Msk
	Color Frame Buffer Line Length.
#define	LTDC_LxCFBLR_CFBP_Pos   (16U)
#define	LTDC_LxCFBLR_CFBP_Msk   (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)
	0x1FFF0000
#define	LTDC_LxCFBLR_CFBP   LTDC_LxCFBLR_CFBP_Msk
	Color Frame Buffer Pitch in bytes.
#define	LTDC_LxCFBLNR_CFBLNBR_Pos   (0U)
#define	LTDC_LxCFBLNR_CFBLNBR_Msk   (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)
	0x000007FF
#define	LTDC_LxCFBLNR_CFBLNBR   LTDC_LxCFBLNR_CFBLNBR_Msk
	Frame Buffer Line Number.
#define	LTDC_LxCLUTWR_BLUE_Pos   (0U)
#define	LTDC_LxCLUTWR_BLUE_Msk   (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)
	0x000000FF
#define	LTDC_LxCLUTWR_BLUE   LTDC_LxCLUTWR_BLUE_Msk
	Blue value.
#define	LTDC_LxCLUTWR_GREEN_Pos   (8U)
#define	LTDC_LxCLUTWR_GREEN_Msk   (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)
	0x0000FF00
#define	LTDC_LxCLUTWR_GREEN   LTDC_LxCLUTWR_GREEN_Msk
	Green value.
#define	LTDC_LxCLUTWR_RED_Pos   (16U)
#define	LTDC_LxCLUTWR_RED_Msk   (0xFFUL << LTDC_LxCLUTWR_RED_Pos)
	0x00FF0000
#define	LTDC_LxCLUTWR_RED   LTDC_LxCLUTWR_RED_Msk
	Red value.
#define	LTDC_LxCLUTWR_CLUTADD_Pos   (24U)
#define	LTDC_LxCLUTWR_CLUTADD_Msk   (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)
	0xFF000000
#define	LTDC_LxCLUTWR_CLUTADD   LTDC_LxCLUTWR_CLUTADD_Msk
	CLUT address.
#define	MDMA_GISR0_GIF0_Pos   (0U)
#define	MDMA_GISR0_GIF0_Msk   (0x1UL << MDMA_GISR0_GIF0_Pos)
	0x00000001
#define	MDMA_GISR0_GIF0   MDMA_GISR0_GIF0_Msk
	Channel 0 global interrupt flag.
#define	MDMA_GISR0_GIF1_Pos   (1U)
#define	MDMA_GISR0_GIF1_Msk   (0x1UL << MDMA_GISR0_GIF1_Pos)
	0x00000002
#define	MDMA_GISR0_GIF1   MDMA_GISR0_GIF1_Msk
	Channel 1 global interrupt flag.
#define	MDMA_GISR0_GIF2_Pos   (2U)
#define	MDMA_GISR0_GIF2_Msk   (0x1UL << MDMA_GISR0_GIF2_Pos)
	0x00000004
#define	MDMA_GISR0_GIF2   MDMA_GISR0_GIF2_Msk
	Channel 2 global interrupt flag.
#define	MDMA_GISR0_GIF3_Pos   (3U)
#define	MDMA_GISR0_GIF3_Msk   (0x1UL << MDMA_GISR0_GIF3_Pos)
	0x00000008
#define	MDMA_GISR0_GIF3   MDMA_GISR0_GIF3_Msk
	Channel 3 global interrupt flag.
#define	MDMA_GISR0_GIF4_Pos   (4U)
#define	MDMA_GISR0_GIF4_Msk   (0x1UL << MDMA_GISR0_GIF4_Pos)
	0x00000010
#define	MDMA_GISR0_GIF4   MDMA_GISR0_GIF4_Msk
	Channel 4 global interrupt flag.
#define	MDMA_GISR0_GIF5_Pos   (5U)
#define	MDMA_GISR0_GIF5_Msk   (0x1UL << MDMA_GISR0_GIF5_Pos)
	0x00000020
#define	MDMA_GISR0_GIF5   MDMA_GISR0_GIF5_Msk
	Channel 5 global interrupt flag.
#define	MDMA_GISR0_GIF6_Pos   (6U)
#define	MDMA_GISR0_GIF6_Msk   (0x1UL << MDMA_GISR0_GIF6_Pos)
	0x00000040
#define	MDMA_GISR0_GIF6   MDMA_GISR0_GIF6_Msk
	Channel 6 global interrupt flag.
#define	MDMA_GISR0_GIF7_Pos   (7U)
#define	MDMA_GISR0_GIF7_Msk   (0x1UL << MDMA_GISR0_GIF7_Pos)
	0x00000080
#define	MDMA_GISR0_GIF7   MDMA_GISR0_GIF7_Msk
	Channel 7 global interrupt flag.
#define	MDMA_GISR0_GIF8_Pos   (8U)
#define	MDMA_GISR0_GIF8_Msk   (0x1UL << MDMA_GISR0_GIF8_Pos)
	0x00000100
#define	MDMA_GISR0_GIF8   MDMA_GISR0_GIF8_Msk
	Channel 8 global interrupt flag.
#define	MDMA_GISR0_GIF9_Pos   (9U)
#define	MDMA_GISR0_GIF9_Msk   (0x1UL << MDMA_GISR0_GIF9_Pos)
	0x00000200
#define	MDMA_GISR0_GIF9   MDMA_GISR0_GIF9_Msk
	Channel 9 global interrupt flag.
#define	MDMA_GISR0_GIF10_Pos   (10U)
#define	MDMA_GISR0_GIF10_Msk   (0x1UL << MDMA_GISR0_GIF10_Pos)
	0x00000400
#define	MDMA_GISR0_GIF10   MDMA_GISR0_GIF10_Msk
	Channel 10 global interrupt flag.
#define	MDMA_GISR0_GIF11_Pos   (11U)
#define	MDMA_GISR0_GIF11_Msk   (0x1UL << MDMA_GISR0_GIF11_Pos)
	0x00000800
#define	MDMA_GISR0_GIF11   MDMA_GISR0_GIF11_Msk
	Channel 11 global interrupt flag.
#define	MDMA_GISR0_GIF12_Pos   (12U)
#define	MDMA_GISR0_GIF12_Msk   (0x1UL << MDMA_GISR0_GIF12_Pos)
	0x00001000
#define	MDMA_GISR0_GIF12   MDMA_GISR0_GIF12_Msk
	Channel 12 global interrupt flag.
#define	MDMA_GISR0_GIF13_Pos   (13U)
#define	MDMA_GISR0_GIF13_Msk   (0x1UL << MDMA_GISR0_GIF13_Pos)
	0x00002000
#define	MDMA_GISR0_GIF13   MDMA_GISR0_GIF13_Msk
	Channel 13 global interrupt flag.
#define	MDMA_GISR0_GIF14_Pos   (14U)
#define	MDMA_GISR0_GIF14_Msk   (0x1UL << MDMA_GISR0_GIF14_Pos)
	0x00004000
#define	MDMA_GISR0_GIF14   MDMA_GISR0_GIF14_Msk
	Channel 14 global interrupt flag.
#define	MDMA_GISR0_GIF15_Pos   (15U)
#define	MDMA_GISR0_GIF15_Msk   (0x1UL << MDMA_GISR0_GIF15_Pos)
	0x00008000
#define	MDMA_GISR0_GIF15   MDMA_GISR0_GIF15_Msk
	Channel 15 global interrupt flag.
#define	MDMA_CISR_TEIF_Pos   (0U)
#define	MDMA_CISR_TEIF_Msk   (0x1UL << MDMA_CISR_TEIF_Pos)
	0x00000001
#define	MDMA_CISR_TEIF   MDMA_CISR_TEIF_Msk
	Channel x transfer error interrupt flag.
#define	MDMA_CISR_CTCIF_Pos   (1U)
#define	MDMA_CISR_CTCIF_Msk   (0x1UL << MDMA_CISR_CTCIF_Pos)
	0x00000002
#define	MDMA_CISR_CTCIF   MDMA_CISR_CTCIF_Msk
	Channel x Channel Transfer Complete interrupt flag.
#define	MDMA_CISR_BRTIF_Pos   (2U)
#define	MDMA_CISR_BRTIF_Msk   (0x1UL << MDMA_CISR_BRTIF_Pos)
	0x00000004
#define	MDMA_CISR_BRTIF   MDMA_CISR_BRTIF_Msk
	Channel x block repeat transfer complete interrupt flag.
#define	MDMA_CISR_BTIF_Pos   (3U)
#define	MDMA_CISR_BTIF_Msk   (0x1UL << MDMA_CISR_BTIF_Pos)
	0x00000008
#define	MDMA_CISR_BTIF   MDMA_CISR_BTIF_Msk
	Channel x block transfer complete interrupt flag.
#define	MDMA_CISR_TCIF_Pos   (4U)
#define	MDMA_CISR_TCIF_Msk   (0x1UL << MDMA_CISR_TCIF_Pos)
	0x00000010
#define	MDMA_CISR_TCIF   MDMA_CISR_TCIF_Msk
	Channel x buffer transfer complete interrupt flag.
#define	MDMA_CISR_CRQA_Pos   (16U)
#define	MDMA_CISR_CRQA_Msk   (0x1UL << MDMA_CISR_CRQA_Pos)
	0x00010000
#define	MDMA_CISR_CRQA   MDMA_CISR_CRQA_Msk
	Channel x request Active flag.
#define	MDMA_CIFCR_CTEIF_Pos   (0U)
#define	MDMA_CIFCR_CTEIF_Msk   (0x1UL << MDMA_CIFCR_CTEIF_Pos)
	0x00000001
#define	MDMA_CIFCR_CTEIF   MDMA_CIFCR_CTEIF_Msk
	Channel x clear transfer error interrupt flag.
#define	MDMA_CIFCR_CCTCIF_Pos   (1U)
#define	MDMA_CIFCR_CCTCIF_Msk   (0x1UL << MDMA_CIFCR_CCTCIF_Pos)
	0x00000002
#define	MDMA_CIFCR_CCTCIF   MDMA_CIFCR_CCTCIF_Msk
	Clear Channel transfer complete interrupt flag for channel x.
#define	MDMA_CIFCR_CBRTIF_Pos   (2U)
#define	MDMA_CIFCR_CBRTIF_Msk   (0x1UL << MDMA_CIFCR_CBRTIF_Pos)
	0x00000004
#define	MDMA_CIFCR_CBRTIF   MDMA_CIFCR_CBRTIF_Msk
	Channel x clear block repeat transfer complete interrupt flag.
#define	MDMA_CIFCR_CBTIF_Pos   (3U)
#define	MDMA_CIFCR_CBTIF_Msk   (0x1UL << MDMA_CIFCR_CBTIF_Pos)
	0x00000008
#define	MDMA_CIFCR_CBTIF   MDMA_CIFCR_CBTIF_Msk
	Channel x Clear block transfer complete interrupt flag.
#define	MDMA_CIFCR_CLTCIF_Pos   (4U)
#define	MDMA_CIFCR_CLTCIF_Msk   (0x1UL << MDMA_CIFCR_CLTCIF_Pos)
	0x00000010
#define	MDMA_CIFCR_CLTCIF   MDMA_CIFCR_CLTCIF_Msk
	CLear Transfer buffer Complete Interrupt Flag for channel.
#define	MDMA_CESR_TEA_Pos   (0U)
#define	MDMA_CESR_TEA_Msk   (0x7FUL << MDMA_CESR_TEA_Pos)
	0x0000007F
#define	MDMA_CESR_TEA   MDMA_CESR_TEA_Msk
	Transfer Error Address.
#define	MDMA_CESR_TED_Pos   (7U)
#define	MDMA_CESR_TED_Msk   (0x1UL << MDMA_CESR_TED_Pos)
	0x00000080
#define	MDMA_CESR_TED   MDMA_CESR_TED_Msk
	Transfer Error Direction.
#define	MDMA_CESR_TELD_Pos   (8U)
#define	MDMA_CESR_TELD_Msk   (0x1UL << MDMA_CESR_TELD_Pos)
	0x00000100
#define	MDMA_CESR_TELD   MDMA_CESR_TELD_Msk
	Transfer Error Link Data.
#define	MDMA_CESR_TEMD_Pos   (9U)
#define	MDMA_CESR_TEMD_Msk   (0x1UL << MDMA_CESR_TEMD_Pos)
	0x00000200
#define	MDMA_CESR_TEMD   MDMA_CESR_TEMD_Msk
	Transfer Error Mask Data.
#define	MDMA_CESR_ASE_Pos   (10U)
#define	MDMA_CESR_ASE_Msk   (0x1UL << MDMA_CESR_ASE_Pos)
	0x00000400
#define	MDMA_CESR_ASE   MDMA_CESR_ASE_Msk
	Address/Size Error.
#define	MDMA_CESR_BSE_Pos   (11U)
#define	MDMA_CESR_BSE_Msk   (0x1UL << MDMA_CESR_BSE_Pos)
	0x00000800
#define	MDMA_CESR_BSE   MDMA_CESR_BSE_Msk
	Block Size Error.
#define	MDMA_CCR_EN_Pos   (0U)
#define	MDMA_CCR_EN_Msk   (0x1UL << MDMA_CCR_EN_Pos)
	0x00000001
#define	MDMA_CCR_EN   MDMA_CCR_EN_Msk
	Channel enable / flag channel ready when read low.
#define	MDMA_CCR_TEIE_Pos   (1U)
#define	MDMA_CCR_TEIE_Msk   (0x1UL << MDMA_CCR_TEIE_Pos)
	0x00000002
#define	MDMA_CCR_TEIE   MDMA_CCR_TEIE_Msk
	Transfer error interrupt enable.
#define	MDMA_CCR_CTCIE_Pos   (2U)
#define	MDMA_CCR_CTCIE_Msk   (0x1UL << MDMA_CCR_CTCIE_Pos)
	0x00000004
#define	MDMA_CCR_CTCIE   MDMA_CCR_CTCIE_Msk
	Channel Transfer Complete interrupt enable.
#define	MDMA_CCR_BRTIE_Pos   (3U)
#define	MDMA_CCR_BRTIE_Msk   (0x1UL << MDMA_CCR_BRTIE_Pos)
	0x00000008
#define	MDMA_CCR_BRTIE   MDMA_CCR_BRTIE_Msk
	Block Repeat transfer interrupt enable.
#define	MDMA_CCR_BTIE_Pos   (4U)
#define	MDMA_CCR_BTIE_Msk   (0x1UL << MDMA_CCR_BTIE_Pos)
	0x00000010
#define	MDMA_CCR_BTIE   MDMA_CCR_BTIE_Msk
	Block Transfer interrupt enable.
#define	MDMA_CCR_TCIE_Pos   (5U)
#define	MDMA_CCR_TCIE_Msk   (0x1UL << MDMA_CCR_TCIE_Pos)
	0x00000020
#define	MDMA_CCR_TCIE   MDMA_CCR_TCIE_Msk
	buffer Transfer Complete interrupt enable
#define	MDMA_CCR_PL_Pos   (6U)
#define	MDMA_CCR_PL_Msk   (0x3UL << MDMA_CCR_PL_Pos)
	0x000000C0
#define	MDMA_CCR_PL   MDMA_CCR_PL_Msk
	Priority level.
#define	MDMA_CCR_PL_0   (0x1UL << MDMA_CCR_PL_Pos)
	0x00000040
#define	MDMA_CCR_PL_1   (0x2UL << MDMA_CCR_PL_Pos)
	0x00000080
#define	MDMA_CCR_BEX_Pos   (12U)
#define	MDMA_CCR_BEX_Msk   (0x1UL << MDMA_CCR_BEX_Pos)
	0x00001000
#define	MDMA_CCR_BEX   MDMA_CCR_BEX_Msk
	Byte Endianness eXchange.
#define	MDMA_CCR_HEX_Pos   (13U)
#define	MDMA_CCR_HEX_Msk   (0x1UL << MDMA_CCR_HEX_Pos)
	0x00002000
#define	MDMA_CCR_HEX   MDMA_CCR_HEX_Msk
	Half word Endianness eXchange.
#define	MDMA_CCR_WEX_Pos   (14U)
#define	MDMA_CCR_WEX_Msk   (0x1UL << MDMA_CCR_WEX_Pos)
	0x00004000
#define	MDMA_CCR_WEX   MDMA_CCR_WEX_Msk
	Word Endianness eXchange.
#define	MDMA_CCR_SWRQ_Pos   (16U)
#define	MDMA_CCR_SWRQ_Msk   (0x1UL << MDMA_CCR_SWRQ_Pos)
	0x00010000
#define	MDMA_CCR_SWRQ   MDMA_CCR_SWRQ_Msk
	SW ReQuest.
#define	MDMA_CTCR_SINC_Pos   (0U)
#define	MDMA_CTCR_SINC_Msk   (0x3UL << MDMA_CTCR_SINC_Pos)
	0x00000003
#define	MDMA_CTCR_SINC   MDMA_CTCR_SINC_Msk
	Source increment mode.
#define	MDMA_CTCR_SINC_0   (0x1UL << MDMA_CTCR_SINC_Pos)
	0x00000001
#define	MDMA_CTCR_SINC_1   (0x2UL << MDMA_CTCR_SINC_Pos)
	0x00000002
#define	MDMA_CTCR_DINC_Pos   (2U)
#define	MDMA_CTCR_DINC_Msk   (0x3UL << MDMA_CTCR_DINC_Pos)
	0x0000000C
#define	MDMA_CTCR_DINC   MDMA_CTCR_DINC_Msk
	Source increment mode.
#define	MDMA_CTCR_DINC_0   (0x1UL << MDMA_CTCR_DINC_Pos)
	0x00000004
#define	MDMA_CTCR_DINC_1   (0x2UL << MDMA_CTCR_DINC_Pos)
	0x00000008
#define	MDMA_CTCR_SSIZE_Pos   (4U)
#define	MDMA_CTCR_SSIZE_Msk   (0x3UL << MDMA_CTCR_SSIZE_Pos)
	0x00000030
#define	MDMA_CTCR_SSIZE   MDMA_CTCR_SSIZE_Msk
	Source data size.
#define	MDMA_CTCR_SSIZE_0   (0x1UL << MDMA_CTCR_SSIZE_Pos)
	0x00000010
#define	MDMA_CTCR_SSIZE_1   (0x2UL << MDMA_CTCR_SSIZE_Pos)
	0x00000020
#define	MDMA_CTCR_DSIZE_Pos   (6U)
#define	MDMA_CTCR_DSIZE_Msk   (0x3UL << MDMA_CTCR_DSIZE_Pos)
	0x000000C0
#define	MDMA_CTCR_DSIZE   MDMA_CTCR_DSIZE_Msk
	Destination data size.
#define	MDMA_CTCR_DSIZE_0   (0x1UL << MDMA_CTCR_DSIZE_Pos)
	0x00000040
#define	MDMA_CTCR_DSIZE_1   (0x2UL << MDMA_CTCR_DSIZE_Pos)
	0x00000080
#define	MDMA_CTCR_SINCOS_Pos   (8U)
#define	MDMA_CTCR_SINCOS_Msk   (0x3UL << MDMA_CTCR_SINCOS_Pos)
	0x00000300
#define	MDMA_CTCR_SINCOS   MDMA_CTCR_SINCOS_Msk
	Source increment offset size.
#define	MDMA_CTCR_SINCOS_0   (0x1UL << MDMA_CTCR_SINCOS_Pos)
	0x00000100
#define	MDMA_CTCR_SINCOS_1   (0x2UL << MDMA_CTCR_SINCOS_Pos)
	0x00000200
#define	MDMA_CTCR_DINCOS_Pos   (10U)
#define	MDMA_CTCR_DINCOS_Msk   (0x3UL << MDMA_CTCR_DINCOS_Pos)
	0x00000C00
#define	MDMA_CTCR_DINCOS   MDMA_CTCR_DINCOS_Msk
	Destination increment offset size.
#define	MDMA_CTCR_DINCOS_0   (0x1UL << MDMA_CTCR_DINCOS_Pos)
	0x00000400
#define	MDMA_CTCR_DINCOS_1   (0x2UL << MDMA_CTCR_DINCOS_Pos)
	0x00000800
#define	MDMA_CTCR_SBURST_Pos   (12U)
#define	MDMA_CTCR_SBURST_Msk   (0x7UL << MDMA_CTCR_SBURST_Pos)
	0x00007000
#define	MDMA_CTCR_SBURST   MDMA_CTCR_SBURST_Msk
	Source burst transfer configuration.
#define	MDMA_CTCR_SBURST_0   (0x1UL << MDMA_CTCR_SBURST_Pos)
	0x00001000
#define	MDMA_CTCR_SBURST_1   (0x2UL << MDMA_CTCR_SBURST_Pos)
	0x00002000
#define	MDMA_CTCR_SBURST_2   (0x4UL << MDMA_CTCR_SBURST_Pos)
	0x00004000
#define	MDMA_CTCR_DBURST_Pos   (15U)
#define	MDMA_CTCR_DBURST_Msk   (0x7UL << MDMA_CTCR_DBURST_Pos)
	0x00038000
#define	MDMA_CTCR_DBURST   MDMA_CTCR_DBURST_Msk
	Destination burst transfer configuration.
#define	MDMA_CTCR_DBURST_0   (0x1UL << MDMA_CTCR_DBURST_Pos)
	0x00008000
#define	MDMA_CTCR_DBURST_1   (0x2UL << MDMA_CTCR_DBURST_Pos)
	0x00010000
#define	MDMA_CTCR_DBURST_2   (0x4UL << MDMA_CTCR_DBURST_Pos)
	0x00020000
#define	MDMA_CTCR_TLEN_Pos   (18U)
#define	MDMA_CTCR_TLEN_Msk   (0x7FUL << MDMA_CTCR_TLEN_Pos)
	0x01FC0000
#define	MDMA_CTCR_TLEN   MDMA_CTCR_TLEN_Msk
	buffer Transfer Length (number of bytes - 1)
#define	MDMA_CTCR_PKE_Pos   (25U)
#define	MDMA_CTCR_PKE_Msk   (0x1UL << MDMA_CTCR_PKE_Pos)
	0x02000000
#define	MDMA_CTCR_PKE   MDMA_CTCR_PKE_Msk
	PacK Enable.
#define	MDMA_CTCR_PAM_Pos   (26U)
#define	MDMA_CTCR_PAM_Msk   (0x3UL << MDMA_CTCR_PAM_Pos)
	0x0C000000
#define	MDMA_CTCR_PAM   MDMA_CTCR_PAM_Msk
	Padding/Alignment Mode.
#define	MDMA_CTCR_PAM_0   (0x1UL << MDMA_CTCR_PAM_Pos)
	0x4000000
#define	MDMA_CTCR_PAM_1   (0x2UL << MDMA_CTCR_PAM_Pos)
	0x8000000
#define	MDMA_CTCR_TRGM_Pos   (28U)
#define	MDMA_CTCR_TRGM_Msk   (0x3UL << MDMA_CTCR_TRGM_Pos)
	0x30000000
#define	MDMA_CTCR_TRGM   MDMA_CTCR_TRGM_Msk
	Trigger Mode.
#define	MDMA_CTCR_TRGM_0   (0x1UL << MDMA_CTCR_TRGM_Pos)
	0x10000000
#define	MDMA_CTCR_TRGM_1   (0x2UL << MDMA_CTCR_TRGM_Pos)
	0x20000000
#define	MDMA_CTCR_SWRM_Pos   (30U)
#define	MDMA_CTCR_SWRM_Msk   (0x1UL << MDMA_CTCR_SWRM_Pos)
	0x40000000
#define	MDMA_CTCR_SWRM   MDMA_CTCR_SWRM_Msk
	SW Request Mode.
#define	MDMA_CTCR_BWM_Pos   (31U)
#define	MDMA_CTCR_BWM_Msk   (0x1UL << MDMA_CTCR_BWM_Pos)
	0x80000000
#define	MDMA_CTCR_BWM   MDMA_CTCR_BWM_Msk
	Bufferable Write Mode.
#define	MDMA_CBNDTR_BNDT_Pos   (0U)
#define	MDMA_CBNDTR_BNDT_Msk   (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)
	0x0001FFFF
#define	MDMA_CBNDTR_BNDT   MDMA_CBNDTR_BNDT_Msk
	Block Number of data bytes to transfer.
#define	MDMA_CBNDTR_BRSUM_Pos   (18U)
#define	MDMA_CBNDTR_BRSUM_Msk   (0x1UL << MDMA_CBNDTR_BRSUM_Pos)
	0x00040000
#define	MDMA_CBNDTR_BRSUM   MDMA_CBNDTR_BRSUM_Msk
	Block Repeat Source address Update Mode.
#define	MDMA_CBNDTR_BRDUM_Pos   (19U)
#define	MDMA_CBNDTR_BRDUM_Msk   (0x1UL << MDMA_CBNDTR_BRDUM_Pos)
	0x00080000
#define	MDMA_CBNDTR_BRDUM   MDMA_CBNDTR_BRDUM_Msk
	Block Repeat Destination address Update Mode.
#define	MDMA_CBNDTR_BRC_Pos   (20U)
#define	MDMA_CBNDTR_BRC_Msk   (0xFFFUL << MDMA_CBNDTR_BRC_Pos)
	0xFFF00000
#define	MDMA_CBNDTR_BRC   MDMA_CBNDTR_BRC_Msk
	Block Repeat Count.
#define	MDMA_CSAR_SAR_Pos   (0U)
#define	MDMA_CSAR_SAR_Msk   (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)
	0xFFFFFFFF
#define	MDMA_CSAR_SAR   MDMA_CSAR_SAR_Msk
	Source address.
#define	MDMA_CDAR_DAR_Pos   (0U)
#define	MDMA_CDAR_DAR_Msk   (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)
	0xFFFFFFFF
#define	MDMA_CDAR_DAR   MDMA_CDAR_DAR_Msk
	Destination address.
#define	MDMA_CBRUR_SUV_Pos   (0U)
#define	MDMA_CBRUR_SUV_Msk   (0xFFFFUL << MDMA_CBRUR_SUV_Pos)
	0x0000FFFF
#define	MDMA_CBRUR_SUV   MDMA_CBRUR_SUV_Msk
	Source address Update Value.
#define	MDMA_CBRUR_DUV_Pos   (16U)
#define	MDMA_CBRUR_DUV_Msk   (0xFFFFUL << MDMA_CBRUR_DUV_Pos)
	0xFFFF0000
#define	MDMA_CBRUR_DUV   MDMA_CBRUR_DUV_Msk
	Destination address Update Value.
#define	MDMA_CLAR_LAR_Pos   (0U)
#define	MDMA_CLAR_LAR_Msk   (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)
	0xFFFFFFFF
#define	MDMA_CLAR_LAR   MDMA_CLAR_LAR_Msk
	Link Address Register.
#define	MDMA_CTBR_TSEL_Pos   (0U)
#define	MDMA_CTBR_TSEL_Msk   (0xFFUL << MDMA_CTBR_TSEL_Pos)
	0x000000FF
#define	MDMA_CTBR_TSEL   MDMA_CTBR_TSEL_Msk
	Trigger SELection.
#define	MDMA_CTBR_SBUS_Pos   (16U)
#define	MDMA_CTBR_SBUS_Msk   (0x1UL << MDMA_CTBR_SBUS_Pos)
	0x00010000
#define	MDMA_CTBR_SBUS   MDMA_CTBR_SBUS_Msk
	Source BUS select.
#define	MDMA_CTBR_DBUS_Pos   (17U)
#define	MDMA_CTBR_DBUS_Msk   (0x1UL << MDMA_CTBR_DBUS_Pos)
	0x00020000
#define	MDMA_CTBR_DBUS   MDMA_CTBR_DBUS_Msk
	Destination BUS select.
#define	MDMA_CMAR_MAR_Pos   (0U)
#define	MDMA_CMAR_MAR_Msk   (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)
	0xFFFFFFFF
#define	MDMA_CMAR_MAR   MDMA_CMAR_MAR_Msk
	Mask address.
#define	MDMA_CMDR_MDR_Pos   (0U)
#define	MDMA_CMDR_MDR_Msk   (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)
	0xFFFFFFFF
#define	MDMA_CMDR_MDR   MDMA_CMDR_MDR_Msk
	Mask Data.
#define	OPAMP_CSR_OPAMPxEN_Pos   (0U)
#define	OPAMP_CSR_OPAMPxEN_Msk   (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)
	0x00000001
#define	OPAMP_CSR_OPAMPxEN   OPAMP_CSR_OPAMPxEN_Msk
	OPAMP enable.
#define	OPAMP_CSR_FORCEVP_Pos   (1U)
#define	OPAMP_CSR_FORCEVP_Msk   (0x1UL << OPAMP_CSR_FORCEVP_Pos)
	0x00000002
#define	OPAMP_CSR_FORCEVP   OPAMP_CSR_FORCEVP_Msk
	Force internal reference on VP.
#define	OPAMP_CSR_VPSEL_Pos   (2U)
#define	OPAMP_CSR_VPSEL_Msk   (0x3UL << OPAMP_CSR_VPSEL_Pos)
	0x0000000C
#define	OPAMP_CSR_VPSEL   OPAMP_CSR_VPSEL_Msk
	Non inverted input selection.
#define	OPAMP_CSR_VPSEL_0   (0x1UL << OPAMP_CSR_VPSEL_Pos)
	0x00000004
#define	OPAMP_CSR_VPSEL_1   (0x2UL << OPAMP_CSR_VPSEL_Pos)
	0x00000008
#define	OPAMP_CSR_VMSEL_Pos   (5U)
#define	OPAMP_CSR_VMSEL_Msk   (0x3UL << OPAMP_CSR_VMSEL_Pos)
	0x00000060
#define	OPAMP_CSR_VMSEL   OPAMP_CSR_VMSEL_Msk
	Inverting input selection.
#define	OPAMP_CSR_VMSEL_0   (0x1UL << OPAMP_CSR_VMSEL_Pos)
	0x00000020
#define	OPAMP_CSR_VMSEL_1   (0x2UL << OPAMP_CSR_VMSEL_Pos)
	0x00000040
#define	OPAMP_CSR_OPAHSM_Pos   (8U)
#define	OPAMP_CSR_OPAHSM_Msk   (0x1UL << OPAMP_CSR_OPAHSM_Pos)
	0x00000100
#define	OPAMP_CSR_OPAHSM   OPAMP_CSR_OPAHSM_Msk
	Operational amplifier high speed mode.
#define	OPAMP_CSR_CALON_Pos   (11U)
#define	OPAMP_CSR_CALON_Msk   (0x1UL << OPAMP_CSR_CALON_Pos)
	0x00000800
#define	OPAMP_CSR_CALON   OPAMP_CSR_CALON_Msk
	Calibration mode enable.
#define	OPAMP_CSR_CALSEL_Pos   (12U)
#define	OPAMP_CSR_CALSEL_Msk   (0x3UL << OPAMP_CSR_CALSEL_Pos)
	0x00003000
#define	OPAMP_CSR_CALSEL   OPAMP_CSR_CALSEL_Msk
	Calibration selection.
#define	OPAMP_CSR_CALSEL_0   (0x1UL << OPAMP_CSR_CALSEL_Pos)
	0x00001000
#define	OPAMP_CSR_CALSEL_1   (0x2UL << OPAMP_CSR_CALSEL_Pos)
	0x00002000
#define	OPAMP_CSR_PGGAIN_Pos   (14U)
#define	OPAMP_CSR_PGGAIN_Msk   (0xFUL << OPAMP_CSR_PGGAIN_Pos)
	0x0003C000
#define	OPAMP_CSR_PGGAIN   OPAMP_CSR_PGGAIN_Msk
	Operational amplifier Programmable amplifier gain value.
#define	OPAMP_CSR_PGGAIN_0   (0x1UL << OPAMP_CSR_PGGAIN_Pos)
	0x00004000
#define	OPAMP_CSR_PGGAIN_1   (0x2UL << OPAMP_CSR_PGGAIN_Pos)
	0x00008000
#define	OPAMP_CSR_PGGAIN_2   (0x4UL << OPAMP_CSR_PGGAIN_Pos)
	0x00010000
#define	OPAMP_CSR_PGGAIN_3   (0x8UL << OPAMP_CSR_PGGAIN_Pos)
	0x00020000
#define	OPAMP_CSR_USERTRIM_Pos   (18U)
#define	OPAMP_CSR_USERTRIM_Msk   (0x1UL << OPAMP_CSR_USERTRIM_Pos)
	0x00040000
#define	OPAMP_CSR_USERTRIM   OPAMP_CSR_USERTRIM_Msk
	User trimming enable.
#define	OPAMP_CSR_TSTREF_Pos   (29U)
#define	OPAMP_CSR_TSTREF_Msk   (0x1UL << OPAMP_CSR_TSTREF_Pos)
	0x20000000
#define	OPAMP_CSR_TSTREF   OPAMP_CSR_TSTREF_Msk
	OpAmp calibration reference voltage output control.
#define	OPAMP_CSR_CALOUT_Pos   (30U)
#define	OPAMP_CSR_CALOUT_Msk   (0x1UL << OPAMP_CSR_CALOUT_Pos)
	0x40000000
#define	OPAMP_CSR_CALOUT   OPAMP_CSR_CALOUT_Msk
	Operational amplifier calibration output.
#define	OPAMP1_CSR_OPAEN_Pos   (0U)
#define	OPAMP1_CSR_OPAEN_Msk   (0x1UL << OPAMP1_CSR_OPAEN_Pos)
	0x00000001
#define	OPAMP1_CSR_OPAEN   OPAMP1_CSR_OPAEN_Msk
	Operational amplifier1 Enable.
#define	OPAMP1_CSR_FORCEVP_Pos   (1U)
#define	OPAMP1_CSR_FORCEVP_Msk   (0x1UL << OPAMP1_CSR_FORCEVP_Pos)
	0x00000002
#define	OPAMP1_CSR_FORCEVP   OPAMP1_CSR_FORCEVP_Msk
	Force internal reference on VP.
#define	OPAMP1_CSR_VPSEL_Pos   (2U)
#define	OPAMP1_CSR_VPSEL_Msk   (0x3UL << OPAMP1_CSR_VPSEL_Pos)
	0x0000000C
#define	OPAMP1_CSR_VPSEL   OPAMP1_CSR_VPSEL_Msk
	Non inverted input selection.
#define	OPAMP1_CSR_VPSEL_0   (0x1UL << OPAMP1_CSR_VPSEL_Pos)
	0x00000004
#define	OPAMP1_CSR_VPSEL_1   (0x2UL << OPAMP1_CSR_VPSEL_Pos)
	0x00000008
#define	OPAMP1_CSR_VMSEL_Pos   (5U)
#define	OPAMP1_CSR_VMSEL_Msk   (0x3UL << OPAMP1_CSR_VMSEL_Pos)
	0x00000060
#define	OPAMP1_CSR_VMSEL   OPAMP1_CSR_VMSEL_Msk
	Inverting input selection.
#define	OPAMP1_CSR_VMSEL_0   (0x1UL << OPAMP1_CSR_VMSEL_Pos)
	0x00000020
#define	OPAMP1_CSR_VMSEL_1   (0x2UL << OPAMP1_CSR_VMSEL_Pos)
	0x00000040
#define	OPAMP1_CSR_OPAHSM_Pos   (8U)
#define	OPAMP1_CSR_OPAHSM_Msk   (0x1UL << OPAMP1_CSR_OPAHSM_Pos)
	0x00000100
#define	OPAMP1_CSR_OPAHSM   OPAMP1_CSR_OPAHSM_Msk
	Operational amplifier1 high speed mode.
#define	OPAMP1_CSR_CALON_Pos   (11U)
#define	OPAMP1_CSR_CALON_Msk   (0x1UL << OPAMP1_CSR_CALON_Pos)
	0x00000800
#define	OPAMP1_CSR_CALON   OPAMP1_CSR_CALON_Msk
	Calibration mode enable.
#define	OPAMP1_CSR_CALSEL_Pos   (12U)
#define	OPAMP1_CSR_CALSEL_Msk   (0x3UL << OPAMP1_CSR_CALSEL_Pos)
	0x00003000
#define	OPAMP1_CSR_CALSEL   OPAMP1_CSR_CALSEL_Msk
	Calibration selection.
#define	OPAMP1_CSR_CALSEL_0   (0x1UL << OPAMP1_CSR_CALSEL_Pos)
	0x00001000
#define	OPAMP1_CSR_CALSEL_1   (0x2UL << OPAMP1_CSR_CALSEL_Pos)
	0x00002000
#define	OPAMP1_CSR_PGGAIN_Pos   (14U)
#define	OPAMP1_CSR_PGGAIN_Msk   (0xFUL << OPAMP1_CSR_PGGAIN_Pos)
	0x0003C000
#define	OPAMP1_CSR_PGGAIN   OPAMP1_CSR_PGGAIN_Msk
	Operational amplifier1 Programmable amplifier gain value.
#define	OPAMP1_CSR_PGGAIN_0   (0x1UL << OPAMP1_CSR_PGGAIN_Pos)
	0x00004000
#define	OPAMP1_CSR_PGGAIN_1   (0x2UL << OPAMP1_CSR_PGGAIN_Pos)
	0x00008000
#define	OPAMP1_CSR_PGGAIN_2   (0x4UL << OPAMP1_CSR_PGGAIN_Pos)
	0x00010000
#define	OPAMP1_CSR_PGGAIN_3   (0x8UL << OPAMP1_CSR_PGGAIN_Pos)
	0x00020000
#define	OPAMP1_CSR_USERTRIM_Pos   (18U)
#define	OPAMP1_CSR_USERTRIM_Msk   (0x1UL << OPAMP1_CSR_USERTRIM_Pos)
	0x00040000
#define	OPAMP1_CSR_USERTRIM   OPAMP1_CSR_USERTRIM_Msk
	User trimming enable.
#define	OPAMP1_CSR_TSTREF_Pos   (29U)
#define	OPAMP1_CSR_TSTREF_Msk   (0x1UL << OPAMP1_CSR_TSTREF_Pos)
	0x20000000
#define	OPAMP1_CSR_TSTREF   OPAMP1_CSR_TSTREF_Msk
	OpAmp calibration reference voltage output control.
#define	OPAMP1_CSR_CALOUT_Pos   (30U)
#define	OPAMP1_CSR_CALOUT_Msk   (0x1UL << OPAMP1_CSR_CALOUT_Pos)
	0x40000000
#define	OPAMP1_CSR_CALOUT   OPAMP1_CSR_CALOUT_Msk
	Operational amplifier1 calibration output.
#define	OPAMP2_CSR_OPAEN_Pos   (0U)
#define	OPAMP2_CSR_OPAEN_Msk   (0x1UL << OPAMP2_CSR_OPAEN_Pos)
	0x00000001
#define	OPAMP2_CSR_OPAEN   OPAMP2_CSR_OPAEN_Msk
	Operational amplifier2 Enable.
#define	OPAMP2_CSR_FORCEVP_Pos   (1U)
#define	OPAMP2_CSR_FORCEVP_Msk   (0x1UL << OPAMP2_CSR_FORCEVP_Pos)
	0x00000002
#define	OPAMP2_CSR_FORCEVP   OPAMP2_CSR_FORCEVP_Msk
	Force internal reference on VP.
#define	OPAMP2_CSR_VPSEL_Pos   (2U)
#define	OPAMP2_CSR_VPSEL_Msk   (0x3UL << OPAMP2_CSR_VPSEL_Pos)
	0x0000000C
#define	OPAMP2_CSR_VPSEL   OPAMP2_CSR_VPSEL_Msk
	Non inverted input selection.
#define	OPAMP2_CSR_VPSEL_0   (0x1UL << OPAMP2_CSR_VPSEL_Pos)
	0x00000004
#define	OPAMP2_CSR_VPSEL_1   (0x2UL << OPAMP2_CSR_VPSEL_Pos)
	0x00000008
#define	OPAMP2_CSR_VMSEL_Pos   (5U)
#define	OPAMP2_CSR_VMSEL_Msk   (0x3UL << OPAMP2_CSR_VMSEL_Pos)
	0x00000060
#define	OPAMP2_CSR_VMSEL   OPAMP2_CSR_VMSEL_Msk
	Inverting input selection.
#define	OPAMP2_CSR_VMSEL_0   (0x1UL << OPAMP2_CSR_VMSEL_Pos)
	0x00000020
#define	OPAMP2_CSR_VMSEL_1   (0x2UL << OPAMP2_CSR_VMSEL_Pos)
	0x00000040
#define	OPAMP2_CSR_OPAHSM_Pos   (8U)
#define	OPAMP2_CSR_OPAHSM_Msk   (0x1UL << OPAMP2_CSR_OPAHSM_Pos)
	0x00000100
#define	OPAMP2_CSR_OPAHSM   OPAMP2_CSR_OPAHSM_Msk
	Operational amplifier2 high speed mode.
#define	OPAMP2_CSR_CALON_Pos   (11U)
#define	OPAMP2_CSR_CALON_Msk   (0x1UL << OPAMP2_CSR_CALON_Pos)
	0x00000800
#define	OPAMP2_CSR_CALON   OPAMP2_CSR_CALON_Msk
	Calibration mode enable.
#define	OPAMP2_CSR_CALSEL_Pos   (12U)
#define	OPAMP2_CSR_CALSEL_Msk   (0x3UL << OPAMP2_CSR_CALSEL_Pos)
	0x00003000
#define	OPAMP2_CSR_CALSEL   OPAMP2_CSR_CALSEL_Msk
	Calibration selection.
#define	OPAMP2_CSR_CALSEL_0   (0x1UL << OPAMP2_CSR_CALSEL_Pos)
	0x00001000
#define	OPAMP2_CSR_CALSEL_1   (0x2UL << OPAMP2_CSR_CALSEL_Pos)
	0x00002000
#define	OPAMP2_CSR_PGGAIN_Pos   (14U)
#define	OPAMP2_CSR_PGGAIN_Msk   (0xFUL << OPAMP2_CSR_PGGAIN_Pos)
	0x0003C000
#define	OPAMP2_CSR_PGGAIN   OPAMP2_CSR_PGGAIN_Msk
	Operational amplifier2 Programmable amplifier gain value.
#define	OPAMP2_CSR_PGGAIN_0   (0x1UL << OPAMP2_CSR_PGGAIN_Pos)
	0x00004000
#define	OPAMP2_CSR_PGGAIN_1   (0x2UL << OPAMP2_CSR_PGGAIN_Pos)
	0x00008000
#define	OPAMP2_CSR_PGGAIN_2   (0x4UL << OPAMP2_CSR_PGGAIN_Pos)
	0x00010000
#define	OPAMP2_CSR_PGGAIN_3   (0x8UL << OPAMP2_CSR_PGGAIN_Pos)
	0x00020000
#define	OPAMP2_CSR_USERTRIM_Pos   (18U)
#define	OPAMP2_CSR_USERTRIM_Msk   (0x1UL << OPAMP2_CSR_USERTRIM_Pos)
	0x00040000
#define	OPAMP2_CSR_USERTRIM   OPAMP2_CSR_USERTRIM_Msk
	User trimming enable.
#define	OPAMP2_CSR_TSTREF_Pos   (29U)
#define	OPAMP2_CSR_TSTREF_Msk   (0x1UL << OPAMP2_CSR_TSTREF_Pos)
	0x20000000
#define	OPAMP2_CSR_TSTREF   OPAMP2_CSR_TSTREF_Msk
	OpAmp calibration reference voltage output control.
#define	OPAMP2_CSR_CALOUT_Pos   (30U)
#define	OPAMP2_CSR_CALOUT_Msk   (0x1UL << OPAMP2_CSR_CALOUT_Pos)
	0x40000000
#define	OPAMP2_CSR_CALOUT   OPAMP2_CSR_CALOUT_Msk
	Operational amplifier2 calibration output.
#define	OPAMP_OTR_TRIMOFFSETN_Pos   (0U)
#define	OPAMP_OTR_TRIMOFFSETN_Msk   (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos)
	0x0000001F
#define	OPAMP_OTR_TRIMOFFSETN   OPAMP_OTR_TRIMOFFSETN_Msk
	Trim for NMOS differential pairs.
#define	OPAMP_OTR_TRIMOFFSETP_Pos   (8U)
#define	OPAMP_OTR_TRIMOFFSETP_Msk   (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos)
	0x00001F00
#define	OPAMP_OTR_TRIMOFFSETP   OPAMP_OTR_TRIMOFFSETP_Msk
	Trim for PMOS differential pairs.
#define	OPAMP1_OTR_TRIMOFFSETN_Pos   (0U)
#define	OPAMP1_OTR_TRIMOFFSETN_Msk   (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos)
	0x0000001F
#define	OPAMP1_OTR_TRIMOFFSETN   OPAMP1_OTR_TRIMOFFSETN_Msk
	Trim for NMOS differential pairs.
#define	OPAMP1_OTR_TRIMOFFSETP_Pos   (8U)
#define	OPAMP1_OTR_TRIMOFFSETP_Msk   (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos)
	0x00001F00
#define	OPAMP1_OTR_TRIMOFFSETP   OPAMP1_OTR_TRIMOFFSETP_Msk
	Trim for PMOS differential pairs.
#define	OPAMP2_OTR_TRIMOFFSETN_Pos   (0U)
#define	OPAMP2_OTR_TRIMOFFSETN_Msk   (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos)
	0x0000001F
#define	OPAMP2_OTR_TRIMOFFSETN   OPAMP2_OTR_TRIMOFFSETN_Msk
	Trim for NMOS differential pairs.
#define	OPAMP2_OTR_TRIMOFFSETP_Pos   (8U)
#define	OPAMP2_OTR_TRIMOFFSETP_Msk   (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos)
	0x00001F00
#define	OPAMP2_OTR_TRIMOFFSETP   OPAMP2_OTR_TRIMOFFSETP_Msk
	Trim for PMOS differential pairs.
#define	OPAMP_HSOTR_TRIMHSOFFSETN_Pos   (0U)
#define	OPAMP_HSOTR_TRIMHSOFFSETN_Msk   (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos)
	0x0000001F
#define	OPAMP_HSOTR_TRIMHSOFFSETN   OPAMP_HSOTR_TRIMHSOFFSETN_Msk
	Trim for NMOS differential pairs.
#define	OPAMP_HSOTR_TRIMHSOFFSETP_Pos   (8U)
#define	OPAMP_HSOTR_TRIMHSOFFSETP_Msk   (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos)
	0x00001F00
#define	OPAMP_HSOTR_TRIMHSOFFSETP   OPAMP_HSOTR_TRIMHSOFFSETP_Msk
	Trim for PMOS differential pairs.
#define	OPAMP1_HSOTR_TRIMHSOFFSETN_Pos   (0U)
#define	OPAMP1_HSOTR_TRIMHSOFFSETN_Msk   (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos)
	0x0000001F
#define	OPAMP1_HSOTR_TRIMHSOFFSETN   OPAMP1_HSOTR_TRIMHSOFFSETN_Msk
	Trim for NMOS differential pairs.
#define	OPAMP1_HSOTR_TRIMHSOFFSETP_Pos   (8U)
#define	OPAMP1_HSOTR_TRIMHSOFFSETP_Msk   (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos)
	0x00001F00
#define	OPAMP1_HSOTR_TRIMHSOFFSETP   OPAMP1_HSOTR_TRIMHSOFFSETP_Msk
	Trim for PMOS differential pairs.
#define	OPAMP2_HSOTR_TRIMHSOFFSETN_Pos   (0U)
#define	OPAMP2_HSOTR_TRIMHSOFFSETN_Msk   (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos)
	0x0000001F
#define	OPAMP2_HSOTR_TRIMHSOFFSETN   OPAMP2_HSOTR_TRIMHSOFFSETN_Msk
	Trim for NMOS differential pairs.
#define	OPAMP2_HSOTR_TRIMHSOFFSETP_Pos   (8U)
#define	OPAMP2_HSOTR_TRIMHSOFFSETP_Msk   (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos)
	0x00001F00
#define	OPAMP2_HSOTR_TRIMHSOFFSETP   OPAMP2_HSOTR_TRIMHSOFFSETP_Msk
	Trim for PMOS differential pairs.
#define	PSSI_CR_OUTEN_Pos   (31U)
#define	PSSI_CR_OUTEN_Msk   (0x1UL << PSSI_CR_OUTEN_Pos)
	0x80000000
#define	PSSI_CR_OUTEN   PSSI_CR_OUTEN_Msk
	Data direction selection.
#define	PSSI_CR_DMAEN_Pos   (30U)
#define	PSSI_CR_DMAEN_Msk   (0x1UL << PSSI_CR_DMAEN_Pos)
	0x40000000
#define	PSSI_CR_DMAEN   PSSI_CR_DMAEN_Msk
	DMA enable.
#define	PSSI_CR_DERDYCFG_Pos   (18U)
#define	PSSI_CR_DERDYCFG_Msk   (0x7UL << PSSI_CR_DERDYCFG_Pos)
	0x001C0000
#define	PSSI_CR_DERDYCFG   PSSI_CR_DERDYCFG_Msk
	Data enable and ready configuration.
#define	PSSI_CR_ENABLE_Pos   (14U)
#define	PSSI_CR_ENABLE_Msk   (0x1UL << PSSI_CR_ENABLE_Pos)
	0x00004000
#define	PSSI_CR_ENABLE   PSSI_CR_ENABLE_Msk
	PSSI enable.
#define	PSSI_CR_EDM_Pos   (10U)
#define	PSSI_CR_EDM_Msk   (0x3UL << PSSI_CR_EDM_Pos)
	0x00000C00
#define	PSSI_CR_EDM   PSSI_CR_EDM_Msk
	Extended data mode.
#define	PSSI_CR_RDYPOL_Pos   (8U)
#define	PSSI_CR_RDYPOL_Msk   (0x1UL << PSSI_CR_RDYPOL_Pos)
	0x00000C00
#define	PSSI_CR_RDYPOL   PSSI_CR_RDYPOL_Msk
	Ready polarity.
#define	PSSI_CR_DEPOL_Pos   (6U)
#define	PSSI_CR_DEPOL_Msk   (0x1UL << PSSI_CR_DEPOL_Pos)
	0x00000C00
#define	PSSI_CR_DEPOL   PSSI_CR_DEPOL_Msk
	Data enable polarity.
#define	PSSI_CR_CKPOL_Pos   (5U)
#define	PSSI_CR_CKPOL_Msk   (0x1UL << PSSI_CR_CKPOL_Pos)
	0x00000C00
#define	PSSI_CR_CKPOL   PSSI_CR_CKPOL_Msk
	Parallel data clock polarity.
#define	PSSI_SR_RTT1B_Pos   (3U)
#define	PSSI_SR_RTT1B_Msk   (0x1UL << PSSI_SR_RTT1B_Pos)
	0x00000008
#define	PSSI_SR_RTT1B   PSSI_SR_RTT1B_Msk
	Ready to transfer one byte.
#define	PSSI_SR_RTT4B_Pos   (2U)
#define	PSSI_SR_RTT4B_Msk   (0x1UL << PSSI_SR_RTT4B_Pos)
	0x00000004
#define	PSSI_SR_RTT4B   PSSI_SR_RTT4B_Msk
	Ready to transfer four bytes.
#define	PSSI_RIS_OVR_RIS_Pos   (1U)
#define	PSSI_RIS_OVR_RIS_Msk   (0x1UL << PSSI_RIS_OVR_RIS_Pos)
	0x00000002
#define	PSSI_RIS_OVR_RIS   PSSI_RIS_OVR_RIS_Msk
	Data buffer overrun/underrun raw interrupt status.
#define	PSSI_IER_OVR_IE_Pos   (1U)
#define	PSSI_IER_OVR_IE_Msk   (0x1UL << PSSI_IER_OVR_IE_Pos)
	0x00000002
#define	PSSI_IER_OVR_IE   PSSI_IER_OVR_IE_Msk
	Data buffer overrun/underrun interrupt enable.
#define	PSSI_MIS_OVR_MIS_Pos   (1U)
#define	PSSI_MIS_OVR_MIS_Msk   (0x1UL << PSSI_MIS_OVR_MIS_Pos)
	0x00000002
#define	PSSI_MIS_OVR_MIS   PSSI_MIS_OVR_MIS_Msk
	Data buffer overrun/underrun masked interrupt status.
#define	PSSI_ICR_OVR_ISC_Pos   (1U)
#define	PSSI_ICR_OVR_ISC_Msk   (0x1UL << PSSI_ICR_OVR_ISC_Pos)
	0x00000002
#define	PSSI_ICR_OVR_ISC   PSSI_ICR_OVR_ISC_Msk
	Data buffer overrun/underrun interrupt status clear.
#define	PSSI_DR_DR_Pos   (0U)
#define	PSSI_DR_DR_Msk   (0xFFFFFFFFUL << PSSI_DR_DR_Pos)
	0xFFFFFFF
#define	PSSI_DR_DR   PSSI_DR_DR_Msk
	Data register.
#define	POWER_DOMAINS_NUMBER   3U
	3 Domains
#define	PWR_CR1_ALS_Pos   (17U)
#define	PWR_CR1_ALS_Msk   (0x3UL << PWR_CR1_ALS_Pos)
	0x00060000
#define	PWR_CR1_ALS   PWR_CR1_ALS_Msk
	Analog Voltage Detector level selection.
#define	PWR_CR1_ALS_0   (0x1UL << PWR_CR1_ALS_Pos)
	0x00020000
#define	PWR_CR1_ALS_1   (0x2UL << PWR_CR1_ALS_Pos)
	0x00040000
#define	PWR_CR1_AVDEN_Pos   (16U)
#define	PWR_CR1_AVDEN_Msk   (0x1UL << PWR_CR1_AVDEN_Pos)
	0x00010000
#define	PWR_CR1_AVDEN   PWR_CR1_AVDEN_Msk
	Analog Voltage Detector Enable.
#define	PWR_CR1_SVOS_Pos   (14U)
#define	PWR_CR1_SVOS_Msk   (0x3UL << PWR_CR1_SVOS_Pos)
	0x0000C000
#define	PWR_CR1_SVOS   PWR_CR1_SVOS_Msk
	System STOP mode Voltage Scaling selection.
#define	PWR_CR1_SVOS_0   (0x1UL << PWR_CR1_SVOS_Pos)
	0x00004000
#define	PWR_CR1_SVOS_1   (0x2UL << PWR_CR1_SVOS_Pos)
	0x00008000
#define	PWR_CR1_FLPS_Pos   (9U)
#define	PWR_CR1_FLPS_Msk   (0x1UL << PWR_CR1_FLPS_Pos)
	0x00000200
#define	PWR_CR1_FLPS   PWR_CR1_FLPS_Msk
	Flash low power mode in DSTOP.
#define	PWR_CR1_DBP_Pos   (8U)
#define	PWR_CR1_DBP_Msk   (0x1UL << PWR_CR1_DBP_Pos)
	0x00000100
#define	PWR_CR1_DBP   PWR_CR1_DBP_Msk
	Disable Back-up domain Protection.
#define	PWR_CR1_PLS_Pos   (5U)
#define	PWR_CR1_PLS_Msk   (0x7UL << PWR_CR1_PLS_Pos)
	0x000000E0
#define	PWR_CR1_PLS   PWR_CR1_PLS_Msk
	Programmable Voltage Detector level selection.
#define	PWR_CR1_PLS_0   (0x1UL << PWR_CR1_PLS_Pos)
	0x00000020
#define	PWR_CR1_PLS_1   (0x2UL << PWR_CR1_PLS_Pos)
	0x00000040
#define	PWR_CR1_PLS_2   (0x4UL << PWR_CR1_PLS_Pos)
	0x00000080
#define	PWR_CR1_PVDEN_Pos   (4U)
#define	PWR_CR1_PVDEN_Msk   (0x1UL << PWR_CR1_PVDEN_Pos)
	0x00000010
#define	PWR_CR1_PVDEN   PWR_CR1_PVDEN_Msk
	Programmable Voltage detector enable.
#define	PWR_CR1_LPDS_Pos   (0U)
#define	PWR_CR1_LPDS_Msk   (0x1UL << PWR_CR1_LPDS_Pos)
	0x00000001
#define	PWR_CR1_LPDS   PWR_CR1_LPDS_Msk
	Low Power Deepsleep with SVOS3.
#define	PWR_CR1_PLS_LEV0   (0UL)
	PVD level 0.
#define	PWR_CR1_PLS_LEV1_Pos   (5U)
#define	PWR_CR1_PLS_LEV1_Msk   (0x1UL << PWR_CR1_PLS_LEV1_Pos)
	0x00000020
#define	PWR_CR1_PLS_LEV1   PWR_CR1_PLS_LEV1_Msk
	PVD level 1.
#define	PWR_CR1_PLS_LEV2_Pos   (6U)
#define	PWR_CR1_PLS_LEV2_Msk   (0x1UL << PWR_CR1_PLS_LEV2_Pos)
	0x00000040
#define	PWR_CR1_PLS_LEV2   PWR_CR1_PLS_LEV2_Msk
	PVD level 2.
#define	PWR_CR1_PLS_LEV3_Pos   (5U)
#define	PWR_CR1_PLS_LEV3_Msk   (0x3UL << PWR_CR1_PLS_LEV3_Pos)
	0x00000060
#define	PWR_CR1_PLS_LEV3   PWR_CR1_PLS_LEV3_Msk
	PVD level 3.
#define	PWR_CR1_PLS_LEV4_Pos   (7U)
#define	PWR_CR1_PLS_LEV4_Msk   (0x1UL << PWR_CR1_PLS_LEV4_Pos)
	0x00000080
#define	PWR_CR1_PLS_LEV4   PWR_CR1_PLS_LEV4_Msk
	PVD level 4.
#define	PWR_CR1_PLS_LEV5_Pos   (5U)
#define	PWR_CR1_PLS_LEV5_Msk   (0x5UL << PWR_CR1_PLS_LEV5_Pos)
	0x000000A0
#define	PWR_CR1_PLS_LEV5   PWR_CR1_PLS_LEV5_Msk
	PVD level 5.
#define	PWR_CR1_PLS_LEV6_Pos   (6U)
#define	PWR_CR1_PLS_LEV6_Msk   (0x3UL << PWR_CR1_PLS_LEV6_Pos)
	0x000000C0
#define	PWR_CR1_PLS_LEV6   PWR_CR1_PLS_LEV6_Msk
	PVD level 6.
#define	PWR_CR1_PLS_LEV7_Pos   (5U)
#define	PWR_CR1_PLS_LEV7_Msk   (0x7UL << PWR_CR1_PLS_LEV7_Pos)
	0x000000E0
#define	PWR_CR1_PLS_LEV7   PWR_CR1_PLS_LEV7_Msk
	PVD level 7.
#define	PWR_CR1_ALS_LEV0   (0UL)
	AVD level 0.
#define	PWR_CR1_ALS_LEV1_Pos   (17U)
#define	PWR_CR1_ALS_LEV1_Msk   (0x1UL << PWR_CR1_ALS_LEV1_Pos)
	0x00020000
#define	PWR_CR1_ALS_LEV1   PWR_CR1_ALS_LEV1_Msk
	AVD level 1.
#define	PWR_CR1_ALS_LEV2_Pos   (18U)
#define	PWR_CR1_ALS_LEV2_Msk   (0x1UL << PWR_CR1_ALS_LEV2_Pos)
	0x00040000
#define	PWR_CR1_ALS_LEV2   PWR_CR1_ALS_LEV2_Msk
	AVD level 2.
#define	PWR_CR1_ALS_LEV3_Pos   (17U)
#define	PWR_CR1_ALS_LEV3_Msk   (0x3UL << PWR_CR1_ALS_LEV3_Pos)
	0x00060000
#define	PWR_CR1_ALS_LEV3   PWR_CR1_ALS_LEV3_Msk
	AVD level 3.
#define	PWR_CSR1_AVDO_Pos   (16U)
#define	PWR_CSR1_AVDO_Msk   (0x1UL << PWR_CSR1_AVDO_Pos)
	0x00010000
#define	PWR_CSR1_AVDO   PWR_CSR1_AVDO_Msk
	Analog Voltage Detect Output.
#define	PWR_CSR1_ACTVOS_Pos   (14U)
#define	PWR_CSR1_ACTVOS_Msk   (0x3UL << PWR_CSR1_ACTVOS_Pos)
	0x0000C000
#define	PWR_CSR1_ACTVOS   PWR_CSR1_ACTVOS_Msk
	Current actual used VOS for VDD11 Voltage Scaling.
#define	PWR_CSR1_ACTVOS_0   (0x1UL << PWR_CSR1_ACTVOS_Pos)
	0x00004000
#define	PWR_CSR1_ACTVOS_1   (0x2UL << PWR_CSR1_ACTVOS_Pos)
	0x00008000
#define	PWR_CSR1_ACTVOSRDY_Pos   (13U)
#define	PWR_CSR1_ACTVOSRDY_Msk   (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)
	0x00002000
#define	PWR_CSR1_ACTVOSRDY   PWR_CSR1_ACTVOSRDY_Msk
	Ready bit for current actual used VOS for VDD11 Voltage Scaling.
#define	PWR_CSR1_PVDO_Pos   (4U)
#define	PWR_CSR1_PVDO_Msk   (0x1UL << PWR_CSR1_PVDO_Pos)
	0x00000010
#define	PWR_CSR1_PVDO   PWR_CSR1_PVDO_Msk
	Programmable Voltage Detect Output.
#define	PWR_CR2_TEMPH_Pos   (23U)
#define	PWR_CR2_TEMPH_Msk   (0x1UL << PWR_CR2_TEMPH_Pos)
	0x00800000
#define	PWR_CR2_TEMPH   PWR_CR2_TEMPH_Msk
	Monitored temperature level above high threshold.
#define	PWR_CR2_TEMPL_Pos   (22U)
#define	PWR_CR2_TEMPL_Msk   (0x1UL << PWR_CR2_TEMPL_Pos)
	0x00400000
#define	PWR_CR2_TEMPL   PWR_CR2_TEMPL_Msk
	Monitored temperature level above low threshold.
#define	PWR_CR2_VBATH_Pos   (21U)
#define	PWR_CR2_VBATH_Msk   (0x1UL << PWR_CR2_VBATH_Pos)
	0x00200000
#define	PWR_CR2_VBATH   PWR_CR2_VBATH_Msk
	Monitored VBAT level above high threshold.
#define	PWR_CR2_VBATL_Pos   (20U)
#define	PWR_CR2_VBATL_Msk   (0x1UL << PWR_CR2_VBATL_Pos)
	0x00100000
#define	PWR_CR2_VBATL   PWR_CR2_VBATL_Msk
	Monitored VBAT level above low threshold.
#define	PWR_CR2_BRRDY_Pos   (16U)
#define	PWR_CR2_BRRDY_Msk   (0x1UL << PWR_CR2_BRRDY_Pos)
	0x00010000
#define	PWR_CR2_BRRDY   PWR_CR2_BRRDY_Msk
	Backup regulator ready.
#define	PWR_CR2_MONEN_Pos   (4U)
#define	PWR_CR2_MONEN_Msk   (0x1UL << PWR_CR2_MONEN_Pos)
	0x00000010
#define	PWR_CR2_MONEN   PWR_CR2_MONEN_Msk
	VBAT and temperature monitoring enable.
#define	PWR_CR2_BREN_Pos   (0U)
#define	PWR_CR2_BREN_Msk   (0x1UL << PWR_CR2_BREN_Pos)
	0x00000001
#define	PWR_CR2_BREN   PWR_CR2_BREN_Msk
	Backup regulator enable.
#define	PWR_CR3_USB33RDY_Pos   (26U)
#define	PWR_CR3_USB33RDY_Msk   (0x1UL << PWR_CR3_USB33RDY_Pos)
	0x04000000
#define	PWR_CR3_USB33RDY   PWR_CR3_USB33RDY_Msk
	USB supply ready.
#define	PWR_CR3_USBREGEN_Pos   (25U)
#define	PWR_CR3_USBREGEN_Msk   (0x1UL << PWR_CR3_USBREGEN_Pos)
	0x02000000
#define	PWR_CR3_USBREGEN   PWR_CR3_USBREGEN_Msk
	USB regulator enable.
#define	PWR_CR3_USB33DEN_Pos   (24U)
#define	PWR_CR3_USB33DEN_Msk   (0x1UL << PWR_CR3_USB33DEN_Pos)
	0x01000000
#define	PWR_CR3_USB33DEN   PWR_CR3_USB33DEN_Msk
	VDD33_USB voltage level detector enable.
#define	PWR_CR3_VBRS_Pos   (9U)
#define	PWR_CR3_VBRS_Msk   (0x1UL << PWR_CR3_VBRS_Pos)
	0x00000200
#define	PWR_CR3_VBRS   PWR_CR3_VBRS_Msk
	VBAT charging resistor selection.
#define	PWR_CR3_VBE_Pos   (8U)
#define	PWR_CR3_VBE_Msk   (0x1UL << PWR_CR3_VBE_Pos)
	0x00000100
#define	PWR_CR3_VBE   PWR_CR3_VBE_Msk
	VBAT charging enable.
#define	PWR_CR3_SCUEN_Pos   (2U)
#define	PWR_CR3_SCUEN_Msk   (0x1UL << PWR_CR3_SCUEN_Pos)
	0x00000004
#define	PWR_CR3_SCUEN   PWR_CR3_SCUEN_Msk
	Supply configuration update enable.
#define	PWR_CR3_LDOEN_Pos   (1U)
#define	PWR_CR3_LDOEN_Msk   (0x1UL << PWR_CR3_LDOEN_Pos)
	0x00000002
#define	PWR_CR3_LDOEN   PWR_CR3_LDOEN_Msk
	Low Drop Output regulator enable.
#define	PWR_CR3_BYPASS_Pos   (0U)
#define	PWR_CR3_BYPASS_Msk   (0x1UL << PWR_CR3_BYPASS_Pos)
	0x00000001
#define	PWR_CR3_BYPASS   PWR_CR3_BYPASS_Msk
	Power Management Unit bypass.
#define	PWR_CPUCR_RUN_D3_Pos   (11U)
#define	PWR_CPUCR_RUN_D3_Msk   (0x1UL << PWR_CPUCR_RUN_D3_Pos)
	0x00000800
#define	PWR_CPUCR_RUN_D3   PWR_CPUCR_RUN_D3_Msk
	Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes.
#define	PWR_CPUCR_CSSF_Pos   (9U)
#define	PWR_CPUCR_CSSF_Msk   (0x1UL << PWR_CPUCR_CSSF_Pos)
	0x00000200
#define	PWR_CPUCR_CSSF   PWR_CPUCR_CSSF_Msk
	Clear D1 domain CPU1 STANDBY, STOP and HOLD flags.
#define	PWR_CPUCR_SBF_D2_Pos   (8U)
#define	PWR_CPUCR_SBF_D2_Msk   (0x1UL << PWR_CPUCR_SBF_D2_Pos)
	0x00000100
#define	PWR_CPUCR_SBF_D2   PWR_CPUCR_SBF_D2_Msk
	D2 domain DSTANDBY Flag.
#define	PWR_CPUCR_SBF_D1_Pos   (7U)
#define	PWR_CPUCR_SBF_D1_Msk   (0x1UL << PWR_CPUCR_SBF_D1_Pos)
	0x00000080
#define	PWR_CPUCR_SBF_D1   PWR_CPUCR_SBF_D1_Msk
	D1 domain DSTANDBY Flag.
#define	PWR_CPUCR_SBF_Pos   (6U)
#define	PWR_CPUCR_SBF_Msk   (0x1UL << PWR_CPUCR_SBF_Pos)
	0x00000040
#define	PWR_CPUCR_SBF   PWR_CPUCR_SBF_Msk
	System STANDBY Flag.
#define	PWR_CPUCR_STOPF_Pos   (5U)
#define	PWR_CPUCR_STOPF_Msk   (0x1UL << PWR_CPUCR_STOPF_Pos)
	0x00000020
#define	PWR_CPUCR_STOPF   PWR_CPUCR_STOPF_Msk
	STOP Flag.
#define	PWR_CPUCR_PDDS_D3_Pos   (2U)
#define	PWR_CPUCR_PDDS_D3_Msk   (0x1UL << PWR_CPUCR_PDDS_D3_Pos)
	0x00000004
#define	PWR_CPUCR_PDDS_D3   PWR_CPUCR_PDDS_D3_Msk
	System D3 domain Power Down Deepsleep.
#define	PWR_CPUCR_PDDS_D2_Pos   (1U)
#define	PWR_CPUCR_PDDS_D2_Msk   (0x1UL << PWR_CPUCR_PDDS_D2_Pos)
	0x00000002
#define	PWR_CPUCR_PDDS_D2   PWR_CPUCR_PDDS_D2_Msk
	D2 domain Power Down Deepsleep.
#define	PWR_CPUCR_PDDS_D1_Pos   (0U)
#define	PWR_CPUCR_PDDS_D1_Msk   (0x1UL << PWR_CPUCR_PDDS_D1_Pos)
	0x00000001
#define	PWR_CPUCR_PDDS_D1   PWR_CPUCR_PDDS_D1_Msk
	D1 domain Power Down Deepsleep selection.
#define	PWR_D3CR_VOS_Pos   (14U)
#define	PWR_D3CR_VOS_Msk   (0x3UL << PWR_D3CR_VOS_Pos)
	0x0000C000
#define	PWR_D3CR_VOS   PWR_D3CR_VOS_Msk
	Voltage Scaling selection according performance.
#define	PWR_D3CR_VOS_0   (0x1UL << PWR_D3CR_VOS_Pos)
	0x00004000
#define	PWR_D3CR_VOS_1   (0x2UL << PWR_D3CR_VOS_Pos)
	0x00008000
#define	PWR_D3CR_VOSRDY_Pos   (13U)
#define	PWR_D3CR_VOSRDY_Msk   (0x1UL << PWR_D3CR_VOSRDY_Pos)
	0x00002000
#define	PWR_D3CR_VOSRDY   PWR_D3CR_VOSRDY_Msk
	VOS Ready bit for VDD11 Voltage Scaling output selection.
#define	PWR_WKUPCR_WKUPC6_Pos   (5U)
#define	PWR_WKUPCR_WKUPC6_Msk   (0x1UL << PWR_WKUPCR_WKUPC6_Pos)
	0x00000020
#define	PWR_WKUPCR_WKUPC6   PWR_WKUPCR_WKUPC6_Msk
	Clear Wakeup Pin Flag 6.
#define	PWR_WKUPCR_WKUPC4_Pos   (3U)
#define	PWR_WKUPCR_WKUPC4_Msk   (0x1UL << PWR_WKUPCR_WKUPC4_Pos)
	0x00000008
#define	PWR_WKUPCR_WKUPC4   PWR_WKUPCR_WKUPC4_Msk
	Clear Wakeup Pin Flag 4.
#define	PWR_WKUPCR_WKUPC2_Pos   (1U)
#define	PWR_WKUPCR_WKUPC2_Msk   (0x1UL << PWR_WKUPCR_WKUPC2_Pos)
	0x00000002
#define	PWR_WKUPCR_WKUPC2   PWR_WKUPCR_WKUPC2_Msk
	Clear Wakeup Pin Flag 2.
#define	PWR_WKUPCR_WKUPC1_Pos   (0U)
#define	PWR_WKUPCR_WKUPC1_Msk   (0x1UL << PWR_WKUPCR_WKUPC1_Pos)
	0x00000001
#define	PWR_WKUPCR_WKUPC1   PWR_WKUPCR_WKUPC1_Msk
	Clear Wakeup Pin Flag 1.
#define	PWR_WKUPFR_WKUPF6_Pos   (5U)
#define	PWR_WKUPFR_WKUPF6_Msk   (0x1UL << PWR_WKUPFR_WKUPF6_Pos)
	0x00000020
#define	PWR_WKUPFR_WKUPF6   PWR_WKUPFR_WKUPF6_Msk
	Wakeup Pin Flag 6.
#define	PWR_WKUPFR_WKUPF4_Pos   (3U)
#define	PWR_WKUPFR_WKUPF4_Msk   (0x1UL << PWR_WKUPFR_WKUPF4_Pos)
	0x00000008
#define	PWR_WKUPFR_WKUPF4   PWR_WKUPFR_WKUPF4_Msk
	Wakeup Pin Flag 4.
#define	PWR_WKUPFR_WKUPF2_Pos   (1U)
#define	PWR_WKUPFR_WKUPF2_Msk   (0x1UL << PWR_WKUPFR_WKUPF2_Pos)
	0x00000002
#define	PWR_WKUPFR_WKUPF2   PWR_WKUPFR_WKUPF2_Msk
	Wakeup Pin Flag 2.
#define	PWR_WKUPFR_WKUPF1_Pos   (0U)
#define	PWR_WKUPFR_WKUPF1_Msk   (0x1UL << PWR_WKUPFR_WKUPF1_Pos)
	0x00000001
#define	PWR_WKUPFR_WKUPF1   PWR_WKUPFR_WKUPF1_Msk
	Wakeup Pin Flag 1.
#define	PWR_WKUPEPR_WKUPPUPD6_Pos   (26U)
#define	PWR_WKUPEPR_WKUPPUPD6_Msk   (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)
	0x0C000000
#define	PWR_WKUPEPR_WKUPPUPD6   PWR_WKUPEPR_WKUPPUPD6_Msk
	Wakeup Pin pull configuration for WKUP6.
#define	PWR_WKUPEPR_WKUPPUPD6_0   (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)
	0x04000000
#define	PWR_WKUPEPR_WKUPPUPD6_1   (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)
	0x08000000
#define	PWR_WKUPEPR_WKUPPUPD4_Pos   (22U)
#define	PWR_WKUPEPR_WKUPPUPD4_Msk   (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)
	0x00C00000
#define	PWR_WKUPEPR_WKUPPUPD4   PWR_WKUPEPR_WKUPPUPD4_Msk
	Wakeup Pin pull configuration for WKUP4.
#define	PWR_WKUPEPR_WKUPPUPD4_0   (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)
	0x00400000
#define	PWR_WKUPEPR_WKUPPUPD4_1   (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)
	0x00800000
#define	PWR_WKUPEPR_WKUPPUPD2_Pos   (18U)
#define	PWR_WKUPEPR_WKUPPUPD2_Msk   (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)
	0x000C0000
#define	PWR_WKUPEPR_WKUPPUPD2   PWR_WKUPEPR_WKUPPUPD2_Msk
	Wakeup Pin pull configuration for WKUP2.
#define	PWR_WKUPEPR_WKUPPUPD2_0   (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)
	0x00040000
#define	PWR_WKUPEPR_WKUPPUPD2_1   (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)
	0x00080000
#define	PWR_WKUPEPR_WKUPPUPD1_Pos   (16U)
#define	PWR_WKUPEPR_WKUPPUPD1_Msk   (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)
	0x00030000
#define	PWR_WKUPEPR_WKUPPUPD1   PWR_WKUPEPR_WKUPPUPD1_Msk
	Wakeup Pin pull configuration for WKUP1.
#define	PWR_WKUPEPR_WKUPPUPD1_0   (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)
	0x00010000
#define	PWR_WKUPEPR_WKUPPUPD1_1   (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)
	0x00020000
#define	PWR_WKUPEPR_WKUPP6_Pos   (13U)
#define	PWR_WKUPEPR_WKUPP6_Msk   (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)
	0x00002000
#define	PWR_WKUPEPR_WKUPP6   PWR_WKUPEPR_WKUPP6_Msk
	Wakeup Pin Polarity for WKUP6.
#define	PWR_WKUPEPR_WKUPP4_Pos   (11U)
#define	PWR_WKUPEPR_WKUPP4_Msk   (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)
	0x00000800
#define	PWR_WKUPEPR_WKUPP4   PWR_WKUPEPR_WKUPP4_Msk
	Wakeup Pin Polarity for WKUP4.
#define	PWR_WKUPEPR_WKUPP2_Pos   (9U)
#define	PWR_WKUPEPR_WKUPP2_Msk   (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)
	0x00000200
#define	PWR_WKUPEPR_WKUPP2   PWR_WKUPEPR_WKUPP2_Msk
	Wakeup Pin Polarity for WKUP2.
#define	PWR_WKUPEPR_WKUPP1_Pos   (8U)
#define	PWR_WKUPEPR_WKUPP1_Msk   (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)
	0x00000100
#define	PWR_WKUPEPR_WKUPP1   PWR_WKUPEPR_WKUPP1_Msk
	Wakeup Pin Polarity for WKUP1.
#define	PWR_WKUPEPR_WKUPEN6_Pos   (5U)
#define	PWR_WKUPEPR_WKUPEN6_Msk   (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)
	0x00000020
#define	PWR_WKUPEPR_WKUPEN6   PWR_WKUPEPR_WKUPEN6_Msk
	Enable Wakeup Pin WKUP6.
#define	PWR_WKUPEPR_WKUPEN4_Pos   (3U)
#define	PWR_WKUPEPR_WKUPEN4_Msk   (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)
	0x00000008
#define	PWR_WKUPEPR_WKUPEN4   PWR_WKUPEPR_WKUPEN4_Msk
	Enable Wakeup Pin WKUP4.
#define	PWR_WKUPEPR_WKUPEN2_Pos   (1U)
#define	PWR_WKUPEPR_WKUPEN2_Msk   (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)
	0x00000002
#define	PWR_WKUPEPR_WKUPEN2   PWR_WKUPEPR_WKUPEN2_Msk
	Enable Wakeup Pin WKUP2.
#define	PWR_WKUPEPR_WKUPEN1_Pos   (0U)
#define	PWR_WKUPEPR_WKUPEN1_Msk   (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)
	0x00000001
#define	PWR_WKUPEPR_WKUPEN1   PWR_WKUPEPR_WKUPEN1_Msk
	Enable Wakeup Pin WKUP1.
#define	PWR_WKUPEPR_WKUPEN_Pos   (0U)
#define	PWR_WKUPEPR_WKUPEN_Msk   (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)
	0x0000003F
#define	PWR_WKUPEPR_WKUPEN   PWR_WKUPEPR_WKUPEN_Msk
	Enable all Wakeup Pin.
#define	RCC_VER_3_0
#define	RCC_CR_HSION_Pos   (0U)
#define	RCC_CR_HSION_Msk   (0x1UL << RCC_CR_HSION_Pos)
	0x00000001
#define	RCC_CR_HSION   RCC_CR_HSION_Msk
	Internal High Speed clock enable.
#define	RCC_CR_HSIKERON_Pos   (1U)
#define	RCC_CR_HSIKERON_Msk   (0x1UL << RCC_CR_HSIKERON_Pos)
	0x00000002
#define	RCC_CR_HSIKERON   RCC_CR_HSIKERON_Msk
	Internal High Speed clock enable for some IPs Kernel.
#define	RCC_CR_HSIRDY_Pos   (2U)
#define	RCC_CR_HSIRDY_Msk   (0x1UL << RCC_CR_HSIRDY_Pos)
	0x00000004
#define	RCC_CR_HSIRDY   RCC_CR_HSIRDY_Msk
	Internal High Speed clock ready flag.
#define	RCC_CR_HSIDIV_Pos   (3U)
#define	RCC_CR_HSIDIV_Msk   (0x3UL << RCC_CR_HSIDIV_Pos)
	0x00000018
#define	RCC_CR_HSIDIV   RCC_CR_HSIDIV_Msk
	Internal High Speed clock divider selection.
#define	RCC_CR_HSIDIV_1   (0x0UL << RCC_CR_HSIDIV_Pos)
	0x00000000
#define	RCC_CR_HSIDIV_2   (0x1UL << RCC_CR_HSIDIV_Pos)
	0x00000008
#define	RCC_CR_HSIDIV_4   (0x2UL << RCC_CR_HSIDIV_Pos)
	0x00000010
#define	RCC_CR_HSIDIV_8   (0x3UL << RCC_CR_HSIDIV_Pos)
	0x00000018
#define	RCC_CR_HSIDIVF_Pos   (5U)
#define	RCC_CR_HSIDIVF_Msk   (0x1UL << RCC_CR_HSIDIVF_Pos)
	0x00000020
#define	RCC_CR_HSIDIVF   RCC_CR_HSIDIVF_Msk
	HSI Divider flag.
#define	RCC_CR_CSION_Pos   (7U)
#define	RCC_CR_CSION_Msk   (0x1UL << RCC_CR_CSION_Pos)
	0x00000080
#define	RCC_CR_CSION   RCC_CR_CSION_Msk
	The Internal RC 4MHz oscillator clock enable.
#define	RCC_CR_CSIRDY_Pos   (8U)
#define	RCC_CR_CSIRDY_Msk   (0x1UL << RCC_CR_CSIRDY_Pos)
	0x00000100
#define	RCC_CR_CSIRDY   RCC_CR_CSIRDY_Msk
	The Internal RC 4MHz oscillator clock ready.
#define	RCC_CR_CSIKERON_Pos   (9U)
#define	RCC_CR_CSIKERON_Msk   (0x1UL << RCC_CR_CSIKERON_Pos)
	0x00000200
#define	RCC_CR_CSIKERON   RCC_CR_CSIKERON_Msk
	Internal RC 4MHz oscillator clock enable for some IPs Kernel.
#define	RCC_CR_HSI48ON_Pos   (12U)
#define	RCC_CR_HSI48ON_Msk   (0x1UL << RCC_CR_HSI48ON_Pos)
	0x00001000
#define	RCC_CR_HSI48ON   RCC_CR_HSI48ON_Msk
	HSI48 clock enable clock enable.
#define	RCC_CR_HSI48RDY_Pos   (13U)
#define	RCC_CR_HSI48RDY_Msk   (0x1UL << RCC_CR_HSI48RDY_Pos)
	0x00002000
#define	RCC_CR_HSI48RDY   RCC_CR_HSI48RDY_Msk
	HSI48 clock ready.
#define	RCC_CR_D1CKRDY_Pos   (14U)
#define	RCC_CR_D1CKRDY_Msk   (0x1UL << RCC_CR_D1CKRDY_Pos)
	0x00004000
#define	RCC_CR_D1CKRDY   RCC_CR_D1CKRDY_Msk
	D1 domain clocks ready flag.
#define	RCC_CR_D2CKRDY_Pos   (15U)
#define	RCC_CR_D2CKRDY_Msk   (0x1UL << RCC_CR_D2CKRDY_Pos)
	0x00008000
#define	RCC_CR_D2CKRDY   RCC_CR_D2CKRDY_Msk
	D2 domain clocks ready flag.
#define	RCC_CR_HSEON_Pos   (16U)
#define	RCC_CR_HSEON_Msk   (0x1UL << RCC_CR_HSEON_Pos)
	0x00010000
#define	RCC_CR_HSEON   RCC_CR_HSEON_Msk
	External High Speed clock enable.
#define	RCC_CR_HSERDY_Pos   (17U)
#define	RCC_CR_HSERDY_Msk   (0x1UL << RCC_CR_HSERDY_Pos)
	0x00020000
#define	RCC_CR_HSERDY   RCC_CR_HSERDY_Msk
	External High Speed clock ready.
#define	RCC_CR_HSEBYP_Pos   (18U)
#define	RCC_CR_HSEBYP_Msk   (0x1UL << RCC_CR_HSEBYP_Pos)
	0x00040000
#define	RCC_CR_HSEBYP   RCC_CR_HSEBYP_Msk
	External High Speed clock Bypass.
#define	RCC_CR_CSSHSEON_Pos   (19U)
#define	RCC_CR_CSSHSEON_Msk   (0x1UL << RCC_CR_CSSHSEON_Pos)
	0x00080000
#define	RCC_CR_CSSHSEON   RCC_CR_CSSHSEON_Msk
	HSE Clock security System enable.
#define	RCC_CR_PLL1ON_Pos   (24U)
#define	RCC_CR_PLL1ON_Msk   (0x1UL << RCC_CR_PLL1ON_Pos)
	0x01000000
#define	RCC_CR_PLL1ON   RCC_CR_PLL1ON_Msk
	System PLL1 clock enable.
#define	RCC_CR_PLL1RDY_Pos   (25U)
#define	RCC_CR_PLL1RDY_Msk   (0x1UL << RCC_CR_PLL1RDY_Pos)
	0x02000000
#define	RCC_CR_PLL1RDY   RCC_CR_PLL1RDY_Msk
	System PLL1 clock ready.
#define	RCC_CR_PLL2ON_Pos   (26U)
#define	RCC_CR_PLL2ON_Msk   (0x1UL << RCC_CR_PLL2ON_Pos)
	0x04000000
#define	RCC_CR_PLL2ON   RCC_CR_PLL2ON_Msk
	System PLL2 clock enable.
#define	RCC_CR_PLL2RDY_Pos   (27U)
#define	RCC_CR_PLL2RDY_Msk   (0x1UL << RCC_CR_PLL2RDY_Pos)
	0x08000000
#define	RCC_CR_PLL2RDY   RCC_CR_PLL2RDY_Msk
	System PLL2 clock ready.
#define	RCC_CR_PLL3ON_Pos   (28U)
#define	RCC_CR_PLL3ON_Msk   (0x1UL << RCC_CR_PLL3ON_Pos)
	0x10000000
#define	RCC_CR_PLL3ON   RCC_CR_PLL3ON_Msk
	System PLL3 clock enable.
#define	RCC_CR_PLL3RDY_Pos   (29U)
#define	RCC_CR_PLL3RDY_Msk   (0x1UL << RCC_CR_PLL3RDY_Pos)
	0x20000000
#define	RCC_CR_PLL3RDY   RCC_CR_PLL3RDY_Msk
	System PLL3 clock ready.
#define	RCC_CR_PLLON_Pos   (24U)
#define	RCC_CR_PLLON_Msk   (0x1UL << RCC_CR_PLLON_Pos)
	0x01000000
#define	RCC_CR_PLLON   RCC_CR_PLLON_Msk
	System PLL clock enable.
#define	RCC_CR_PLLRDY_Pos   (25U)
#define	RCC_CR_PLLRDY_Msk   (0x1UL << RCC_CR_PLLRDY_Pos)
	0x02000000
#define	RCC_CR_PLLRDY   RCC_CR_PLLRDY_Msk
	System PLL clock ready.
#define	RCC_HSICFGR_HSICAL_Pos   (0U)
	< HSICAL configuration
#define	RCC_HSICFGR_HSICAL_Msk   (0xFFFUL << RCC_HSICFGR_HSICAL_Pos)
	0x00000FFF
#define	RCC_HSICFGR_HSICAL   RCC_HSICFGR_HSICAL_Msk
	HSICAL[11:0] bits.
#define	RCC_HSICFGR_HSICAL_0   (0x001UL << RCC_HSICFGR_HSICAL_Pos)
	0x00000001
#define	RCC_HSICFGR_HSICAL_1   (0x002UL << RCC_HSICFGR_HSICAL_Pos)
	0x00000002
#define	RCC_HSICFGR_HSICAL_2   (0x004UL << RCC_HSICFGR_HSICAL_Pos)
	0x00000004
#define	RCC_HSICFGR_HSICAL_3   (0x008UL << RCC_HSICFGR_HSICAL_Pos)
	0x00000008
#define	RCC_HSICFGR_HSICAL_4   (0x010UL << RCC_HSICFGR_HSICAL_Pos)
	0x00000010
#define	RCC_HSICFGR_HSICAL_5   (0x020UL << RCC_HSICFGR_HSICAL_Pos)
	0x00000020
#define	RCC_HSICFGR_HSICAL_6   (0x040UL << RCC_HSICFGR_HSICAL_Pos)
	0x00000040
#define	RCC_HSICFGR_HSICAL_7   (0x080UL << RCC_HSICFGR_HSICAL_Pos)
	0x00000080
#define	RCC_HSICFGR_HSICAL_8   (0x100UL << RCC_HSICFGR_HSICAL_Pos)
	0x00000100
#define	RCC_HSICFGR_HSICAL_9   (0x200UL << RCC_HSICFGR_HSICAL_Pos)
	0x00000200
#define	RCC_HSICFGR_HSICAL_10   (0x400UL << RCC_HSICFGR_HSICAL_Pos)
	0x00000400
#define	RCC_HSICFGR_HSICAL_11   (0x800UL << RCC_HSICFGR_HSICAL_Pos)
	0x00000800
#define	RCC_HSICFGR_HSITRIM_Pos   (24U)
#define	RCC_HSICFGR_HSITRIM_Msk   (0x7FUL << RCC_HSICFGR_HSITRIM_Pos)
	0x7F000000
#define	RCC_HSICFGR_HSITRIM   RCC_HSICFGR_HSITRIM_Msk
	HSITRIM[6:0] bits.
#define	RCC_HSICFGR_HSITRIM_0   (0x01UL << RCC_HSICFGR_HSITRIM_Pos)
	0x01000000
#define	RCC_HSICFGR_HSITRIM_1   (0x02UL << RCC_HSICFGR_HSITRIM_Pos)
	0x02000000
#define	RCC_HSICFGR_HSITRIM_2   (0x04UL << RCC_HSICFGR_HSITRIM_Pos)
	0x04000000
#define	RCC_HSICFGR_HSITRIM_3   (0x08UL << RCC_HSICFGR_HSITRIM_Pos)
	0x08000000
#define	RCC_HSICFGR_HSITRIM_4   (0x10UL << RCC_HSICFGR_HSITRIM_Pos)
	0x10000000
#define	RCC_HSICFGR_HSITRIM_5   (0x20UL << RCC_HSICFGR_HSITRIM_Pos)
	0x20000000
#define	RCC_HSICFGR_HSITRIM_6   (0x40UL << RCC_HSICFGR_HSITRIM_Pos)
	0x40000000
#define	RCC_CRRCR_HSI48CAL_Pos   (0U)
	< HSI48CAL configuration
#define	RCC_CRRCR_HSI48CAL_Msk   (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos)
	0x000003FF
#define	RCC_CRRCR_HSI48CAL   RCC_CRRCR_HSI48CAL_Msk
	HSI48CAL[9:0] bits.
#define	RCC_CRRCR_HSI48CAL_0   (0x001UL << RCC_CRRCR_HSI48CAL_Pos)
	0x00000001
#define	RCC_CRRCR_HSI48CAL_1   (0x002UL << RCC_CRRCR_HSI48CAL_Pos)
	0x00000002
#define	RCC_CRRCR_HSI48CAL_2   (0x004UL << RCC_CRRCR_HSI48CAL_Pos)
	0x00000004
#define	RCC_CRRCR_HSI48CAL_3   (0x008UL << RCC_CRRCR_HSI48CAL_Pos)
	0x00000008
#define	RCC_CRRCR_HSI48CAL_4   (0x010UL << RCC_CRRCR_HSI48CAL_Pos)
	0x00000010
#define	RCC_CRRCR_HSI48CAL_5   (0x020UL << RCC_CRRCR_HSI48CAL_Pos)
	0x00000020
#define	RCC_CRRCR_HSI48CAL_6   (0x040UL << RCC_CRRCR_HSI48CAL_Pos)
	0x00000040
#define	RCC_CRRCR_HSI48CAL_7   (0x080UL << RCC_CRRCR_HSI48CAL_Pos)
	0x00000080
#define	RCC_CRRCR_HSI48CAL_8   (0x100UL << RCC_CRRCR_HSI48CAL_Pos)
	0x00000100
#define	RCC_CRRCR_HSI48CAL_9   (0x200UL << RCC_CRRCR_HSI48CAL_Pos)
	0x00000200
#define	RCC_CSICFGR_CSICAL_Pos   (0U)
	< CSICAL configuration
#define	RCC_CSICFGR_CSICAL_Msk   (0xFFUL << RCC_CSICFGR_CSICAL_Pos)
	0x000000FF
#define	RCC_CSICFGR_CSICAL   RCC_CSICFGR_CSICAL_Msk
	CSICAL[7:0] bits.
#define	RCC_CSICFGR_CSICAL_0   (0x01UL << RCC_CSICFGR_CSICAL_Pos)
	0x00000001
#define	RCC_CSICFGR_CSICAL_1   (0x02UL << RCC_CSICFGR_CSICAL_Pos)
	0x00000002
#define	RCC_CSICFGR_CSICAL_2   (0x04UL << RCC_CSICFGR_CSICAL_Pos)
	0x00000004
#define	RCC_CSICFGR_CSICAL_3   (0x08UL << RCC_CSICFGR_CSICAL_Pos)
	0x00000008
#define	RCC_CSICFGR_CSICAL_4   (0x10UL << RCC_CSICFGR_CSICAL_Pos)
	0x00000010
#define	RCC_CSICFGR_CSICAL_5   (0x20UL << RCC_CSICFGR_CSICAL_Pos)
	0x00000020
#define	RCC_CSICFGR_CSICAL_6   (0x40UL << RCC_CSICFGR_CSICAL_Pos)
	0x00000040
#define	RCC_CSICFGR_CSICAL_7   (0x80UL << RCC_CSICFGR_CSICAL_Pos)
	0x00000080
#define	RCC_CSICFGR_CSITRIM_Pos   (24U)
#define	RCC_CSICFGR_CSITRIM_Msk   (0x3FUL << RCC_CSICFGR_CSITRIM_Pos)
	0x3F000000
#define	RCC_CSICFGR_CSITRIM   RCC_CSICFGR_CSITRIM_Msk
	CSITRIM[5:0] bits.
#define	RCC_CSICFGR_CSITRIM_0   (0x01UL << RCC_CSICFGR_CSITRIM_Pos)
	0x01000000
#define	RCC_CSICFGR_CSITRIM_1   (0x02UL << RCC_CSICFGR_CSITRIM_Pos)
	0x02000000
#define	RCC_CSICFGR_CSITRIM_2   (0x04UL << RCC_CSICFGR_CSITRIM_Pos)
	0x04000000
#define	RCC_CSICFGR_CSITRIM_3   (0x08UL << RCC_CSICFGR_CSITRIM_Pos)
	0x08000000
#define	RCC_CSICFGR_CSITRIM_4   (0x10UL << RCC_CSICFGR_CSITRIM_Pos)
	0x10000000
#define	RCC_CSICFGR_CSITRIM_5   (0x20UL << RCC_CSICFGR_CSITRIM_Pos)
	0x20000000
#define	RCC_CFGR_SW_Pos   (0U)
	< SW configuration
#define	RCC_CFGR_SW_Msk   (0x7UL << RCC_CFGR_SW_Pos)
	0x00000007
#define	RCC_CFGR_SW   RCC_CFGR_SW_Msk
	SW[2:0] bits (System clock Switch).
#define	RCC_CFGR_SW_0   (0x1UL << RCC_CFGR_SW_Pos)
	0x00000001
#define	RCC_CFGR_SW_1   (0x2UL << RCC_CFGR_SW_Pos)
	0x00000002
#define	RCC_CFGR_SW_2   (0x4UL << RCC_CFGR_SW_Pos)
	0x00000004
#define	RCC_CFGR_SW_HSI   (0x00000000UL)
	HSI selection as system clock.
#define	RCC_CFGR_SW_CSI   (0x00000001UL)
	CSI selection as system clock.
#define	RCC_CFGR_SW_HSE   (0x00000002UL)
	HSE selection as system clock.
#define	RCC_CFGR_SW_PLL1   (0x00000003UL)
	PLL1 selection as system clock.
#define	RCC_CFGR_SWS_Pos   (3U)
#define	RCC_CFGR_SWS_Msk   (0x7UL << RCC_CFGR_SWS_Pos)
	0x00000038
#define	RCC_CFGR_SWS   RCC_CFGR_SWS_Msk
	SWS[2:0] bits (System Clock Switch Status).
#define	RCC_CFGR_SWS_0   (0x1UL << RCC_CFGR_SWS_Pos)
	0x00000008
#define	RCC_CFGR_SWS_1   (0x2UL << RCC_CFGR_SWS_Pos)
	0x00000010
#define	RCC_CFGR_SWS_2   (0x4UL << RCC_CFGR_SWS_Pos)
	0x00000020
#define	RCC_CFGR_SWS_HSI   (0x00000000UL)
	HSI used as system clock.
#define	RCC_CFGR_SWS_CSI   (0x00000008UL)
	CSI used as system clock.
#define	RCC_CFGR_SWS_HSE   (0x00000010UL)
	HSE used as system clock.
#define	RCC_CFGR_SWS_PLL1   (0x00000018UL)
	PLL1 used as system clock.
#define	RCC_CFGR_STOPWUCK_Pos   (6U)
#define	RCC_CFGR_STOPWUCK_Msk   (0x1UL << RCC_CFGR_STOPWUCK_Pos)
	0x00000040
#define	RCC_CFGR_STOPWUCK   RCC_CFGR_STOPWUCK_Msk
	Wake Up from stop and CSS backup clock selection.
#define	RCC_CFGR_STOPKERWUCK_Pos   (7U)
#define	RCC_CFGR_STOPKERWUCK_Msk   (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)
	0x00000080
#define	RCC_CFGR_STOPKERWUCK   RCC_CFGR_STOPKERWUCK_Msk
	Kernel Clock Selection after a Wake Up from STOP.
#define	RCC_CFGR_RTCPRE_Pos   (8U)
#define	RCC_CFGR_RTCPRE_Msk   (0x3FUL << RCC_CFGR_RTCPRE_Pos)
#define	RCC_CFGR_RTCPRE   RCC_CFGR_RTCPRE_Msk
	0x00003F00
#define	RCC_CFGR_RTCPRE_0   (0x1UL << RCC_CFGR_RTCPRE_Pos)
	0x00000100
#define	RCC_CFGR_RTCPRE_1   (0x2UL << RCC_CFGR_RTCPRE_Pos)
	0x00000200
#define	RCC_CFGR_RTCPRE_2   (0x4UL << RCC_CFGR_RTCPRE_Pos)
	0x00000400
#define	RCC_CFGR_RTCPRE_3   (0x8UL << RCC_CFGR_RTCPRE_Pos)
	0x00000800
#define	RCC_CFGR_RTCPRE_4   (0x10UL << RCC_CFGR_RTCPRE_Pos)
	0x00001000
#define	RCC_CFGR_RTCPRE_5   (0x20UL << RCC_CFGR_RTCPRE_Pos)
	0x00002000
#define	RCC_CFGR_TIMPRE_Pos   (15U)
#define	RCC_CFGR_TIMPRE_Msk   (0x1UL << RCC_CFGR_TIMPRE_Pos)
#define	RCC_CFGR_TIMPRE   RCC_CFGR_TIMPRE_Msk
	0x00008000
#define	RCC_CFGR_MCO1_Pos   (22U)
#define	RCC_CFGR_MCO1_Msk   (0x7UL << RCC_CFGR_MCO1_Pos)
#define	RCC_CFGR_MCO1   RCC_CFGR_MCO1_Msk
	0x01C00000
#define	RCC_CFGR_MCO1_0   (0x1UL << RCC_CFGR_MCO1_Pos)
	0x00400000
#define	RCC_CFGR_MCO1_1   (0x2UL << RCC_CFGR_MCO1_Pos)
	0x00800000
#define	RCC_CFGR_MCO1_2   (0x4UL << RCC_CFGR_MCO1_Pos)
	0x01000000
#define	RCC_CFGR_MCO1PRE_Pos   (18U)
#define	RCC_CFGR_MCO1PRE_Msk   (0xFUL << RCC_CFGR_MCO1PRE_Pos)
#define	RCC_CFGR_MCO1PRE   RCC_CFGR_MCO1PRE_Msk
	0x003C0000
#define	RCC_CFGR_MCO1PRE_0   (0x1UL << RCC_CFGR_MCO1PRE_Pos)
	0x00040000
#define	RCC_CFGR_MCO1PRE_1   (0x2UL << RCC_CFGR_MCO1PRE_Pos)
	0x00080000
#define	RCC_CFGR_MCO1PRE_2   (0x4UL << RCC_CFGR_MCO1PRE_Pos)
	0x00100000
#define	RCC_CFGR_MCO1PRE_3   (0x8UL << RCC_CFGR_MCO1PRE_Pos)
	0x00200000
#define	RCC_CFGR_MCO2PRE_Pos   (25U)
#define	RCC_CFGR_MCO2PRE_Msk   (0xFUL << RCC_CFGR_MCO2PRE_Pos)
#define	RCC_CFGR_MCO2PRE   RCC_CFGR_MCO2PRE_Msk
	0x1E000000
#define	RCC_CFGR_MCO2PRE_0   (0x1UL << RCC_CFGR_MCO2PRE_Pos)
	0x02000000
#define	RCC_CFGR_MCO2PRE_1   (0x2UL << RCC_CFGR_MCO2PRE_Pos)
	0x04000000
#define	RCC_CFGR_MCO2PRE_2   (0x4UL << RCC_CFGR_MCO2PRE_Pos)
	0x08000000
#define	RCC_CFGR_MCO2PRE_3   (0x8UL << RCC_CFGR_MCO2PRE_Pos)
	0x10000000
#define	RCC_CFGR_MCO2_Pos   (29U)
#define	RCC_CFGR_MCO2_Msk   (0x7UL << RCC_CFGR_MCO2_Pos)
#define	RCC_CFGR_MCO2   RCC_CFGR_MCO2_Msk
	0xE0000000
#define	RCC_CFGR_MCO2_0   (0x1UL << RCC_CFGR_MCO2_Pos)
	0x20000000
#define	RCC_CFGR_MCO2_1   (0x2UL << RCC_CFGR_MCO2_Pos)
	0x40000000
#define	RCC_CFGR_MCO2_2   (0x4UL << RCC_CFGR_MCO2_Pos)
	0x80000000
#define	RCC_D1CFGR_HPRE_Pos   (0U)
	< D1HPRE configuration
#define	RCC_D1CFGR_HPRE_Msk   (0xFUL << RCC_D1CFGR_HPRE_Pos)
	0x0000000F
#define	RCC_D1CFGR_HPRE   RCC_D1CFGR_HPRE_Msk
	HPRE[3:0] bits (AHB3 prescaler).
#define	RCC_D1CFGR_HPRE_0   (0x1UL << RCC_D1CFGR_HPRE_Pos)
	0x00000001
#define	RCC_D1CFGR_HPRE_1   (0x2UL << RCC_D1CFGR_HPRE_Pos)
	0x00000002
#define	RCC_D1CFGR_HPRE_2   (0x4UL << RCC_D1CFGR_HPRE_Pos)
	0x00000004
#define	RCC_D1CFGR_HPRE_3   (0x8UL << RCC_D1CFGR_HPRE_Pos)
	0x00000008
#define	RCC_D1CFGR_HPRE_DIV1   (0U)
	AHB3 Clock not divided.
#define	RCC_D1CFGR_HPRE_DIV2_Pos   (3U)
#define	RCC_D1CFGR_HPRE_DIV2_Msk   (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos)
	0x00000008
#define	RCC_D1CFGR_HPRE_DIV2   RCC_D1CFGR_HPRE_DIV2_Msk
	AHB3 Clock divided by 2.
#define	RCC_D1CFGR_HPRE_DIV4_Pos   (0U)
#define	RCC_D1CFGR_HPRE_DIV4_Msk   (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos)
	0x00000009
#define	RCC_D1CFGR_HPRE_DIV4   RCC_D1CFGR_HPRE_DIV4_Msk
	AHB3 Clock divided by 4.
#define	RCC_D1CFGR_HPRE_DIV8_Pos   (1U)
#define	RCC_D1CFGR_HPRE_DIV8_Msk   (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos)
	0x0000000A
#define	RCC_D1CFGR_HPRE_DIV8   RCC_D1CFGR_HPRE_DIV8_Msk
	AHB3 Clock divided by 8.
#define	RCC_D1CFGR_HPRE_DIV16_Pos   (0U)
#define	RCC_D1CFGR_HPRE_DIV16_Msk   (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos)
	0x0000000B
#define	RCC_D1CFGR_HPRE_DIV16   RCC_D1CFGR_HPRE_DIV16_Msk
	AHB3 Clock divided by 16.
#define	RCC_D1CFGR_HPRE_DIV64_Pos   (2U)
#define	RCC_D1CFGR_HPRE_DIV64_Msk   (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos)
	0x0000000C
#define	RCC_D1CFGR_HPRE_DIV64   RCC_D1CFGR_HPRE_DIV64_Msk
	AHB3 Clock divided by 64.
#define	RCC_D1CFGR_HPRE_DIV128_Pos   (0U)
#define	RCC_D1CFGR_HPRE_DIV128_Msk   (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos)
	0x0000000D
#define	RCC_D1CFGR_HPRE_DIV128   RCC_D1CFGR_HPRE_DIV128_Msk
	AHB3 Clock divided by 128.
#define	RCC_D1CFGR_HPRE_DIV256_Pos   (1U)
#define	RCC_D1CFGR_HPRE_DIV256_Msk   (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos)
	0x0000000E
#define	RCC_D1CFGR_HPRE_DIV256   RCC_D1CFGR_HPRE_DIV256_Msk
	AHB3 Clock divided by 256.
#define	RCC_D1CFGR_HPRE_DIV512_Pos   (0U)
#define	RCC_D1CFGR_HPRE_DIV512_Msk   (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos)
	0x0000000F
#define	RCC_D1CFGR_HPRE_DIV512   RCC_D1CFGR_HPRE_DIV512_Msk
	AHB3 Clock divided by 512.
#define	RCC_D1CFGR_D1PPRE_Pos   (4U)
#define	RCC_D1CFGR_D1PPRE_Msk   (0x7UL << RCC_D1CFGR_D1PPRE_Pos)
	0x00000070
#define	RCC_D1CFGR_D1PPRE   RCC_D1CFGR_D1PPRE_Msk
	D1PRE[2:0] bits (APB3 prescaler).
#define	RCC_D1CFGR_D1PPRE_0   (0x1UL << RCC_D1CFGR_D1PPRE_Pos)
	0x00000010
#define	RCC_D1CFGR_D1PPRE_1   (0x2UL << RCC_D1CFGR_D1PPRE_Pos)
	0x00000020
#define	RCC_D1CFGR_D1PPRE_2   (0x4UL << RCC_D1CFGR_D1PPRE_Pos)
	0x00000040
#define	RCC_D1CFGR_D1PPRE_DIV1   (0U)
	APB3 clock not divided.
#define	RCC_D1CFGR_D1PPRE_DIV2_Pos   (6U)
#define	RCC_D1CFGR_D1PPRE_DIV2_Msk   (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos)
	0x00000040
#define	RCC_D1CFGR_D1PPRE_DIV2   RCC_D1CFGR_D1PPRE_DIV2_Msk
	APB3 clock divided by 2.
#define	RCC_D1CFGR_D1PPRE_DIV4_Pos   (4U)
#define	RCC_D1CFGR_D1PPRE_DIV4_Msk   (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos)
	0x00000050
#define	RCC_D1CFGR_D1PPRE_DIV4   RCC_D1CFGR_D1PPRE_DIV4_Msk
	APB3 clock divided by 4.
#define	RCC_D1CFGR_D1PPRE_DIV8_Pos   (5U)
#define	RCC_D1CFGR_D1PPRE_DIV8_Msk   (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos)
	0x00000060
#define	RCC_D1CFGR_D1PPRE_DIV8   RCC_D1CFGR_D1PPRE_DIV8_Msk
	APB3 clock divided by 8.
#define	RCC_D1CFGR_D1PPRE_DIV16_Pos   (4U)
#define	RCC_D1CFGR_D1PPRE_DIV16_Msk   (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos)
	0x00000070
#define	RCC_D1CFGR_D1PPRE_DIV16   RCC_D1CFGR_D1PPRE_DIV16_Msk
	APB3 clock divided by 16.
#define	RCC_D1CFGR_D1CPRE_Pos   (8U)
#define	RCC_D1CFGR_D1CPRE_Msk   (0xFUL << RCC_D1CFGR_D1CPRE_Pos)
	0x00000F00
#define	RCC_D1CFGR_D1CPRE   RCC_D1CFGR_D1CPRE_Msk
	D1CPRE[2:0] bits (Domain 1 Core prescaler).
#define	RCC_D1CFGR_D1CPRE_0   (0x1UL << RCC_D1CFGR_D1CPRE_Pos)
	0x00000100
#define	RCC_D1CFGR_D1CPRE_1   (0x2UL << RCC_D1CFGR_D1CPRE_Pos)
	0x00000200
#define	RCC_D1CFGR_D1CPRE_2   (0x4UL << RCC_D1CFGR_D1CPRE_Pos)
	0x00000400
#define	RCC_D1CFGR_D1CPRE_3   (0x8UL << RCC_D1CFGR_D1CPRE_Pos)
	0x00000800
#define	RCC_D1CFGR_D1CPRE_DIV1   (0U)
	Domain 1 Core clock not divided.
#define	RCC_D1CFGR_D1CPRE_DIV2_Pos   (11U)
#define	RCC_D1CFGR_D1CPRE_DIV2_Msk   (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos)
	0x00000800
#define	RCC_D1CFGR_D1CPRE_DIV2   RCC_D1CFGR_D1CPRE_DIV2_Msk
	Domain 1 Core clock divided by 2.
#define	RCC_D1CFGR_D1CPRE_DIV4_Pos   (8U)
#define	RCC_D1CFGR_D1CPRE_DIV4_Msk   (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos)
	0x00000900
#define	RCC_D1CFGR_D1CPRE_DIV4   RCC_D1CFGR_D1CPRE_DIV4_Msk
	Domain 1 Core clock divided by 4.
#define	RCC_D1CFGR_D1CPRE_DIV8_Pos   (9U)
#define	RCC_D1CFGR_D1CPRE_DIV8_Msk   (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos)
	0x00000A00
#define	RCC_D1CFGR_D1CPRE_DIV8   RCC_D1CFGR_D1CPRE_DIV8_Msk
	Domain 1 Core clock divided by 8.
#define	RCC_D1CFGR_D1CPRE_DIV16_Pos   (8U)
#define	RCC_D1CFGR_D1CPRE_DIV16_Msk   (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos)
	0x00000B00
#define	RCC_D1CFGR_D1CPRE_DIV16   RCC_D1CFGR_D1CPRE_DIV16_Msk
	Domain 1 Core clock divided by 16.
#define	RCC_D1CFGR_D1CPRE_DIV64_Pos   (10U)
#define	RCC_D1CFGR_D1CPRE_DIV64_Msk   (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos)
	0x00000C00
#define	RCC_D1CFGR_D1CPRE_DIV64   RCC_D1CFGR_D1CPRE_DIV64_Msk
	Domain 1 Core clock divided by 64.
#define	RCC_D1CFGR_D1CPRE_DIV128_Pos   (8U)
#define	RCC_D1CFGR_D1CPRE_DIV128_Msk   (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos)
	0x00000D00
#define	RCC_D1CFGR_D1CPRE_DIV128   RCC_D1CFGR_D1CPRE_DIV128_Msk
	Domain 1 Core clock divided by 128.
#define	RCC_D1CFGR_D1CPRE_DIV256_Pos   (9U)
#define	RCC_D1CFGR_D1CPRE_DIV256_Msk   (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos)
	0x00000E00
#define	RCC_D1CFGR_D1CPRE_DIV256   RCC_D1CFGR_D1CPRE_DIV256_Msk
	Domain 1 Core clock divided by 256.
#define	RCC_D1CFGR_D1CPRE_DIV512_Pos   (8U)
#define	RCC_D1CFGR_D1CPRE_DIV512_Msk   (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos)
	0x00000F00
#define	RCC_D1CFGR_D1CPRE_DIV512   RCC_D1CFGR_D1CPRE_DIV512_Msk
	Domain 1 Core clock divided by 512.
#define	RCC_D2CFGR_D2PPRE1_Pos   (4U)
	< D2PPRE1 configuration
#define	RCC_D2CFGR_D2PPRE1_Msk   (0x7UL << RCC_D2CFGR_D2PPRE1_Pos)
	0x00000070
#define	RCC_D2CFGR_D2PPRE1   RCC_D2CFGR_D2PPRE1_Msk
	D1PPRE1[2:0] bits (APB1 prescaler).
#define	RCC_D2CFGR_D2PPRE1_0   (0x1UL << RCC_D2CFGR_D2PPRE1_Pos)
	0x00000010
#define	RCC_D2CFGR_D2PPRE1_1   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos)
	0x00000020
#define	RCC_D2CFGR_D2PPRE1_2   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos)
	0x00000040
#define	RCC_D2CFGR_D2PPRE1_DIV1   (0U)
	APB1 clock not divided.
#define	RCC_D2CFGR_D2PPRE1_DIV2_Pos   (6U)
#define	RCC_D2CFGR_D2PPRE1_DIV2_Msk   (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos)
	0x00000040
#define	RCC_D2CFGR_D2PPRE1_DIV2   RCC_D2CFGR_D2PPRE1_DIV2_Msk
	APB1 clock divided by 2.
#define	RCC_D2CFGR_D2PPRE1_DIV4_Pos   (4U)
#define	RCC_D2CFGR_D2PPRE1_DIV4_Msk   (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos)
	0x00000050
#define	RCC_D2CFGR_D2PPRE1_DIV4   RCC_D2CFGR_D2PPRE1_DIV4_Msk
	APB1 clock divided by 4.
#define	RCC_D2CFGR_D2PPRE1_DIV8_Pos   (5U)
#define	RCC_D2CFGR_D2PPRE1_DIV8_Msk   (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos)
	0x00000060
#define	RCC_D2CFGR_D2PPRE1_DIV8   RCC_D2CFGR_D2PPRE1_DIV8_Msk
	APB1 clock divided by 8.
#define	RCC_D2CFGR_D2PPRE1_DIV16_Pos   (4U)
#define	RCC_D2CFGR_D2PPRE1_DIV16_Msk   (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos)
	0x00000070
#define	RCC_D2CFGR_D2PPRE1_DIV16   RCC_D2CFGR_D2PPRE1_DIV16_Msk
	APB1 clock divided by 16.
#define	RCC_D2CFGR_D2PPRE2_Pos   (8U)
#define	RCC_D2CFGR_D2PPRE2_Msk   (0x7UL << RCC_D2CFGR_D2PPRE2_Pos)
	0x00000700
#define	RCC_D2CFGR_D2PPRE2   RCC_D2CFGR_D2PPRE2_Msk
	D2PPRE2[2:0] bits (APB2 prescaler).
#define	RCC_D2CFGR_D2PPRE2_0   (0x1UL << RCC_D2CFGR_D2PPRE2_Pos)
	0x00000100
#define	RCC_D2CFGR_D2PPRE2_1   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos)
	0x00000200
#define	RCC_D2CFGR_D2PPRE2_2   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos)
	0x00000400
#define	RCC_D2CFGR_D2PPRE2_DIV1   (0U)
	APB2 clock not divided.
#define	RCC_D2CFGR_D2PPRE2_DIV2_Pos   (10U)
#define	RCC_D2CFGR_D2PPRE2_DIV2_Msk   (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos)
	0x00000400
#define	RCC_D2CFGR_D2PPRE2_DIV2   RCC_D2CFGR_D2PPRE2_DIV2_Msk
	APB2 clock divided by 2.
#define	RCC_D2CFGR_D2PPRE2_DIV4_Pos   (8U)
#define	RCC_D2CFGR_D2PPRE2_DIV4_Msk   (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos)
	0x00000500
#define	RCC_D2CFGR_D2PPRE2_DIV4   RCC_D2CFGR_D2PPRE2_DIV4_Msk
	APB2 clock divided by 4.
#define	RCC_D2CFGR_D2PPRE2_DIV8_Pos   (9U)
#define	RCC_D2CFGR_D2PPRE2_DIV8_Msk   (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos)
	0x00000600
#define	RCC_D2CFGR_D2PPRE2_DIV8   RCC_D2CFGR_D2PPRE2_DIV8_Msk
	APB2 clock divided by 8.
#define	RCC_D2CFGR_D2PPRE2_DIV16_Pos   (8U)
#define	RCC_D2CFGR_D2PPRE2_DIV16_Msk   (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos)
	0x00000700
#define	RCC_D2CFGR_D2PPRE2_DIV16   RCC_D2CFGR_D2PPRE2_DIV16_Msk
	APB2 clock divided by 16.
#define	RCC_D3CFGR_D3PPRE_Pos   (4U)
	< D3PPRE configuration
#define	RCC_D3CFGR_D3PPRE_Msk   (0x7UL << RCC_D3CFGR_D3PPRE_Pos)
	0x00000070
#define	RCC_D3CFGR_D3PPRE   RCC_D3CFGR_D3PPRE_Msk
	D3PPRE1[2:0] bits (APB4 prescaler).
#define	RCC_D3CFGR_D3PPRE_0   (0x1UL << RCC_D3CFGR_D3PPRE_Pos)
	0x00000010
#define	RCC_D3CFGR_D3PPRE_1   (0x2UL << RCC_D3CFGR_D3PPRE_Pos)
	0x00000020
#define	RCC_D3CFGR_D3PPRE_2   (0x4UL << RCC_D3CFGR_D3PPRE_Pos)
	0x00000040
#define	RCC_D3CFGR_D3PPRE_DIV1   (0U)
	APB4 clock not divided.
#define	RCC_D3CFGR_D3PPRE_DIV2_Pos   (6U)
#define	RCC_D3CFGR_D3PPRE_DIV2_Msk   (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos)
	0x00000040
#define	RCC_D3CFGR_D3PPRE_DIV2   RCC_D3CFGR_D3PPRE_DIV2_Msk
	APB4 clock divided by 2.
#define	RCC_D3CFGR_D3PPRE_DIV4_Pos   (4U)
#define	RCC_D3CFGR_D3PPRE_DIV4_Msk   (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos)
	0x00000050
#define	RCC_D3CFGR_D3PPRE_DIV4   RCC_D3CFGR_D3PPRE_DIV4_Msk
	APB4 clock divided by 4.
#define	RCC_D3CFGR_D3PPRE_DIV8_Pos   (5U)
#define	RCC_D3CFGR_D3PPRE_DIV8_Msk   (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos)
	0x00000060
#define	RCC_D3CFGR_D3PPRE_DIV8   RCC_D3CFGR_D3PPRE_DIV8_Msk
	APB4 clock divided by 8.
#define	RCC_D3CFGR_D3PPRE_DIV16_Pos   (4U)
#define	RCC_D3CFGR_D3PPRE_DIV16_Msk   (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos)
	0x00000070
#define	RCC_D3CFGR_D3PPRE_DIV16   RCC_D3CFGR_D3PPRE_DIV16_Msk
	APB4 clock divided by 16.
#define	RCC_PLLCKSELR_PLLSRC_Pos   (0U)
#define	RCC_PLLCKSELR_PLLSRC_Msk   (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos)
	0x00000003
#define	RCC_PLLCKSELR_PLLSRC   RCC_PLLCKSELR_PLLSRC_Msk
#define	RCC_PLLCKSELR_PLLSRC_HSI   (0U)
	HSI source clock selected.
#define	RCC_PLLCKSELR_PLLSRC_CSI_Pos   (0U)
#define	RCC_PLLCKSELR_PLLSRC_CSI_Msk   (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos)
	0x00000001
#define	RCC_PLLCKSELR_PLLSRC_CSI   RCC_PLLCKSELR_PLLSRC_CSI_Msk
	CSI source clock selected.
#define	RCC_PLLCKSELR_PLLSRC_HSE_Pos   (1U)
#define	RCC_PLLCKSELR_PLLSRC_HSE_Msk   (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos)
	0x00000002
#define	RCC_PLLCKSELR_PLLSRC_HSE   RCC_PLLCKSELR_PLLSRC_HSE_Msk
	HSE source clock selected.
#define	RCC_PLLCKSELR_PLLSRC_NONE_Pos   (0U)
#define	RCC_PLLCKSELR_PLLSRC_NONE_Msk   (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos)
	0x00000003
#define	RCC_PLLCKSELR_PLLSRC_NONE   RCC_PLLCKSELR_PLLSRC_NONE_Msk
	No source clock selected.
#define	RCC_PLLCKSELR_DIVM1_Pos   (4U)
#define	RCC_PLLCKSELR_DIVM1_Msk   (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos)
	0x000003F0
#define	RCC_PLLCKSELR_DIVM1   RCC_PLLCKSELR_DIVM1_Msk
#define	RCC_PLLCKSELR_DIVM1_0   (0x01UL << RCC_PLLCKSELR_DIVM1_Pos)
	0x00000010
#define	RCC_PLLCKSELR_DIVM1_1   (0x02UL << RCC_PLLCKSELR_DIVM1_Pos)
	0x00000020
#define	RCC_PLLCKSELR_DIVM1_2   (0x04UL << RCC_PLLCKSELR_DIVM1_Pos)
	0x00000040
#define	RCC_PLLCKSELR_DIVM1_3   (0x08UL << RCC_PLLCKSELR_DIVM1_Pos)
	0x00000080
#define	RCC_PLLCKSELR_DIVM1_4   (0x10UL << RCC_PLLCKSELR_DIVM1_Pos)
	0x00000100
#define	RCC_PLLCKSELR_DIVM1_5   (0x20UL << RCC_PLLCKSELR_DIVM1_Pos)
	0x00000200
#define	RCC_PLLCKSELR_DIVM2_Pos   (12U)
#define	RCC_PLLCKSELR_DIVM2_Msk   (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos)
	0x0003F000
#define	RCC_PLLCKSELR_DIVM2   RCC_PLLCKSELR_DIVM2_Msk
#define	RCC_PLLCKSELR_DIVM2_0   (0x01UL << RCC_PLLCKSELR_DIVM2_Pos)
	0x00001000
#define	RCC_PLLCKSELR_DIVM2_1   (0x02UL << RCC_PLLCKSELR_DIVM2_Pos)
	0x00002000
#define	RCC_PLLCKSELR_DIVM2_2   (0x04UL << RCC_PLLCKSELR_DIVM2_Pos)
	0x00004000
#define	RCC_PLLCKSELR_DIVM2_3   (0x08UL << RCC_PLLCKSELR_DIVM2_Pos)
	0x00008000
#define	RCC_PLLCKSELR_DIVM2_4   (0x10UL << RCC_PLLCKSELR_DIVM2_Pos)
	0x00010000
#define	RCC_PLLCKSELR_DIVM2_5   (0x20UL << RCC_PLLCKSELR_DIVM2_Pos)
	0x00020000
#define	RCC_PLLCKSELR_DIVM3_Pos   (20U)
#define	RCC_PLLCKSELR_DIVM3_Msk   (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos)
	0x03F00000
#define	RCC_PLLCKSELR_DIVM3   RCC_PLLCKSELR_DIVM3_Msk
#define	RCC_PLLCKSELR_DIVM3_0   (0x01UL << RCC_PLLCKSELR_DIVM3_Pos)
	0x00100000
#define	RCC_PLLCKSELR_DIVM3_1   (0x02UL << RCC_PLLCKSELR_DIVM3_Pos)
	0x00200000
#define	RCC_PLLCKSELR_DIVM3_2   (0x04UL << RCC_PLLCKSELR_DIVM3_Pos)
	0x00400000
#define	RCC_PLLCKSELR_DIVM3_3   (0x08UL << RCC_PLLCKSELR_DIVM3_Pos)
	0x00800000
#define	RCC_PLLCKSELR_DIVM3_4   (0x10UL << RCC_PLLCKSELR_DIVM3_Pos)
	0x01000000
#define	RCC_PLLCKSELR_DIVM3_5   (0x20UL << RCC_PLLCKSELR_DIVM3_Pos)
	0x02000000
#define	RCC_PLLCFGR_PLL1FRACEN_Pos   (0U)
#define	RCC_PLLCFGR_PLL1FRACEN_Msk   (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos)
	0x00000001
#define	RCC_PLLCFGR_PLL1FRACEN   RCC_PLLCFGR_PLL1FRACEN_Msk
#define	RCC_PLLCFGR_PLL1VCOSEL_Pos   (1U)
#define	RCC_PLLCFGR_PLL1VCOSEL_Msk   (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos)
	0x00000002
#define	RCC_PLLCFGR_PLL1VCOSEL   RCC_PLLCFGR_PLL1VCOSEL_Msk
#define	RCC_PLLCFGR_PLL1RGE_Pos   (2U)
#define	RCC_PLLCFGR_PLL1RGE_Msk   (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos)
	0x0000000C
#define	RCC_PLLCFGR_PLL1RGE   RCC_PLLCFGR_PLL1RGE_Msk
#define	RCC_PLLCFGR_PLL1RGE_0   (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos)
	0x00000000
#define	RCC_PLLCFGR_PLL1RGE_1   (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos)
	0x00000004
#define	RCC_PLLCFGR_PLL1RGE_2   (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos)
	0x00000008
#define	RCC_PLLCFGR_PLL1RGE_3   (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos)
	0x0000000C
#define	RCC_PLLCFGR_PLL2FRACEN_Pos   (4U)
#define	RCC_PLLCFGR_PLL2FRACEN_Msk   (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos)
	0x00000010
#define	RCC_PLLCFGR_PLL2FRACEN   RCC_PLLCFGR_PLL2FRACEN_Msk
#define	RCC_PLLCFGR_PLL2VCOSEL_Pos   (5U)
#define	RCC_PLLCFGR_PLL2VCOSEL_Msk   (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos)
	0x00000020
#define	RCC_PLLCFGR_PLL2VCOSEL   RCC_PLLCFGR_PLL2VCOSEL_Msk
#define	RCC_PLLCFGR_PLL2RGE_Pos   (6U)
#define	RCC_PLLCFGR_PLL2RGE_Msk   (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos)
	0x000000C0
#define	RCC_PLLCFGR_PLL2RGE   RCC_PLLCFGR_PLL2RGE_Msk
#define	RCC_PLLCFGR_PLL2RGE_0   (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos)
	0x00000000
#define	RCC_PLLCFGR_PLL2RGE_1   (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos)
	0x00000040
#define	RCC_PLLCFGR_PLL2RGE_2   (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos)
	0x00000080
#define	RCC_PLLCFGR_PLL2RGE_3   (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos)
	0x000000C0
#define	RCC_PLLCFGR_PLL3FRACEN_Pos   (8U)
#define	RCC_PLLCFGR_PLL3FRACEN_Msk   (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos)
	0x00000100
#define	RCC_PLLCFGR_PLL3FRACEN   RCC_PLLCFGR_PLL3FRACEN_Msk
#define	RCC_PLLCFGR_PLL3VCOSEL_Pos   (9U)
#define	RCC_PLLCFGR_PLL3VCOSEL_Msk   (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos)
	0x00000200
#define	RCC_PLLCFGR_PLL3VCOSEL   RCC_PLLCFGR_PLL3VCOSEL_Msk
#define	RCC_PLLCFGR_PLL3RGE_Pos   (10U)
#define	RCC_PLLCFGR_PLL3RGE_Msk   (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos)
	0x00000C00
#define	RCC_PLLCFGR_PLL3RGE   RCC_PLLCFGR_PLL3RGE_Msk
#define	RCC_PLLCFGR_PLL3RGE_0   (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos)
	0x00000000
#define	RCC_PLLCFGR_PLL3RGE_1   (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos)
	0x00000400
#define	RCC_PLLCFGR_PLL3RGE_2   (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos)
	0x00000800
#define	RCC_PLLCFGR_PLL3RGE_3   (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos)
	0x00000C00
#define	RCC_PLLCFGR_DIVP1EN_Pos   (16U)
#define	RCC_PLLCFGR_DIVP1EN_Msk   (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos)
	0x00010000
#define	RCC_PLLCFGR_DIVP1EN   RCC_PLLCFGR_DIVP1EN_Msk
#define	RCC_PLLCFGR_DIVQ1EN_Pos   (17U)
#define	RCC_PLLCFGR_DIVQ1EN_Msk   (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos)
	0x00020000
#define	RCC_PLLCFGR_DIVQ1EN   RCC_PLLCFGR_DIVQ1EN_Msk
#define	RCC_PLLCFGR_DIVR1EN_Pos   (18U)
#define	RCC_PLLCFGR_DIVR1EN_Msk   (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos)
	0x00040000
#define	RCC_PLLCFGR_DIVR1EN   RCC_PLLCFGR_DIVR1EN_Msk
#define	RCC_PLLCFGR_DIVP2EN_Pos   (19U)
#define	RCC_PLLCFGR_DIVP2EN_Msk   (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos)
	0x00080000
#define	RCC_PLLCFGR_DIVP2EN   RCC_PLLCFGR_DIVP2EN_Msk
#define	RCC_PLLCFGR_DIVQ2EN_Pos   (20U)
#define	RCC_PLLCFGR_DIVQ2EN_Msk   (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos)
	0x00100000
#define	RCC_PLLCFGR_DIVQ2EN   RCC_PLLCFGR_DIVQ2EN_Msk
#define	RCC_PLLCFGR_DIVR2EN_Pos   (21U)
#define	RCC_PLLCFGR_DIVR2EN_Msk   (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos)
	0x00200000
#define	RCC_PLLCFGR_DIVR2EN   RCC_PLLCFGR_DIVR2EN_Msk
#define	RCC_PLLCFGR_DIVP3EN_Pos   (22U)
#define	RCC_PLLCFGR_DIVP3EN_Msk   (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos)
	0x00400000
#define	RCC_PLLCFGR_DIVP3EN   RCC_PLLCFGR_DIVP3EN_Msk
#define	RCC_PLLCFGR_DIVQ3EN_Pos   (23U)
#define	RCC_PLLCFGR_DIVQ3EN_Msk   (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos)
	0x00800000
#define	RCC_PLLCFGR_DIVQ3EN   RCC_PLLCFGR_DIVQ3EN_Msk
#define	RCC_PLLCFGR_DIVR3EN_Pos   (24U)
#define	RCC_PLLCFGR_DIVR3EN_Msk   (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos)
	0x01000000
#define	RCC_PLLCFGR_DIVR3EN   RCC_PLLCFGR_DIVR3EN_Msk
#define	RCC_PLL1DIVR_N1_Pos   (0U)
#define	RCC_PLL1DIVR_N1_Msk   (0x1FFUL << RCC_PLL1DIVR_N1_Pos)
	0x000001FF
#define	RCC_PLL1DIVR_N1   RCC_PLL1DIVR_N1_Msk
#define	RCC_PLL1DIVR_P1_Pos   (9U)
#define	RCC_PLL1DIVR_P1_Msk   (0x7FUL << RCC_PLL1DIVR_P1_Pos)
	0x0000FE00
#define	RCC_PLL1DIVR_P1   RCC_PLL1DIVR_P1_Msk
#define	RCC_PLL1DIVR_Q1_Pos   (16U)
#define	RCC_PLL1DIVR_Q1_Msk   (0x7FUL << RCC_PLL1DIVR_Q1_Pos)
	0x007F0000
#define	RCC_PLL1DIVR_Q1   RCC_PLL1DIVR_Q1_Msk
#define	RCC_PLL1DIVR_R1_Pos   (24U)
#define	RCC_PLL1DIVR_R1_Msk   (0x7FUL << RCC_PLL1DIVR_R1_Pos)
	0x7F000000
#define	RCC_PLL1DIVR_R1   RCC_PLL1DIVR_R1_Msk
#define	RCC_PLL1FRACR_FRACN1_Pos   (3U)
#define	RCC_PLL1FRACR_FRACN1_Msk   (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos)
	0x0000FFF8
#define	RCC_PLL1FRACR_FRACN1   RCC_PLL1FRACR_FRACN1_Msk
#define	RCC_PLL2DIVR_N2_Pos   (0U)
#define	RCC_PLL2DIVR_N2_Msk   (0x1FFUL << RCC_PLL2DIVR_N2_Pos)
	0x000001FF
#define	RCC_PLL2DIVR_N2   RCC_PLL2DIVR_N2_Msk
#define	RCC_PLL2DIVR_P2_Pos   (9U)
#define	RCC_PLL2DIVR_P2_Msk   (0x7FUL << RCC_PLL2DIVR_P2_Pos)
	0x0000FE00
#define	RCC_PLL2DIVR_P2   RCC_PLL2DIVR_P2_Msk
#define	RCC_PLL2DIVR_Q2_Pos   (16U)
#define	RCC_PLL2DIVR_Q2_Msk   (0x7FUL << RCC_PLL2DIVR_Q2_Pos)
	0x007F0000
#define	RCC_PLL2DIVR_Q2   RCC_PLL2DIVR_Q2_Msk
#define	RCC_PLL2DIVR_R2_Pos   (24U)
#define	RCC_PLL2DIVR_R2_Msk   (0x7FUL << RCC_PLL2DIVR_R2_Pos)
	0x7F000000
#define	RCC_PLL2DIVR_R2   RCC_PLL2DIVR_R2_Msk
#define	RCC_PLL2FRACR_FRACN2_Pos   (3U)
#define	RCC_PLL2FRACR_FRACN2_Msk   (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos)
	0x0000FFF8
#define	RCC_PLL2FRACR_FRACN2   RCC_PLL2FRACR_FRACN2_Msk
#define	RCC_PLL3DIVR_N3_Pos   (0U)
#define	RCC_PLL3DIVR_N3_Msk   (0x1FFUL << RCC_PLL3DIVR_N3_Pos)
	0x000001FF
#define	RCC_PLL3DIVR_N3   RCC_PLL3DIVR_N3_Msk
#define	RCC_PLL3DIVR_P3_Pos   (9U)
#define	RCC_PLL3DIVR_P3_Msk   (0x7FUL << RCC_PLL3DIVR_P3_Pos)
	0x0000FE00
#define	RCC_PLL3DIVR_P3   RCC_PLL3DIVR_P3_Msk
#define	RCC_PLL3DIVR_Q3_Pos   (16U)
#define	RCC_PLL3DIVR_Q3_Msk   (0x7FUL << RCC_PLL3DIVR_Q3_Pos)
	0x007F0000
#define	RCC_PLL3DIVR_Q3   RCC_PLL3DIVR_Q3_Msk
#define	RCC_PLL3DIVR_R3_Pos   (24U)
#define	RCC_PLL3DIVR_R3_Msk   (0x7FUL << RCC_PLL3DIVR_R3_Pos)
	0x7F000000
#define	RCC_PLL3DIVR_R3   RCC_PLL3DIVR_R3_Msk
#define	RCC_PLL3FRACR_FRACN3_Pos   (3U)
#define	RCC_PLL3FRACR_FRACN3_Msk   (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos)
	0x0000FFF8
#define	RCC_PLL3FRACR_FRACN3   RCC_PLL3FRACR_FRACN3_Msk
#define	RCC_D1CCIPR_FMCSEL_Pos   (0U)
#define	RCC_D1CCIPR_FMCSEL_Msk   (0x3UL << RCC_D1CCIPR_FMCSEL_Pos)
	0x00000003
#define	RCC_D1CCIPR_FMCSEL   RCC_D1CCIPR_FMCSEL_Msk
#define	RCC_D1CCIPR_FMCSEL_0   (0x1UL << RCC_D1CCIPR_FMCSEL_Pos)
	0x00000001
#define	RCC_D1CCIPR_FMCSEL_1   (0x2UL << RCC_D1CCIPR_FMCSEL_Pos)
	0x00000002
#define	RCC_D1CCIPR_OCTOSPISEL_Pos   (4U)
#define	RCC_D1CCIPR_OCTOSPISEL_Msk   (0x3UL << RCC_D1CCIPR_OCTOSPISEL_Pos)
	0x00000030
#define	RCC_D1CCIPR_OCTOSPISEL   RCC_D1CCIPR_OCTOSPISEL_Msk
#define	RCC_D1CCIPR_OCTOSPISEL_0   (0x1UL << RCC_D1CCIPR_OCTOSPISEL_Pos)
	0x00000010
#define	RCC_D1CCIPR_OCTOSPISEL_1   (0x2UL << RCC_D1CCIPR_OCTOSPISEL_Pos)
	0x00000020
#define	RCC_D1CCIPR_SDMMCSEL_Pos   (16U)
#define	RCC_D1CCIPR_SDMMCSEL_Msk   (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos)
	0x00010000
#define	RCC_D1CCIPR_SDMMCSEL   RCC_D1CCIPR_SDMMCSEL_Msk
#define	RCC_D1CCIPR_CKPERSEL_Pos   (28U)
#define	RCC_D1CCIPR_CKPERSEL_Msk   (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos)
	0x30000000
#define	RCC_D1CCIPR_CKPERSEL   RCC_D1CCIPR_CKPERSEL_Msk
#define	RCC_D1CCIPR_CKPERSEL_0   (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos)
	0x10000000
#define	RCC_D1CCIPR_CKPERSEL_1   (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos)
	0x20000000
#define	RCC_D2CCIP1R_SAI1SEL_Pos   (0U)
#define	RCC_D2CCIP1R_SAI1SEL_Msk   (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos)
	0x00000007
#define	RCC_D2CCIP1R_SAI1SEL   RCC_D2CCIP1R_SAI1SEL_Msk
#define	RCC_D2CCIP1R_SAI1SEL_0   (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos)
	0x00000001
#define	RCC_D2CCIP1R_SAI1SEL_1   (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos)
	0x00000002
#define	RCC_D2CCIP1R_SAI1SEL_2   (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos)
	0x00000004
#define	RCC_D2CCIP1R_SPI123SEL_Pos   (12U)
#define	RCC_D2CCIP1R_SPI123SEL_Msk   (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos)
	0x00007000
#define	RCC_D2CCIP1R_SPI123SEL   RCC_D2CCIP1R_SPI123SEL_Msk
#define	RCC_D2CCIP1R_SPI123SEL_0   (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos)
	0x00001000
#define	RCC_D2CCIP1R_SPI123SEL_1   (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos)
	0x00002000
#define	RCC_D2CCIP1R_SPI123SEL_2   (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos)
	0x00004000
#define	RCC_D2CCIP1R_SPI45SEL_Pos   (16U)
#define	RCC_D2CCIP1R_SPI45SEL_Msk   (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos)
	0x00070000
#define	RCC_D2CCIP1R_SPI45SEL   RCC_D2CCIP1R_SPI45SEL_Msk
#define	RCC_D2CCIP1R_SPI45SEL_0   (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos)
	0x00010000
#define	RCC_D2CCIP1R_SPI45SEL_1   (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos)
	0x00020000
#define	RCC_D2CCIP1R_SPI45SEL_2   (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos)
	0x00040000
#define	RCC_D2CCIP1R_SPDIFSEL_Pos   (20U)
#define	RCC_D2CCIP1R_SPDIFSEL_Msk   (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos)
	0x00300000
#define	RCC_D2CCIP1R_SPDIFSEL   RCC_D2CCIP1R_SPDIFSEL_Msk
#define	RCC_D2CCIP1R_SPDIFSEL_0   (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos)
	0x00100000
#define	RCC_D2CCIP1R_SPDIFSEL_1   (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos)
	0x00200000
#define	RCC_D2CCIP1R_DFSDM1SEL_Pos   (24U)
#define	RCC_D2CCIP1R_DFSDM1SEL_Msk   (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos)
	0x01000000
#define	RCC_D2CCIP1R_DFSDM1SEL   RCC_D2CCIP1R_DFSDM1SEL_Msk
#define	RCC_D2CCIP1R_FDCANSEL_Pos   (28U)
#define	RCC_D2CCIP1R_FDCANSEL_Msk   (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos)
	0x30000000
#define	RCC_D2CCIP1R_FDCANSEL   RCC_D2CCIP1R_FDCANSEL_Msk
#define	RCC_D2CCIP1R_FDCANSEL_0   (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos)
	0x10000000
#define	RCC_D2CCIP1R_FDCANSEL_1   (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos)
	0x20000000
#define	RCC_D2CCIP1R_SWPSEL_Pos   (31U)
#define	RCC_D2CCIP1R_SWPSEL_Msk   (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos)
	0x80000000
#define	RCC_D2CCIP1R_SWPSEL   RCC_D2CCIP1R_SWPSEL_Msk
#define	RCC_D2CCIP2R_USART16910SEL_Pos   (3U)
#define	RCC_D2CCIP2R_USART16910SEL_Msk   (0x7UL << RCC_D2CCIP2R_USART16910SEL_Pos)
	0x00000038
#define	RCC_D2CCIP2R_USART16910SEL   RCC_D2CCIP2R_USART16910SEL_Msk
#define	RCC_D2CCIP2R_USART16910SEL_0   (0x1UL << RCC_D2CCIP2R_USART16910SEL_Pos)
	0x00000008
#define	RCC_D2CCIP2R_USART16910SEL_1   (0x2UL << RCC_D2CCIP2R_USART16910SEL_Pos)
	0x00000010
#define	RCC_D2CCIP2R_USART16910SEL_2   (0x4UL << RCC_D2CCIP2R_USART16910SEL_Pos)
	0x00000020
#define	RCC_D2CCIP2R_USART28SEL_Pos   (0U)
#define	RCC_D2CCIP2R_USART28SEL_Msk   (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos)
	0x00000007
#define	RCC_D2CCIP2R_USART28SEL   RCC_D2CCIP2R_USART28SEL_Msk
#define	RCC_D2CCIP2R_USART28SEL_0   (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos)
	0x00000001
#define	RCC_D2CCIP2R_USART28SEL_1   (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos)
	0x00000002
#define	RCC_D2CCIP2R_USART28SEL_2   (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos)
	0x00000004
#define	RCC_D2CCIP2R_RNGSEL_Pos   (8U)
#define	RCC_D2CCIP2R_RNGSEL_Msk   (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos)
	0x00000300
#define	RCC_D2CCIP2R_RNGSEL   RCC_D2CCIP2R_RNGSEL_Msk
#define	RCC_D2CCIP2R_RNGSEL_0   (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos)
	0x00000100
#define	RCC_D2CCIP2R_RNGSEL_1   (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos)
	0x00000200
#define	RCC_D2CCIP2R_I2C1235SEL_Pos   (12U)
#define	RCC_D2CCIP2R_I2C1235SEL_Msk   (0x3UL << RCC_D2CCIP2R_I2C1235SEL_Pos)
	0x00003000
#define	RCC_D2CCIP2R_I2C1235SEL   RCC_D2CCIP2R_I2C1235SEL_Msk
#define	RCC_D2CCIP2R_I2C1235SEL_0   (0x1UL << RCC_D2CCIP2R_I2C1235SEL_Pos)
	0x00001000
#define	RCC_D2CCIP2R_I2C1235SEL_1   (0x2UL << RCC_D2CCIP2R_I2C1235SEL_Pos)
	0x00002000
#define	RCC_D2CCIP2R_USBSEL_Pos   (20U)
#define	RCC_D2CCIP2R_USBSEL_Msk   (0x3UL << RCC_D2CCIP2R_USBSEL_Pos)
	0x00300000
#define	RCC_D2CCIP2R_USBSEL   RCC_D2CCIP2R_USBSEL_Msk
#define	RCC_D2CCIP2R_USBSEL_0   (0x1UL << RCC_D2CCIP2R_USBSEL_Pos)
	0x00100000
#define	RCC_D2CCIP2R_USBSEL_1   (0x2UL << RCC_D2CCIP2R_USBSEL_Pos)
	0x00200000
#define	RCC_D2CCIP2R_CECSEL_Pos   (22U)
#define	RCC_D2CCIP2R_CECSEL_Msk   (0x3UL << RCC_D2CCIP2R_CECSEL_Pos)
	0x00C00000
#define	RCC_D2CCIP2R_CECSEL   RCC_D2CCIP2R_CECSEL_Msk
#define	RCC_D2CCIP2R_CECSEL_0   (0x1UL << RCC_D2CCIP2R_CECSEL_Pos)
	0x00400000
#define	RCC_D2CCIP2R_CECSEL_1   (0x2UL << RCC_D2CCIP2R_CECSEL_Pos)
	0x00800000
#define	RCC_D2CCIP2R_LPTIM1SEL_Pos   (28U)
#define	RCC_D2CCIP2R_LPTIM1SEL_Msk   (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
	0x70000000
#define	RCC_D2CCIP2R_LPTIM1SEL   RCC_D2CCIP2R_LPTIM1SEL_Msk
#define	RCC_D2CCIP2R_LPTIM1SEL_0   (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
	0x10000000
#define	RCC_D2CCIP2R_LPTIM1SEL_1   (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
	0x20000000
#define	RCC_D2CCIP2R_LPTIM1SEL_2   (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
	0x40000000
#define	RCC_D3CCIPR_LPUART1SEL_Pos   (0U)
#define	RCC_D3CCIPR_LPUART1SEL_Msk   (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos)
	0x00000007
#define	RCC_D3CCIPR_LPUART1SEL   RCC_D3CCIPR_LPUART1SEL_Msk
#define	RCC_D3CCIPR_LPUART1SEL_0   (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos)
	0x00000001
#define	RCC_D3CCIPR_LPUART1SEL_1   (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos)
	0x00000002
#define	RCC_D3CCIPR_LPUART1SEL_2   (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos)
	0x00000004
#define	RCC_D3CCIPR_I2C4SEL_Pos   (8U)
#define	RCC_D3CCIPR_I2C4SEL_Msk   (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos)
	0x00000300
#define	RCC_D3CCIPR_I2C4SEL   RCC_D3CCIPR_I2C4SEL_Msk
#define	RCC_D3CCIPR_I2C4SEL_0   (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos)
	0x00000100
#define	RCC_D3CCIPR_I2C4SEL_1   (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos)
	0x00000200
#define	RCC_D3CCIPR_LPTIM2SEL_Pos   (10U)
#define	RCC_D3CCIPR_LPTIM2SEL_Msk   (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos)
	0x00001C00
#define	RCC_D3CCIPR_LPTIM2SEL   RCC_D3CCIPR_LPTIM2SEL_Msk
#define	RCC_D3CCIPR_LPTIM2SEL_0   (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos)
	0x00000400
#define	RCC_D3CCIPR_LPTIM2SEL_1   (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos)
	0x00000800
#define	RCC_D3CCIPR_LPTIM2SEL_2   (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos)
	0x00001000
#define	RCC_D3CCIPR_LPTIM345SEL_Pos   (13U)
#define	RCC_D3CCIPR_LPTIM345SEL_Msk   (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos)
	0x0000E000
#define	RCC_D3CCIPR_LPTIM345SEL   RCC_D3CCIPR_LPTIM345SEL_Msk
#define	RCC_D3CCIPR_LPTIM345SEL_0   (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos)
	0x00002000
#define	RCC_D3CCIPR_LPTIM345SEL_1   (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos)
	0x00004000
#define	RCC_D3CCIPR_LPTIM345SEL_2   (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos)
	0x00008000
#define	RCC_D3CCIPR_SAI4ASEL_Pos   (21U)
#define	RCC_D3CCIPR_SAI4ASEL_Msk   (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos)
	0x00E00000
#define	RCC_D3CCIPR_SAI4ASEL   RCC_D3CCIPR_SAI4ASEL_Msk
#define	RCC_D3CCIPR_SAI4ASEL_0   (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos)
	0x00200000
#define	RCC_D3CCIPR_SAI4ASEL_1   (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos)
	0x00400000
#define	RCC_D3CCIPR_SAI4ASEL_2   (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos)
	0x00800000
#define	RCC_D3CCIPR_SAI4BSEL_Pos   (24U)
#define	RCC_D3CCIPR_SAI4BSEL_Msk   (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos)
	0x07000000
#define	RCC_D3CCIPR_SAI4BSEL   RCC_D3CCIPR_SAI4BSEL_Msk
#define	RCC_D3CCIPR_SAI4BSEL_0   (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos)
	0x01000000
#define	RCC_D3CCIPR_SAI4BSEL_1   (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos)
	0x02000000
#define	RCC_D3CCIPR_SAI4BSEL_2   (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos)
	0x04000000
#define	RCC_D3CCIPR_ADCSEL_Pos   (16U)
#define	RCC_D3CCIPR_ADCSEL_Msk   (0x3UL << RCC_D3CCIPR_ADCSEL_Pos)
	0x00030000
#define	RCC_D3CCIPR_ADCSEL   RCC_D3CCIPR_ADCSEL_Msk
#define	RCC_D3CCIPR_ADCSEL_0   (0x1UL << RCC_D3CCIPR_ADCSEL_Pos)
	0x00010000
#define	RCC_D3CCIPR_ADCSEL_1   (0x2UL << RCC_D3CCIPR_ADCSEL_Pos)
	0x00020000
#define	RCC_D3CCIPR_SPI6SEL_Pos   (28U)
#define	RCC_D3CCIPR_SPI6SEL_Msk   (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos)
	0x70000000
#define	RCC_D3CCIPR_SPI6SEL   RCC_D3CCIPR_SPI6SEL_Msk
#define	RCC_D3CCIPR_SPI6SEL_0   (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos)
	0x10000000
#define	RCC_D3CCIPR_SPI6SEL_1   (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos)
	0x20000000
#define	RCC_D3CCIPR_SPI6SEL_2   (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos)
	0x40000000
#define	RCC_CIER_LSIRDYIE_Pos   (0U)
#define	RCC_CIER_LSIRDYIE_Msk   (0x1UL << RCC_CIER_LSIRDYIE_Pos)
	0x00000001
#define	RCC_CIER_LSIRDYIE   RCC_CIER_LSIRDYIE_Msk
#define	RCC_CIER_LSERDYIE_Pos   (1U)
#define	RCC_CIER_LSERDYIE_Msk   (0x1UL << RCC_CIER_LSERDYIE_Pos)
	0x00000002
#define	RCC_CIER_LSERDYIE   RCC_CIER_LSERDYIE_Msk
#define	RCC_CIER_HSIRDYIE_Pos   (2U)
#define	RCC_CIER_HSIRDYIE_Msk   (0x1UL << RCC_CIER_HSIRDYIE_Pos)
	0x00000004
#define	RCC_CIER_HSIRDYIE   RCC_CIER_HSIRDYIE_Msk
#define	RCC_CIER_HSERDYIE_Pos   (3U)
#define	RCC_CIER_HSERDYIE_Msk   (0x1UL << RCC_CIER_HSERDYIE_Pos)
	0x00000008
#define	RCC_CIER_HSERDYIE   RCC_CIER_HSERDYIE_Msk
#define	RCC_CIER_CSIRDYIE_Pos   (4U)
#define	RCC_CIER_CSIRDYIE_Msk   (0x1UL << RCC_CIER_CSIRDYIE_Pos)
	0x00000010
#define	RCC_CIER_CSIRDYIE   RCC_CIER_CSIRDYIE_Msk
#define	RCC_CIER_HSI48RDYIE_Pos   (5U)
#define	RCC_CIER_HSI48RDYIE_Msk   (0x1UL << RCC_CIER_HSI48RDYIE_Pos)
	0x00000020
#define	RCC_CIER_HSI48RDYIE   RCC_CIER_HSI48RDYIE_Msk
#define	RCC_CIER_PLL1RDYIE_Pos   (6U)
#define	RCC_CIER_PLL1RDYIE_Msk   (0x1UL << RCC_CIER_PLL1RDYIE_Pos)
	0x00000040
#define	RCC_CIER_PLL1RDYIE   RCC_CIER_PLL1RDYIE_Msk
#define	RCC_CIER_PLL2RDYIE_Pos   (7U)
#define	RCC_CIER_PLL2RDYIE_Msk   (0x1UL << RCC_CIER_PLL2RDYIE_Pos)
	0x00000080
#define	RCC_CIER_PLL2RDYIE   RCC_CIER_PLL2RDYIE_Msk
#define	RCC_CIER_PLL3RDYIE_Pos   (8U)
#define	RCC_CIER_PLL3RDYIE_Msk   (0x1UL << RCC_CIER_PLL3RDYIE_Pos)
	0x00000100
#define	RCC_CIER_PLL3RDYIE   RCC_CIER_PLL3RDYIE_Msk
#define	RCC_CIER_LSECSSIE_Pos   (9U)
#define	RCC_CIER_LSECSSIE_Msk   (0x1UL << RCC_CIER_LSECSSIE_Pos)
	0x00000200
#define	RCC_CIER_LSECSSIE   RCC_CIER_LSECSSIE_Msk
#define	RCC_CIFR_LSIRDYF_Pos   (0U)
#define	RCC_CIFR_LSIRDYF_Msk   (0x1UL << RCC_CIFR_LSIRDYF_Pos)
	0x00000001
#define	RCC_CIFR_LSIRDYF   RCC_CIFR_LSIRDYF_Msk
#define	RCC_CIFR_LSERDYF_Pos   (1U)
#define	RCC_CIFR_LSERDYF_Msk   (0x1UL << RCC_CIFR_LSERDYF_Pos)
	0x00000002
#define	RCC_CIFR_LSERDYF   RCC_CIFR_LSERDYF_Msk
#define	RCC_CIFR_HSIRDYF_Pos   (2U)
#define	RCC_CIFR_HSIRDYF_Msk   (0x1UL << RCC_CIFR_HSIRDYF_Pos)
	0x00000004
#define	RCC_CIFR_HSIRDYF   RCC_CIFR_HSIRDYF_Msk
#define	RCC_CIFR_HSERDYF_Pos   (3U)
#define	RCC_CIFR_HSERDYF_Msk   (0x1UL << RCC_CIFR_HSERDYF_Pos)
	0x00000008
#define	RCC_CIFR_HSERDYF   RCC_CIFR_HSERDYF_Msk
#define	RCC_CIFR_CSIRDYF_Pos   (4U)
#define	RCC_CIFR_CSIRDYF_Msk   (0x1UL << RCC_CIFR_CSIRDYF_Pos)
	0x00000010
#define	RCC_CIFR_CSIRDYF   RCC_CIFR_CSIRDYF_Msk
#define	RCC_CIFR_HSI48RDYF_Pos   (5U)
#define	RCC_CIFR_HSI48RDYF_Msk   (0x1UL << RCC_CIFR_HSI48RDYF_Pos)
	0x00000020
#define	RCC_CIFR_HSI48RDYF   RCC_CIFR_HSI48RDYF_Msk
#define	RCC_CIFR_PLLRDYF_Pos   (6U)
#define	RCC_CIFR_PLLRDYF_Msk   (0x1UL << RCC_CIFR_PLLRDYF_Pos)
	0x00000040
#define	RCC_CIFR_PLLRDYF   RCC_CIFR_PLLRDYF_Msk
#define	RCC_CIFR_PLL2RDYF_Pos   (7U)
#define	RCC_CIFR_PLL2RDYF_Msk   (0x1UL << RCC_CIFR_PLL2RDYF_Pos)
	0x00000080
#define	RCC_CIFR_PLL2RDYF   RCC_CIFR_PLL2RDYF_Msk
#define	RCC_CIFR_PLL3RDYF_Pos   (8U)
#define	RCC_CIFR_PLL3RDYF_Msk   (0x1UL << RCC_CIFR_PLL3RDYF_Pos)
	0x00000100
#define	RCC_CIFR_PLL3RDYF   RCC_CIFR_PLL3RDYF_Msk
#define	RCC_CIFR_LSECSSF_Pos   (9U)
#define	RCC_CIFR_LSECSSF_Msk   (0x1UL << RCC_CIFR_LSECSSF_Pos)
	0x00000200
#define	RCC_CIFR_LSECSSF   RCC_CIFR_LSECSSF_Msk
#define	RCC_CIFR_HSECSSF_Pos   (10U)
#define	RCC_CIFR_HSECSSF_Msk   (0x1UL << RCC_CIFR_HSECSSF_Pos)
	0x00000400
#define	RCC_CIFR_HSECSSF   RCC_CIFR_HSECSSF_Msk
#define	RCC_CICR_LSIRDYC_Pos   (0U)
#define	RCC_CICR_LSIRDYC_Msk   (0x1UL << RCC_CICR_LSIRDYC_Pos)
	0x00000001
#define	RCC_CICR_LSIRDYC   RCC_CICR_LSIRDYC_Msk
#define	RCC_CICR_LSERDYC_Pos   (1U)
#define	RCC_CICR_LSERDYC_Msk   (0x1UL << RCC_CICR_LSERDYC_Pos)
	0x00000002
#define	RCC_CICR_LSERDYC   RCC_CICR_LSERDYC_Msk
#define	RCC_CICR_HSIRDYC_Pos   (2U)
#define	RCC_CICR_HSIRDYC_Msk   (0x1UL << RCC_CICR_HSIRDYC_Pos)
	0x00000004
#define	RCC_CICR_HSIRDYC   RCC_CICR_HSIRDYC_Msk
#define	RCC_CICR_HSERDYC_Pos   (3U)
#define	RCC_CICR_HSERDYC_Msk   (0x1UL << RCC_CICR_HSERDYC_Pos)
	0x00000008
#define	RCC_CICR_HSERDYC   RCC_CICR_HSERDYC_Msk
#define	RCC_CICR_CSIRDYC_Pos   (4U)
#define	RCC_CICR_CSIRDYC_Msk   (0x1UL << RCC_CICR_CSIRDYC_Pos)
	0x00000010
#define	RCC_CICR_CSIRDYC   RCC_CICR_CSIRDYC_Msk
#define	RCC_CICR_HSI48RDYC_Pos   (5U)
#define	RCC_CICR_HSI48RDYC_Msk   (0x1UL << RCC_CICR_HSI48RDYC_Pos)
	0x00000020
#define	RCC_CICR_HSI48RDYC   RCC_CICR_HSI48RDYC_Msk
#define	RCC_CICR_PLLRDYC_Pos   (6U)
#define	RCC_CICR_PLLRDYC_Msk   (0x1UL << RCC_CICR_PLLRDYC_Pos)
	0x00000040
#define	RCC_CICR_PLLRDYC   RCC_CICR_PLLRDYC_Msk
#define	RCC_CICR_PLL2RDYC_Pos   (7U)
#define	RCC_CICR_PLL2RDYC_Msk   (0x1UL << RCC_CICR_PLL2RDYC_Pos)
	0x00000080
#define	RCC_CICR_PLL2RDYC   RCC_CICR_PLL2RDYC_Msk
#define	RCC_CICR_PLL3RDYC_Pos   (8U)
#define	RCC_CICR_PLL3RDYC_Msk   (0x1UL << RCC_CICR_PLL3RDYC_Pos)
	0x00000100
#define	RCC_CICR_PLL3RDYC   RCC_CICR_PLL3RDYC_Msk
#define	RCC_CICR_LSECSSC_Pos   (9U)
#define	RCC_CICR_LSECSSC_Msk   (0x1UL << RCC_CICR_LSECSSC_Pos)
	0x00000200
#define	RCC_CICR_LSECSSC   RCC_CICR_LSECSSC_Msk
#define	RCC_CICR_HSECSSC_Pos   (10U)
#define	RCC_CICR_HSECSSC_Msk   (0x1UL << RCC_CICR_HSECSSC_Pos)
	0x00000400
#define	RCC_CICR_HSECSSC   RCC_CICR_HSECSSC_Msk
#define	RCC_BDCR_LSEON_Pos   (0U)
#define	RCC_BDCR_LSEON_Msk   (0x1UL << RCC_BDCR_LSEON_Pos)
	0x00000001
#define	RCC_BDCR_LSEON   RCC_BDCR_LSEON_Msk
#define	RCC_BDCR_LSERDY_Pos   (1U)
#define	RCC_BDCR_LSERDY_Msk   (0x1UL << RCC_BDCR_LSERDY_Pos)
	0x00000002
#define	RCC_BDCR_LSERDY   RCC_BDCR_LSERDY_Msk
#define	RCC_BDCR_LSEBYP_Pos   (2U)
#define	RCC_BDCR_LSEBYP_Msk   (0x1UL << RCC_BDCR_LSEBYP_Pos)
	0x00000004
#define	RCC_BDCR_LSEBYP   RCC_BDCR_LSEBYP_Msk
#define	RCC_BDCR_LSEDRV_Pos   (3U)
#define	RCC_BDCR_LSEDRV_Msk   (0x3UL << RCC_BDCR_LSEDRV_Pos)
	0x00000018
#define	RCC_BDCR_LSEDRV   RCC_BDCR_LSEDRV_Msk
#define	RCC_BDCR_LSEDRV_0   (0x1UL << RCC_BDCR_LSEDRV_Pos)
	0x00000008
#define	RCC_BDCR_LSEDRV_1   (0x2UL << RCC_BDCR_LSEDRV_Pos)
	0x00000010
#define	RCC_BDCR_LSECSSON_Pos   (5U)
#define	RCC_BDCR_LSECSSON_Msk   (0x1UL << RCC_BDCR_LSECSSON_Pos)
	0x00000020
#define	RCC_BDCR_LSECSSON   RCC_BDCR_LSECSSON_Msk
#define	RCC_BDCR_LSECSSD_Pos   (6U)
#define	RCC_BDCR_LSECSSD_Msk   (0x1UL << RCC_BDCR_LSECSSD_Pos)
	0x00000040
#define	RCC_BDCR_LSECSSD   RCC_BDCR_LSECSSD_Msk
#define	RCC_BDCR_RTCSEL_Pos   (8U)
#define	RCC_BDCR_RTCSEL_Msk   (0x3UL << RCC_BDCR_RTCSEL_Pos)
	0x00000300
#define	RCC_BDCR_RTCSEL   RCC_BDCR_RTCSEL_Msk
#define	RCC_BDCR_RTCSEL_0   (0x1UL << RCC_BDCR_RTCSEL_Pos)
	0x00000100
#define	RCC_BDCR_RTCSEL_1   (0x2UL << RCC_BDCR_RTCSEL_Pos)
	0x00000200
#define	RCC_BDCR_RTCEN_Pos   (15U)
#define	RCC_BDCR_RTCEN_Msk   (0x1UL << RCC_BDCR_RTCEN_Pos)
	0x00008000
#define	RCC_BDCR_RTCEN   RCC_BDCR_RTCEN_Msk
#define	RCC_BDCR_VSWRST_Pos   (16U)
#define	RCC_BDCR_VSWRST_Msk   (0x1UL << RCC_BDCR_VSWRST_Pos)
	0x00010000
#define	RCC_BDCR_VSWRST   RCC_BDCR_VSWRST_Msk
#define	RCC_BDCR_BDRST_Pos   RCC_BDCR_VSWRST_Pos
#define	RCC_BDCR_BDRST_Msk   RCC_BDCR_VSWRST_Msk
#define	RCC_BDCR_BDRST   RCC_BDCR_VSWRST
#define	RCC_CSR_LSION_Pos   (0U)
#define	RCC_CSR_LSION_Msk   (0x1UL << RCC_CSR_LSION_Pos)
	0x00000001
#define	RCC_CSR_LSION   RCC_CSR_LSION_Msk
#define	RCC_CSR_LSIRDY_Pos   (1U)
#define	RCC_CSR_LSIRDY_Msk   (0x1UL << RCC_CSR_LSIRDY_Pos)
	0x00000002
#define	RCC_CSR_LSIRDY   RCC_CSR_LSIRDY_Msk
#define	RCC_AHB3ENR_MDMAEN_Pos   (0U)
#define	RCC_AHB3ENR_MDMAEN_Msk   (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)
	0x00000001
#define	RCC_AHB3ENR_MDMAEN   RCC_AHB3ENR_MDMAEN_Msk
#define	RCC_AHB3ENR_DMA2DEN_Pos   (4U)
#define	RCC_AHB3ENR_DMA2DEN_Msk   (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)
	0x00000010
#define	RCC_AHB3ENR_DMA2DEN   RCC_AHB3ENR_DMA2DEN_Msk
#define	RCC_AHB3ENR_FMCEN_Pos   (12U)
#define	RCC_AHB3ENR_FMCEN_Msk   (0x1UL << RCC_AHB3ENR_FMCEN_Pos)
	0x00001000
#define	RCC_AHB3ENR_FMCEN   RCC_AHB3ENR_FMCEN_Msk
#define	RCC_AHB3ENR_OSPI1EN_Pos   (14U)
#define	RCC_AHB3ENR_OSPI1EN_Msk   (0x1UL << RCC_AHB3ENR_OSPI1EN_Pos)
	0x00004000
#define	RCC_AHB3ENR_OSPI1EN   RCC_AHB3ENR_OSPI1EN_Msk
#define	RCC_AHB3ENR_SDMMC1EN_Pos   (16U)
#define	RCC_AHB3ENR_SDMMC1EN_Msk   (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)
	0x00010000
#define	RCC_AHB3ENR_SDMMC1EN   RCC_AHB3ENR_SDMMC1EN_Msk
#define	RCC_AHB3ENR_OSPI2EN_Pos   (19U)
#define	RCC_AHB3ENR_OSPI2EN_Msk   (0x1UL << RCC_AHB3ENR_OSPI2EN_Pos)
	0x00040000
#define	RCC_AHB3ENR_OSPI2EN   RCC_AHB3ENR_OSPI2EN_Msk
#define	RCC_AHB3ENR_IOMNGREN_Pos   (21U)
#define	RCC_AHB3ENR_IOMNGREN_Msk   (0x1UL << RCC_AHB3ENR_IOMNGREN_Pos)
	0x00100000
#define	RCC_AHB3ENR_IOMNGREN   RCC_AHB3ENR_IOMNGREN_Msk
#define	RCC_AHB1ENR_DMA1EN_Pos   (0U)
#define	RCC_AHB1ENR_DMA1EN_Msk   (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
	0x00000001
#define	RCC_AHB1ENR_DMA1EN   RCC_AHB1ENR_DMA1EN_Msk
#define	RCC_AHB1ENR_DMA2EN_Pos   (1U)
#define	RCC_AHB1ENR_DMA2EN_Msk   (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
	0x00000002
#define	RCC_AHB1ENR_DMA2EN   RCC_AHB1ENR_DMA2EN_Msk
#define	RCC_AHB1ENR_ADC12EN_Pos   (5U)
#define	RCC_AHB1ENR_ADC12EN_Msk   (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)
	0x00000020
#define	RCC_AHB1ENR_ADC12EN   RCC_AHB1ENR_ADC12EN_Msk
#define	RCC_AHB1ENR_ETH1MACEN_Pos   (15U)
#define	RCC_AHB1ENR_ETH1MACEN_Msk   (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos)
	0x00008000
#define	RCC_AHB1ENR_ETH1MACEN   RCC_AHB1ENR_ETH1MACEN_Msk
#define	RCC_AHB1ENR_ETH1TXEN_Pos   (16U)
#define	RCC_AHB1ENR_ETH1TXEN_Msk   (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos)
	0x00010000
#define	RCC_AHB1ENR_ETH1TXEN   RCC_AHB1ENR_ETH1TXEN_Msk
#define	RCC_AHB1ENR_ETH1RXEN_Pos   (17U)
#define	RCC_AHB1ENR_ETH1RXEN_Msk   (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos)
	0x00020000
#define	RCC_AHB1ENR_ETH1RXEN   RCC_AHB1ENR_ETH1RXEN_Msk
#define	RCC_AHB1ENR_USB1OTGHSEN_Pos   (25U)
#define	RCC_AHB1ENR_USB1OTGHSEN_Msk   (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)
	0x02000000
#define	RCC_AHB1ENR_USB1OTGHSEN   RCC_AHB1ENR_USB1OTGHSEN_Msk
#define	RCC_AHB1ENR_USB1OTGHSULPIEN_Pos   (26U)
#define	RCC_AHB1ENR_USB1OTGHSULPIEN_Msk   (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos)
	0x04000000
#define	RCC_AHB1ENR_USB1OTGHSULPIEN   RCC_AHB1ENR_USB1OTGHSULPIEN_Msk
#define	RCC_AHB2ENR_DCMI_PSSIEN_Pos   (0U)
#define	RCC_AHB2ENR_DCMI_PSSIEN_Msk   (0x1UL << RCC_AHB2ENR_DCMI_PSSIEN_Pos)
	0x00000001
#define	RCC_AHB2ENR_DCMI_PSSIEN   RCC_AHB2ENR_DCMI_PSSIEN_Msk
#define	RCC_AHB2ENR_RNGEN_Pos   (6U)
#define	RCC_AHB2ENR_RNGEN_Msk   (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
	0x00000040
#define	RCC_AHB2ENR_RNGEN   RCC_AHB2ENR_RNGEN_Msk
#define	RCC_AHB2ENR_SDMMC2EN_Pos   (9U)
#define	RCC_AHB2ENR_SDMMC2EN_Msk   (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)
	0x00000200
#define	RCC_AHB2ENR_SDMMC2EN   RCC_AHB2ENR_SDMMC2EN_Msk
#define	RCC_AHB2ENR_FMACEN_Pos   (16U)
#define	RCC_AHB2ENR_FMACEN_Msk   (0x1UL << RCC_AHB2ENR_FMACEN_Pos)
	0x00010000
#define	RCC_AHB2ENR_FMACEN   RCC_AHB2ENR_FMACEN_Msk
#define	RCC_AHB2ENR_CORDICEN_Pos   (17U)
#define	RCC_AHB2ENR_CORDICEN_Msk   (0x1UL << RCC_AHB2ENR_CORDICEN_Pos)
	0x00020000
#define	RCC_AHB2ENR_CORDICEN   RCC_AHB2ENR_CORDICEN_Msk
#define	RCC_AHB2ENR_SRAM1EN_Pos   (29U)
#define	RCC_AHB2ENR_SRAM1EN_Msk   (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos)
	0x20000000
#define	RCC_AHB2ENR_SRAM1EN   RCC_AHB2ENR_SRAM1EN_Msk
#define	RCC_AHB2ENR_SRAM2EN_Pos   (30U)
#define	RCC_AHB2ENR_SRAM2EN_Msk   (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)
	0x40000000
#define	RCC_AHB2ENR_SRAM2EN   RCC_AHB2ENR_SRAM2EN_Msk
#define	RCC_AHB2ENR_DCMIEN_Pos   RCC_AHB2ENR_DCMI_PSSIEN_Pos
#define	RCC_AHB2ENR_DCMIEN_Msk   RCC_AHB2ENR_DCMI_PSSIEN_Msk
#define	RCC_AHB2ENR_DCMIEN   RCC_AHB2ENR_DCMI_PSSIEN
#define	RCC_AHB2ENR_D2SRAM1EN_Pos   RCC_AHB2ENR_SRAM1EN_Pos
#define	RCC_AHB2ENR_D2SRAM1EN_Msk   RCC_AHB2ENR_SRAM1EN_Msk
#define	RCC_AHB2ENR_D2SRAM1EN   RCC_AHB2ENR_SRAM1EN
#define	RCC_AHB2ENR_D2SRAM2EN_Pos   RCC_AHB2ENR_SRAM2EN_Pos
#define	RCC_AHB2ENR_D2SRAM2EN_Msk   RCC_AHB2ENR_SRAM2EN_Msk
#define	RCC_AHB2ENR_D2SRAM2EN   RCC_AHB2ENR_SRAM2EN
#define	RCC_AHB4ENR_GPIOAEN_Pos   (0U)
#define	RCC_AHB4ENR_GPIOAEN_Msk   (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)
	0x00000001
#define	RCC_AHB4ENR_GPIOAEN   RCC_AHB4ENR_GPIOAEN_Msk
#define	RCC_AHB4ENR_GPIOBEN_Pos   (1U)
#define	RCC_AHB4ENR_GPIOBEN_Msk   (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)
	0x00000002
#define	RCC_AHB4ENR_GPIOBEN   RCC_AHB4ENR_GPIOBEN_Msk
#define	RCC_AHB4ENR_GPIOCEN_Pos   (2U)
#define	RCC_AHB4ENR_GPIOCEN_Msk   (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)
	0x00000004
#define	RCC_AHB4ENR_GPIOCEN   RCC_AHB4ENR_GPIOCEN_Msk
#define	RCC_AHB4ENR_GPIODEN_Pos   (3U)
#define	RCC_AHB4ENR_GPIODEN_Msk   (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)
	0x00000008
#define	RCC_AHB4ENR_GPIODEN   RCC_AHB4ENR_GPIODEN_Msk
#define	RCC_AHB4ENR_GPIOEEN_Pos   (4U)
#define	RCC_AHB4ENR_GPIOEEN_Msk   (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)
	0x00000010
#define	RCC_AHB4ENR_GPIOEEN   RCC_AHB4ENR_GPIOEEN_Msk
#define	RCC_AHB4ENR_GPIOFEN_Pos   (5U)
#define	RCC_AHB4ENR_GPIOFEN_Msk   (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)
	0x00000020
#define	RCC_AHB4ENR_GPIOFEN   RCC_AHB4ENR_GPIOFEN_Msk
#define	RCC_AHB4ENR_GPIOGEN_Pos   (6U)
#define	RCC_AHB4ENR_GPIOGEN_Msk   (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)
	0x00000040
#define	RCC_AHB4ENR_GPIOGEN   RCC_AHB4ENR_GPIOGEN_Msk
#define	RCC_AHB4ENR_GPIOHEN_Pos   (7U)
#define	RCC_AHB4ENR_GPIOHEN_Msk   (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)
	0x00000080
#define	RCC_AHB4ENR_GPIOHEN   RCC_AHB4ENR_GPIOHEN_Msk
#define	RCC_AHB4ENR_GPIOJEN_Pos   (9U)
#define	RCC_AHB4ENR_GPIOJEN_Msk   (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)
	0x00000200
#define	RCC_AHB4ENR_GPIOJEN   RCC_AHB4ENR_GPIOJEN_Msk
#define	RCC_AHB4ENR_GPIOKEN_Pos   (10U)
#define	RCC_AHB4ENR_GPIOKEN_Msk   (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)
	0x00000400
#define	RCC_AHB4ENR_GPIOKEN   RCC_AHB4ENR_GPIOKEN_Msk
#define	RCC_AHB4ENR_CRCEN_Pos   (19U)
#define	RCC_AHB4ENR_CRCEN_Msk   (0x1UL << RCC_AHB4ENR_CRCEN_Pos)
	0x00080000
#define	RCC_AHB4ENR_CRCEN   RCC_AHB4ENR_CRCEN_Msk
#define	RCC_AHB4ENR_BDMAEN_Pos   (21U)
#define	RCC_AHB4ENR_BDMAEN_Msk   (0x1UL << RCC_AHB4ENR_BDMAEN_Pos)
	0x00200000
#define	RCC_AHB4ENR_BDMAEN   RCC_AHB4ENR_BDMAEN_Msk
#define	RCC_AHB4ENR_ADC3EN_Pos   (24U)
#define	RCC_AHB4ENR_ADC3EN_Msk   (0x1UL << RCC_AHB4ENR_ADC3EN_Pos)
	0x01000000
#define	RCC_AHB4ENR_ADC3EN   RCC_AHB4ENR_ADC3EN_Msk
#define	RCC_AHB4ENR_HSEMEN_Pos   (25U)
#define	RCC_AHB4ENR_HSEMEN_Msk   (0x1UL << RCC_AHB4ENR_HSEMEN_Pos)
	0x02000000
#define	RCC_AHB4ENR_HSEMEN   RCC_AHB4ENR_HSEMEN_Msk
#define	RCC_AHB4ENR_BKPRAMEN_Pos   (28U)
#define	RCC_AHB4ENR_BKPRAMEN_Msk   (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)
	0x10000000
#define	RCC_AHB4ENR_BKPRAMEN   RCC_AHB4ENR_BKPRAMEN_Msk
#define	RCC_APB3ENR_LTDCEN_Pos   (3U)
#define	RCC_APB3ENR_LTDCEN_Msk   (0x1UL << RCC_APB3ENR_LTDCEN_Pos)
	0x00000008
#define	RCC_APB3ENR_LTDCEN   RCC_APB3ENR_LTDCEN_Msk
#define	RCC_APB3ENR_WWDG1EN_Pos   (6U)
#define	RCC_APB3ENR_WWDG1EN_Msk   (0x1UL << RCC_APB3ENR_WWDG1EN_Pos)
	0x00000040
#define	RCC_APB3ENR_WWDG1EN   RCC_APB3ENR_WWDG1EN_Msk
#define	RCC_APB1LENR_TIM2EN_Pos   (0U)
#define	RCC_APB1LENR_TIM2EN_Msk   (0x1UL << RCC_APB1LENR_TIM2EN_Pos)
	0x00000001
#define	RCC_APB1LENR_TIM2EN   RCC_APB1LENR_TIM2EN_Msk
#define	RCC_APB1LENR_TIM3EN_Pos   (1U)
#define	RCC_APB1LENR_TIM3EN_Msk   (0x1UL << RCC_APB1LENR_TIM3EN_Pos)
	0x00000002
#define	RCC_APB1LENR_TIM3EN   RCC_APB1LENR_TIM3EN_Msk
#define	RCC_APB1LENR_TIM4EN_Pos   (2U)
#define	RCC_APB1LENR_TIM4EN_Msk   (0x1UL << RCC_APB1LENR_TIM4EN_Pos)
	0x00000004
#define	RCC_APB1LENR_TIM4EN   RCC_APB1LENR_TIM4EN_Msk
#define	RCC_APB1LENR_TIM5EN_Pos   (3U)
#define	RCC_APB1LENR_TIM5EN_Msk   (0x1UL << RCC_APB1LENR_TIM5EN_Pos)
	0x00000008
#define	RCC_APB1LENR_TIM5EN   RCC_APB1LENR_TIM5EN_Msk
#define	RCC_APB1LENR_TIM6EN_Pos   (4U)
#define	RCC_APB1LENR_TIM6EN_Msk   (0x1UL << RCC_APB1LENR_TIM6EN_Pos)
	0x00000010
#define	RCC_APB1LENR_TIM6EN   RCC_APB1LENR_TIM6EN_Msk
#define	RCC_APB1LENR_TIM7EN_Pos   (5U)
#define	RCC_APB1LENR_TIM7EN_Msk   (0x1UL << RCC_APB1LENR_TIM7EN_Pos)
	0x00000020
#define	RCC_APB1LENR_TIM7EN   RCC_APB1LENR_TIM7EN_Msk
#define	RCC_APB1LENR_TIM12EN_Pos   (6U)
#define	RCC_APB1LENR_TIM12EN_Msk   (0x1UL << RCC_APB1LENR_TIM12EN_Pos)
	0x00000040
#define	RCC_APB1LENR_TIM12EN   RCC_APB1LENR_TIM12EN_Msk
#define	RCC_APB1LENR_TIM13EN_Pos   (7U)
#define	RCC_APB1LENR_TIM13EN_Msk   (0x1UL << RCC_APB1LENR_TIM13EN_Pos)
	0x00000080
#define	RCC_APB1LENR_TIM13EN   RCC_APB1LENR_TIM13EN_Msk
#define	RCC_APB1LENR_TIM14EN_Pos   (8U)
#define	RCC_APB1LENR_TIM14EN_Msk   (0x1UL << RCC_APB1LENR_TIM14EN_Pos)
	0x00000100
#define	RCC_APB1LENR_TIM14EN   RCC_APB1LENR_TIM14EN_Msk
#define	RCC_APB1LENR_LPTIM1EN_Pos   (9U)
#define	RCC_APB1LENR_LPTIM1EN_Msk   (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos)
	0x00000200
#define	RCC_APB1LENR_LPTIM1EN   RCC_APB1LENR_LPTIM1EN_Msk
#define	RCC_APB1LENR_SPI2EN_Pos   (14U)
#define	RCC_APB1LENR_SPI2EN_Msk   (0x1UL << RCC_APB1LENR_SPI2EN_Pos)
	0x00004000
#define	RCC_APB1LENR_SPI2EN   RCC_APB1LENR_SPI2EN_Msk
#define	RCC_APB1LENR_SPI3EN_Pos   (15U)
#define	RCC_APB1LENR_SPI3EN_Msk   (0x1UL << RCC_APB1LENR_SPI3EN_Pos)
	0x00008000
#define	RCC_APB1LENR_SPI3EN   RCC_APB1LENR_SPI3EN_Msk
#define	RCC_APB1LENR_SPDIFRXEN_Pos   (16U)
#define	RCC_APB1LENR_SPDIFRXEN_Msk   (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos)
	0x00010000
#define	RCC_APB1LENR_SPDIFRXEN   RCC_APB1LENR_SPDIFRXEN_Msk
#define	RCC_APB1LENR_USART2EN_Pos   (17U)
#define	RCC_APB1LENR_USART2EN_Msk   (0x1UL << RCC_APB1LENR_USART2EN_Pos)
	0x00020000
#define	RCC_APB1LENR_USART2EN   RCC_APB1LENR_USART2EN_Msk
#define	RCC_APB1LENR_USART3EN_Pos   (18U)
#define	RCC_APB1LENR_USART3EN_Msk   (0x1UL << RCC_APB1LENR_USART3EN_Pos)
	0x00040000
#define	RCC_APB1LENR_USART3EN   RCC_APB1LENR_USART3EN_Msk
#define	RCC_APB1LENR_UART4EN_Pos   (19U)
#define	RCC_APB1LENR_UART4EN_Msk   (0x1UL << RCC_APB1LENR_UART4EN_Pos)
	0x00080000
#define	RCC_APB1LENR_UART4EN   RCC_APB1LENR_UART4EN_Msk
#define	RCC_APB1LENR_UART5EN_Pos   (20U)
#define	RCC_APB1LENR_UART5EN_Msk   (0x1UL << RCC_APB1LENR_UART5EN_Pos)
	0x00100000
#define	RCC_APB1LENR_UART5EN   RCC_APB1LENR_UART5EN_Msk
#define	RCC_APB1LENR_I2C1EN_Pos   (21U)
#define	RCC_APB1LENR_I2C1EN_Msk   (0x1UL << RCC_APB1LENR_I2C1EN_Pos)
	0x00200000
#define	RCC_APB1LENR_I2C1EN   RCC_APB1LENR_I2C1EN_Msk
#define	RCC_APB1LENR_I2C2EN_Pos   (22U)
#define	RCC_APB1LENR_I2C2EN_Msk   (0x1UL << RCC_APB1LENR_I2C2EN_Pos)
	0x00400000
#define	RCC_APB1LENR_I2C2EN   RCC_APB1LENR_I2C2EN_Msk
#define	RCC_APB1LENR_I2C3EN_Pos   (23U)
#define	RCC_APB1LENR_I2C3EN_Msk   (0x1UL << RCC_APB1LENR_I2C3EN_Pos)
	0x00800000
#define	RCC_APB1LENR_I2C3EN   RCC_APB1LENR_I2C3EN_Msk
#define	RCC_APB1LENR_I2C5EN_Pos   (25U)
#define	RCC_APB1LENR_I2C5EN_Msk   (0x1UL << RCC_APB1LENR_I2C5EN_Pos)
	0x02000000
#define	RCC_APB1LENR_I2C5EN   RCC_APB1LENR_I2C5EN_Msk
#define	RCC_APB1LENR_CECEN_Pos   (27U)
#define	RCC_APB1LENR_CECEN_Msk   (0x1UL << RCC_APB1LENR_CECEN_Pos)
	0x08000000
#define	RCC_APB1LENR_CECEN   RCC_APB1LENR_CECEN_Msk
#define	RCC_APB1LENR_DAC12EN_Pos   (29U)
#define	RCC_APB1LENR_DAC12EN_Msk   (0x1UL << RCC_APB1LENR_DAC12EN_Pos)
	0x20000000
#define	RCC_APB1LENR_DAC12EN   RCC_APB1LENR_DAC12EN_Msk
#define	RCC_APB1LENR_UART7EN_Pos   (30U)
#define	RCC_APB1LENR_UART7EN_Msk   (0x1UL << RCC_APB1LENR_UART7EN_Pos)
	0x40000000
#define	RCC_APB1LENR_UART7EN   RCC_APB1LENR_UART7EN_Msk
#define	RCC_APB1LENR_UART8EN_Pos   (31U)
#define	RCC_APB1LENR_UART8EN_Msk   (0x1UL << RCC_APB1LENR_UART8EN_Pos)
	0x80000000
#define	RCC_APB1LENR_UART8EN   RCC_APB1LENR_UART8EN_Msk
#define	RCC_APB1LENR_HDMICECEN_Pos   RCC_APB1LENR_CECEN_Pos
#define	RCC_APB1LENR_HDMICECEN_Msk   RCC_APB1LENR_CECEN_Msk
#define	RCC_APB1LENR_HDMICECEN   RCC_APB1LENR_CECEN
#define	RCC_APB1HENR_CRSEN_Pos   (1U)
#define	RCC_APB1HENR_CRSEN_Msk   (0x1UL << RCC_APB1HENR_CRSEN_Pos)
	0x00000002
#define	RCC_APB1HENR_CRSEN   RCC_APB1HENR_CRSEN_Msk
#define	RCC_APB1HENR_SWPMIEN_Pos   (2U)
#define	RCC_APB1HENR_SWPMIEN_Msk   (0x1UL << RCC_APB1HENR_SWPMIEN_Pos)
	0x00000004
#define	RCC_APB1HENR_SWPMIEN   RCC_APB1HENR_SWPMIEN_Msk
#define	RCC_APB1HENR_OPAMPEN_Pos   (4U)
#define	RCC_APB1HENR_OPAMPEN_Msk   (0x1UL << RCC_APB1HENR_OPAMPEN_Pos)
	0x00000010
#define	RCC_APB1HENR_OPAMPEN   RCC_APB1HENR_OPAMPEN_Msk
#define	RCC_APB1HENR_MDIOSEN_Pos   (5U)
#define	RCC_APB1HENR_MDIOSEN_Msk   (0x1UL << RCC_APB1HENR_MDIOSEN_Pos)
	0x00000020
#define	RCC_APB1HENR_MDIOSEN   RCC_APB1HENR_MDIOSEN_Msk
#define	RCC_APB1HENR_FDCANEN_Pos   (8U)
#define	RCC_APB1HENR_FDCANEN_Msk   (0x1UL << RCC_APB1HENR_FDCANEN_Pos)
	0x00000100
#define	RCC_APB1HENR_FDCANEN   RCC_APB1HENR_FDCANEN_Msk
#define	RCC_APB1HENR_TIM23EN_Pos   (24U)
#define	RCC_APB1HENR_TIM23EN_Msk   (0x1UL << RCC_APB1HENR_TIM23EN_Pos)
	0x01000000
#define	RCC_APB1HENR_TIM23EN   RCC_APB1HENR_TIM23EN_Msk
#define	RCC_APB1HENR_TIM24EN_Pos   (25U)
#define	RCC_APB1HENR_TIM24EN_Msk   (0x1UL << RCC_APB1HENR_TIM24EN_Pos)
	0x02000000
#define	RCC_APB1HENR_TIM24EN   RCC_APB1HENR_TIM24EN_Msk
#define	RCC_APB2ENR_TIM1EN_Pos   (0U)
#define	RCC_APB2ENR_TIM1EN_Msk   (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
	0x00000001
#define	RCC_APB2ENR_TIM1EN   RCC_APB2ENR_TIM1EN_Msk
#define	RCC_APB2ENR_TIM8EN_Pos   (1U)
#define	RCC_APB2ENR_TIM8EN_Msk   (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
	0x00000002
#define	RCC_APB2ENR_TIM8EN   RCC_APB2ENR_TIM8EN_Msk
#define	RCC_APB2ENR_USART1EN_Pos   (4U)
#define	RCC_APB2ENR_USART1EN_Msk   (0x1UL << RCC_APB2ENR_USART1EN_Pos)
	0x00000010
#define	RCC_APB2ENR_USART1EN   RCC_APB2ENR_USART1EN_Msk
#define	RCC_APB2ENR_USART6EN_Pos   (5U)
#define	RCC_APB2ENR_USART6EN_Msk   (0x1UL << RCC_APB2ENR_USART6EN_Pos)
	0x00000020
#define	RCC_APB2ENR_USART6EN   RCC_APB2ENR_USART6EN_Msk
#define	RCC_APB2ENR_UART9EN_Pos   (6U)
#define	RCC_APB2ENR_UART9EN_Msk   (0x1UL << RCC_APB2ENR_UART9EN_Pos)
	0x00000040
#define	RCC_APB2ENR_UART9EN   RCC_APB2ENR_UART9EN_Msk
#define	RCC_APB2ENR_USART10EN_Pos   (7U)
#define	RCC_APB2ENR_USART10EN_Msk   (0x1UL << RCC_APB2ENR_USART10EN_Pos)
	0x00000080
#define	RCC_APB2ENR_USART10EN   RCC_APB2ENR_USART10EN_Msk
#define	RCC_APB2ENR_SPI1EN_Pos   (12U)
#define	RCC_APB2ENR_SPI1EN_Msk   (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
	0x00001000
#define	RCC_APB2ENR_SPI1EN   RCC_APB2ENR_SPI1EN_Msk
#define	RCC_APB2ENR_SPI4EN_Pos   (13U)
#define	RCC_APB2ENR_SPI4EN_Msk   (0x1UL << RCC_APB2ENR_SPI4EN_Pos)
	0x00002000
#define	RCC_APB2ENR_SPI4EN   RCC_APB2ENR_SPI4EN_Msk
#define	RCC_APB2ENR_TIM15EN_Pos   (16U)
#define	RCC_APB2ENR_TIM15EN_Msk   (0x1UL << RCC_APB2ENR_TIM15EN_Pos)
	0x00010000
#define	RCC_APB2ENR_TIM15EN   RCC_APB2ENR_TIM15EN_Msk
#define	RCC_APB2ENR_TIM16EN_Pos   (17U)
#define	RCC_APB2ENR_TIM16EN_Msk   (0x1UL << RCC_APB2ENR_TIM16EN_Pos)
	0x00020000
#define	RCC_APB2ENR_TIM16EN   RCC_APB2ENR_TIM16EN_Msk
#define	RCC_APB2ENR_TIM17EN_Pos   (18U)
#define	RCC_APB2ENR_TIM17EN_Msk   (0x1UL << RCC_APB2ENR_TIM17EN_Pos)
	0x00040000
#define	RCC_APB2ENR_TIM17EN   RCC_APB2ENR_TIM17EN_Msk
#define	RCC_APB2ENR_SPI5EN_Pos   (20U)
#define	RCC_APB2ENR_SPI5EN_Msk   (0x1UL << RCC_APB2ENR_SPI5EN_Pos)
	0x00100000
#define	RCC_APB2ENR_SPI5EN   RCC_APB2ENR_SPI5EN_Msk
#define	RCC_APB2ENR_SAI1EN_Pos   (22U)
#define	RCC_APB2ENR_SAI1EN_Msk   (0x1UL << RCC_APB2ENR_SAI1EN_Pos)
	0x00400000
#define	RCC_APB2ENR_SAI1EN   RCC_APB2ENR_SAI1EN_Msk
#define	RCC_APB2ENR_DFSDM1EN_Pos   (30U)
#define	RCC_APB2ENR_DFSDM1EN_Msk   (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos)
	0x40000000
#define	RCC_APB2ENR_DFSDM1EN   RCC_APB2ENR_DFSDM1EN_Msk
#define	RCC_APB4ENR_SYSCFGEN_Pos   (1U)
#define	RCC_APB4ENR_SYSCFGEN_Msk   (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos)
	0x00000002
#define	RCC_APB4ENR_SYSCFGEN   RCC_APB4ENR_SYSCFGEN_Msk
#define	RCC_APB4ENR_LPUART1EN_Pos   (3U)
#define	RCC_APB4ENR_LPUART1EN_Msk   (0x1UL << RCC_APB4ENR_LPUART1EN_Pos)
	0x00000008
#define	RCC_APB4ENR_LPUART1EN   RCC_APB4ENR_LPUART1EN_Msk
#define	RCC_APB4ENR_SPI6EN_Pos   (5U)
#define	RCC_APB4ENR_SPI6EN_Msk   (0x1UL << RCC_APB4ENR_SPI6EN_Pos)
	0x00000020
#define	RCC_APB4ENR_SPI6EN   RCC_APB4ENR_SPI6EN_Msk
#define	RCC_APB4ENR_I2C4EN_Pos   (7U)
#define	RCC_APB4ENR_I2C4EN_Msk   (0x1UL << RCC_APB4ENR_I2C4EN_Pos)
	0x00000080
#define	RCC_APB4ENR_I2C4EN   RCC_APB4ENR_I2C4EN_Msk
#define	RCC_APB4ENR_LPTIM2EN_Pos   (9U)
#define	RCC_APB4ENR_LPTIM2EN_Msk   (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos)
	0x00000200
#define	RCC_APB4ENR_LPTIM2EN   RCC_APB4ENR_LPTIM2EN_Msk
#define	RCC_APB4ENR_LPTIM3EN_Pos   (10U)
#define	RCC_APB4ENR_LPTIM3EN_Msk   (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos)
	0x00000400
#define	RCC_APB4ENR_LPTIM3EN   RCC_APB4ENR_LPTIM3EN_Msk
#define	RCC_APB4ENR_LPTIM4EN_Pos   (11U)
#define	RCC_APB4ENR_LPTIM4EN_Msk   (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos)
	0x00000800
#define	RCC_APB4ENR_LPTIM4EN   RCC_APB4ENR_LPTIM4EN_Msk
#define	RCC_APB4ENR_LPTIM5EN_Pos   (12U)
#define	RCC_APB4ENR_LPTIM5EN_Msk   (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos)
	0x00001000
#define	RCC_APB4ENR_LPTIM5EN   RCC_APB4ENR_LPTIM5EN_Msk
#define	RCC_APB4ENR_COMP12EN_Pos   (14U)
#define	RCC_APB4ENR_COMP12EN_Msk   (0x1UL << RCC_APB4ENR_COMP12EN_Pos)
	0x00004000
#define	RCC_APB4ENR_COMP12EN   RCC_APB4ENR_COMP12EN_Msk
#define	RCC_APB4ENR_VREFEN_Pos   (15U)
#define	RCC_APB4ENR_VREFEN_Msk   (0x1UL << RCC_APB4ENR_VREFEN_Pos)
	0x00008000
#define	RCC_APB4ENR_VREFEN   RCC_APB4ENR_VREFEN_Msk
#define	RCC_APB4ENR_RTCAPBEN_Pos   (16U)
#define	RCC_APB4ENR_RTCAPBEN_Msk   (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos)
	0x00010000
#define	RCC_APB4ENR_RTCAPBEN   RCC_APB4ENR_RTCAPBEN_Msk
#define	RCC_APB4ENR_SAI4EN_Pos   (21U)
#define	RCC_APB4ENR_SAI4EN_Msk   (0x1UL << RCC_APB4ENR_SAI4EN_Pos)
	0x00200000
#define	RCC_APB4ENR_SAI4EN   RCC_APB4ENR_SAI4EN_Msk
#define	RCC_APB4ENR_DTSEN_Pos   (26U)
#define	RCC_APB4ENR_DTSEN_Msk   (0x1UL << RCC_APB4ENR_DTSEN_Pos)
	0x04000000
#define	RCC_APB4ENR_DTSEN   RCC_APB4ENR_DTSEN_Msk
#define	RCC_AHB3RSTR_MDMARST_Pos   (0U)
#define	RCC_AHB3RSTR_MDMARST_Msk   (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)
	0x00000001
#define	RCC_AHB3RSTR_MDMARST   RCC_AHB3RSTR_MDMARST_Msk
#define	RCC_AHB3RSTR_DMA2DRST_Pos   (4U)
#define	RCC_AHB3RSTR_DMA2DRST_Msk   (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)
	0x00000010
#define	RCC_AHB3RSTR_DMA2DRST   RCC_AHB3RSTR_DMA2DRST_Msk
#define	RCC_AHB3RSTR_FMCRST_Pos   (12U)
#define	RCC_AHB3RSTR_FMCRST_Msk   (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)
	0x00001000
#define	RCC_AHB3RSTR_FMCRST   RCC_AHB3RSTR_FMCRST_Msk
#define	RCC_AHB3RSTR_OSPI1RST_Pos   (14U)
#define	RCC_AHB3RSTR_OSPI1RST_Msk   (0x1UL << RCC_AHB3RSTR_OSPI1RST_Pos)
	0x00004000
#define	RCC_AHB3RSTR_OSPI1RST   RCC_AHB3RSTR_OSPI1RST_Msk
#define	RCC_AHB3RSTR_SDMMC1RST_Pos   (16U)
#define	RCC_AHB3RSTR_SDMMC1RST_Msk   (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)
	0x00010000
#define	RCC_AHB3RSTR_SDMMC1RST   RCC_AHB3RSTR_SDMMC1RST_Msk
#define	RCC_AHB3RSTR_OSPI2RST_Pos   (19U)
#define	RCC_AHB3RSTR_OSPI2RST_Msk   (0x1UL << RCC_AHB3RSTR_OSPI2RST_Pos)
	0x00008000
#define	RCC_AHB3RSTR_OSPI2RST   RCC_AHB3RSTR_OSPI2RST_Msk
#define	RCC_AHB3RSTR_IOMNGRRST_Pos   (21U)
#define	RCC_AHB3RSTR_IOMNGRRST_Msk   (0x1UL << RCC_AHB3RSTR_IOMNGRRST_Pos)
	0x00020000
#define	RCC_AHB3RSTR_IOMNGRRST   RCC_AHB3RSTR_IOMNGRRST_Msk
#define	RCC_AHB3RSTR_CPURST_Pos   (31U)
#define	RCC_AHB3RSTR_CPURST_Msk   (0x1UL << RCC_AHB3RSTR_CPURST_Pos)
	0x80000000
#define	RCC_AHB3RSTR_CPURST   RCC_AHB3RSTR_CPURST_Msk
#define	RCC_AHB1RSTR_DMA1RST_Pos   (0U)
#define	RCC_AHB1RSTR_DMA1RST_Msk   (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
	0x00000001
#define	RCC_AHB1RSTR_DMA1RST   RCC_AHB1RSTR_DMA1RST_Msk
#define	RCC_AHB1RSTR_DMA2RST_Pos   (1U)
#define	RCC_AHB1RSTR_DMA2RST_Msk   (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
	0x00000002
#define	RCC_AHB1RSTR_DMA2RST   RCC_AHB1RSTR_DMA2RST_Msk
#define	RCC_AHB1RSTR_ADC12RST_Pos   (5U)
#define	RCC_AHB1RSTR_ADC12RST_Msk   (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)
	0x00000020
#define	RCC_AHB1RSTR_ADC12RST   RCC_AHB1RSTR_ADC12RST_Msk
#define	RCC_AHB1RSTR_ETH1MACRST_Pos   (15U)
#define	RCC_AHB1RSTR_ETH1MACRST_Msk   (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos)
	0x00008000
#define	RCC_AHB1RSTR_ETH1MACRST   RCC_AHB1RSTR_ETH1MACRST_Msk
#define	RCC_AHB1RSTR_USB1OTGHSRST_Pos   (25U)
#define	RCC_AHB1RSTR_USB1OTGHSRST_Msk   (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos)
	0x02000000
#define	RCC_AHB1RSTR_USB1OTGHSRST   RCC_AHB1RSTR_USB1OTGHSRST_Msk
#define	RCC_AHB2RSTR_DCMI_PSSIRST_Pos   (0U)
#define	RCC_AHB2RSTR_DCMI_PSSIRST_Msk   (0x1UL << RCC_AHB2RSTR_DCMI_PSSIRST_Pos)
	0x00000001
#define	RCC_AHB2RSTR_DCMI_PSSIRST   RCC_AHB2RSTR_DCMI_PSSIRST_Msk
#define	RCC_AHB2RSTR_RNGRST_Pos   (6U)
#define	RCC_AHB2RSTR_RNGRST_Msk   (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
	0x00000040
#define	RCC_AHB2RSTR_RNGRST   RCC_AHB2RSTR_RNGRST_Msk
#define	RCC_AHB2RSTR_SDMMC2RST_Pos   (9U)
#define	RCC_AHB2RSTR_SDMMC2RST_Msk   (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)
	0x00000200
#define	RCC_AHB2RSTR_SDMMC2RST   RCC_AHB2RSTR_SDMMC2RST_Msk
#define	RCC_AHB2RSTR_FMACRST_Pos   (16U)
#define	RCC_AHB2RSTR_FMACRST_Msk   (0x1UL << RCC_AHB2RSTR_FMACRST_Pos)
	0x00010000
#define	RCC_AHB2RSTR_FMACRST   RCC_AHB2RSTR_FMACRST_Msk
#define	RCC_AHB2RSTR_CORDICRST_Pos   (17U)
#define	RCC_AHB2RSTR_CORDICRST_Msk   (0x1UL << RCC_AHB2RSTR_CORDICRST_Pos)
	0x00020000
#define	RCC_AHB2RSTR_CORDICRST   RCC_AHB2RSTR_CORDICRST_Msk
#define	RCC_AHB2RSTR_DCMIRST_Pos   RCC_AHB2RSTR_DCMI_PSSIRST_Pos
#define	RCC_AHB2RSTR_DCMIRST_Msk   RCC_AHB2RSTR_DCMI_PSSIRST_Msk
#define	RCC_AHB2RSTR_DCMIRST   RCC_AHB2RSTR_DCMI_PSSIRST
#define	RCC_AHB4RSTR_GPIOARST_Pos   (0U)
#define	RCC_AHB4RSTR_GPIOARST_Msk   (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)
	0x00000001
#define	RCC_AHB4RSTR_GPIOARST   RCC_AHB4RSTR_GPIOARST_Msk
#define	RCC_AHB4RSTR_GPIOBRST_Pos   (1U)
#define	RCC_AHB4RSTR_GPIOBRST_Msk   (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)
	0x00000002
#define	RCC_AHB4RSTR_GPIOBRST   RCC_AHB4RSTR_GPIOBRST_Msk
#define	RCC_AHB4RSTR_GPIOCRST_Pos   (2U)
#define	RCC_AHB4RSTR_GPIOCRST_Msk   (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)
	0x00000004
#define	RCC_AHB4RSTR_GPIOCRST   RCC_AHB4RSTR_GPIOCRST_Msk
#define	RCC_AHB4RSTR_GPIODRST_Pos   (3U)
#define	RCC_AHB4RSTR_GPIODRST_Msk   (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)
	0x00000008
#define	RCC_AHB4RSTR_GPIODRST   RCC_AHB4RSTR_GPIODRST_Msk
#define	RCC_AHB4RSTR_GPIOERST_Pos   (4U)
#define	RCC_AHB4RSTR_GPIOERST_Msk   (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)
	0x00000010
#define	RCC_AHB4RSTR_GPIOERST   RCC_AHB4RSTR_GPIOERST_Msk
#define	RCC_AHB4RSTR_GPIOFRST_Pos   (5U)
#define	RCC_AHB4RSTR_GPIOFRST_Msk   (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)
	0x00000020
#define	RCC_AHB4RSTR_GPIOFRST   RCC_AHB4RSTR_GPIOFRST_Msk
#define	RCC_AHB4RSTR_GPIOGRST_Pos   (6U)
#define	RCC_AHB4RSTR_GPIOGRST_Msk   (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)
	0x00000040
#define	RCC_AHB4RSTR_GPIOGRST   RCC_AHB4RSTR_GPIOGRST_Msk
#define	RCC_AHB4RSTR_GPIOHRST_Pos   (7U)
#define	RCC_AHB4RSTR_GPIOHRST_Msk   (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)
	0x00000080
#define	RCC_AHB4RSTR_GPIOHRST   RCC_AHB4RSTR_GPIOHRST_Msk
#define	RCC_AHB4RSTR_GPIOJRST_Pos   (9U)
#define	RCC_AHB4RSTR_GPIOJRST_Msk   (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)
	0x00000200
#define	RCC_AHB4RSTR_GPIOJRST   RCC_AHB4RSTR_GPIOJRST_Msk
#define	RCC_AHB4RSTR_GPIOKRST_Pos   (10U)
#define	RCC_AHB4RSTR_GPIOKRST_Msk   (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)
	0x00000400
#define	RCC_AHB4RSTR_GPIOKRST   RCC_AHB4RSTR_GPIOKRST_Msk
#define	RCC_AHB4RSTR_CRCRST_Pos   (19U)
#define	RCC_AHB4RSTR_CRCRST_Msk   (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)
	0x00080000
#define	RCC_AHB4RSTR_CRCRST   RCC_AHB4RSTR_CRCRST_Msk
#define	RCC_AHB4RSTR_BDMARST_Pos   (21U)
#define	RCC_AHB4RSTR_BDMARST_Msk   (0x1UL << RCC_AHB4RSTR_BDMARST_Pos)
	0x00200000
#define	RCC_AHB4RSTR_BDMARST   RCC_AHB4RSTR_BDMARST_Msk
#define	RCC_AHB4RSTR_ADC3RST_Pos   (24U)
#define	RCC_AHB4RSTR_ADC3RST_Msk   (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos)
	0x01000000
#define	RCC_AHB4RSTR_ADC3RST   RCC_AHB4RSTR_ADC3RST_Msk
#define	RCC_AHB4RSTR_HSEMRST_Pos   (25U)
#define	RCC_AHB4RSTR_HSEMRST_Msk   (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos)
	0x02000000
#define	RCC_AHB4RSTR_HSEMRST   RCC_AHB4RSTR_HSEMRST_Msk
#define	RCC_APB3RSTR_LTDCRST_Pos   (3U)
#define	RCC_APB3RSTR_LTDCRST_Msk   (0x1UL << RCC_APB3RSTR_LTDCRST_Pos)
	0x00000008
#define	RCC_APB3RSTR_LTDCRST   RCC_APB3RSTR_LTDCRST_Msk
#define	RCC_APB1LRSTR_TIM2RST_Pos   (0U)
#define	RCC_APB1LRSTR_TIM2RST_Msk   (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos)
	0x00000001
#define	RCC_APB1LRSTR_TIM2RST   RCC_APB1LRSTR_TIM2RST_Msk
#define	RCC_APB1LRSTR_TIM3RST_Pos   (1U)
#define	RCC_APB1LRSTR_TIM3RST_Msk   (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos)
	0x00000002
#define	RCC_APB1LRSTR_TIM3RST   RCC_APB1LRSTR_TIM3RST_Msk
#define	RCC_APB1LRSTR_TIM4RST_Pos   (2U)
#define	RCC_APB1LRSTR_TIM4RST_Msk   (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos)
	0x00000004
#define	RCC_APB1LRSTR_TIM4RST   RCC_APB1LRSTR_TIM4RST_Msk
#define	RCC_APB1LRSTR_TIM5RST_Pos   (3U)
#define	RCC_APB1LRSTR_TIM5RST_Msk   (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos)
	0x00000008
#define	RCC_APB1LRSTR_TIM5RST   RCC_APB1LRSTR_TIM5RST_Msk
#define	RCC_APB1LRSTR_TIM6RST_Pos   (4U)
#define	RCC_APB1LRSTR_TIM6RST_Msk   (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos)
	0x00000010
#define	RCC_APB1LRSTR_TIM6RST   RCC_APB1LRSTR_TIM6RST_Msk
#define	RCC_APB1LRSTR_TIM7RST_Pos   (5U)
#define	RCC_APB1LRSTR_TIM7RST_Msk   (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos)
	0x00000020
#define	RCC_APB1LRSTR_TIM7RST   RCC_APB1LRSTR_TIM7RST_Msk
#define	RCC_APB1LRSTR_TIM12RST_Pos   (6U)
#define	RCC_APB1LRSTR_TIM12RST_Msk   (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos)
	0x00000040
#define	RCC_APB1LRSTR_TIM12RST   RCC_APB1LRSTR_TIM12RST_Msk
#define	RCC_APB1LRSTR_TIM13RST_Pos   (7U)
#define	RCC_APB1LRSTR_TIM13RST_Msk   (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos)
	0x00000080
#define	RCC_APB1LRSTR_TIM13RST   RCC_APB1LRSTR_TIM13RST_Msk
#define	RCC_APB1LRSTR_TIM14RST_Pos   (8U)
#define	RCC_APB1LRSTR_TIM14RST_Msk   (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos)
	0x00000100
#define	RCC_APB1LRSTR_TIM14RST   RCC_APB1LRSTR_TIM14RST_Msk
#define	RCC_APB1LRSTR_LPTIM1RST_Pos   (9U)
#define	RCC_APB1LRSTR_LPTIM1RST_Msk   (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos)
	0x00000200
#define	RCC_APB1LRSTR_LPTIM1RST   RCC_APB1LRSTR_LPTIM1RST_Msk
#define	RCC_APB1LRSTR_SPI2RST_Pos   (14U)
#define	RCC_APB1LRSTR_SPI2RST_Msk   (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos)
	0x00004000
#define	RCC_APB1LRSTR_SPI2RST   RCC_APB1LRSTR_SPI2RST_Msk
#define	RCC_APB1LRSTR_SPI3RST_Pos   (15U)
#define	RCC_APB1LRSTR_SPI3RST_Msk   (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos)
	0x00008000
#define	RCC_APB1LRSTR_SPI3RST   RCC_APB1LRSTR_SPI3RST_Msk
#define	RCC_APB1LRSTR_SPDIFRXRST_Pos   (16U)
#define	RCC_APB1LRSTR_SPDIFRXRST_Msk   (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos)
	0x00010000
#define	RCC_APB1LRSTR_SPDIFRXRST   RCC_APB1LRSTR_SPDIFRXRST_Msk
#define	RCC_APB1LRSTR_USART2RST_Pos   (17U)
#define	RCC_APB1LRSTR_USART2RST_Msk   (0x1UL << RCC_APB1LRSTR_USART2RST_Pos)
	0x00020000
#define	RCC_APB1LRSTR_USART2RST   RCC_APB1LRSTR_USART2RST_Msk
#define	RCC_APB1LRSTR_USART3RST_Pos   (18U)
#define	RCC_APB1LRSTR_USART3RST_Msk   (0x1UL << RCC_APB1LRSTR_USART3RST_Pos)
	0x00040000
#define	RCC_APB1LRSTR_USART3RST   RCC_APB1LRSTR_USART3RST_Msk
#define	RCC_APB1LRSTR_UART4RST_Pos   (19U)
#define	RCC_APB1LRSTR_UART4RST_Msk   (0x1UL << RCC_APB1LRSTR_UART4RST_Pos)
	0x00080000
#define	RCC_APB1LRSTR_UART4RST   RCC_APB1LRSTR_UART4RST_Msk
#define	RCC_APB1LRSTR_UART5RST_Pos   (20U)
#define	RCC_APB1LRSTR_UART5RST_Msk   (0x1UL << RCC_APB1LRSTR_UART5RST_Pos)
	0x00100000
#define	RCC_APB1LRSTR_UART5RST   RCC_APB1LRSTR_UART5RST_Msk
#define	RCC_APB1LRSTR_I2C1RST_Pos   (21U)
#define	RCC_APB1LRSTR_I2C1RST_Msk   (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos)
	0x00200000
#define	RCC_APB1LRSTR_I2C1RST   RCC_APB1LRSTR_I2C1RST_Msk
#define	RCC_APB1LRSTR_I2C2RST_Pos   (22U)
#define	RCC_APB1LRSTR_I2C2RST_Msk   (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos)
	0x00400000
#define	RCC_APB1LRSTR_I2C2RST   RCC_APB1LRSTR_I2C2RST_Msk
#define	RCC_APB1LRSTR_I2C3RST_Pos   (23U)
#define	RCC_APB1LRSTR_I2C3RST_Msk   (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos)
	0x00800000
#define	RCC_APB1LRSTR_I2C3RST   RCC_APB1LRSTR_I2C3RST_Msk
#define	RCC_APB1LRSTR_I2C5RST_Pos   (25U)
#define	RCC_APB1LRSTR_I2C5RST_Msk   (0x1UL << RCC_APB1LRSTR_I2C5RST_Pos)
	0x02000000
#define	RCC_APB1LRSTR_I2C5RST   RCC_APB1LRSTR_I2C5RST_Msk
#define	RCC_APB1LRSTR_CECRST_Pos   (27U)
#define	RCC_APB1LRSTR_CECRST_Msk   (0x1UL << RCC_APB1LRSTR_CECRST_Pos)
	0x08000000
#define	RCC_APB1LRSTR_CECRST   RCC_APB1LRSTR_CECRST_Msk
#define	RCC_APB1LRSTR_DAC12RST_Pos   (29U)
#define	RCC_APB1LRSTR_DAC12RST_Msk   (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos)
	0x20000000
#define	RCC_APB1LRSTR_DAC12RST   RCC_APB1LRSTR_DAC12RST_Msk
#define	RCC_APB1LRSTR_UART7RST_Pos   (30U)
#define	RCC_APB1LRSTR_UART7RST_Msk   (0x1UL << RCC_APB1LRSTR_UART7RST_Pos)
	0x40000000
#define	RCC_APB1LRSTR_UART7RST   RCC_APB1LRSTR_UART7RST_Msk
#define	RCC_APB1LRSTR_UART8RST_Pos   (31U)
#define	RCC_APB1LRSTR_UART8RST_Msk   (0x1UL << RCC_APB1LRSTR_UART8RST_Pos)
	0x80000000
#define	RCC_APB1LRSTR_UART8RST   RCC_APB1LRSTR_UART8RST_Msk
#define	RCC_APB1LRSTR_HDMICECRST_Pos   RCC_APB1LRSTR_CECRST_Pos
#define	RCC_APB1LRSTR_HDMICECRST_Msk   RCC_APB1LRSTR_CECRST_Msk
#define	RCC_APB1LRSTR_HDMICECRST   RCC_APB1LRSTR_CECRST
#define	RCC_APB1HRSTR_CRSRST_Pos   (1U)
#define	RCC_APB1HRSTR_CRSRST_Msk   (0x1UL << RCC_APB1HRSTR_CRSRST_Pos)
	0x00000002
#define	RCC_APB1HRSTR_CRSRST   RCC_APB1HRSTR_CRSRST_Msk
#define	RCC_APB1HRSTR_SWPMIRST_Pos   (2U)
#define	RCC_APB1HRSTR_SWPMIRST_Msk   (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos)
	0x00000004
#define	RCC_APB1HRSTR_SWPMIRST   RCC_APB1HRSTR_SWPMIRST_Msk
#define	RCC_APB1HRSTR_OPAMPRST_Pos   (4U)
#define	RCC_APB1HRSTR_OPAMPRST_Msk   (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos)
	0x00000010
#define	RCC_APB1HRSTR_OPAMPRST   RCC_APB1HRSTR_OPAMPRST_Msk
#define	RCC_APB1HRSTR_MDIOSRST_Pos   (5U)
#define	RCC_APB1HRSTR_MDIOSRST_Msk   (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos)
	0x00000020
#define	RCC_APB1HRSTR_MDIOSRST   RCC_APB1HRSTR_MDIOSRST_Msk
#define	RCC_APB1HRSTR_FDCANRST_Pos   (8U)
#define	RCC_APB1HRSTR_FDCANRST_Msk   (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos)
	0x00000100
#define	RCC_APB1HRSTR_FDCANRST   RCC_APB1HRSTR_FDCANRST_Msk
#define	RCC_APB1HRSTR_TIM23RST_Pos   (24U)
#define	RCC_APB1HRSTR_TIM23RST_Msk   (0x1UL << RCC_APB1HRSTR_TIM23RST_Pos)
	0x01000000
#define	RCC_APB1HRSTR_TIM23RST   RCC_APB1HRSTR_TIM23RST_Msk
#define	RCC_APB1HRSTR_TIM24RST_Pos   (25U)
#define	RCC_APB1HRSTR_TIM24RST_Msk   (0x1UL << RCC_APB1HRSTR_TIM24RST_Pos)
	0x02000000
#define	RCC_APB1HRSTR_TIM24RST   RCC_APB1HRSTR_TIM24RST_Msk
#define	RCC_APB2RSTR_TIM1RST_Pos   (0U)
#define	RCC_APB2RSTR_TIM1RST_Msk   (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
	0x00000001
#define	RCC_APB2RSTR_TIM1RST   RCC_APB2RSTR_TIM1RST_Msk
#define	RCC_APB2RSTR_TIM8RST_Pos   (1U)
#define	RCC_APB2RSTR_TIM8RST_Msk   (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
	0x00000002
#define	RCC_APB2RSTR_TIM8RST   RCC_APB2RSTR_TIM8RST_Msk
#define	RCC_APB2RSTR_USART1RST_Pos   (4U)
#define	RCC_APB2RSTR_USART1RST_Msk   (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
	0x00000010
#define	RCC_APB2RSTR_USART1RST   RCC_APB2RSTR_USART1RST_Msk
#define	RCC_APB2RSTR_USART6RST_Pos   (5U)
#define	RCC_APB2RSTR_USART6RST_Msk   (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
	0x00000020
#define	RCC_APB2RSTR_USART6RST   RCC_APB2RSTR_USART6RST_Msk
#define	RCC_APB2RSTR_UART9RST_Pos   (6U)
#define	RCC_APB2RSTR_UART9RST_Msk   (0x1UL << RCC_APB2RSTR_UART9RST_Pos)
	0x00000040
#define	RCC_APB2RSTR_UART9RST   RCC_APB2RSTR_UART9RST_Msk
#define	RCC_APB2RSTR_USART10RST_Pos   (7U)
#define	RCC_APB2RSTR_USART10RST_Msk   (0x1UL << RCC_APB2RSTR_USART10RST_Pos)
	0x00000080
#define	RCC_APB2RSTR_USART10RST   RCC_APB2RSTR_USART10RST_Msk
#define	RCC_APB2RSTR_SPI1RST_Pos   (12U)
#define	RCC_APB2RSTR_SPI1RST_Msk   (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
	0x00001000
#define	RCC_APB2RSTR_SPI1RST   RCC_APB2RSTR_SPI1RST_Msk
#define	RCC_APB2RSTR_SPI4RST_Pos   (13U)
#define	RCC_APB2RSTR_SPI4RST_Msk   (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)
	0x00002000
#define	RCC_APB2RSTR_SPI4RST   RCC_APB2RSTR_SPI4RST_Msk
#define	RCC_APB2RSTR_TIM15RST_Pos   (16U)
#define	RCC_APB2RSTR_TIM15RST_Msk   (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)
	0x00010000
#define	RCC_APB2RSTR_TIM15RST   RCC_APB2RSTR_TIM15RST_Msk
#define	RCC_APB2RSTR_TIM16RST_Pos   (17U)
#define	RCC_APB2RSTR_TIM16RST_Msk   (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)
	0x00020000
#define	RCC_APB2RSTR_TIM16RST   RCC_APB2RSTR_TIM16RST_Msk
#define	RCC_APB2RSTR_TIM17RST_Pos   (18U)
#define	RCC_APB2RSTR_TIM17RST_Msk   (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)
	0x00040000
#define	RCC_APB2RSTR_TIM17RST   RCC_APB2RSTR_TIM17RST_Msk
#define	RCC_APB2RSTR_SPI5RST_Pos   (20U)
#define	RCC_APB2RSTR_SPI5RST_Msk   (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)
	0x00100000
#define	RCC_APB2RSTR_SPI5RST   RCC_APB2RSTR_SPI5RST_Msk
#define	RCC_APB2RSTR_SAI1RST_Pos   (22U)
#define	RCC_APB2RSTR_SAI1RST_Msk   (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)
	0x00400000
#define	RCC_APB2RSTR_SAI1RST   RCC_APB2RSTR_SAI1RST_Msk
#define	RCC_APB2RSTR_DFSDM1RST_Pos   (30U)
#define	RCC_APB2RSTR_DFSDM1RST_Msk   (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos)
	0x10000000
#define	RCC_APB2RSTR_DFSDM1RST   RCC_APB2RSTR_DFSDM1RST_Msk
#define	RCC_APB4RSTR_SYSCFGRST_Pos   (1U)
#define	RCC_APB4RSTR_SYSCFGRST_Msk   (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos)
	0x00000002
#define	RCC_APB4RSTR_SYSCFGRST   RCC_APB4RSTR_SYSCFGRST_Msk
#define	RCC_APB4RSTR_LPUART1RST_Pos   (3U)
#define	RCC_APB4RSTR_LPUART1RST_Msk   (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos)
	0x00000008
#define	RCC_APB4RSTR_LPUART1RST   RCC_APB4RSTR_LPUART1RST_Msk
#define	RCC_APB4RSTR_SPI6RST_Pos   (5U)
#define	RCC_APB4RSTR_SPI6RST_Msk   (0x1UL << RCC_APB4RSTR_SPI6RST_Pos)
	0x00000020
#define	RCC_APB4RSTR_SPI6RST   RCC_APB4RSTR_SPI6RST_Msk
#define	RCC_APB4RSTR_I2C4RST_Pos   (7U)
#define	RCC_APB4RSTR_I2C4RST_Msk   (0x1UL << RCC_APB4RSTR_I2C4RST_Pos)
	0x00000080
#define	RCC_APB4RSTR_I2C4RST   RCC_APB4RSTR_I2C4RST_Msk
#define	RCC_APB4RSTR_LPTIM2RST_Pos   (9U)
#define	RCC_APB4RSTR_LPTIM2RST_Msk   (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos)
	0x00000200
#define	RCC_APB4RSTR_LPTIM2RST   RCC_APB4RSTR_LPTIM2RST_Msk
#define	RCC_APB4RSTR_LPTIM3RST_Pos   (10U)
#define	RCC_APB4RSTR_LPTIM3RST_Msk   (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos)
	0x00000400
#define	RCC_APB4RSTR_LPTIM3RST   RCC_APB4RSTR_LPTIM3RST_Msk
#define	RCC_APB4RSTR_LPTIM4RST_Pos   (11U)
#define	RCC_APB4RSTR_LPTIM4RST_Msk   (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos)
	0x00000800
#define	RCC_APB4RSTR_LPTIM4RST   RCC_APB4RSTR_LPTIM4RST_Msk
#define	RCC_APB4RSTR_LPTIM5RST_Pos   (12U)
#define	RCC_APB4RSTR_LPTIM5RST_Msk   (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos)
	0x00001000
#define	RCC_APB4RSTR_LPTIM5RST   RCC_APB4RSTR_LPTIM5RST_Msk
#define	RCC_APB4RSTR_COMP12RST_Pos   (14U)
#define	RCC_APB4RSTR_COMP12RST_Msk   (0x1UL << RCC_APB4RSTR_COMP12RST_Pos)
	0x00004000
#define	RCC_APB4RSTR_COMP12RST   RCC_APB4RSTR_COMP12RST_Msk
#define	RCC_APB4RSTR_VREFRST_Pos   (15U)
#define	RCC_APB4RSTR_VREFRST_Msk   (0x1UL << RCC_APB4RSTR_VREFRST_Pos)
	0x00008000
#define	RCC_APB4RSTR_VREFRST   RCC_APB4RSTR_VREFRST_Msk
#define	RCC_APB4RSTR_SAI4RST_Pos   (21U)
#define	RCC_APB4RSTR_SAI4RST_Msk   (0x1UL << RCC_APB4RSTR_SAI4RST_Pos)
	0x00200000
#define	RCC_APB4RSTR_SAI4RST   RCC_APB4RSTR_SAI4RST_Msk
#define	RCC_APB4RSTR_DTSRST_Pos   (26U)
#define	RCC_APB4RSTR_DTSRST_Msk   (0x1UL << RCC_APB4RSTR_DTSRST_Pos)
	0x04000000
#define	RCC_APB4RSTR_DTSRST   RCC_APB4RSTR_DTSRST_Msk
#define	RCC_GCR_WW1RSC_Pos   (0U)
#define	RCC_GCR_WW1RSC_Msk   (0x1UL << RCC_GCR_WW1RSC_Pos)
	0x00000001
#define	RCC_GCR_WW1RSC   RCC_GCR_WW1RSC_Msk
#define	RCC_D3AMR_BDMAAMEN_Pos   (0U)
#define	RCC_D3AMR_BDMAAMEN_Msk   (0x1UL << RCC_D3AMR_BDMAAMEN_Pos)
	0x00000001
#define	RCC_D3AMR_BDMAAMEN   RCC_D3AMR_BDMAAMEN_Msk
#define	RCC_D3AMR_LPUART1AMEN_Pos   (3U)
#define	RCC_D3AMR_LPUART1AMEN_Msk   (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos)
	0x00000008
#define	RCC_D3AMR_LPUART1AMEN   RCC_D3AMR_LPUART1AMEN_Msk
#define	RCC_D3AMR_SPI6AMEN_Pos   (5U)
#define	RCC_D3AMR_SPI6AMEN_Msk   (0x1UL << RCC_D3AMR_SPI6AMEN_Pos)
	0x00000020
#define	RCC_D3AMR_SPI6AMEN   RCC_D3AMR_SPI6AMEN_Msk
#define	RCC_D3AMR_I2C4AMEN_Pos   (7U)
#define	RCC_D3AMR_I2C4AMEN_Msk   (0x1UL << RCC_D3AMR_I2C4AMEN_Pos)
	0x00000080
#define	RCC_D3AMR_I2C4AMEN   RCC_D3AMR_I2C4AMEN_Msk
#define	RCC_D3AMR_LPTIM2AMEN_Pos   (9U)
#define	RCC_D3AMR_LPTIM2AMEN_Msk   (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos)
	0x00000200
#define	RCC_D3AMR_LPTIM2AMEN   RCC_D3AMR_LPTIM2AMEN_Msk
#define	RCC_D3AMR_LPTIM3AMEN_Pos   (10U)
#define	RCC_D3AMR_LPTIM3AMEN_Msk   (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos)
	0x00000400
#define	RCC_D3AMR_LPTIM3AMEN   RCC_D3AMR_LPTIM3AMEN_Msk
#define	RCC_D3AMR_LPTIM4AMEN_Pos   (11U)
#define	RCC_D3AMR_LPTIM4AMEN_Msk   (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos)
	0x00000800
#define	RCC_D3AMR_LPTIM4AMEN   RCC_D3AMR_LPTIM4AMEN_Msk
#define	RCC_D3AMR_LPTIM5AMEN_Pos   (12U)
#define	RCC_D3AMR_LPTIM5AMEN_Msk   (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos)
	0x00001000
#define	RCC_D3AMR_LPTIM5AMEN   RCC_D3AMR_LPTIM5AMEN_Msk
#define	RCC_D3AMR_COMP12AMEN_Pos   (14U)
#define	RCC_D3AMR_COMP12AMEN_Msk   (0x1UL << RCC_D3AMR_COMP12AMEN_Pos)
	0x00004000
#define	RCC_D3AMR_COMP12AMEN   RCC_D3AMR_COMP12AMEN_Msk
#define	RCC_D3AMR_VREFAMEN_Pos   (15U)
#define	RCC_D3AMR_VREFAMEN_Msk   (0x1UL << RCC_D3AMR_VREFAMEN_Pos)
	0x00008000
#define	RCC_D3AMR_VREFAMEN   RCC_D3AMR_VREFAMEN_Msk
#define	RCC_D3AMR_RTCAMEN_Pos   (16U)
#define	RCC_D3AMR_RTCAMEN_Msk   (0x1UL << RCC_D3AMR_RTCAMEN_Pos)
	0x00010000
#define	RCC_D3AMR_RTCAMEN   RCC_D3AMR_RTCAMEN_Msk
#define	RCC_D3AMR_CRCAMEN_Pos   (19U)
#define	RCC_D3AMR_CRCAMEN_Msk   (0x1UL << RCC_D3AMR_CRCAMEN_Pos)
	0x00080000
#define	RCC_D3AMR_CRCAMEN   RCC_D3AMR_CRCAMEN_Msk
#define	RCC_D3AMR_SAI4AMEN_Pos   (21U)
#define	RCC_D3AMR_SAI4AMEN_Msk   (0x1UL << RCC_D3AMR_SAI4AMEN_Pos)
	0x00200000
#define	RCC_D3AMR_SAI4AMEN   RCC_D3AMR_SAI4AMEN_Msk
#define	RCC_D3AMR_ADC3AMEN_Pos   (24U)
#define	RCC_D3AMR_ADC3AMEN_Msk   (0x1UL << RCC_D3AMR_ADC3AMEN_Pos)
	0x01000000
#define	RCC_D3AMR_ADC3AMEN   RCC_D3AMR_ADC3AMEN_Msk
#define	RCC_D3AMR_DTSAMEN_Pos   (26U)
#define	RCC_D3AMR_DTSAMEN_Msk   (0x1UL << RCC_D3AMR_DTSAMEN_Pos)
	0x04000000
#define	RCC_D3AMR_DTSAMEN   RCC_D3AMR_DTSAMEN_Msk
#define	RCC_D3AMR_BKPRAMAMEN_Pos   (28U)
#define	RCC_D3AMR_BKPRAMAMEN_Msk   (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos)
	0x10000000
#define	RCC_D3AMR_BKPRAMAMEN   RCC_D3AMR_BKPRAMAMEN_Msk
#define	RCC_D3AMR_SRAM4AMEN_Pos   (29U)
#define	RCC_D3AMR_SRAM4AMEN_Msk   (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos)
	0x20000000
#define	RCC_D3AMR_SRAM4AMEN   RCC_D3AMR_SRAM4AMEN_Msk
#define	RCC_AHB3LPENR_MDMALPEN_Pos   (0U)
#define	RCC_AHB3LPENR_MDMALPEN_Msk   (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)
	0x00000001
#define	RCC_AHB3LPENR_MDMALPEN   RCC_AHB3LPENR_MDMALPEN_Msk
#define	RCC_AHB3LPENR_DMA2DLPEN_Pos   (4U)
#define	RCC_AHB3LPENR_DMA2DLPEN_Msk   (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)
	0x00000010
#define	RCC_AHB3LPENR_DMA2DLPEN   RCC_AHB3LPENR_DMA2DLPEN_Msk
#define	RCC_AHB3LPENR_FLASHLPEN_Pos   (8U)
#define	RCC_AHB3LPENR_FLASHLPEN_Msk   (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)
	0x00000100
#define	RCC_AHB3LPENR_FLASHLPEN   RCC_AHB3LPENR_FLASHLPEN_Msk
#define	RCC_AHB3LPENR_FMCLPEN_Pos   (12U)
#define	RCC_AHB3LPENR_FMCLPEN_Msk   (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)
	0x00001000
#define	RCC_AHB3LPENR_FMCLPEN   RCC_AHB3LPENR_FMCLPEN_Msk
#define	RCC_AHB3LPENR_OSPI1LPEN_Pos   (14U)
#define	RCC_AHB3LPENR_OSPI1LPEN_Msk   (0x1UL << RCC_AHB3LPENR_OSPI1LPEN_Pos)
	0x00004000
#define	RCC_AHB3LPENR_OSPI1LPEN   RCC_AHB3LPENR_OSPI1LPEN_Msk
#define	RCC_AHB3LPENR_SDMMC1LPEN_Pos   (16U)
#define	RCC_AHB3LPENR_SDMMC1LPEN_Msk   (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)
	0x00010000
#define	RCC_AHB3LPENR_SDMMC1LPEN   RCC_AHB3LPENR_SDMMC1LPEN_Msk
#define	RCC_AHB3LPENR_OSPI2LPEN_Pos   (19U)
#define	RCC_AHB3LPENR_OSPI2LPEN_Msk   (0x1UL << RCC_AHB3LPENR_OSPI2LPEN_Pos)
	0x00080000
#define	RCC_AHB3LPENR_OSPI2LPEN   RCC_AHB3LPENR_OSPI2LPEN_Msk
#define	RCC_AHB3LPENR_IOMNGRLPEN_Pos   (21U)
#define	RCC_AHB3LPENR_IOMNGRLPEN_Msk   (0x1UL << RCC_AHB3LPENR_IOMNGRLPEN_Pos)
	0x00200000
#define	RCC_AHB3LPENR_IOMNGRLPEN   RCC_AHB3LPENR_IOMNGRLPEN_Msk
#define	RCC_AHB3LPENR_DTCM1LPEN_Pos   (28U)
#define	RCC_AHB3LPENR_DTCM1LPEN_Msk   (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)
	0x10000000
#define	RCC_AHB3LPENR_DTCM1LPEN   RCC_AHB3LPENR_DTCM1LPEN_Msk
#define	RCC_AHB3LPENR_DTCM2LPEN_Pos   (29U)
#define	RCC_AHB3LPENR_DTCM2LPEN_Msk   (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)
	0x20000000
#define	RCC_AHB3LPENR_DTCM2LPEN   RCC_AHB3LPENR_DTCM2LPEN_Msk
#define	RCC_AHB3LPENR_ITCMLPEN_Pos   (30U)
#define	RCC_AHB3LPENR_ITCMLPEN_Msk   (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)
	0x40000000
#define	RCC_AHB3LPENR_ITCMLPEN   RCC_AHB3LPENR_ITCMLPEN_Msk
#define	RCC_AHB3LPENR_AXISRAMLPEN_Pos   (31U)
#define	RCC_AHB3LPENR_AXISRAMLPEN_Msk   (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos)
	0x80000000
#define	RCC_AHB3LPENR_AXISRAMLPEN   RCC_AHB3LPENR_AXISRAMLPEN_Msk
#define	RCC_AHB1LPENR_DMA1LPEN_Pos   (0U)
#define	RCC_AHB1LPENR_DMA1LPEN_Msk   (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
	0x00000001
#define	RCC_AHB1LPENR_DMA1LPEN   RCC_AHB1LPENR_DMA1LPEN_Msk
#define	RCC_AHB1LPENR_DMA2LPEN_Pos   (1U)
#define	RCC_AHB1LPENR_DMA2LPEN_Msk   (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
	0x00000002
#define	RCC_AHB1LPENR_DMA2LPEN   RCC_AHB1LPENR_DMA2LPEN_Msk
#define	RCC_AHB1LPENR_ADC12LPEN_Pos   (5U)
#define	RCC_AHB1LPENR_ADC12LPEN_Msk   (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos)
	0x00000020
#define	RCC_AHB1LPENR_ADC12LPEN   RCC_AHB1LPENR_ADC12LPEN_Msk
#define	RCC_AHB1LPENR_ETH1MACLPEN_Pos   (15U)
#define	RCC_AHB1LPENR_ETH1MACLPEN_Msk   (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos)
	0x00008000
#define	RCC_AHB1LPENR_ETH1MACLPEN   RCC_AHB1LPENR_ETH1MACLPEN_Msk
#define	RCC_AHB1LPENR_ETH1TXLPEN_Pos   (16U)
#define	RCC_AHB1LPENR_ETH1TXLPEN_Msk   (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos)
	0x00010000
#define	RCC_AHB1LPENR_ETH1TXLPEN   RCC_AHB1LPENR_ETH1TXLPEN_Msk
#define	RCC_AHB1LPENR_ETH1RXLPEN_Pos   (17U)
#define	RCC_AHB1LPENR_ETH1RXLPEN_Msk   (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos)
	0x00020000
#define	RCC_AHB1LPENR_ETH1RXLPEN   RCC_AHB1LPENR_ETH1RXLPEN_Msk
#define	RCC_AHB1LPENR_USB1OTGHSLPEN_Pos   (25U)
#define	RCC_AHB1LPENR_USB1OTGHSLPEN_Msk   (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos)
	0x02000000
#define	RCC_AHB1LPENR_USB1OTGHSLPEN   RCC_AHB1LPENR_USB1OTGHSLPEN_Msk
#define	RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos   (26U)
#define	RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk   (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos)
	0x04000000
#define	RCC_AHB1LPENR_USB1OTGHSULPILPEN   RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk
#define	RCC_AHB2LPENR_DCMI_PSSILPEN_Pos   (0U)
#define	RCC_AHB2LPENR_DCMI_PSSILPEN_Msk   (0x1UL << RCC_AHB2LPENR_DCMI_PSSILPEN_Pos)
	0x00000001
#define	RCC_AHB2LPENR_DCMI_PSSILPEN   RCC_AHB2LPENR_DCMI_PSSILPEN_Msk
#define	RCC_AHB2LPENR_RNGLPEN_Pos   (6U)
#define	RCC_AHB2LPENR_RNGLPEN_Msk   (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
	0x00000040
#define	RCC_AHB2LPENR_RNGLPEN   RCC_AHB2LPENR_RNGLPEN_Msk
#define	RCC_AHB2LPENR_SDMMC2LPEN_Pos   (9U)
#define	RCC_AHB2LPENR_SDMMC2LPEN_Msk   (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos)
	0x00000200
#define	RCC_AHB2LPENR_SDMMC2LPEN   RCC_AHB2LPENR_SDMMC2LPEN_Msk
#define	RCC_AHB2LPENR_FMACLPEN_Pos   (16U)
#define	RCC_AHB2LPENR_FMACLPEN_Msk   (0x1UL << RCC_AHB2LPENR_FMACLPEN_Pos)
	0x00010000
#define	RCC_AHB2LPENR_FMACLPEN   RCC_AHB2LPENR_FMACLPEN_Msk
#define	RCC_AHB2LPENR_CORDICLPEN_Pos   (17U)
#define	RCC_AHB2LPENR_CORDICLPEN_Msk   (0x1UL << RCC_AHB2LPENR_CORDICLPEN_Pos)
	0x00020000
#define	RCC_AHB2LPENR_CORDICLPEN   RCC_AHB2LPENR_CORDICLPEN_Msk
#define	RCC_AHB2LPENR_SRAM1LPEN_Pos   (29U)
#define	RCC_AHB2LPENR_SRAM1LPEN_Msk   (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos)
	0x20000000
#define	RCC_AHB2LPENR_SRAM1LPEN   RCC_AHB2LPENR_SRAM1LPEN_Msk
#define	RCC_AHB2LPENR_SRAM2LPEN_Pos   (30U)
#define	RCC_AHB2LPENR_SRAM2LPEN_Msk   (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos)
	0x40000000
#define	RCC_AHB2LPENR_SRAM2LPEN   RCC_AHB2LPENR_SRAM2LPEN_Msk
#define	RCC_AHB2LPENR_DCMILPEN_Pos   RCC_AHB2LPENR_DCMI_PSSILPEN_Pos
#define	RCC_AHB2LPENR_DCMILPEN_Msk   RCC_AHB2LPENR_DCMI_PSSILPEN_Msk
#define	RCC_AHB2LPENR_DCMILPEN   RCC_AHB2LPENR_DCMI_PSSILPEN
#define	RCC_AHB2LPENR_D2SRAM1LPEN_Pos   RCC_AHB2LPENR_SRAM1LPEN_Pos
#define	RCC_AHB2LPENR_D2SRAM1LPEN_Msk   RCC_AHB2LPENR_SRAM1LPEN_Msk
#define	RCC_AHB2LPENR_D2SRAM1LPEN   RCC_AHB2LPENR_SRAM1LPEN
#define	RCC_AHB2LPENR_D2SRAM2LPEN_Pos   RCC_AHB2LPENR_SRAM2LPEN_Pos
#define	RCC_AHB2LPENR_D2SRAM2LPEN_Msk   RCC_AHB2LPENR_SRAM2LPEN_Msk
#define	RCC_AHB2LPENR_D2SRAM2LPEN   RCC_AHB2LPENR_SRAM2LPEN
#define	RCC_AHB4LPENR_GPIOALPEN_Pos   (0U)
#define	RCC_AHB4LPENR_GPIOALPEN_Msk   (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos)
	0x00000001
#define	RCC_AHB4LPENR_GPIOALPEN   RCC_AHB4LPENR_GPIOALPEN_Msk
#define	RCC_AHB4LPENR_GPIOBLPEN_Pos   (1U)
#define	RCC_AHB4LPENR_GPIOBLPEN_Msk   (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos)
	0x00000002
#define	RCC_AHB4LPENR_GPIOBLPEN   RCC_AHB4LPENR_GPIOBLPEN_Msk
#define	RCC_AHB4LPENR_GPIOCLPEN_Pos   (2U)
#define	RCC_AHB4LPENR_GPIOCLPEN_Msk   (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos)
	0x00000004
#define	RCC_AHB4LPENR_GPIOCLPEN   RCC_AHB4LPENR_GPIOCLPEN_Msk
#define	RCC_AHB4LPENR_GPIODLPEN_Pos   (3U)
#define	RCC_AHB4LPENR_GPIODLPEN_Msk   (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos)
	0x00000008
#define	RCC_AHB4LPENR_GPIODLPEN   RCC_AHB4LPENR_GPIODLPEN_Msk
#define	RCC_AHB4LPENR_GPIOELPEN_Pos   (4U)
#define	RCC_AHB4LPENR_GPIOELPEN_Msk   (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos)
	0x00000010
#define	RCC_AHB4LPENR_GPIOELPEN   RCC_AHB4LPENR_GPIOELPEN_Msk
#define	RCC_AHB4LPENR_GPIOFLPEN_Pos   (5U)
#define	RCC_AHB4LPENR_GPIOFLPEN_Msk   (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos)
	0x00000020
#define	RCC_AHB4LPENR_GPIOFLPEN   RCC_AHB4LPENR_GPIOFLPEN_Msk
#define	RCC_AHB4LPENR_GPIOGLPEN_Pos   (6U)
#define	RCC_AHB4LPENR_GPIOGLPEN_Msk   (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos)
	0x00000040
#define	RCC_AHB4LPENR_GPIOGLPEN   RCC_AHB4LPENR_GPIOGLPEN_Msk
#define	RCC_AHB4LPENR_GPIOHLPEN_Pos   (7U)
#define	RCC_AHB4LPENR_GPIOHLPEN_Msk   (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos)
	0x00000080
#define	RCC_AHB4LPENR_GPIOHLPEN   RCC_AHB4LPENR_GPIOHLPEN_Msk
#define	RCC_AHB4LPENR_GPIOJLPEN_Pos   (9U)
#define	RCC_AHB4LPENR_GPIOJLPEN_Msk   (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos)
	0x00000200
#define	RCC_AHB4LPENR_GPIOJLPEN   RCC_AHB4LPENR_GPIOJLPEN_Msk
#define	RCC_AHB4LPENR_GPIOKLPEN_Pos   (10U)
#define	RCC_AHB4LPENR_GPIOKLPEN_Msk   (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos)
	0x00000400
#define	RCC_AHB4LPENR_GPIOKLPEN   RCC_AHB4LPENR_GPIOKLPEN_Msk
#define	RCC_AHB4LPENR_CRCLPEN_Pos   (19U)
#define	RCC_AHB4LPENR_CRCLPEN_Msk   (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos)
	0x00080000
#define	RCC_AHB4LPENR_CRCLPEN   RCC_AHB4LPENR_CRCLPEN_Msk
#define	RCC_AHB4LPENR_BDMALPEN_Pos   (21U)
#define	RCC_AHB4LPENR_BDMALPEN_Msk   (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos)
	0x00200000
#define	RCC_AHB4LPENR_BDMALPEN   RCC_AHB4LPENR_BDMALPEN_Msk
#define	RCC_AHB4LPENR_ADC3LPEN_Pos   (24U)
#define	RCC_AHB4LPENR_ADC3LPEN_Msk   (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos)
	0x01000000
#define	RCC_AHB4LPENR_ADC3LPEN   RCC_AHB4LPENR_ADC3LPEN_Msk
#define	RCC_AHB4LPENR_BKPRAMLPEN_Pos   (28U)
#define	RCC_AHB4LPENR_BKPRAMLPEN_Msk   (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos)
	0x10000000
#define	RCC_AHB4LPENR_BKPRAMLPEN   RCC_AHB4LPENR_BKPRAMLPEN_Msk
#define	RCC_AHB4LPENR_SRAM4LPEN_Pos   (29U)
#define	RCC_AHB4LPENR_SRAM4LPEN_Msk   (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos)
	0x20000000
#define	RCC_AHB4LPENR_SRAM4LPEN   RCC_AHB4LPENR_SRAM4LPEN_Msk
#define	RCC_AHB4LPENR_D3SRAM1LPEN_Pos   RCC_AHB4LPENR_SRAM4LPEN_Pos
#define	RCC_AHB4LPENR_D3SRAM1LPEN_Msk   RCC_AHB4LPENR_SRAM4LPEN_Msk
#define	RCC_AHB4LPENR_D3SRAM1LPEN   RCC_AHB4LPENR_SRAM4LPEN
#define	RCC_APB3LPENR_LTDCLPEN_Pos   (3U)
#define	RCC_APB3LPENR_LTDCLPEN_Msk   (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos)
	0x00000008
#define	RCC_APB3LPENR_LTDCLPEN   RCC_APB3LPENR_LTDCLPEN_Msk
#define	RCC_APB3LPENR_WWDG1LPEN_Pos   (6U)
#define	RCC_APB3LPENR_WWDG1LPEN_Msk   (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos)
	0x00000040
#define	RCC_APB3LPENR_WWDG1LPEN   RCC_APB3LPENR_WWDG1LPEN_Msk
#define	RCC_APB1LLPENR_TIM2LPEN_Pos   (0U)
#define	RCC_APB1LLPENR_TIM2LPEN_Msk   (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos)
	0x00000001
#define	RCC_APB1LLPENR_TIM2LPEN   RCC_APB1LLPENR_TIM2LPEN_Msk
#define	RCC_APB1LLPENR_TIM3LPEN_Pos   (1U)
#define	RCC_APB1LLPENR_TIM3LPEN_Msk   (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos)
	0x00000002
#define	RCC_APB1LLPENR_TIM3LPEN   RCC_APB1LLPENR_TIM3LPEN_Msk
#define	RCC_APB1LLPENR_TIM4LPEN_Pos   (2U)
#define	RCC_APB1LLPENR_TIM4LPEN_Msk   (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos)
	0x00000004
#define	RCC_APB1LLPENR_TIM4LPEN   RCC_APB1LLPENR_TIM4LPEN_Msk
#define	RCC_APB1LLPENR_TIM5LPEN_Pos   (3U)
#define	RCC_APB1LLPENR_TIM5LPEN_Msk   (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos)
	0x00000008
#define	RCC_APB1LLPENR_TIM5LPEN   RCC_APB1LLPENR_TIM5LPEN_Msk
#define	RCC_APB1LLPENR_TIM6LPEN_Pos   (4U)
#define	RCC_APB1LLPENR_TIM6LPEN_Msk   (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos)
	0x00000010
#define	RCC_APB1LLPENR_TIM6LPEN   RCC_APB1LLPENR_TIM6LPEN_Msk
#define	RCC_APB1LLPENR_TIM7LPEN_Pos   (5U)
#define	RCC_APB1LLPENR_TIM7LPEN_Msk   (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos)
	0x00000020
#define	RCC_APB1LLPENR_TIM7LPEN   RCC_APB1LLPENR_TIM7LPEN_Msk
#define	RCC_APB1LLPENR_TIM12LPEN_Pos   (6U)
#define	RCC_APB1LLPENR_TIM12LPEN_Msk   (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos)
	0x00000040
#define	RCC_APB1LLPENR_TIM12LPEN   RCC_APB1LLPENR_TIM12LPEN_Msk
#define	RCC_APB1LLPENR_TIM13LPEN_Pos   (7U)
#define	RCC_APB1LLPENR_TIM13LPEN_Msk   (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos)
	0x00000080
#define	RCC_APB1LLPENR_TIM13LPEN   RCC_APB1LLPENR_TIM13LPEN_Msk
#define	RCC_APB1LLPENR_TIM14LPEN_Pos   (8U)
#define	RCC_APB1LLPENR_TIM14LPEN_Msk   (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos)
	0x00000100
#define	RCC_APB1LLPENR_TIM14LPEN   RCC_APB1LLPENR_TIM14LPEN_Msk
#define	RCC_APB1LLPENR_LPTIM1LPEN_Pos   (9U)
#define	RCC_APB1LLPENR_LPTIM1LPEN_Msk   (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos)
	0x00000200
#define	RCC_APB1LLPENR_LPTIM1LPEN   RCC_APB1LLPENR_LPTIM1LPEN_Msk
#define	RCC_APB1LLPENR_SPI2LPEN_Pos   (14U)
#define	RCC_APB1LLPENR_SPI2LPEN_Msk   (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos)
	0x00004000
#define	RCC_APB1LLPENR_SPI2LPEN   RCC_APB1LLPENR_SPI2LPEN_Msk
#define	RCC_APB1LLPENR_SPI3LPEN_Pos   (15U)
#define	RCC_APB1LLPENR_SPI3LPEN_Msk   (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos)
	0x00008000
#define	RCC_APB1LLPENR_SPI3LPEN   RCC_APB1LLPENR_SPI3LPEN_Msk
#define	RCC_APB1LLPENR_SPDIFRXLPEN_Pos   (16U)
#define	RCC_APB1LLPENR_SPDIFRXLPEN_Msk   (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos)
	0x00010000
#define	RCC_APB1LLPENR_SPDIFRXLPEN   RCC_APB1LLPENR_SPDIFRXLPEN_Msk
#define	RCC_APB1LLPENR_USART2LPEN_Pos   (17U)
#define	RCC_APB1LLPENR_USART2LPEN_Msk   (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos)
	0x00020000
#define	RCC_APB1LLPENR_USART2LPEN   RCC_APB1LLPENR_USART2LPEN_Msk
#define	RCC_APB1LLPENR_USART3LPEN_Pos   (18U)
#define	RCC_APB1LLPENR_USART3LPEN_Msk   (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos)
	0x00040000
#define	RCC_APB1LLPENR_USART3LPEN   RCC_APB1LLPENR_USART3LPEN_Msk
#define	RCC_APB1LLPENR_UART4LPEN_Pos   (19U)
#define	RCC_APB1LLPENR_UART4LPEN_Msk   (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos)
	0x00080000
#define	RCC_APB1LLPENR_UART4LPEN   RCC_APB1LLPENR_UART4LPEN_Msk
#define	RCC_APB1LLPENR_UART5LPEN_Pos   (20U)
#define	RCC_APB1LLPENR_UART5LPEN_Msk   (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos)
	0x00100000
#define	RCC_APB1LLPENR_UART5LPEN   RCC_APB1LLPENR_UART5LPEN_Msk
#define	RCC_APB1LLPENR_I2C1LPEN_Pos   (21U)
#define	RCC_APB1LLPENR_I2C1LPEN_Msk   (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos)
	0x00200000
#define	RCC_APB1LLPENR_I2C1LPEN   RCC_APB1LLPENR_I2C1LPEN_Msk
#define	RCC_APB1LLPENR_I2C2LPEN_Pos   (22U)
#define	RCC_APB1LLPENR_I2C2LPEN_Msk   (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos)
	0x00400000
#define	RCC_APB1LLPENR_I2C2LPEN   RCC_APB1LLPENR_I2C2LPEN_Msk
#define	RCC_APB1LLPENR_I2C3LPEN_Pos   (23U)
#define	RCC_APB1LLPENR_I2C3LPEN_Msk   (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos)
	0x00800000
#define	RCC_APB1LLPENR_I2C3LPEN   RCC_APB1LLPENR_I2C3LPEN_Msk
#define	RCC_APB1LLPENR_I2C5LPEN_Pos   (25U)
#define	RCC_APB1LLPENR_I2C5LPEN_Msk   (0x1UL << RCC_APB1LLPENR_I2C5LPEN_Pos)
	0x02000000
#define	RCC_APB1LLPENR_I2C5LPEN   RCC_APB1LLPENR_I2C5LPEN_Msk
#define	RCC_APB1LLPENR_CECLPEN_Pos   (27U)
#define	RCC_APB1LLPENR_CECLPEN_Msk   (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos)
	0x08000000
#define	RCC_APB1LLPENR_CECLPEN   RCC_APB1LLPENR_CECLPEN_Msk
#define	RCC_APB1LLPENR_DAC12LPEN_Pos   (29U)
#define	RCC_APB1LLPENR_DAC12LPEN_Msk   (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos)
	0x20000000
#define	RCC_APB1LLPENR_DAC12LPEN   RCC_APB1LLPENR_DAC12LPEN_Msk
#define	RCC_APB1LLPENR_UART7LPEN_Pos   (30U)
#define	RCC_APB1LLPENR_UART7LPEN_Msk   (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos)
	0x40000000
#define	RCC_APB1LLPENR_UART7LPEN   RCC_APB1LLPENR_UART7LPEN_Msk
#define	RCC_APB1LLPENR_UART8LPEN_Pos   (31U)
#define	RCC_APB1LLPENR_UART8LPEN_Msk   (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos)
	0x80000000
#define	RCC_APB1LLPENR_UART8LPEN   RCC_APB1LLPENR_UART8LPEN_Msk
#define	RCC_APB1LLPENR_HDMICECEN_Pos   RCC_APB1LLPENR_CECLPEN_Pos
#define	RCC_APB1LLPENR_HDMICECEN_Msk   RCC_APB1LLPENR_CECLPEN_Msk
#define	RCC_APB1LLPENR_HDMICECEN   RCC_APB1LLPENR_CECLPEN
#define	RCC_APB1HLPENR_CRSLPEN_Pos   (1U)
#define	RCC_APB1HLPENR_CRSLPEN_Msk   (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos)
	0x00000002
#define	RCC_APB1HLPENR_CRSLPEN   RCC_APB1HLPENR_CRSLPEN_Msk
#define	RCC_APB1HLPENR_SWPMILPEN_Pos   (2U)
#define	RCC_APB1HLPENR_SWPMILPEN_Msk   (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos)
	0x00000004
#define	RCC_APB1HLPENR_SWPMILPEN   RCC_APB1HLPENR_SWPMILPEN_Msk
#define	RCC_APB1HLPENR_OPAMPLPEN_Pos   (4U)
#define	RCC_APB1HLPENR_OPAMPLPEN_Msk   (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos)
	0x00000010
#define	RCC_APB1HLPENR_OPAMPLPEN   RCC_APB1HLPENR_OPAMPLPEN_Msk
#define	RCC_APB1HLPENR_MDIOSLPEN_Pos   (5U)
#define	RCC_APB1HLPENR_MDIOSLPEN_Msk   (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos)
	0x00000020
#define	RCC_APB1HLPENR_MDIOSLPEN   RCC_APB1HLPENR_MDIOSLPEN_Msk
#define	RCC_APB1HLPENR_FDCANLPEN_Pos   (8U)
#define	RCC_APB1HLPENR_FDCANLPEN_Msk   (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos)
	0x00000100
#define	RCC_APB1HLPENR_FDCANLPEN   RCC_APB1HLPENR_FDCANLPEN_Msk
#define	RCC_APB1HLPENR_TIM23LPEN_Pos   (24U)
#define	RCC_APB1HLPENR_TIM23LPEN_Msk   (0x1UL << RCC_APB1HLPENR_TIM23LPEN_Pos)
	0x01000000
#define	RCC_APB1HLPENR_TIM23LPEN   RCC_APB1HLPENR_TIM23LPEN_Msk
#define	RCC_APB1HLPENR_TIM24LPEN_Pos   (25U)
#define	RCC_APB1HLPENR_TIM24LPEN_Msk   (0x1UL << RCC_APB1HLPENR_TIM24LPEN_Pos)
	0x02000000
#define	RCC_APB1HLPENR_TIM24LPEN   RCC_APB1HLPENR_TIM24LPEN_Msk
#define	RCC_APB2LPENR_TIM1LPEN_Pos   (0U)
#define	RCC_APB2LPENR_TIM1LPEN_Msk   (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
	0x00000001
#define	RCC_APB2LPENR_TIM1LPEN   RCC_APB2LPENR_TIM1LPEN_Msk
#define	RCC_APB2LPENR_TIM8LPEN_Pos   (1U)
#define	RCC_APB2LPENR_TIM8LPEN_Msk   (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
	0x00000002
#define	RCC_APB2LPENR_TIM8LPEN   RCC_APB2LPENR_TIM8LPEN_Msk
#define	RCC_APB2LPENR_USART1LPEN_Pos   (4U)
#define	RCC_APB2LPENR_USART1LPEN_Msk   (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
	0x00000010
#define	RCC_APB2LPENR_USART1LPEN   RCC_APB2LPENR_USART1LPEN_Msk
#define	RCC_APB2LPENR_USART6LPEN_Pos   (5U)
#define	RCC_APB2LPENR_USART6LPEN_Msk   (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
	0x00000020
#define	RCC_APB2LPENR_USART6LPEN   RCC_APB2LPENR_USART6LPEN_Msk
#define	RCC_APB2LPENR_UART9LPEN_Pos   (6U)
#define	RCC_APB2LPENR_UART9LPEN_Msk   (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos)
	0x00000040
#define	RCC_APB2LPENR_UART9LPEN   RCC_APB2LPENR_UART9LPEN_Msk
#define	RCC_APB2LPENR_USART10LPEN_Pos   (7U)
#define	RCC_APB2LPENR_USART10LPEN_Msk   (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos)
	0x00000080
#define	RCC_APB2LPENR_USART10LPEN   RCC_APB2LPENR_USART10LPEN_Msk
#define	RCC_APB2LPENR_SPI1LPEN_Pos   (12U)
#define	RCC_APB2LPENR_SPI1LPEN_Msk   (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
	0x00001000
#define	RCC_APB2LPENR_SPI1LPEN   RCC_APB2LPENR_SPI1LPEN_Msk
#define	RCC_APB2LPENR_SPI4LPEN_Pos   (13U)
#define	RCC_APB2LPENR_SPI4LPEN_Msk   (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos)
	0x00002000
#define	RCC_APB2LPENR_SPI4LPEN   RCC_APB2LPENR_SPI4LPEN_Msk
#define	RCC_APB2LPENR_TIM15LPEN_Pos   (16U)
#define	RCC_APB2LPENR_TIM15LPEN_Msk   (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos)
	0x00010000
#define	RCC_APB2LPENR_TIM15LPEN   RCC_APB2LPENR_TIM15LPEN_Msk
#define	RCC_APB2LPENR_TIM16LPEN_Pos   (17U)
#define	RCC_APB2LPENR_TIM16LPEN_Msk   (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos)
	0x00020000
#define	RCC_APB2LPENR_TIM16LPEN   RCC_APB2LPENR_TIM16LPEN_Msk
#define	RCC_APB2LPENR_TIM17LPEN_Pos   (18U)
#define	RCC_APB2LPENR_TIM17LPEN_Msk   (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos)
	0x00040000
#define	RCC_APB2LPENR_TIM17LPEN   RCC_APB2LPENR_TIM17LPEN_Msk
#define	RCC_APB2LPENR_SPI5LPEN_Pos   (20U)
#define	RCC_APB2LPENR_SPI5LPEN_Msk   (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos)
	0x00100000
#define	RCC_APB2LPENR_SPI5LPEN   RCC_APB2LPENR_SPI5LPEN_Msk
#define	RCC_APB2LPENR_SAI1LPEN_Pos   (22U)
#define	RCC_APB2LPENR_SAI1LPEN_Msk   (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos)
	0x00400000
#define	RCC_APB2LPENR_SAI1LPEN   RCC_APB2LPENR_SAI1LPEN_Msk
#define	RCC_APB2LPENR_DFSDM1LPEN_Pos   (30U)
#define	RCC_APB2LPENR_DFSDM1LPEN_Msk   (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos)
	0x40000000
#define	RCC_APB2LPENR_DFSDM1LPEN   RCC_APB2LPENR_DFSDM1LPEN_Msk
#define	RCC_APB4LPENR_SYSCFGLPEN_Pos   (1U)
#define	RCC_APB4LPENR_SYSCFGLPEN_Msk   (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos)
	0x00000002
#define	RCC_APB4LPENR_SYSCFGLPEN   RCC_APB4LPENR_SYSCFGLPEN_Msk
#define	RCC_APB4LPENR_LPUART1LPEN_Pos   (3U)
#define	RCC_APB4LPENR_LPUART1LPEN_Msk   (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos)
	0x00000008
#define	RCC_APB4LPENR_LPUART1LPEN   RCC_APB4LPENR_LPUART1LPEN_Msk
#define	RCC_APB4LPENR_SPI6LPEN_Pos   (5U)
#define	RCC_APB4LPENR_SPI6LPEN_Msk   (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos)
	0x00000020
#define	RCC_APB4LPENR_SPI6LPEN   RCC_APB4LPENR_SPI6LPEN_Msk
#define	RCC_APB4LPENR_I2C4LPEN_Pos   (7U)
#define	RCC_APB4LPENR_I2C4LPEN_Msk   (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos)
	0x00000080
#define	RCC_APB4LPENR_I2C4LPEN   RCC_APB4LPENR_I2C4LPEN_Msk
#define	RCC_APB4LPENR_LPTIM2LPEN_Pos   (9U)
#define	RCC_APB4LPENR_LPTIM2LPEN_Msk   (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos)
	0x00000200
#define	RCC_APB4LPENR_LPTIM2LPEN   RCC_APB4LPENR_LPTIM2LPEN_Msk
#define	RCC_APB4LPENR_LPTIM3LPEN_Pos   (10U)
#define	RCC_APB4LPENR_LPTIM3LPEN_Msk   (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos)
	0x00000400
#define	RCC_APB4LPENR_LPTIM3LPEN   RCC_APB4LPENR_LPTIM3LPEN_Msk
#define	RCC_APB4LPENR_LPTIM4LPEN_Pos   (11U)
#define	RCC_APB4LPENR_LPTIM4LPEN_Msk   (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos)
	0x00000800
#define	RCC_APB4LPENR_LPTIM4LPEN   RCC_APB4LPENR_LPTIM4LPEN_Msk
#define	RCC_APB4LPENR_LPTIM5LPEN_Pos   (12U)
#define	RCC_APB4LPENR_LPTIM5LPEN_Msk   (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos)
	0x00001000
#define	RCC_APB4LPENR_LPTIM5LPEN   RCC_APB4LPENR_LPTIM5LPEN_Msk
#define	RCC_APB4LPENR_COMP12LPEN_Pos   (14U)
#define	RCC_APB4LPENR_COMP12LPEN_Msk   (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos)
	0x00004000
#define	RCC_APB4LPENR_COMP12LPEN   RCC_APB4LPENR_COMP12LPEN_Msk
#define	RCC_APB4LPENR_VREFLPEN_Pos   (15U)
#define	RCC_APB4LPENR_VREFLPEN_Msk   (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos)
	0x00008000
#define	RCC_APB4LPENR_VREFLPEN   RCC_APB4LPENR_VREFLPEN_Msk
#define	RCC_APB4LPENR_RTCAPBLPEN_Pos   (16U)
#define	RCC_APB4LPENR_RTCAPBLPEN_Msk   (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos)
	0x00010000
#define	RCC_APB4LPENR_RTCAPBLPEN   RCC_APB4LPENR_RTCAPBLPEN_Msk
#define	RCC_APB4LPENR_SAI4LPEN_Pos   (21U)
#define	RCC_APB4LPENR_SAI4LPEN_Msk   (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos)
	0x00200000
#define	RCC_APB4LPENR_SAI4LPEN   RCC_APB4LPENR_SAI4LPEN_Msk
#define	RCC_APB4LPENR_DTSLPEN_Pos   (26U)
#define	RCC_APB4LPENR_DTSLPEN_Msk   (0x1UL << RCC_APB4LPENR_DTSLPEN_Pos)
	0x04000000
#define	RCC_APB4LPENR_DTSLPEN   RCC_APB4LPENR_DTSLPEN_Msk
#define	RCC_RSR_RMVF_Pos   (16U)
#define	RCC_RSR_RMVF_Msk   (0x1UL << RCC_RSR_RMVF_Pos)
	0x00010000
#define	RCC_RSR_RMVF   RCC_RSR_RMVF_Msk
#define	RCC_RSR_CPURSTF_Pos   (17U)
#define	RCC_RSR_CPURSTF_Msk   (0x1UL << RCC_RSR_CPURSTF_Pos)
	0x00020000
#define	RCC_RSR_CPURSTF   RCC_RSR_CPURSTF_Msk
#define	RCC_RSR_D1RSTF_Pos   (19U)
#define	RCC_RSR_D1RSTF_Msk   (0x1UL << RCC_RSR_D1RSTF_Pos)
	0x00080000
#define	RCC_RSR_D1RSTF   RCC_RSR_D1RSTF_Msk
#define	RCC_RSR_D2RSTF_Pos   (20U)
#define	RCC_RSR_D2RSTF_Msk   (0x1UL << RCC_RSR_D2RSTF_Pos)
	0x00100000
#define	RCC_RSR_D2RSTF   RCC_RSR_D2RSTF_Msk
#define	RCC_RSR_BORRSTF_Pos   (21U)
#define	RCC_RSR_BORRSTF_Msk   (0x1UL << RCC_RSR_BORRSTF_Pos)
	0x00200000
#define	RCC_RSR_BORRSTF   RCC_RSR_BORRSTF_Msk
#define	RCC_RSR_PINRSTF_Pos   (22U)
#define	RCC_RSR_PINRSTF_Msk   (0x1UL << RCC_RSR_PINRSTF_Pos)
	0x00400000
#define	RCC_RSR_PINRSTF   RCC_RSR_PINRSTF_Msk
#define	RCC_RSR_PORRSTF_Pos   (23U)
#define	RCC_RSR_PORRSTF_Msk   (0x1UL << RCC_RSR_PORRSTF_Pos)
	0x00800000
#define	RCC_RSR_PORRSTF   RCC_RSR_PORRSTF_Msk
#define	RCC_RSR_SFTRSTF_Pos   (24U)
#define	RCC_RSR_SFTRSTF_Msk   (0x1UL << RCC_RSR_SFTRSTF_Pos)
	0x01000000
#define	RCC_RSR_SFTRSTF   RCC_RSR_SFTRSTF_Msk
#define	RCC_RSR_IWDG1RSTF_Pos   (26U)
#define	RCC_RSR_IWDG1RSTF_Msk   (0x1UL << RCC_RSR_IWDG1RSTF_Pos)
	0x04000000
#define	RCC_RSR_IWDG1RSTF   RCC_RSR_IWDG1RSTF_Msk
#define	RCC_RSR_WWDG1RSTF_Pos   (28U)
#define	RCC_RSR_WWDG1RSTF_Msk   (0x1UL << RCC_RSR_WWDG1RSTF_Pos)
	0x10000000
#define	RCC_RSR_WWDG1RSTF   RCC_RSR_WWDG1RSTF_Msk
#define	RCC_RSR_LPWRRSTF_Pos   (30U)
#define	RCC_RSR_LPWRRSTF_Msk   (0x1UL << RCC_RSR_LPWRRSTF_Pos)
	0x40000000
#define	RCC_RSR_LPWRRSTF   RCC_RSR_LPWRRSTF_Msk
#define	RNG_VER_3_2
#define	RNG_CR_RNGEN_Pos   (2U)
#define	RNG_CR_RNGEN_Msk   (0x1UL << RNG_CR_RNGEN_Pos)
	0x00000004
#define	RNG_CR_RNGEN   RNG_CR_RNGEN_Msk
#define	RNG_CR_IE_Pos   (3U)
#define	RNG_CR_IE_Msk   (0x1UL << RNG_CR_IE_Pos)
	0x00000008
#define	RNG_CR_IE   RNG_CR_IE_Msk
#define	RNG_CR_CED_Pos   (5U)
#define	RNG_CR_CED_Msk   (0x1UL << RNG_CR_CED_Pos)
	0x00000020
#define	RNG_CR_CED   RNG_CR_CED_Msk
#define	RNG_CR_RNG_CONFIG3_Pos   (8U)
#define	RNG_CR_RNG_CONFIG3_Msk   (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
	0x00000F00
#define	RNG_CR_RNG_CONFIG3   RNG_CR_RNG_CONFIG3_Msk
#define	RNG_CR_NISTC_Pos   (12U)
#define	RNG_CR_NISTC_Msk   (0x1UL << RNG_CR_NISTC_Pos)
	0x00001000
#define	RNG_CR_NISTC   RNG_CR_NISTC_Msk
#define	RNG_CR_RNG_CONFIG2_Pos   (13U)
#define	RNG_CR_RNG_CONFIG2_Msk   (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
	0x0000E000
#define	RNG_CR_RNG_CONFIG2   RNG_CR_RNG_CONFIG2_Msk
#define	RNG_CR_CLKDIV_Pos   (16U)
#define	RNG_CR_CLKDIV_Msk   (0xFUL << RNG_CR_CLKDIV_Pos)
	0x000F0000
#define	RNG_CR_CLKDIV   RNG_CR_CLKDIV_Msk
#define	RNG_CR_CLKDIV_0   (0x1UL << RNG_CR_CLKDIV_Pos)
	0x00010000
#define	RNG_CR_CLKDIV_1   (0x2UL << RNG_CR_CLKDIV_Pos)
	0x00020000
#define	RNG_CR_CLKDIV_2   (0x4UL << RNG_CR_CLKDIV_Pos)
	0x00040000
#define	RNG_CR_CLKDIV_3   (0x8UL << RNG_CR_CLKDIV_Pos)
	0x00080000
#define	RNG_CR_RNG_CONFIG1_Pos   (20U)
#define	RNG_CR_RNG_CONFIG1_Msk   (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
	0x03F00000
#define	RNG_CR_RNG_CONFIG1   RNG_CR_RNG_CONFIG1_Msk
#define	RNG_CR_CONDRST_Pos   (30U)
#define	RNG_CR_CONDRST_Msk   (0x1UL << RNG_CR_CONDRST_Pos)
	0x40000000
#define	RNG_CR_CONDRST   RNG_CR_CONDRST_Msk
#define	RNG_CR_CONFIGLOCK_Pos   (31U)
#define	RNG_CR_CONFIGLOCK_Msk   (0x1UL << RNG_CR_CONFIGLOCK_Pos)
	0x80000000
#define	RNG_CR_CONFIGLOCK   RNG_CR_CONFIGLOCK_Msk
#define	RNG_SR_DRDY_Pos   (0U)
#define	RNG_SR_DRDY_Msk   (0x1UL << RNG_SR_DRDY_Pos)
	0x00000001
#define	RNG_SR_DRDY   RNG_SR_DRDY_Msk
#define	RNG_SR_CECS_Pos   (1U)
#define	RNG_SR_CECS_Msk   (0x1UL << RNG_SR_CECS_Pos)
	0x00000002
#define	RNG_SR_CECS   RNG_SR_CECS_Msk
#define	RNG_SR_SECS_Pos   (2U)
#define	RNG_SR_SECS_Msk   (0x1UL << RNG_SR_SECS_Pos)
	0x00000004
#define	RNG_SR_SECS   RNG_SR_SECS_Msk
#define	RNG_SR_CEIS_Pos   (5U)
#define	RNG_SR_CEIS_Msk   (0x1UL << RNG_SR_CEIS_Pos)
	0x00000020
#define	RNG_SR_CEIS   RNG_SR_CEIS_Msk
#define	RNG_SR_SEIS_Pos   (6U)
#define	RNG_SR_SEIS_Msk   (0x1UL << RNG_SR_SEIS_Pos)
	0x00000040
#define	RNG_SR_SEIS   RNG_SR_SEIS_Msk
#define	RTC_TR_PM_Pos   (22U)
#define	RTC_TR_PM_Msk   (0x1UL << RTC_TR_PM_Pos)
	0x00400000
#define	RTC_TR_PM   RTC_TR_PM_Msk
#define	RTC_TR_HT_Pos   (20U)
#define	RTC_TR_HT_Msk   (0x3UL << RTC_TR_HT_Pos)
	0x00300000
#define	RTC_TR_HT   RTC_TR_HT_Msk
#define	RTC_TR_HT_0   (0x1UL << RTC_TR_HT_Pos)
	0x00100000
#define	RTC_TR_HT_1   (0x2UL << RTC_TR_HT_Pos)
	0x00200000
#define	RTC_TR_HU_Pos   (16U)
#define	RTC_TR_HU_Msk   (0xFUL << RTC_TR_HU_Pos)
	0x000F0000
#define	RTC_TR_HU   RTC_TR_HU_Msk
#define	RTC_TR_HU_0   (0x1UL << RTC_TR_HU_Pos)
	0x00010000
#define	RTC_TR_HU_1   (0x2UL << RTC_TR_HU_Pos)
	0x00020000
#define	RTC_TR_HU_2   (0x4UL << RTC_TR_HU_Pos)
	0x00040000
#define	RTC_TR_HU_3   (0x8UL << RTC_TR_HU_Pos)
	0x00080000
#define	RTC_TR_MNT_Pos   (12U)
#define	RTC_TR_MNT_Msk   (0x7UL << RTC_TR_MNT_Pos)
	0x00007000
#define	RTC_TR_MNT   RTC_TR_MNT_Msk
#define	RTC_TR_MNT_0   (0x1UL << RTC_TR_MNT_Pos)
	0x00001000
#define	RTC_TR_MNT_1   (0x2UL << RTC_TR_MNT_Pos)
	0x00002000
#define	RTC_TR_MNT_2   (0x4UL << RTC_TR_MNT_Pos)
	0x00004000
#define	RTC_TR_MNU_Pos   (8U)
#define	RTC_TR_MNU_Msk   (0xFUL << RTC_TR_MNU_Pos)
	0x00000F00
#define	RTC_TR_MNU   RTC_TR_MNU_Msk
#define	RTC_TR_MNU_0   (0x1UL << RTC_TR_MNU_Pos)
	0x00000100
#define	RTC_TR_MNU_1   (0x2UL << RTC_TR_MNU_Pos)
	0x00000200
#define	RTC_TR_MNU_2   (0x4UL << RTC_TR_MNU_Pos)
	0x00000400
#define	RTC_TR_MNU_3   (0x8UL << RTC_TR_MNU_Pos)
	0x00000800
#define	RTC_TR_ST_Pos   (4U)
#define	RTC_TR_ST_Msk   (0x7UL << RTC_TR_ST_Pos)
	0x00000070
#define	RTC_TR_ST   RTC_TR_ST_Msk
#define	RTC_TR_ST_0   (0x1UL << RTC_TR_ST_Pos)
	0x00000010
#define	RTC_TR_ST_1   (0x2UL << RTC_TR_ST_Pos)
	0x00000020
#define	RTC_TR_ST_2   (0x4UL << RTC_TR_ST_Pos)
	0x00000040
#define	RTC_TR_SU_Pos   (0U)
#define	RTC_TR_SU_Msk   (0xFUL << RTC_TR_SU_Pos)
	0x0000000F
#define	RTC_TR_SU   RTC_TR_SU_Msk
#define	RTC_TR_SU_0   (0x1UL << RTC_TR_SU_Pos)
	0x00000001
#define	RTC_TR_SU_1   (0x2UL << RTC_TR_SU_Pos)
	0x00000002
#define	RTC_TR_SU_2   (0x4UL << RTC_TR_SU_Pos)
	0x00000004
#define	RTC_TR_SU_3   (0x8UL << RTC_TR_SU_Pos)
	0x00000008
#define	RTC_DR_YT_Pos   (20U)
#define	RTC_DR_YT_Msk   (0xFUL << RTC_DR_YT_Pos)
	0x00F00000
#define	RTC_DR_YT   RTC_DR_YT_Msk
#define	RTC_DR_YT_0   (0x1UL << RTC_DR_YT_Pos)
	0x00100000
#define	RTC_DR_YT_1   (0x2UL << RTC_DR_YT_Pos)
	0x00200000
#define	RTC_DR_YT_2   (0x4UL << RTC_DR_YT_Pos)
	0x00400000
#define	RTC_DR_YT_3   (0x8UL << RTC_DR_YT_Pos)
	0x00800000
#define	RTC_DR_YU_Pos   (16U)
#define	RTC_DR_YU_Msk   (0xFUL << RTC_DR_YU_Pos)
	0x000F0000
#define	RTC_DR_YU   RTC_DR_YU_Msk
#define	RTC_DR_YU_0   (0x1UL << RTC_DR_YU_Pos)
	0x00010000
#define	RTC_DR_YU_1   (0x2UL << RTC_DR_YU_Pos)
	0x00020000
#define	RTC_DR_YU_2   (0x4UL << RTC_DR_YU_Pos)
	0x00040000
#define	RTC_DR_YU_3   (0x8UL << RTC_DR_YU_Pos)
	0x00080000
#define	RTC_DR_WDU_Pos   (13U)
#define	RTC_DR_WDU_Msk   (0x7UL << RTC_DR_WDU_Pos)
	0x0000E000
#define	RTC_DR_WDU   RTC_DR_WDU_Msk
#define	RTC_DR_WDU_0   (0x1UL << RTC_DR_WDU_Pos)
	0x00002000
#define	RTC_DR_WDU_1   (0x2UL << RTC_DR_WDU_Pos)
	0x00004000
#define	RTC_DR_WDU_2   (0x4UL << RTC_DR_WDU_Pos)
	0x00008000
#define	RTC_DR_MT_Pos   (12U)
#define	RTC_DR_MT_Msk   (0x1UL << RTC_DR_MT_Pos)
	0x00001000
#define	RTC_DR_MT   RTC_DR_MT_Msk
#define	RTC_DR_MU_Pos   (8U)
#define	RTC_DR_MU_Msk   (0xFUL << RTC_DR_MU_Pos)
	0x00000F00
#define	RTC_DR_MU   RTC_DR_MU_Msk
#define	RTC_DR_MU_0   (0x1UL << RTC_DR_MU_Pos)
	0x00000100
#define	RTC_DR_MU_1   (0x2UL << RTC_DR_MU_Pos)
	0x00000200
#define	RTC_DR_MU_2   (0x4UL << RTC_DR_MU_Pos)
	0x00000400
#define	RTC_DR_MU_3   (0x8UL << RTC_DR_MU_Pos)
	0x00000800
#define	RTC_DR_DT_Pos   (4U)
#define	RTC_DR_DT_Msk   (0x3UL << RTC_DR_DT_Pos)
	0x00000030
#define	RTC_DR_DT   RTC_DR_DT_Msk
#define	RTC_DR_DT_0   (0x1UL << RTC_DR_DT_Pos)
	0x00000010
#define	RTC_DR_DT_1   (0x2UL << RTC_DR_DT_Pos)
	0x00000020
#define	RTC_DR_DU_Pos   (0U)
#define	RTC_DR_DU_Msk   (0xFUL << RTC_DR_DU_Pos)
	0x0000000F
#define	RTC_DR_DU   RTC_DR_DU_Msk
#define	RTC_DR_DU_0   (0x1UL << RTC_DR_DU_Pos)
	0x00000001
#define	RTC_DR_DU_1   (0x2UL << RTC_DR_DU_Pos)
	0x00000002
#define	RTC_DR_DU_2   (0x4UL << RTC_DR_DU_Pos)
	0x00000004
#define	RTC_DR_DU_3   (0x8UL << RTC_DR_DU_Pos)
	0x00000008
#define	RTC_CR_ITSE_Pos   (24U)
#define	RTC_CR_ITSE_Msk   (0x1UL << RTC_CR_ITSE_Pos)
	0x01000000
#define	RTC_CR_ITSE   RTC_CR_ITSE_Msk
#define	RTC_CR_COE_Pos   (23U)
#define	RTC_CR_COE_Msk   (0x1UL << RTC_CR_COE_Pos)
	0x00800000
#define	RTC_CR_COE   RTC_CR_COE_Msk
#define	RTC_CR_OSEL_Pos   (21U)
#define	RTC_CR_OSEL_Msk   (0x3UL << RTC_CR_OSEL_Pos)
	0x00600000
#define	RTC_CR_OSEL   RTC_CR_OSEL_Msk
#define	RTC_CR_OSEL_0   (0x1UL << RTC_CR_OSEL_Pos)
	0x00200000
#define	RTC_CR_OSEL_1   (0x2UL << RTC_CR_OSEL_Pos)
	0x00400000
#define	RTC_CR_POL_Pos   (20U)
#define	RTC_CR_POL_Msk   (0x1UL << RTC_CR_POL_Pos)
	0x00100000
#define	RTC_CR_POL   RTC_CR_POL_Msk
#define	RTC_CR_COSEL_Pos   (19U)
#define	RTC_CR_COSEL_Msk   (0x1UL << RTC_CR_COSEL_Pos)
	0x00080000
#define	RTC_CR_COSEL   RTC_CR_COSEL_Msk
#define	RTC_CR_BKP_Pos   (18U)
#define	RTC_CR_BKP_Msk   (0x1UL << RTC_CR_BKP_Pos)
	0x00040000
#define	RTC_CR_BKP   RTC_CR_BKP_Msk
#define	RTC_CR_SUB1H_Pos   (17U)
#define	RTC_CR_SUB1H_Msk   (0x1UL << RTC_CR_SUB1H_Pos)
	0x00020000
#define	RTC_CR_SUB1H   RTC_CR_SUB1H_Msk
#define	RTC_CR_ADD1H_Pos   (16U)
#define	RTC_CR_ADD1H_Msk   (0x1UL << RTC_CR_ADD1H_Pos)
	0x00010000
#define	RTC_CR_ADD1H   RTC_CR_ADD1H_Msk
#define	RTC_CR_TSIE_Pos   (15U)
#define	RTC_CR_TSIE_Msk   (0x1UL << RTC_CR_TSIE_Pos)
	0x00008000
#define	RTC_CR_TSIE   RTC_CR_TSIE_Msk
#define	RTC_CR_WUTIE_Pos   (14U)
#define	RTC_CR_WUTIE_Msk   (0x1UL << RTC_CR_WUTIE_Pos)
	0x00004000
#define	RTC_CR_WUTIE   RTC_CR_WUTIE_Msk
#define	RTC_CR_ALRBIE_Pos   (13U)
#define	RTC_CR_ALRBIE_Msk   (0x1UL << RTC_CR_ALRBIE_Pos)
	0x00002000
#define	RTC_CR_ALRBIE   RTC_CR_ALRBIE_Msk
#define	RTC_CR_ALRAIE_Pos   (12U)
#define	RTC_CR_ALRAIE_Msk   (0x1UL << RTC_CR_ALRAIE_Pos)
	0x00001000
#define	RTC_CR_ALRAIE   RTC_CR_ALRAIE_Msk
#define	RTC_CR_TSE_Pos   (11U)
#define	RTC_CR_TSE_Msk   (0x1UL << RTC_CR_TSE_Pos)
	0x00000800
#define	RTC_CR_TSE   RTC_CR_TSE_Msk
#define	RTC_CR_WUTE_Pos   (10U)
#define	RTC_CR_WUTE_Msk   (0x1UL << RTC_CR_WUTE_Pos)
	0x00000400
#define	RTC_CR_WUTE   RTC_CR_WUTE_Msk
#define	RTC_CR_ALRBE_Pos   (9U)
#define	RTC_CR_ALRBE_Msk   (0x1UL << RTC_CR_ALRBE_Pos)
	0x00000200
#define	RTC_CR_ALRBE   RTC_CR_ALRBE_Msk
#define	RTC_CR_ALRAE_Pos   (8U)
#define	RTC_CR_ALRAE_Msk   (0x1UL << RTC_CR_ALRAE_Pos)
	0x00000100
#define	RTC_CR_ALRAE   RTC_CR_ALRAE_Msk
#define	RTC_CR_FMT_Pos   (6U)
#define	RTC_CR_FMT_Msk   (0x1UL << RTC_CR_FMT_Pos)
	0x00000040
#define	RTC_CR_FMT   RTC_CR_FMT_Msk
#define	RTC_CR_BYPSHAD_Pos   (5U)
#define	RTC_CR_BYPSHAD_Msk   (0x1UL << RTC_CR_BYPSHAD_Pos)
	0x00000020
#define	RTC_CR_BYPSHAD   RTC_CR_BYPSHAD_Msk
#define	RTC_CR_REFCKON_Pos   (4U)
#define	RTC_CR_REFCKON_Msk   (0x1UL << RTC_CR_REFCKON_Pos)
	0x00000010
#define	RTC_CR_REFCKON   RTC_CR_REFCKON_Msk
#define	RTC_CR_TSEDGE_Pos   (3U)
#define	RTC_CR_TSEDGE_Msk   (0x1UL << RTC_CR_TSEDGE_Pos)
	0x00000008
#define	RTC_CR_TSEDGE   RTC_CR_TSEDGE_Msk
#define	RTC_CR_WUCKSEL_Pos   (0U)
#define	RTC_CR_WUCKSEL_Msk   (0x7UL << RTC_CR_WUCKSEL_Pos)
	0x00000007
#define	RTC_CR_WUCKSEL   RTC_CR_WUCKSEL_Msk
#define	RTC_CR_WUCKSEL_0   (0x1UL << RTC_CR_WUCKSEL_Pos)
	0x00000001
#define	RTC_CR_WUCKSEL_1   (0x2UL << RTC_CR_WUCKSEL_Pos)
	0x00000002
#define	RTC_CR_WUCKSEL_2   (0x4UL << RTC_CR_WUCKSEL_Pos)
	0x00000004
#define	RTC_ISR_ITSF_Pos   (17U)
#define	RTC_ISR_ITSF_Msk   (0x1UL << RTC_ISR_ITSF_Pos)
	0x00020000
#define	RTC_ISR_ITSF   RTC_ISR_ITSF_Msk
#define	RTC_ISR_RECALPF_Pos   (16U)
#define	RTC_ISR_RECALPF_Msk   (0x1UL << RTC_ISR_RECALPF_Pos)
	0x00010000
#define	RTC_ISR_RECALPF   RTC_ISR_RECALPF_Msk
#define	RTC_ISR_TAMP3F_Pos   (15U)
#define	RTC_ISR_TAMP3F_Msk   (0x1UL << RTC_ISR_TAMP3F_Pos)
	0x00008000
#define	RTC_ISR_TAMP3F   RTC_ISR_TAMP3F_Msk
#define	RTC_ISR_TAMP2F_Pos   (14U)
#define	RTC_ISR_TAMP2F_Msk   (0x1UL << RTC_ISR_TAMP2F_Pos)
	0x00004000
#define	RTC_ISR_TAMP2F   RTC_ISR_TAMP2F_Msk
#define	RTC_ISR_TAMP1F_Pos   (13U)
#define	RTC_ISR_TAMP1F_Msk   (0x1UL << RTC_ISR_TAMP1F_Pos)
	0x00002000
#define	RTC_ISR_TAMP1F   RTC_ISR_TAMP1F_Msk
#define	RTC_ISR_TSOVF_Pos   (12U)
#define	RTC_ISR_TSOVF_Msk   (0x1UL << RTC_ISR_TSOVF_Pos)
	0x00001000
#define	RTC_ISR_TSOVF   RTC_ISR_TSOVF_Msk
#define	RTC_ISR_TSF_Pos   (11U)
#define	RTC_ISR_TSF_Msk   (0x1UL << RTC_ISR_TSF_Pos)
	0x00000800
#define	RTC_ISR_TSF   RTC_ISR_TSF_Msk
#define	RTC_ISR_WUTF_Pos   (10U)
#define	RTC_ISR_WUTF_Msk   (0x1UL << RTC_ISR_WUTF_Pos)
	0x00000400
#define	RTC_ISR_WUTF   RTC_ISR_WUTF_Msk
#define	RTC_ISR_ALRBF_Pos   (9U)
#define	RTC_ISR_ALRBF_Msk   (0x1UL << RTC_ISR_ALRBF_Pos)
	0x00000200
#define	RTC_ISR_ALRBF   RTC_ISR_ALRBF_Msk
#define	RTC_ISR_ALRAF_Pos   (8U)
#define	RTC_ISR_ALRAF_Msk   (0x1UL << RTC_ISR_ALRAF_Pos)
	0x00000100
#define	RTC_ISR_ALRAF   RTC_ISR_ALRAF_Msk
#define	RTC_ISR_INIT_Pos   (7U)
#define	RTC_ISR_INIT_Msk   (0x1UL << RTC_ISR_INIT_Pos)
	0x00000080
#define	RTC_ISR_INIT   RTC_ISR_INIT_Msk
#define	RTC_ISR_INITF_Pos   (6U)
#define	RTC_ISR_INITF_Msk   (0x1UL << RTC_ISR_INITF_Pos)
	0x00000040
#define	RTC_ISR_INITF   RTC_ISR_INITF_Msk
#define	RTC_ISR_RSF_Pos   (5U)
#define	RTC_ISR_RSF_Msk   (0x1UL << RTC_ISR_RSF_Pos)
	0x00000020
#define	RTC_ISR_RSF   RTC_ISR_RSF_Msk
#define	RTC_ISR_INITS_Pos   (4U)
#define	RTC_ISR_INITS_Msk   (0x1UL << RTC_ISR_INITS_Pos)
	0x00000010
#define	RTC_ISR_INITS   RTC_ISR_INITS_Msk
#define	RTC_ISR_SHPF_Pos   (3U)
#define	RTC_ISR_SHPF_Msk   (0x1UL << RTC_ISR_SHPF_Pos)
	0x00000008
#define	RTC_ISR_SHPF   RTC_ISR_SHPF_Msk
#define	RTC_ISR_WUTWF_Pos   (2U)
#define	RTC_ISR_WUTWF_Msk   (0x1UL << RTC_ISR_WUTWF_Pos)
	0x00000004
#define	RTC_ISR_WUTWF   RTC_ISR_WUTWF_Msk
#define	RTC_ISR_ALRBWF_Pos   (1U)
#define	RTC_ISR_ALRBWF_Msk   (0x1UL << RTC_ISR_ALRBWF_Pos)
	0x00000002
#define	RTC_ISR_ALRBWF   RTC_ISR_ALRBWF_Msk
#define	RTC_ISR_ALRAWF_Pos   (0U)
#define	RTC_ISR_ALRAWF_Msk   (0x1UL << RTC_ISR_ALRAWF_Pos)
	0x00000001
#define	RTC_ISR_ALRAWF   RTC_ISR_ALRAWF_Msk
#define	RTC_PRER_PREDIV_A_Pos   (16U)
#define	RTC_PRER_PREDIV_A_Msk   (0x7FUL << RTC_PRER_PREDIV_A_Pos)
	0x007F0000
#define	RTC_PRER_PREDIV_A   RTC_PRER_PREDIV_A_Msk
#define	RTC_PRER_PREDIV_S_Pos   (0U)
#define	RTC_PRER_PREDIV_S_Msk   (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
	0x00007FFF
#define	RTC_PRER_PREDIV_S   RTC_PRER_PREDIV_S_Msk
#define	RTC_WUTR_WUT_Pos   (0U)
#define	RTC_WUTR_WUT_Msk   (0xFFFFUL << RTC_WUTR_WUT_Pos)
	0x0000FFFF
#define	RTC_WUTR_WUT   RTC_WUTR_WUT_Msk
#define	RTC_ALRMAR_MSK4_Pos   (31U)
#define	RTC_ALRMAR_MSK4_Msk   (0x1UL << RTC_ALRMAR_MSK4_Pos)
	0x80000000
#define	RTC_ALRMAR_MSK4   RTC_ALRMAR_MSK4_Msk
#define	RTC_ALRMAR_WDSEL_Pos   (30U)
#define	RTC_ALRMAR_WDSEL_Msk   (0x1UL << RTC_ALRMAR_WDSEL_Pos)
	0x40000000
#define	RTC_ALRMAR_WDSEL   RTC_ALRMAR_WDSEL_Msk
#define	RTC_ALRMAR_DT_Pos   (28U)
#define	RTC_ALRMAR_DT_Msk   (0x3UL << RTC_ALRMAR_DT_Pos)
	0x30000000
#define	RTC_ALRMAR_DT   RTC_ALRMAR_DT_Msk
#define	RTC_ALRMAR_DT_0   (0x1UL << RTC_ALRMAR_DT_Pos)
	0x10000000
#define	RTC_ALRMAR_DT_1   (0x2UL << RTC_ALRMAR_DT_Pos)
	0x20000000
#define	RTC_ALRMAR_DU_Pos   (24U)
#define	RTC_ALRMAR_DU_Msk   (0xFUL << RTC_ALRMAR_DU_Pos)
	0x0F000000
#define	RTC_ALRMAR_DU   RTC_ALRMAR_DU_Msk
#define	RTC_ALRMAR_DU_0   (0x1UL << RTC_ALRMAR_DU_Pos)
	0x01000000
#define	RTC_ALRMAR_DU_1   (0x2UL << RTC_ALRMAR_DU_Pos)
	0x02000000
#define	RTC_ALRMAR_DU_2   (0x4UL << RTC_ALRMAR_DU_Pos)
	0x04000000
#define	RTC_ALRMAR_DU_3   (0x8UL << RTC_ALRMAR_DU_Pos)
	0x08000000
#define	RTC_ALRMAR_MSK3_Pos   (23U)
#define	RTC_ALRMAR_MSK3_Msk   (0x1UL << RTC_ALRMAR_MSK3_Pos)
	0x00800000
#define	RTC_ALRMAR_MSK3   RTC_ALRMAR_MSK3_Msk
#define	RTC_ALRMAR_PM_Pos   (22U)
#define	RTC_ALRMAR_PM_Msk   (0x1UL << RTC_ALRMAR_PM_Pos)
	0x00400000
#define	RTC_ALRMAR_PM   RTC_ALRMAR_PM_Msk
#define	RTC_ALRMAR_HT_Pos   (20U)
#define	RTC_ALRMAR_HT_Msk   (0x3UL << RTC_ALRMAR_HT_Pos)
	0x00300000
#define	RTC_ALRMAR_HT   RTC_ALRMAR_HT_Msk
#define	RTC_ALRMAR_HT_0   (0x1UL << RTC_ALRMAR_HT_Pos)
	0x00100000
#define	RTC_ALRMAR_HT_1   (0x2UL << RTC_ALRMAR_HT_Pos)
	0x00200000
#define	RTC_ALRMAR_HU_Pos   (16U)
#define	RTC_ALRMAR_HU_Msk   (0xFUL << RTC_ALRMAR_HU_Pos)
	0x000F0000
#define	RTC_ALRMAR_HU   RTC_ALRMAR_HU_Msk
#define	RTC_ALRMAR_HU_0   (0x1UL << RTC_ALRMAR_HU_Pos)
	0x00010000
#define	RTC_ALRMAR_HU_1   (0x2UL << RTC_ALRMAR_HU_Pos)
	0x00020000
#define	RTC_ALRMAR_HU_2   (0x4UL << RTC_ALRMAR_HU_Pos)
	0x00040000
#define	RTC_ALRMAR_HU_3   (0x8UL << RTC_ALRMAR_HU_Pos)
	0x00080000
#define	RTC_ALRMAR_MSK2_Pos   (15U)
#define	RTC_ALRMAR_MSK2_Msk   (0x1UL << RTC_ALRMAR_MSK2_Pos)
	0x00008000
#define	RTC_ALRMAR_MSK2   RTC_ALRMAR_MSK2_Msk
#define	RTC_ALRMAR_MNT_Pos   (12U)
#define	RTC_ALRMAR_MNT_Msk   (0x7UL << RTC_ALRMAR_MNT_Pos)
	0x00007000
#define	RTC_ALRMAR_MNT   RTC_ALRMAR_MNT_Msk
#define	RTC_ALRMAR_MNT_0   (0x1UL << RTC_ALRMAR_MNT_Pos)
	0x00001000
#define	RTC_ALRMAR_MNT_1   (0x2UL << RTC_ALRMAR_MNT_Pos)
	0x00002000
#define	RTC_ALRMAR_MNT_2   (0x4UL << RTC_ALRMAR_MNT_Pos)
	0x00004000
#define	RTC_ALRMAR_MNU_Pos   (8U)
#define	RTC_ALRMAR_MNU_Msk   (0xFUL << RTC_ALRMAR_MNU_Pos)
	0x00000F00
#define	RTC_ALRMAR_MNU   RTC_ALRMAR_MNU_Msk
#define	RTC_ALRMAR_MNU_0   (0x1UL << RTC_ALRMAR_MNU_Pos)
	0x00000100
#define	RTC_ALRMAR_MNU_1   (0x2UL << RTC_ALRMAR_MNU_Pos)
	0x00000200
#define	RTC_ALRMAR_MNU_2   (0x4UL << RTC_ALRMAR_MNU_Pos)
	0x00000400
#define	RTC_ALRMAR_MNU_3   (0x8UL << RTC_ALRMAR_MNU_Pos)
	0x00000800
#define	RTC_ALRMAR_MSK1_Pos   (7U)
#define	RTC_ALRMAR_MSK1_Msk   (0x1UL << RTC_ALRMAR_MSK1_Pos)
	0x00000080
#define	RTC_ALRMAR_MSK1   RTC_ALRMAR_MSK1_Msk
#define	RTC_ALRMAR_ST_Pos   (4U)
#define	RTC_ALRMAR_ST_Msk   (0x7UL << RTC_ALRMAR_ST_Pos)
	0x00000070
#define	RTC_ALRMAR_ST   RTC_ALRMAR_ST_Msk
#define	RTC_ALRMAR_ST_0   (0x1UL << RTC_ALRMAR_ST_Pos)
	0x00000010
#define	RTC_ALRMAR_ST_1   (0x2UL << RTC_ALRMAR_ST_Pos)
	0x00000020
#define	RTC_ALRMAR_ST_2   (0x4UL << RTC_ALRMAR_ST_Pos)
	0x00000040
#define	RTC_ALRMAR_SU_Pos   (0U)
#define	RTC_ALRMAR_SU_Msk   (0xFUL << RTC_ALRMAR_SU_Pos)
	0x0000000F
#define	RTC_ALRMAR_SU   RTC_ALRMAR_SU_Msk
#define	RTC_ALRMAR_SU_0   (0x1UL << RTC_ALRMAR_SU_Pos)
	0x00000001
#define	RTC_ALRMAR_SU_1   (0x2UL << RTC_ALRMAR_SU_Pos)
	0x00000002
#define	RTC_ALRMAR_SU_2   (0x4UL << RTC_ALRMAR_SU_Pos)
	0x00000004
#define	RTC_ALRMAR_SU_3   (0x8UL << RTC_ALRMAR_SU_Pos)
	0x00000008
#define	RTC_ALRMBR_MSK4_Pos   (31U)
#define	RTC_ALRMBR_MSK4_Msk   (0x1UL << RTC_ALRMBR_MSK4_Pos)
	0x80000000
#define	RTC_ALRMBR_MSK4   RTC_ALRMBR_MSK4_Msk
#define	RTC_ALRMBR_WDSEL_Pos   (30U)
#define	RTC_ALRMBR_WDSEL_Msk   (0x1UL << RTC_ALRMBR_WDSEL_Pos)
	0x40000000
#define	RTC_ALRMBR_WDSEL   RTC_ALRMBR_WDSEL_Msk
#define	RTC_ALRMBR_DT_Pos   (28U)
#define	RTC_ALRMBR_DT_Msk   (0x3UL << RTC_ALRMBR_DT_Pos)
	0x30000000
#define	RTC_ALRMBR_DT   RTC_ALRMBR_DT_Msk
#define	RTC_ALRMBR_DT_0   (0x1UL << RTC_ALRMBR_DT_Pos)
	0x10000000
#define	RTC_ALRMBR_DT_1   (0x2UL << RTC_ALRMBR_DT_Pos)
	0x20000000
#define	RTC_ALRMBR_DU_Pos   (24U)
#define	RTC_ALRMBR_DU_Msk   (0xFUL << RTC_ALRMBR_DU_Pos)
	0x0F000000
#define	RTC_ALRMBR_DU   RTC_ALRMBR_DU_Msk
#define	RTC_ALRMBR_DU_0   (0x1UL << RTC_ALRMBR_DU_Pos)
	0x01000000
#define	RTC_ALRMBR_DU_1   (0x2UL << RTC_ALRMBR_DU_Pos)
	0x02000000
#define	RTC_ALRMBR_DU_2   (0x4UL << RTC_ALRMBR_DU_Pos)
	0x04000000
#define	RTC_ALRMBR_DU_3   (0x8UL << RTC_ALRMBR_DU_Pos)
	0x08000000
#define	RTC_ALRMBR_MSK3_Pos   (23U)
#define	RTC_ALRMBR_MSK3_Msk   (0x1UL << RTC_ALRMBR_MSK3_Pos)
	0x00800000
#define	RTC_ALRMBR_MSK3   RTC_ALRMBR_MSK3_Msk
#define	RTC_ALRMBR_PM_Pos   (22U)
#define	RTC_ALRMBR_PM_Msk   (0x1UL << RTC_ALRMBR_PM_Pos)
	0x00400000
#define	RTC_ALRMBR_PM   RTC_ALRMBR_PM_Msk
#define	RTC_ALRMBR_HT_Pos   (20U)
#define	RTC_ALRMBR_HT_Msk   (0x3UL << RTC_ALRMBR_HT_Pos)
	0x00300000
#define	RTC_ALRMBR_HT   RTC_ALRMBR_HT_Msk
#define	RTC_ALRMBR_HT_0   (0x1UL << RTC_ALRMBR_HT_Pos)
	0x00100000
#define	RTC_ALRMBR_HT_1   (0x2UL << RTC_ALRMBR_HT_Pos)
	0x00200000
#define	RTC_ALRMBR_HU_Pos   (16U)
#define	RTC_ALRMBR_HU_Msk   (0xFUL << RTC_ALRMBR_HU_Pos)
	0x000F0000
#define	RTC_ALRMBR_HU   RTC_ALRMBR_HU_Msk
#define	RTC_ALRMBR_HU_0   (0x1UL << RTC_ALRMBR_HU_Pos)
	0x00010000
#define	RTC_ALRMBR_HU_1   (0x2UL << RTC_ALRMBR_HU_Pos)
	0x00020000
#define	RTC_ALRMBR_HU_2   (0x4UL << RTC_ALRMBR_HU_Pos)
	0x00040000
#define	RTC_ALRMBR_HU_3   (0x8UL << RTC_ALRMBR_HU_Pos)
	0x00080000
#define	RTC_ALRMBR_MSK2_Pos   (15U)
#define	RTC_ALRMBR_MSK2_Msk   (0x1UL << RTC_ALRMBR_MSK2_Pos)
	0x00008000
#define	RTC_ALRMBR_MSK2   RTC_ALRMBR_MSK2_Msk
#define	RTC_ALRMBR_MNT_Pos   (12U)
#define	RTC_ALRMBR_MNT_Msk   (0x7UL << RTC_ALRMBR_MNT_Pos)
	0x00007000
#define	RTC_ALRMBR_MNT   RTC_ALRMBR_MNT_Msk
#define	RTC_ALRMBR_MNT_0   (0x1UL << RTC_ALRMBR_MNT_Pos)
	0x00001000
#define	RTC_ALRMBR_MNT_1   (0x2UL << RTC_ALRMBR_MNT_Pos)
	0x00002000
#define	RTC_ALRMBR_MNT_2   (0x4UL << RTC_ALRMBR_MNT_Pos)
	0x00004000
#define	RTC_ALRMBR_MNU_Pos   (8U)
#define	RTC_ALRMBR_MNU_Msk   (0xFUL << RTC_ALRMBR_MNU_Pos)
	0x00000F00
#define	RTC_ALRMBR_MNU   RTC_ALRMBR_MNU_Msk
#define	RTC_ALRMBR_MNU_0   (0x1UL << RTC_ALRMBR_MNU_Pos)
	0x00000100
#define	RTC_ALRMBR_MNU_1   (0x2UL << RTC_ALRMBR_MNU_Pos)
	0x00000200
#define	RTC_ALRMBR_MNU_2   (0x4UL << RTC_ALRMBR_MNU_Pos)
	0x00000400
#define	RTC_ALRMBR_MNU_3   (0x8UL << RTC_ALRMBR_MNU_Pos)
	0x00000800
#define	RTC_ALRMBR_MSK1_Pos   (7U)
#define	RTC_ALRMBR_MSK1_Msk   (0x1UL << RTC_ALRMBR_MSK1_Pos)
	0x00000080
#define	RTC_ALRMBR_MSK1   RTC_ALRMBR_MSK1_Msk
#define	RTC_ALRMBR_ST_Pos   (4U)
#define	RTC_ALRMBR_ST_Msk   (0x7UL << RTC_ALRMBR_ST_Pos)
	0x00000070
#define	RTC_ALRMBR_ST   RTC_ALRMBR_ST_Msk
#define	RTC_ALRMBR_ST_0   (0x1UL << RTC_ALRMBR_ST_Pos)
	0x00000010
#define	RTC_ALRMBR_ST_1   (0x2UL << RTC_ALRMBR_ST_Pos)
	0x00000020
#define	RTC_ALRMBR_ST_2   (0x4UL << RTC_ALRMBR_ST_Pos)
	0x00000040
#define	RTC_ALRMBR_SU_Pos   (0U)
#define	RTC_ALRMBR_SU_Msk   (0xFUL << RTC_ALRMBR_SU_Pos)
	0x0000000F
#define	RTC_ALRMBR_SU   RTC_ALRMBR_SU_Msk
#define	RTC_ALRMBR_SU_0   (0x1UL << RTC_ALRMBR_SU_Pos)
	0x00000001
#define	RTC_ALRMBR_SU_1   (0x2UL << RTC_ALRMBR_SU_Pos)
	0x00000002
#define	RTC_ALRMBR_SU_2   (0x4UL << RTC_ALRMBR_SU_Pos)
	0x00000004
#define	RTC_ALRMBR_SU_3   (0x8UL << RTC_ALRMBR_SU_Pos)
	0x00000008
#define	RTC_WPR_KEY_Pos   (0U)
#define	RTC_WPR_KEY_Msk   (0xFFUL << RTC_WPR_KEY_Pos)
	0x000000FF
#define	RTC_WPR_KEY   RTC_WPR_KEY_Msk
#define	RTC_SSR_SS_Pos   (0U)
#define	RTC_SSR_SS_Msk   (0xFFFFUL << RTC_SSR_SS_Pos)
	0x0000FFFF
#define	RTC_SSR_SS   RTC_SSR_SS_Msk
#define	RTC_SHIFTR_SUBFS_Pos   (0U)
#define	RTC_SHIFTR_SUBFS_Msk   (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
	0x00007FFF
#define	RTC_SHIFTR_SUBFS   RTC_SHIFTR_SUBFS_Msk
#define	RTC_SHIFTR_ADD1S_Pos   (31U)
#define	RTC_SHIFTR_ADD1S_Msk   (0x1UL << RTC_SHIFTR_ADD1S_Pos)
	0x80000000
#define	RTC_SHIFTR_ADD1S   RTC_SHIFTR_ADD1S_Msk
#define	RTC_TSTR_PM_Pos   (22U)
#define	RTC_TSTR_PM_Msk   (0x1UL << RTC_TSTR_PM_Pos)
	0x00400000
#define	RTC_TSTR_PM   RTC_TSTR_PM_Msk
#define	RTC_TSTR_HT_Pos   (20U)
#define	RTC_TSTR_HT_Msk   (0x3UL << RTC_TSTR_HT_Pos)
	0x00300000
#define	RTC_TSTR_HT   RTC_TSTR_HT_Msk
#define	RTC_TSTR_HT_0   (0x1UL << RTC_TSTR_HT_Pos)
	0x00100000
#define	RTC_TSTR_HT_1   (0x2UL << RTC_TSTR_HT_Pos)
	0x00200000
#define	RTC_TSTR_HU_Pos   (16U)
#define	RTC_TSTR_HU_Msk   (0xFUL << RTC_TSTR_HU_Pos)
	0x000F0000
#define	RTC_TSTR_HU   RTC_TSTR_HU_Msk
#define	RTC_TSTR_HU_0   (0x1UL << RTC_TSTR_HU_Pos)
	0x00010000
#define	RTC_TSTR_HU_1   (0x2UL << RTC_TSTR_HU_Pos)
	0x00020000
#define	RTC_TSTR_HU_2   (0x4UL << RTC_TSTR_HU_Pos)
	0x00040000
#define	RTC_TSTR_HU_3   (0x8UL << RTC_TSTR_HU_Pos)
	0x00080000
#define	RTC_TSTR_MNT_Pos   (12U)
#define	RTC_TSTR_MNT_Msk   (0x7UL << RTC_TSTR_MNT_Pos)
	0x00007000
#define	RTC_TSTR_MNT   RTC_TSTR_MNT_Msk
#define	RTC_TSTR_MNT_0   (0x1UL << RTC_TSTR_MNT_Pos)
	0x00001000
#define	RTC_TSTR_MNT_1   (0x2UL << RTC_TSTR_MNT_Pos)
	0x00002000
#define	RTC_TSTR_MNT_2   (0x4UL << RTC_TSTR_MNT_Pos)
	0x00004000
#define	RTC_TSTR_MNU_Pos   (8U)
#define	RTC_TSTR_MNU_Msk   (0xFUL << RTC_TSTR_MNU_Pos)
	0x00000F00
#define	RTC_TSTR_MNU   RTC_TSTR_MNU_Msk
#define	RTC_TSTR_MNU_0   (0x1UL << RTC_TSTR_MNU_Pos)
	0x00000100
#define	RTC_TSTR_MNU_1   (0x2UL << RTC_TSTR_MNU_Pos)
	0x00000200
#define	RTC_TSTR_MNU_2   (0x4UL << RTC_TSTR_MNU_Pos)
	0x00000400
#define	RTC_TSTR_MNU_3   (0x8UL << RTC_TSTR_MNU_Pos)
	0x00000800
#define	RTC_TSTR_ST_Pos   (4U)
#define	RTC_TSTR_ST_Msk   (0x7UL << RTC_TSTR_ST_Pos)
	0x00000070
#define	RTC_TSTR_ST   RTC_TSTR_ST_Msk
#define	RTC_TSTR_ST_0   (0x1UL << RTC_TSTR_ST_Pos)
	0x00000010
#define	RTC_TSTR_ST_1   (0x2UL << RTC_TSTR_ST_Pos)
	0x00000020
#define	RTC_TSTR_ST_2   (0x4UL << RTC_TSTR_ST_Pos)
	0x00000040
#define	RTC_TSTR_SU_Pos   (0U)
#define	RTC_TSTR_SU_Msk   (0xFUL << RTC_TSTR_SU_Pos)
	0x0000000F
#define	RTC_TSTR_SU   RTC_TSTR_SU_Msk
#define	RTC_TSTR_SU_0   (0x1UL << RTC_TSTR_SU_Pos)
	0x00000001
#define	RTC_TSTR_SU_1   (0x2UL << RTC_TSTR_SU_Pos)
	0x00000002
#define	RTC_TSTR_SU_2   (0x4UL << RTC_TSTR_SU_Pos)
	0x00000004
#define	RTC_TSTR_SU_3   (0x8UL << RTC_TSTR_SU_Pos)
	0x00000008
#define	RTC_TSDR_WDU_Pos   (13U)
#define	RTC_TSDR_WDU_Msk   (0x7UL << RTC_TSDR_WDU_Pos)
	0x0000E000
#define	RTC_TSDR_WDU   RTC_TSDR_WDU_Msk
#define	RTC_TSDR_WDU_0   (0x1UL << RTC_TSDR_WDU_Pos)
	0x00002000
#define	RTC_TSDR_WDU_1   (0x2UL << RTC_TSDR_WDU_Pos)
	0x00004000
#define	RTC_TSDR_WDU_2   (0x4UL << RTC_TSDR_WDU_Pos)
	0x00008000
#define	RTC_TSDR_MT_Pos   (12U)
#define	RTC_TSDR_MT_Msk   (0x1UL << RTC_TSDR_MT_Pos)
	0x00001000
#define	RTC_TSDR_MT   RTC_TSDR_MT_Msk
#define	RTC_TSDR_MU_Pos   (8U)
#define	RTC_TSDR_MU_Msk   (0xFUL << RTC_TSDR_MU_Pos)
	0x00000F00
#define	RTC_TSDR_MU   RTC_TSDR_MU_Msk
#define	RTC_TSDR_MU_0   (0x1UL << RTC_TSDR_MU_Pos)
	0x00000100
#define	RTC_TSDR_MU_1   (0x2UL << RTC_TSDR_MU_Pos)
	0x00000200
#define	RTC_TSDR_MU_2   (0x4UL << RTC_TSDR_MU_Pos)
	0x00000400
#define	RTC_TSDR_MU_3   (0x8UL << RTC_TSDR_MU_Pos)
	0x00000800
#define	RTC_TSDR_DT_Pos   (4U)
#define	RTC_TSDR_DT_Msk   (0x3UL << RTC_TSDR_DT_Pos)
	0x00000030
#define	RTC_TSDR_DT   RTC_TSDR_DT_Msk
#define	RTC_TSDR_DT_0   (0x1UL << RTC_TSDR_DT_Pos)
	0x00000010
#define	RTC_TSDR_DT_1   (0x2UL << RTC_TSDR_DT_Pos)
	0x00000020
#define	RTC_TSDR_DU_Pos   (0U)
#define	RTC_TSDR_DU_Msk   (0xFUL << RTC_TSDR_DU_Pos)
	0x0000000F
#define	RTC_TSDR_DU   RTC_TSDR_DU_Msk
#define	RTC_TSDR_DU_0   (0x1UL << RTC_TSDR_DU_Pos)
	0x00000001
#define	RTC_TSDR_DU_1   (0x2UL << RTC_TSDR_DU_Pos)
	0x00000002
#define	RTC_TSDR_DU_2   (0x4UL << RTC_TSDR_DU_Pos)
	0x00000004
#define	RTC_TSDR_DU_3   (0x8UL << RTC_TSDR_DU_Pos)
	0x00000008
#define	RTC_TSSSR_SS_Pos   (0U)
#define	RTC_TSSSR_SS_Msk   (0xFFFFUL << RTC_TSSSR_SS_Pos)
	0x0000FFFF
#define	RTC_TSSSR_SS   RTC_TSSSR_SS_Msk
#define	RTC_CALR_CALP_Pos   (15U)
#define	RTC_CALR_CALP_Msk   (0x1UL << RTC_CALR_CALP_Pos)
	0x00008000
#define	RTC_CALR_CALP   RTC_CALR_CALP_Msk
#define	RTC_CALR_CALW8_Pos   (14U)
#define	RTC_CALR_CALW8_Msk   (0x1UL << RTC_CALR_CALW8_Pos)
	0x00004000
#define	RTC_CALR_CALW8   RTC_CALR_CALW8_Msk
#define	RTC_CALR_CALW16_Pos   (13U)
#define	RTC_CALR_CALW16_Msk   (0x1UL << RTC_CALR_CALW16_Pos)
	0x00002000
#define	RTC_CALR_CALW16   RTC_CALR_CALW16_Msk
#define	RTC_CALR_CALM_Pos   (0U)
#define	RTC_CALR_CALM_Msk   (0x1FFUL << RTC_CALR_CALM_Pos)
	0x000001FF
#define	RTC_CALR_CALM   RTC_CALR_CALM_Msk
#define	RTC_CALR_CALM_0   (0x001UL << RTC_CALR_CALM_Pos)
	0x00000001
#define	RTC_CALR_CALM_1   (0x002UL << RTC_CALR_CALM_Pos)
	0x00000002
#define	RTC_CALR_CALM_2   (0x004UL << RTC_CALR_CALM_Pos)
	0x00000004
#define	RTC_CALR_CALM_3   (0x008UL << RTC_CALR_CALM_Pos)
	0x00000008
#define	RTC_CALR_CALM_4   (0x010UL << RTC_CALR_CALM_Pos)
	0x00000010
#define	RTC_CALR_CALM_5   (0x020UL << RTC_CALR_CALM_Pos)
	0x00000020
#define	RTC_CALR_CALM_6   (0x040UL << RTC_CALR_CALM_Pos)
	0x00000040
#define	RTC_CALR_CALM_7   (0x080UL << RTC_CALR_CALM_Pos)
	0x00000080
#define	RTC_CALR_CALM_8   (0x100UL << RTC_CALR_CALM_Pos)
	0x00000100
#define	RTC_TAFCR_PC15MODE_Pos   (23U)
#define	RTC_TAFCR_PC15MODE_Msk   (0x1UL << RTC_TAFCR_PC15MODE_Pos)
	0x00800000
#define	RTC_TAFCR_PC15MODE   RTC_TAFCR_PC15MODE_Msk
#define	RTC_TAFCR_PC15VALUE_Pos   (22U)
#define	RTC_TAFCR_PC15VALUE_Msk   (0x1UL << RTC_TAFCR_PC15VALUE_Pos)
	0x00400000
#define	RTC_TAFCR_PC15VALUE   RTC_TAFCR_PC15VALUE_Msk
#define	RTC_TAFCR_PC14MODE_Pos   (21U)
#define	RTC_TAFCR_PC14MODE_Msk   (0x1UL << RTC_TAFCR_PC14MODE_Pos)
	0x00200000
#define	RTC_TAFCR_PC14MODE   RTC_TAFCR_PC14MODE_Msk
#define	RTC_TAFCR_PC14VALUE_Pos   (20U)
#define	RTC_TAFCR_PC14VALUE_Msk   (0x1UL << RTC_TAFCR_PC14VALUE_Pos)
	0x00100000
#define	RTC_TAFCR_PC14VALUE   RTC_TAFCR_PC14VALUE_Msk
#define	RTC_TAFCR_PC13MODE_Pos   (19U)
#define	RTC_TAFCR_PC13MODE_Msk   (0x1UL << RTC_TAFCR_PC13MODE_Pos)
	0x00080000
#define	RTC_TAFCR_PC13MODE   RTC_TAFCR_PC13MODE_Msk
#define	RTC_TAFCR_PC13VALUE_Pos   (18U)
#define	RTC_TAFCR_PC13VALUE_Msk   (0x1UL << RTC_TAFCR_PC13VALUE_Pos)
	0x00040000
#define	RTC_TAFCR_PC13VALUE   RTC_TAFCR_PC13VALUE_Msk
#define	RTC_TAFCR_TAMPPUDIS_Pos   (15U)
#define	RTC_TAFCR_TAMPPUDIS_Msk   (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)
	0x00008000
#define	RTC_TAFCR_TAMPPUDIS   RTC_TAFCR_TAMPPUDIS_Msk
#define	RTC_TAFCR_TAMPPRCH_Pos   (13U)
#define	RTC_TAFCR_TAMPPRCH_Msk   (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)
	0x00006000
#define	RTC_TAFCR_TAMPPRCH   RTC_TAFCR_TAMPPRCH_Msk
#define	RTC_TAFCR_TAMPPRCH_0   (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)
	0x00002000
#define	RTC_TAFCR_TAMPPRCH_1   (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)
	0x00004000
#define	RTC_TAFCR_TAMPFLT_Pos   (11U)
#define	RTC_TAFCR_TAMPFLT_Msk   (0x3UL << RTC_TAFCR_TAMPFLT_Pos)
	0x00001800
#define	RTC_TAFCR_TAMPFLT   RTC_TAFCR_TAMPFLT_Msk
#define	RTC_TAFCR_TAMPFLT_0   (0x1UL << RTC_TAFCR_TAMPFLT_Pos)
	0x00000800
#define	RTC_TAFCR_TAMPFLT_1   (0x2UL << RTC_TAFCR_TAMPFLT_Pos)
	0x00001000
#define	RTC_TAFCR_TAMPFREQ_Pos   (8U)
#define	RTC_TAFCR_TAMPFREQ_Msk   (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)
	0x00000700
#define	RTC_TAFCR_TAMPFREQ   RTC_TAFCR_TAMPFREQ_Msk
#define	RTC_TAFCR_TAMPFREQ_0   (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)
	0x00000100
#define	RTC_TAFCR_TAMPFREQ_1   (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)
	0x00000200
#define	RTC_TAFCR_TAMPFREQ_2   (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)
	0x00000400
#define	RTC_TAFCR_TAMPTS_Pos   (7U)
#define	RTC_TAFCR_TAMPTS_Msk   (0x1UL << RTC_TAFCR_TAMPTS_Pos)
	0x00000080
#define	RTC_TAFCR_TAMPTS   RTC_TAFCR_TAMPTS_Msk
#define	RTC_TAFCR_TAMP3TRG_Pos   (6U)
#define	RTC_TAFCR_TAMP3TRG_Msk   (0x1UL << RTC_TAFCR_TAMP3TRG_Pos)
	0x00000040
#define	RTC_TAFCR_TAMP3TRG   RTC_TAFCR_TAMP3TRG_Msk
#define	RTC_TAFCR_TAMP3E_Pos   (5U)
#define	RTC_TAFCR_TAMP3E_Msk   (0x1UL << RTC_TAFCR_TAMP3E_Pos)
	0x00000020
#define	RTC_TAFCR_TAMP3E   RTC_TAFCR_TAMP3E_Msk
#define	RTC_TAFCR_TAMPIE_Pos   (2U)
#define	RTC_TAFCR_TAMPIE_Msk   (0x1UL << RTC_TAFCR_TAMPIE_Pos)
	0x00000004
#define	RTC_TAFCR_TAMPIE   RTC_TAFCR_TAMPIE_Msk
#define	RTC_TAFCR_TAMP1TRG_Pos   (1U)
#define	RTC_TAFCR_TAMP1TRG_Msk   (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)
	0x00000002
#define	RTC_TAFCR_TAMP1TRG   RTC_TAFCR_TAMP1TRG_Msk
#define	RTC_TAFCR_TAMP1E_Pos   (0U)
#define	RTC_TAFCR_TAMP1E_Msk   (0x1UL << RTC_TAFCR_TAMP1E_Pos)
	0x00000001
#define	RTC_TAFCR_TAMP1E   RTC_TAFCR_TAMP1E_Msk
#define	TAMPCR   TAFCR
#define	RTC_TAMPCR_TAMPPUDIS_Pos   RTC_TAFCR_TAMPPUDIS_Pos
#define	RTC_TAMPCR_TAMPPUDIS_Msk   RTC_TAFCR_TAMPPUDIS_Msk
#define	RTC_TAMPCR_TAMPPUDIS   RTC_TAFCR_TAMPPUDIS
#define	RTC_TAMPCR_TAMPPRCH_Pos   RTC_TAFCR_TAMPPRCH_Pos
#define	RTC_TAMPCR_TAMPPRCH_Msk   RTC_TAFCR_TAMPPRCH_Msk
#define	RTC_TAMPCR_TAMPPRCH   RTC_TAFCR_TAMPPRCH
#define	RTC_TAMPCR_TAMPPRCH_0   RTC_TAFCR_TAMPPRCH_0
#define	RTC_TAMPCR_TAMPPRCH_1   RTC_TAFCR_TAMPPRCH_1
#define	RTC_TAMPCR_TAMPFLT_Pos   RTC_TAFCR_TAMPFLT_Pos
#define	RTC_TAMPCR_TAMPFLT_Msk   RTC_TAFCR_TAMPFLT_Msk
#define	RTC_TAMPCR_TAMPFLT   RTC_TAFCR_TAMPFLT
#define	RTC_TAMPCR_TAMPFLT_0   RTC_TAFCR_TAMPFLT_0
#define	RTC_TAMPCR_TAMPFLT_1   RTC_TAFCR_TAMPFLT_1
#define	RTC_TAMPCR_TAMPFREQ_Pos   RTC_TAFCR_TAMPFREQ_Pos
#define	RTC_TAMPCR_TAMPFREQ_Msk   RTC_TAFCR_TAMPFREQ_Msk
#define	RTC_TAMPCR_TAMPFREQ   RTC_TAFCR_TAMPFREQ
#define	RTC_TAMPCR_TAMPFREQ_0   RTC_TAFCR_TAMPFREQ_0
#define	RTC_TAMPCR_TAMPFREQ_1   RTC_TAFCR_TAMPFREQ_1
#define	RTC_TAMPCR_TAMPFREQ_2   RTC_TAFCR_TAMPFREQ_2
#define	RTC_TAMPCR_TAMPTS_Pos   RTC_TAFCR_TAMPTS_Pos
#define	RTC_TAMPCR_TAMPTS_Msk   RTC_TAFCR_TAMPTS_Msk
#define	RTC_TAMPCR_TAMPTS   RTC_TAFCR_TAMPTS
#define	RTC_TAMPCR_TAMP3TRG_Pos   RTC_TAFCR_TAMP3TRG_Pos
#define	RTC_TAMPCR_TAMP3TRG_Msk   RTC_TAFCR_TAMP3TRG_Msk
#define	RTC_TAMPCR_TAMP3TRG   RTC_TAFCR_TAMP3TRG
#define	RTC_TAMPCR_TAMP3E_Pos   RTC_TAFCR_TAMP3E_Pos
#define	RTC_TAMPCR_TAMP3E_Msk   RTC_TAFCR_TAMP3E_Msk
#define	RTC_TAMPCR_TAMP3E   RTC_TAFCR_TAMP3E
#define	RTC_TAMPCR_TAMPIE_Pos   RTC_TAFCR_TAMPIE_Pos
#define	RTC_TAMPCR_TAMPIE_Msk   RTC_TAFCR_TAMPIE_Msk
#define	RTC_TAMPCR_TAMPIE   RTC_TAFCR_TAMPIE
#define	RTC_TAMPCR_TAMP1TRG_Pos   RTC_TAFCR_TAMP1TRG_Pos
#define	RTC_TAMPCR_TAMP1TRG_Msk   RTC_TAFCR_TAMP1TRG_Msk
#define	RTC_TAMPCR_TAMP1TRG   RTC_TAFCR_TAMP1TRG
#define	RTC_TAMPCR_TAMP1E_Pos   RTC_TAFCR_TAMP1E_Pos
#define	RTC_TAMPCR_TAMP1E_Msk   RTC_TAFCR_TAMP1E_Msk
#define	RTC_TAMPCR_TAMP1E   RTC_TAFCR_TAMP1E
#define	RTC_TAMPCR_TAMP3MF_Pos   (24U)
#define	RTC_TAMPCR_TAMP3MF_Msk   (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)
	0x01000000
#define	RTC_TAMPCR_TAMP3MF   RTC_TAMPCR_TAMP3MF_Msk
#define	RTC_TAMPCR_TAMP3NOERASE_Pos   (23U)
#define	RTC_TAMPCR_TAMP3NOERASE_Msk   (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)
	0x00800000
#define	RTC_TAMPCR_TAMP3NOERASE   RTC_TAMPCR_TAMP3NOERASE_Msk
#define	RTC_TAMPCR_TAMP3IE_Pos   (22U)
#define	RTC_TAMPCR_TAMP3IE_Msk   (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)
	0x00400000
#define	RTC_TAMPCR_TAMP3IE   RTC_TAMPCR_TAMP3IE_Msk
#define	RTC_TAMPCR_TAMP2MF_Pos   (21U)
#define	RTC_TAMPCR_TAMP2MF_Msk   (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)
	0x00200000
#define	RTC_TAMPCR_TAMP2MF   RTC_TAMPCR_TAMP2MF_Msk
#define	RTC_TAMPCR_TAMP2NOERASE_Pos   (20U)
#define	RTC_TAMPCR_TAMP2NOERASE_Msk   (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)
	0x00100000
#define	RTC_TAMPCR_TAMP2NOERASE   RTC_TAMPCR_TAMP2NOERASE_Msk
#define	RTC_TAMPCR_TAMP2IE_Pos   (19U)
#define	RTC_TAMPCR_TAMP2IE_Msk   (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)
	0x00080000
#define	RTC_TAMPCR_TAMP2IE   RTC_TAMPCR_TAMP2IE_Msk
#define	RTC_TAMPCR_TAMP1MF_Pos   (18U)
#define	RTC_TAMPCR_TAMP1MF_Msk   (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)
	0x00040000
#define	RTC_TAMPCR_TAMP1MF   RTC_TAMPCR_TAMP1MF_Msk
#define	RTC_TAMPCR_TAMP1NOERASE_Pos   (17U)
#define	RTC_TAMPCR_TAMP1NOERASE_Msk   (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)
	0x00020000
#define	RTC_TAMPCR_TAMP1NOERASE   RTC_TAMPCR_TAMP1NOERASE_Msk
#define	RTC_TAMPCR_TAMP1IE_Pos   (16U)
#define	RTC_TAMPCR_TAMP1IE_Msk   (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)
	0x00010000
#define	RTC_TAMPCR_TAMP1IE   RTC_TAMPCR_TAMP1IE_Msk
#define	RTC_TAMPCR_TAMP2TRG_Pos   (4U)
#define	RTC_TAMPCR_TAMP2TRG_Msk   (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)
	0x00000010
#define	RTC_TAMPCR_TAMP2TRG   RTC_TAMPCR_TAMP2TRG_Msk
#define	RTC_TAMPCR_TAMP2E_Pos   (3U)
#define	RTC_TAMPCR_TAMP2E_Msk   (0x1UL << RTC_TAMPCR_TAMP2E_Pos)
	0x00000008
#define	RTC_TAMPCR_TAMP2E   RTC_TAMPCR_TAMP2E_Msk
#define	RTC_ALRMASSR_MASKSS_Pos   (24U)
#define	RTC_ALRMASSR_MASKSS_Msk   (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
	0x0F000000
#define	RTC_ALRMASSR_MASKSS   RTC_ALRMASSR_MASKSS_Msk
#define	RTC_ALRMASSR_MASKSS_0   (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
	0x01000000
#define	RTC_ALRMASSR_MASKSS_1   (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
	0x02000000
#define	RTC_ALRMASSR_MASKSS_2   (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
	0x04000000
#define	RTC_ALRMASSR_MASKSS_3   (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
	0x08000000
#define	RTC_ALRMASSR_SS_Pos   (0U)
#define	RTC_ALRMASSR_SS_Msk   (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
	0x00007FFF
#define	RTC_ALRMASSR_SS   RTC_ALRMASSR_SS_Msk
#define	RTC_ALRMBSSR_MASKSS_Pos   (24U)
#define	RTC_ALRMBSSR_MASKSS_Msk   (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
	0x0F000000
#define	RTC_ALRMBSSR_MASKSS   RTC_ALRMBSSR_MASKSS_Msk
#define	RTC_ALRMBSSR_MASKSS_0   (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
	0x01000000
#define	RTC_ALRMBSSR_MASKSS_1   (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
	0x02000000
#define	RTC_ALRMBSSR_MASKSS_2   (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
	0x04000000
#define	RTC_ALRMBSSR_MASKSS_3   (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
	0x08000000
#define	RTC_ALRMBSSR_SS_Pos   (0U)
#define	RTC_ALRMBSSR_SS_Msk   (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
	0x00007FFF
#define	RTC_ALRMBSSR_SS   RTC_ALRMBSSR_SS_Msk
#define	RTC_OR_OUT_RMP_Pos   (1U)
#define	RTC_OR_OUT_RMP_Msk   (0x1UL << RTC_OR_OUT_RMP_Pos)
	0x00000002
#define	RTC_OR_OUT_RMP   RTC_OR_OUT_RMP_Msk
#define	RTC_OR_ALARMOUTTYPE_Pos   (0U)
#define	RTC_OR_ALARMOUTTYPE_Msk   (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)
	0x00000001
#define	RTC_OR_ALARMOUTTYPE   RTC_OR_ALARMOUTTYPE_Msk
#define	RTC_BKP0R_Pos   (0U)
#define	RTC_BKP0R_Msk   (0xFFFFFFFFUL << RTC_BKP0R_Pos)
	0xFFFFFFFF
#define	RTC_BKP0R   RTC_BKP0R_Msk
#define	RTC_BKP1R_Pos   (0U)
#define	RTC_BKP1R_Msk   (0xFFFFFFFFUL << RTC_BKP1R_Pos)
	0xFFFFFFFF
#define	RTC_BKP1R   RTC_BKP1R_Msk
#define	RTC_BKP2R_Pos   (0U)
#define	RTC_BKP2R_Msk   (0xFFFFFFFFUL << RTC_BKP2R_Pos)
	0xFFFFFFFF
#define	RTC_BKP2R   RTC_BKP2R_Msk
#define	RTC_BKP3R_Pos   (0U)
#define	RTC_BKP3R_Msk   (0xFFFFFFFFUL << RTC_BKP3R_Pos)
	0xFFFFFFFF
#define	RTC_BKP3R   RTC_BKP3R_Msk
#define	RTC_BKP4R_Pos   (0U)
#define	RTC_BKP4R_Msk   (0xFFFFFFFFUL << RTC_BKP4R_Pos)
	0xFFFFFFFF
#define	RTC_BKP4R   RTC_BKP4R_Msk
#define	RTC_BKP5R_Pos   (0U)
#define	RTC_BKP5R_Msk   (0xFFFFFFFFUL << RTC_BKP5R_Pos)
	0xFFFFFFFF
#define	RTC_BKP5R   RTC_BKP5R_Msk
#define	RTC_BKP6R_Pos   (0U)
#define	RTC_BKP6R_Msk   (0xFFFFFFFFUL << RTC_BKP6R_Pos)
	0xFFFFFFFF
#define	RTC_BKP6R   RTC_BKP6R_Msk
#define	RTC_BKP7R_Pos   (0U)
#define	RTC_BKP7R_Msk   (0xFFFFFFFFUL << RTC_BKP7R_Pos)
	0xFFFFFFFF
#define	RTC_BKP7R   RTC_BKP7R_Msk
#define	RTC_BKP8R_Pos   (0U)
#define	RTC_BKP8R_Msk   (0xFFFFFFFFUL << RTC_BKP8R_Pos)
	0xFFFFFFFF
#define	RTC_BKP8R   RTC_BKP8R_Msk
#define	RTC_BKP9R_Pos   (0U)
#define	RTC_BKP9R_Msk   (0xFFFFFFFFUL << RTC_BKP9R_Pos)
	0xFFFFFFFF
#define	RTC_BKP9R   RTC_BKP9R_Msk
#define	RTC_BKP10R_Pos   (0U)
#define	RTC_BKP10R_Msk   (0xFFFFFFFFUL << RTC_BKP10R_Pos)
	0xFFFFFFFF
#define	RTC_BKP10R   RTC_BKP10R_Msk
#define	RTC_BKP11R_Pos   (0U)
#define	RTC_BKP11R_Msk   (0xFFFFFFFFUL << RTC_BKP11R_Pos)
	0xFFFFFFFF
#define	RTC_BKP11R   RTC_BKP11R_Msk
#define	RTC_BKP12R_Pos   (0U)
#define	RTC_BKP12R_Msk   (0xFFFFFFFFUL << RTC_BKP12R_Pos)
	0xFFFFFFFF
#define	RTC_BKP12R   RTC_BKP12R_Msk
#define	RTC_BKP13R_Pos   (0U)
#define	RTC_BKP13R_Msk   (0xFFFFFFFFUL << RTC_BKP13R_Pos)
	0xFFFFFFFF
#define	RTC_BKP13R   RTC_BKP13R_Msk
#define	RTC_BKP14R_Pos   (0U)
#define	RTC_BKP14R_Msk   (0xFFFFFFFFUL << RTC_BKP14R_Pos)
	0xFFFFFFFF
#define	RTC_BKP14R   RTC_BKP14R_Msk
#define	RTC_BKP15R_Pos   (0U)
#define	RTC_BKP15R_Msk   (0xFFFFFFFFUL << RTC_BKP15R_Pos)
	0xFFFFFFFF
#define	RTC_BKP15R   RTC_BKP15R_Msk
#define	RTC_BKP16R_Pos   (0U)
#define	RTC_BKP16R_Msk   (0xFFFFFFFFUL << RTC_BKP16R_Pos)
	0xFFFFFFFF
#define	RTC_BKP16R   RTC_BKP16R_Msk
#define	RTC_BKP17R_Pos   (0U)
#define	RTC_BKP17R_Msk   (0xFFFFFFFFUL << RTC_BKP17R_Pos)
	0xFFFFFFFF
#define	RTC_BKP17R   RTC_BKP17R_Msk
#define	RTC_BKP18R_Pos   (0U)
#define	RTC_BKP18R_Msk   (0xFFFFFFFFUL << RTC_BKP18R_Pos)
	0xFFFFFFFF
#define	RTC_BKP18R   RTC_BKP18R_Msk
#define	RTC_BKP19R_Pos   (0U)
#define	RTC_BKP19R_Msk   (0xFFFFFFFFUL << RTC_BKP19R_Pos)
	0xFFFFFFFF
#define	RTC_BKP19R   RTC_BKP19R_Msk
#define	RTC_BKP20R_Pos   (0U)
#define	RTC_BKP20R_Msk   (0xFFFFFFFFUL << RTC_BKP20R_Pos)
	0xFFFFFFFF
#define	RTC_BKP20R   RTC_BKP20R_Msk
#define	RTC_BKP21R_Pos   (0U)
#define	RTC_BKP21R_Msk   (0xFFFFFFFFUL << RTC_BKP21R_Pos)
	0xFFFFFFFF
#define	RTC_BKP21R   RTC_BKP21R_Msk
#define	RTC_BKP22R_Pos   (0U)
#define	RTC_BKP22R_Msk   (0xFFFFFFFFUL << RTC_BKP22R_Pos)
	0xFFFFFFFF
#define	RTC_BKP22R   RTC_BKP22R_Msk
#define	RTC_BKP23R_Pos   (0U)
#define	RTC_BKP23R_Msk   (0xFFFFFFFFUL << RTC_BKP23R_Pos)
	0xFFFFFFFF
#define	RTC_BKP23R   RTC_BKP23R_Msk
#define	RTC_BKP24R_Pos   (0U)
#define	RTC_BKP24R_Msk   (0xFFFFFFFFUL << RTC_BKP24R_Pos)
	0xFFFFFFFF
#define	RTC_BKP24R   RTC_BKP24R_Msk
#define	RTC_BKP25R_Pos   (0U)
#define	RTC_BKP25R_Msk   (0xFFFFFFFFUL << RTC_BKP25R_Pos)
	0xFFFFFFFF
#define	RTC_BKP25R   RTC_BKP25R_Msk
#define	RTC_BKP26R_Pos   (0U)
#define	RTC_BKP26R_Msk   (0xFFFFFFFFUL << RTC_BKP26R_Pos)
	0xFFFFFFFF
#define	RTC_BKP26R   RTC_BKP26R_Msk
#define	RTC_BKP27R_Pos   (0U)
#define	RTC_BKP27R_Msk   (0xFFFFFFFFUL << RTC_BKP27R_Pos)
	0xFFFFFFFF
#define	RTC_BKP27R   RTC_BKP27R_Msk
#define	RTC_BKP28R_Pos   (0U)
#define	RTC_BKP28R_Msk   (0xFFFFFFFFUL << RTC_BKP28R_Pos)
	0xFFFFFFFF
#define	RTC_BKP28R   RTC_BKP28R_Msk
#define	RTC_BKP29R_Pos   (0U)
#define	RTC_BKP29R_Msk   (0xFFFFFFFFUL << RTC_BKP29R_Pos)
	0xFFFFFFFF
#define	RTC_BKP29R   RTC_BKP29R_Msk
#define	RTC_BKP30R_Pos   (0U)
#define	RTC_BKP30R_Msk   (0xFFFFFFFFUL << RTC_BKP30R_Pos)
	0xFFFFFFFF
#define	RTC_BKP30R   RTC_BKP30R_Msk
#define	RTC_BKP31R_Pos   (0U)
#define	RTC_BKP31R_Msk   (0xFFFFFFFFUL << RTC_BKP31R_Pos)
	0xFFFFFFFF
#define	RTC_BKP31R   RTC_BKP31R_Msk
#define	RTC_BKP_NUMBER_Pos   (5U)
#define	RTC_BKP_NUMBER_Msk   (0x1UL << RTC_BKP_NUMBER_Pos)
	0x00000020
#define	RTC_BKP_NUMBER   RTC_BKP_NUMBER_Msk
#define	SPDIFRX_CR_SPDIFEN_Pos   (0U)
#define	SPDIFRX_CR_SPDIFEN_Msk   (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)
	0x00000003
#define	SPDIFRX_CR_SPDIFEN   SPDIFRX_CR_SPDIFEN_Msk
	Peripheral Block Enable.
#define	SPDIFRX_CR_RXDMAEN_Pos   (2U)
#define	SPDIFRX_CR_RXDMAEN_Msk   (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)
	0x00000004
#define	SPDIFRX_CR_RXDMAEN   SPDIFRX_CR_RXDMAEN_Msk
	Receiver DMA Enable for data flow.
#define	SPDIFRX_CR_RXSTEO_Pos   (3U)
#define	SPDIFRX_CR_RXSTEO_Msk   (0x1UL << SPDIFRX_CR_RXSTEO_Pos)
	0x00000008
#define	SPDIFRX_CR_RXSTEO   SPDIFRX_CR_RXSTEO_Msk
	Stereo Mode.
#define	SPDIFRX_CR_DRFMT_Pos   (4U)
#define	SPDIFRX_CR_DRFMT_Msk   (0x3UL << SPDIFRX_CR_DRFMT_Pos)
	0x00000030
#define	SPDIFRX_CR_DRFMT   SPDIFRX_CR_DRFMT_Msk
	RX Data format.
#define	SPDIFRX_CR_PMSK_Pos   (6U)
#define	SPDIFRX_CR_PMSK_Msk   (0x1UL << SPDIFRX_CR_PMSK_Pos)
	0x00000040
#define	SPDIFRX_CR_PMSK   SPDIFRX_CR_PMSK_Msk
	Mask Parity error bit.
#define	SPDIFRX_CR_VMSK_Pos   (7U)
#define	SPDIFRX_CR_VMSK_Msk   (0x1UL << SPDIFRX_CR_VMSK_Pos)
	0x00000080
#define	SPDIFRX_CR_VMSK   SPDIFRX_CR_VMSK_Msk
	Mask of Validity bit.
#define	SPDIFRX_CR_CUMSK_Pos   (8U)
#define	SPDIFRX_CR_CUMSK_Msk   (0x1UL << SPDIFRX_CR_CUMSK_Pos)
	0x00000100
#define	SPDIFRX_CR_CUMSK   SPDIFRX_CR_CUMSK_Msk
	Mask of channel status and user bits.
#define	SPDIFRX_CR_PTMSK_Pos   (9U)
#define	SPDIFRX_CR_PTMSK_Msk   (0x1UL << SPDIFRX_CR_PTMSK_Pos)
	0x00000200
#define	SPDIFRX_CR_PTMSK   SPDIFRX_CR_PTMSK_Msk
	Mask of Preamble Type bits.
#define	SPDIFRX_CR_CBDMAEN_Pos   (10U)
#define	SPDIFRX_CR_CBDMAEN_Msk   (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)
	0x00000400
#define	SPDIFRX_CR_CBDMAEN   SPDIFRX_CR_CBDMAEN_Msk
	Control Buffer DMA ENable for control flow.
#define	SPDIFRX_CR_CHSEL_Pos   (11U)
#define	SPDIFRX_CR_CHSEL_Msk   (0x1UL << SPDIFRX_CR_CHSEL_Pos)
	0x00000800
#define	SPDIFRX_CR_CHSEL   SPDIFRX_CR_CHSEL_Msk
	Channel Selection.
#define	SPDIFRX_CR_NBTR_Pos   (12U)
#define	SPDIFRX_CR_NBTR_Msk   (0x3UL << SPDIFRX_CR_NBTR_Pos)
	0x00003000
#define	SPDIFRX_CR_NBTR   SPDIFRX_CR_NBTR_Msk
	Maximum allowed re-tries during synchronization phase.
#define	SPDIFRX_CR_WFA_Pos   (14U)
#define	SPDIFRX_CR_WFA_Msk   (0x1UL << SPDIFRX_CR_WFA_Pos)
	0x00004000
#define	SPDIFRX_CR_WFA   SPDIFRX_CR_WFA_Msk
	Wait For Activity.
#define	SPDIFRX_CR_INSEL_Pos   (16U)
#define	SPDIFRX_CR_INSEL_Msk   (0x7UL << SPDIFRX_CR_INSEL_Pos)
	0x00070000
#define	SPDIFRX_CR_INSEL   SPDIFRX_CR_INSEL_Msk
	SPDIF input selection.
#define	SPDIFRX_CR_CKSEN_Pos   (20U)
#define	SPDIFRX_CR_CKSEN_Msk   (0x1UL << SPDIFRX_CR_CKSEN_Pos)
	0x00100000
#define	SPDIFRX_CR_CKSEN   SPDIFRX_CR_CKSEN_Msk
	Symbol Clock Enable.
#define	SPDIFRX_CR_CKSBKPEN_Pos   (21U)
#define	SPDIFRX_CR_CKSBKPEN_Msk   (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)
	0x00200000
#define	SPDIFRX_CR_CKSBKPEN   SPDIFRX_CR_CKSBKPEN_Msk
	Backup Symbol Clock Enable.
#define	SPDIFRX_IMR_RXNEIE_Pos   (0U)
#define	SPDIFRX_IMR_RXNEIE_Msk   (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)
	0x00000001
#define	SPDIFRX_IMR_RXNEIE   SPDIFRX_IMR_RXNEIE_Msk
	RXNE interrupt enable.
#define	SPDIFRX_IMR_CSRNEIE_Pos   (1U)
#define	SPDIFRX_IMR_CSRNEIE_Msk   (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)
	0x00000002
#define	SPDIFRX_IMR_CSRNEIE   SPDIFRX_IMR_CSRNEIE_Msk
	Control Buffer Ready Interrupt Enable.
#define	SPDIFRX_IMR_PERRIE_Pos   (2U)
#define	SPDIFRX_IMR_PERRIE_Msk   (0x1UL << SPDIFRX_IMR_PERRIE_Pos)
	0x00000004
#define	SPDIFRX_IMR_PERRIE   SPDIFRX_IMR_PERRIE_Msk
	Parity error interrupt enable.
#define	SPDIFRX_IMR_OVRIE_Pos   (3U)
#define	SPDIFRX_IMR_OVRIE_Msk   (0x1UL << SPDIFRX_IMR_OVRIE_Pos)
	0x00000008
#define	SPDIFRX_IMR_OVRIE   SPDIFRX_IMR_OVRIE_Msk
	Overrun error Interrupt Enable.
#define	SPDIFRX_IMR_SBLKIE_Pos   (4U)
#define	SPDIFRX_IMR_SBLKIE_Msk   (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)
	0x00000010
#define	SPDIFRX_IMR_SBLKIE   SPDIFRX_IMR_SBLKIE_Msk
	Synchronization Block Detected Interrupt Enable.
#define	SPDIFRX_IMR_SYNCDIE_Pos   (5U)
#define	SPDIFRX_IMR_SYNCDIE_Msk   (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)
	0x00000020
#define	SPDIFRX_IMR_SYNCDIE   SPDIFRX_IMR_SYNCDIE_Msk
	Synchronization Done.
#define	SPDIFRX_IMR_IFEIE_Pos   (6U)
#define	SPDIFRX_IMR_IFEIE_Msk   (0x1UL << SPDIFRX_IMR_IFEIE_Pos)
	0x00000040
#define	SPDIFRX_IMR_IFEIE   SPDIFRX_IMR_IFEIE_Msk
	Serial Interface Error Interrupt Enable.
#define	SPDIFRX_SR_RXNE_Pos   (0U)
#define	SPDIFRX_SR_RXNE_Msk   (0x1UL << SPDIFRX_SR_RXNE_Pos)
	0x00000001
#define	SPDIFRX_SR_RXNE   SPDIFRX_SR_RXNE_Msk
	Read data register not empty.
#define	SPDIFRX_SR_CSRNE_Pos   (1U)
#define	SPDIFRX_SR_CSRNE_Msk   (0x1UL << SPDIFRX_SR_CSRNE_Pos)
	0x00000002
#define	SPDIFRX_SR_CSRNE   SPDIFRX_SR_CSRNE_Msk
	The Control Buffer register is not empty.
#define	SPDIFRX_SR_PERR_Pos   (2U)
#define	SPDIFRX_SR_PERR_Msk   (0x1UL << SPDIFRX_SR_PERR_Pos)
	0x00000004
#define	SPDIFRX_SR_PERR   SPDIFRX_SR_PERR_Msk
	Parity error.
#define	SPDIFRX_SR_OVR_Pos   (3U)
#define	SPDIFRX_SR_OVR_Msk   (0x1UL << SPDIFRX_SR_OVR_Pos)
	0x00000008
#define	SPDIFRX_SR_OVR   SPDIFRX_SR_OVR_Msk
	Overrun error.
#define	SPDIFRX_SR_SBD_Pos   (4U)
#define	SPDIFRX_SR_SBD_Msk   (0x1UL << SPDIFRX_SR_SBD_Pos)
	0x00000010
#define	SPDIFRX_SR_SBD   SPDIFRX_SR_SBD_Msk
	Synchronization Block Detected.
#define	SPDIFRX_SR_SYNCD_Pos   (5U)
#define	SPDIFRX_SR_SYNCD_Msk   (0x1UL << SPDIFRX_SR_SYNCD_Pos)
	0x00000020
#define	SPDIFRX_SR_SYNCD   SPDIFRX_SR_SYNCD_Msk
	Synchronization Done.
#define	SPDIFRX_SR_FERR_Pos   (6U)
#define	SPDIFRX_SR_FERR_Msk   (0x1UL << SPDIFRX_SR_FERR_Pos)
	0x00000040
#define	SPDIFRX_SR_FERR   SPDIFRX_SR_FERR_Msk
	Framing error.
#define	SPDIFRX_SR_SERR_Pos   (7U)
#define	SPDIFRX_SR_SERR_Msk   (0x1UL << SPDIFRX_SR_SERR_Pos)
	0x00000080
#define	SPDIFRX_SR_SERR   SPDIFRX_SR_SERR_Msk
	Synchronization error.
#define	SPDIFRX_SR_TERR_Pos   (8U)
#define	SPDIFRX_SR_TERR_Msk   (0x1UL << SPDIFRX_SR_TERR_Pos)
	0x00000100
#define	SPDIFRX_SR_TERR   SPDIFRX_SR_TERR_Msk
	Time-out error.
#define	SPDIFRX_SR_WIDTH5_Pos   (16U)
#define	SPDIFRX_SR_WIDTH5_Msk   (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)
	0x7FFF0000
#define	SPDIFRX_SR_WIDTH5   SPDIFRX_SR_WIDTH5_Msk
	Duration of 5 symbols counted with spdif_clk.
#define	SPDIFRX_IFCR_PERRCF_Pos   (2U)
#define	SPDIFRX_IFCR_PERRCF_Msk   (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)
	0x00000004
#define	SPDIFRX_IFCR_PERRCF   SPDIFRX_IFCR_PERRCF_Msk
	Clears the Parity error flag.
#define	SPDIFRX_IFCR_OVRCF_Pos   (3U)
#define	SPDIFRX_IFCR_OVRCF_Msk   (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)
	0x00000008
#define	SPDIFRX_IFCR_OVRCF   SPDIFRX_IFCR_OVRCF_Msk
	Clears the Overrun error flag.
#define	SPDIFRX_IFCR_SBDCF_Pos   (4U)
#define	SPDIFRX_IFCR_SBDCF_Msk   (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)
	0x00000010
#define	SPDIFRX_IFCR_SBDCF   SPDIFRX_IFCR_SBDCF_Msk
	Clears the Synchronization Block Detected flag.
#define	SPDIFRX_IFCR_SYNCDCF_Pos   (5U)
#define	SPDIFRX_IFCR_SYNCDCF_Msk   (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)
	0x00000020
#define	SPDIFRX_IFCR_SYNCDCF   SPDIFRX_IFCR_SYNCDCF_Msk
	Clears the Synchronization Done flag.
#define	SPDIFRX_DR0_DR_Pos   (0U)
#define	SPDIFRX_DR0_DR_Msk   (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)
	0x00FFFFFF
#define	SPDIFRX_DR0_DR   SPDIFRX_DR0_DR_Msk
	Data value.
#define	SPDIFRX_DR0_PE_Pos   (24U)
#define	SPDIFRX_DR0_PE_Msk   (0x1UL << SPDIFRX_DR0_PE_Pos)
	0x01000000
#define	SPDIFRX_DR0_PE   SPDIFRX_DR0_PE_Msk
	Parity Error bit.
#define	SPDIFRX_DR0_V_Pos   (25U)
#define	SPDIFRX_DR0_V_Msk   (0x1UL << SPDIFRX_DR0_V_Pos)
	0x02000000
#define	SPDIFRX_DR0_V   SPDIFRX_DR0_V_Msk
	Validity bit.
#define	SPDIFRX_DR0_U_Pos   (26U)
#define	SPDIFRX_DR0_U_Msk   (0x1UL << SPDIFRX_DR0_U_Pos)
	0x04000000
#define	SPDIFRX_DR0_U   SPDIFRX_DR0_U_Msk
	User bit.
#define	SPDIFRX_DR0_C_Pos   (27U)
#define	SPDIFRX_DR0_C_Msk   (0x1UL << SPDIFRX_DR0_C_Pos)
	0x08000000
#define	SPDIFRX_DR0_C   SPDIFRX_DR0_C_Msk
	Channel Status bit.
#define	SPDIFRX_DR0_PT_Pos   (28U)
#define	SPDIFRX_DR0_PT_Msk   (0x3UL << SPDIFRX_DR0_PT_Pos)
	0x30000000
#define	SPDIFRX_DR0_PT   SPDIFRX_DR0_PT_Msk
	Preamble Type.
#define	SPDIFRX_DR1_DR_Pos   (8U)
#define	SPDIFRX_DR1_DR_Msk   (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)
	0xFFFFFF00
#define	SPDIFRX_DR1_DR   SPDIFRX_DR1_DR_Msk
	Data value.
#define	SPDIFRX_DR1_PT_Pos   (4U)
#define	SPDIFRX_DR1_PT_Msk   (0x3UL << SPDIFRX_DR1_PT_Pos)
	0x00000030
#define	SPDIFRX_DR1_PT   SPDIFRX_DR1_PT_Msk
	Preamble Type.
#define	SPDIFRX_DR1_C_Pos   (3U)
#define	SPDIFRX_DR1_C_Msk   (0x1UL << SPDIFRX_DR1_C_Pos)
	0x00000008
#define	SPDIFRX_DR1_C   SPDIFRX_DR1_C_Msk
	Channel Status bit.
#define	SPDIFRX_DR1_U_Pos   (2U)
#define	SPDIFRX_DR1_U_Msk   (0x1UL << SPDIFRX_DR1_U_Pos)
	0x00000004
#define	SPDIFRX_DR1_U   SPDIFRX_DR1_U_Msk
	User bit.
#define	SPDIFRX_DR1_V_Pos   (1U)
#define	SPDIFRX_DR1_V_Msk   (0x1UL << SPDIFRX_DR1_V_Pos)
	0x00000002
#define	SPDIFRX_DR1_V   SPDIFRX_DR1_V_Msk
	Validity bit.
#define	SPDIFRX_DR1_PE_Pos   (0U)
#define	SPDIFRX_DR1_PE_Msk   (0x1UL << SPDIFRX_DR1_PE_Pos)
	0x00000001
#define	SPDIFRX_DR1_PE   SPDIFRX_DR1_PE_Msk
	Parity Error bit.
#define	SPDIFRX_DR1_DRNL1_Pos   (16U)
#define	SPDIFRX_DR1_DRNL1_Msk   (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)
	0xFFFF0000
#define	SPDIFRX_DR1_DRNL1   SPDIFRX_DR1_DRNL1_Msk
	Data value Channel B.
#define	SPDIFRX_DR1_DRNL2_Pos   (0U)
#define	SPDIFRX_DR1_DRNL2_Msk   (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)
	0x0000FFFF
#define	SPDIFRX_DR1_DRNL2   SPDIFRX_DR1_DRNL2_Msk
	Data value Channel A.
#define	SPDIFRX_CSR_USR_Pos   (0U)
#define	SPDIFRX_CSR_USR_Msk   (0xFFFFUL << SPDIFRX_CSR_USR_Pos)
	0x0000FFFF
#define	SPDIFRX_CSR_USR   SPDIFRX_CSR_USR_Msk
	User data information.
#define	SPDIFRX_CSR_CS_Pos   (16U)
#define	SPDIFRX_CSR_CS_Msk   (0xFFUL << SPDIFRX_CSR_CS_Pos)
	0x00FF0000
#define	SPDIFRX_CSR_CS   SPDIFRX_CSR_CS_Msk
	Channel A status information.
#define	SPDIFRX_CSR_SOB_Pos   (24U)
#define	SPDIFRX_CSR_SOB_Msk   (0x1UL << SPDIFRX_CSR_SOB_Pos)
	0x01000000
#define	SPDIFRX_CSR_SOB   SPDIFRX_CSR_SOB_Msk
	Start Of Block.
#define	SPDIFRX_DIR_THI_Pos   (0U)
#define	SPDIFRX_DIR_THI_Msk   (0x1FFFUL << SPDIFRX_DIR_THI_Pos)
	0x00001FFF
#define	SPDIFRX_DIR_THI   SPDIFRX_DIR_THI_Msk
	Threshold LOW.
#define	SPDIFRX_DIR_TLO_Pos   (16U)
#define	SPDIFRX_DIR_TLO_Msk   (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)
	0x1FFF0000
#define	SPDIFRX_DIR_TLO   SPDIFRX_DIR_TLO_Msk
	Threshold HIGH.
#define	SPDIFRX_VERR_MINREV_Pos   (0U)
#define	SPDIFRX_VERR_MINREV_Msk   (0xFUL << SPDIFRX_VERR_MINREV_Pos)
	0x0000000F
#define	SPDIFRX_VERR_MINREV   SPDIFRX_VERR_MINREV_Msk
	SPDIFRX Minor revision.
#define	SPDIFRX_VERR_MAJREV_Pos   (4U)
#define	SPDIFRX_VERR_MAJREV_Msk   (0xFUL << SPDIFRX_VERR_MAJREV_Pos)
	0x000000F0
#define	SPDIFRX_VERR_MAJREV   SPDIFRX_VERR_MAJREV_Msk
	SPDIFRX Major revision.
#define	SPDIFRX_IDR_ID_Pos   (0U)
#define	SPDIFRX_IDR_ID_Msk   (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)
	0xFFFFFFFF
#define	SPDIFRX_IDR_ID   SPDIFRX_IDR_ID_Msk
	SPDIFRX identifier.
#define	SPDIFRX_SIDR_SID_Pos   (0U)
#define	SPDIFRX_SIDR_SID_Msk   (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)
	0xFFFFFFFF
#define	SPDIFRX_SIDR_SID   SPDIFRX_SIDR_SID_Msk
	Size of the memory region allocated to SPDIFRX registers.
#define	SAI_VER_V2_1
#define	SAI_GCR_SYNCIN_Pos   (0U)
#define	SAI_GCR_SYNCIN_Msk   (0x3UL << SAI_GCR_SYNCIN_Pos)
	0x00000003
#define	SAI_GCR_SYNCIN   SAI_GCR_SYNCIN_Msk
	SYNCIN[1:0] bits (Synchronization Inputs).
#define	SAI_GCR_SYNCIN_0   (0x1UL << SAI_GCR_SYNCIN_Pos)
	0x00000001
#define	SAI_GCR_SYNCIN_1   (0x2UL << SAI_GCR_SYNCIN_Pos)
	0x00000002
#define	SAI_GCR_SYNCOUT_Pos   (4U)
#define	SAI_GCR_SYNCOUT_Msk   (0x3UL << SAI_GCR_SYNCOUT_Pos)
	0x00000030
#define	SAI_GCR_SYNCOUT   SAI_GCR_SYNCOUT_Msk
	SYNCOUT[1:0] bits (Synchronization Outputs).
#define	SAI_GCR_SYNCOUT_0   (0x1UL << SAI_GCR_SYNCOUT_Pos)
	0x00000010
#define	SAI_GCR_SYNCOUT_1   (0x2UL << SAI_GCR_SYNCOUT_Pos)
	0x00000020
#define	SAI_xCR1_MODE_Pos   (0U)
#define	SAI_xCR1_MODE_Msk   (0x3UL << SAI_xCR1_MODE_Pos)
	0x00000003
#define	SAI_xCR1_MODE   SAI_xCR1_MODE_Msk
	MODE[1:0] bits (Audio Block Mode).
#define	SAI_xCR1_MODE_0   (0x1UL << SAI_xCR1_MODE_Pos)
	0x00000001
#define	SAI_xCR1_MODE_1   (0x2UL << SAI_xCR1_MODE_Pos)
	0x00000002
#define	SAI_xCR1_PRTCFG_Pos   (2U)
#define	SAI_xCR1_PRTCFG_Msk   (0x3UL << SAI_xCR1_PRTCFG_Pos)
	0x0000000C
#define	SAI_xCR1_PRTCFG   SAI_xCR1_PRTCFG_Msk
	PRTCFG[1:0] bits (Protocol Configuration).
#define	SAI_xCR1_PRTCFG_0   (0x1UL << SAI_xCR1_PRTCFG_Pos)
	0x00000004
#define	SAI_xCR1_PRTCFG_1   (0x2UL << SAI_xCR1_PRTCFG_Pos)
	0x00000008
#define	SAI_xCR1_DS_Pos   (5U)
#define	SAI_xCR1_DS_Msk   (0x7UL << SAI_xCR1_DS_Pos)
	0x000000E0
#define	SAI_xCR1_DS   SAI_xCR1_DS_Msk
	DS[1:0] bits (Data Size).
#define	SAI_xCR1_DS_0   (0x1UL << SAI_xCR1_DS_Pos)
	0x00000020
#define	SAI_xCR1_DS_1   (0x2UL << SAI_xCR1_DS_Pos)
	0x00000040
#define	SAI_xCR1_DS_2   (0x4UL << SAI_xCR1_DS_Pos)
	0x00000080
#define	SAI_xCR1_LSBFIRST_Pos   (8U)
#define	SAI_xCR1_LSBFIRST_Msk   (0x1UL << SAI_xCR1_LSBFIRST_Pos)
	0x00000100
#define	SAI_xCR1_LSBFIRST   SAI_xCR1_LSBFIRST_Msk
	LSB First Configuration.
#define	SAI_xCR1_CKSTR_Pos   (9U)
#define	SAI_xCR1_CKSTR_Msk   (0x1UL << SAI_xCR1_CKSTR_Pos)
	0x00000200
#define	SAI_xCR1_CKSTR   SAI_xCR1_CKSTR_Msk
	ClocK STRobing edge.
#define	SAI_xCR1_SYNCEN_Pos   (10U)
#define	SAI_xCR1_SYNCEN_Msk   (0x3UL << SAI_xCR1_SYNCEN_Pos)
	0x00000C00
#define	SAI_xCR1_SYNCEN   SAI_xCR1_SYNCEN_Msk
	SYNCEN[1:0](SYNChronization ENable).
#define	SAI_xCR1_SYNCEN_0   (0x1UL << SAI_xCR1_SYNCEN_Pos)
	0x00000400
#define	SAI_xCR1_SYNCEN_1   (0x2UL << SAI_xCR1_SYNCEN_Pos)
	0x00000800
#define	SAI_xCR1_MONO_Pos   (12U)
#define	SAI_xCR1_MONO_Msk   (0x1UL << SAI_xCR1_MONO_Pos)
	0x00001000
#define	SAI_xCR1_MONO   SAI_xCR1_MONO_Msk
	Mono mode.
#define	SAI_xCR1_OUTDRIV_Pos   (13U)
#define	SAI_xCR1_OUTDRIV_Msk   (0x1UL << SAI_xCR1_OUTDRIV_Pos)
	0x00002000
#define	SAI_xCR1_OUTDRIV   SAI_xCR1_OUTDRIV_Msk
	Output Drive.
#define	SAI_xCR1_SAIEN_Pos   (16U)
#define	SAI_xCR1_SAIEN_Msk   (0x1UL << SAI_xCR1_SAIEN_Pos)
	0x00010000
#define	SAI_xCR1_SAIEN   SAI_xCR1_SAIEN_Msk
	Audio Block enable.
#define	SAI_xCR1_DMAEN_Pos   (17U)
#define	SAI_xCR1_DMAEN_Msk   (0x1UL << SAI_xCR1_DMAEN_Pos)
	0x00020000
#define	SAI_xCR1_DMAEN   SAI_xCR1_DMAEN_Msk
	DMA enable.
#define	SAI_xCR1_NODIV_Pos   (19U)
#define	SAI_xCR1_NODIV_Msk   (0x1UL << SAI_xCR1_NODIV_Pos)
	0x00080000
#define	SAI_xCR1_NODIV   SAI_xCR1_NODIV_Msk
	No Divider Configuration.
#define	SAI_xCR1_MCKDIV_Pos   (20U)
#define	SAI_xCR1_MCKDIV_Msk   (0x3FUL << SAI_xCR1_MCKDIV_Pos)
	0x03F00000
#define	SAI_xCR1_MCKDIV   SAI_xCR1_MCKDIV_Msk
	MCKDIV[5:0] (Master ClocK Divider).
#define	SAI_xCR1_MCKDIV_0   (0x01UL << SAI_xCR1_MCKDIV_Pos)
	0x00100000
#define	SAI_xCR1_MCKDIV_1   (0x02UL << SAI_xCR1_MCKDIV_Pos)
	0x00200000
#define	SAI_xCR1_MCKDIV_2   (0x04UL << SAI_xCR1_MCKDIV_Pos)
	0x00400000
#define	SAI_xCR1_MCKDIV_3   (0x08UL << SAI_xCR1_MCKDIV_Pos)
	0x00800000
#define	SAI_xCR1_MCKDIV_4   (0x10UL << SAI_xCR1_MCKDIV_Pos)
	0x01000000
#define	SAI_xCR1_MCKDIV_5   (0x20UL << SAI_xCR1_MCKDIV_Pos)
	0x02000000
#define	SAI_xCR1_MCKEN_Pos   (27U)
#define	SAI_xCR1_MCKEN_Msk   (0x1UL << SAI_xCR1_MCKEN_Pos)
	0x08000000
#define	SAI_xCR1_MCKEN   SAI_xCR1_MCKEN_Msk
	Master ClocK enable.
#define	SAI_xCR1_OSR_Pos   (26U)
#define	SAI_xCR1_OSR_Msk   (0x1UL << SAI_xCR1_OSR_Pos)
	0x04000000
#define	SAI_xCR1_OSR   SAI_xCR1_OSR_Msk
	OverSampling Ratio for master clock.
#define	SAI_xCR1_NOMCK   SAI_xCR1_NODIV
#define	SAI_xCR2_FTH_Pos   (0U)
#define	SAI_xCR2_FTH_Msk   (0x7UL << SAI_xCR2_FTH_Pos)
	0x00000007
#define	SAI_xCR2_FTH   SAI_xCR2_FTH_Msk
	FTH[2:0](Fifo THreshold).
#define	SAI_xCR2_FTH_0   (0x1UL << SAI_xCR2_FTH_Pos)
	0x00000001
#define	SAI_xCR2_FTH_1   (0x2UL << SAI_xCR2_FTH_Pos)
	0x00000002
#define	SAI_xCR2_FTH_2   (0x4UL << SAI_xCR2_FTH_Pos)
	0x00000004
#define	SAI_xCR2_FFLUSH_Pos   (3U)
#define	SAI_xCR2_FFLUSH_Msk   (0x1UL << SAI_xCR2_FFLUSH_Pos)
	0x00000008
#define	SAI_xCR2_FFLUSH   SAI_xCR2_FFLUSH_Msk
	Fifo FLUSH.
#define	SAI_xCR2_TRIS_Pos   (4U)
#define	SAI_xCR2_TRIS_Msk   (0x1UL << SAI_xCR2_TRIS_Pos)
	0x00000010
#define	SAI_xCR2_TRIS   SAI_xCR2_TRIS_Msk
	TRIState Management on data line.
#define	SAI_xCR2_MUTE_Pos   (5U)
#define	SAI_xCR2_MUTE_Msk   (0x1UL << SAI_xCR2_MUTE_Pos)
	0x00000020
#define	SAI_xCR2_MUTE   SAI_xCR2_MUTE_Msk
	Mute mode.
#define	SAI_xCR2_MUTEVAL_Pos   (6U)
#define	SAI_xCR2_MUTEVAL_Msk   (0x1UL << SAI_xCR2_MUTEVAL_Pos)
	0x00000040
#define	SAI_xCR2_MUTEVAL   SAI_xCR2_MUTEVAL_Msk
	Muate value.
#define	SAI_xCR2_MUTECNT_Pos   (7U)
#define	SAI_xCR2_MUTECNT_Msk   (0x3FUL << SAI_xCR2_MUTECNT_Pos)
	0x00001F80
#define	SAI_xCR2_MUTECNT   SAI_xCR2_MUTECNT_Msk
	MUTECNT[5:0] (MUTE counter).
#define	SAI_xCR2_MUTECNT_0   (0x01UL << SAI_xCR2_MUTECNT_Pos)
	0x00000080
#define	SAI_xCR2_MUTECNT_1   (0x02UL << SAI_xCR2_MUTECNT_Pos)
	0x00000100
#define	SAI_xCR2_MUTECNT_2   (0x04UL << SAI_xCR2_MUTECNT_Pos)
	0x00000200
#define	SAI_xCR2_MUTECNT_3   (0x08UL << SAI_xCR2_MUTECNT_Pos)
	0x00000400
#define	SAI_xCR2_MUTECNT_4   (0x10UL << SAI_xCR2_MUTECNT_Pos)
	0x00000800
#define	SAI_xCR2_MUTECNT_5   (0x20UL << SAI_xCR2_MUTECNT_Pos)
	0x00001000
#define	SAI_xCR2_CPL_Pos   (13U)
#define	SAI_xCR2_CPL_Msk   (0x1UL << SAI_xCR2_CPL_Pos)
	0x00002000
#define	SAI_xCR2_CPL   SAI_xCR2_CPL_Msk
	Complement Bit.
#define	SAI_xCR2_COMP_Pos   (14U)
#define	SAI_xCR2_COMP_Msk   (0x3UL << SAI_xCR2_COMP_Pos)
	0x0000C000
#define	SAI_xCR2_COMP   SAI_xCR2_COMP_Msk
	COMP[1:0] (Companding mode).
#define	SAI_xCR2_COMP_0   (0x1UL << SAI_xCR2_COMP_Pos)
	0x00004000
#define	SAI_xCR2_COMP_1   (0x2UL << SAI_xCR2_COMP_Pos)
	0x00008000
#define	SAI_xFRCR_FRL_Pos   (0U)
#define	SAI_xFRCR_FRL_Msk   (0xFFUL << SAI_xFRCR_FRL_Pos)
	0x000000FF
#define	SAI_xFRCR_FRL   SAI_xFRCR_FRL_Msk
	FRL[7:0](FRame Length).
#define	SAI_xFRCR_FRL_0   (0x01UL << SAI_xFRCR_FRL_Pos)
	0x00000001
#define	SAI_xFRCR_FRL_1   (0x02UL << SAI_xFRCR_FRL_Pos)
	0x00000002
#define	SAI_xFRCR_FRL_2   (0x04UL << SAI_xFRCR_FRL_Pos)
	0x00000004
#define	SAI_xFRCR_FRL_3   (0x08UL << SAI_xFRCR_FRL_Pos)
	0x00000008
#define	SAI_xFRCR_FRL_4   (0x10UL << SAI_xFRCR_FRL_Pos)
	0x00000010
#define	SAI_xFRCR_FRL_5   (0x20UL << SAI_xFRCR_FRL_Pos)
	0x00000020
#define	SAI_xFRCR_FRL_6   (0x40UL << SAI_xFRCR_FRL_Pos)
	0x00000040
#define	SAI_xFRCR_FRL_7   (0x80UL << SAI_xFRCR_FRL_Pos)
	0x00000080
#define	SAI_xFRCR_FSALL_Pos   (8U)
#define	SAI_xFRCR_FSALL_Msk   (0x7FUL << SAI_xFRCR_FSALL_Pos)
	0x00007F00
#define	SAI_xFRCR_FSALL   SAI_xFRCR_FSALL_Msk
	FSALL[6:0] (Frame Synchronization Active Level Length).
#define	SAI_xFRCR_FSALL_0   (0x01UL << SAI_xFRCR_FSALL_Pos)
	0x00000100
#define	SAI_xFRCR_FSALL_1   (0x02UL << SAI_xFRCR_FSALL_Pos)
	0x00000200
#define	SAI_xFRCR_FSALL_2   (0x04UL << SAI_xFRCR_FSALL_Pos)
	0x00000400
#define	SAI_xFRCR_FSALL_3   (0x08UL << SAI_xFRCR_FSALL_Pos)
	0x00000800
#define	SAI_xFRCR_FSALL_4   (0x10UL << SAI_xFRCR_FSALL_Pos)
	0x00001000
#define	SAI_xFRCR_FSALL_5   (0x20UL << SAI_xFRCR_FSALL_Pos)
	0x00002000
#define	SAI_xFRCR_FSALL_6   (0x40UL << SAI_xFRCR_FSALL_Pos)
	0x00004000
#define	SAI_xFRCR_FSDEF_Pos   (16U)
#define	SAI_xFRCR_FSDEF_Msk   (0x1UL << SAI_xFRCR_FSDEF_Pos)
	0x00010000
#define	SAI_xFRCR_FSDEF   SAI_xFRCR_FSDEF_Msk
	Frame Synchronization Definition.
#define	SAI_xFRCR_FSPOL_Pos   (17U)
#define	SAI_xFRCR_FSPOL_Msk   (0x1UL << SAI_xFRCR_FSPOL_Pos)
	0x00020000
#define	SAI_xFRCR_FSPOL   SAI_xFRCR_FSPOL_Msk
	Frame Synchronization POLarity.
#define	SAI_xFRCR_FSOFF_Pos   (18U)
#define	SAI_xFRCR_FSOFF_Msk   (0x1UL << SAI_xFRCR_FSOFF_Pos)
	0x00040000
#define	SAI_xFRCR_FSOFF   SAI_xFRCR_FSOFF_Msk
	Frame Synchronization OFFset.
#define	SAI_xFRCR_FSPO   SAI_xFRCR_FSPOL
#define	SAI_xSLOTR_FBOFF_Pos   (0U)
#define	SAI_xSLOTR_FBOFF_Msk   (0x1FUL << SAI_xSLOTR_FBOFF_Pos)
	0x0000001F
#define	SAI_xSLOTR_FBOFF   SAI_xSLOTR_FBOFF_Msk
	FBOFF[4:0](First Bit Offset).
#define	SAI_xSLOTR_FBOFF_0   (0x01UL << SAI_xSLOTR_FBOFF_Pos)
	0x00000001
#define	SAI_xSLOTR_FBOFF_1   (0x02UL << SAI_xSLOTR_FBOFF_Pos)
	0x00000002
#define	SAI_xSLOTR_FBOFF_2   (0x04UL << SAI_xSLOTR_FBOFF_Pos)
	0x00000004
#define	SAI_xSLOTR_FBOFF_3   (0x08UL << SAI_xSLOTR_FBOFF_Pos)
	0x00000008
#define	SAI_xSLOTR_FBOFF_4   (0x10UL << SAI_xSLOTR_FBOFF_Pos)
	0x00000010
#define	SAI_xSLOTR_SLOTSZ_Pos   (6U)
#define	SAI_xSLOTR_SLOTSZ_Msk   (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)
	0x000000C0
#define	SAI_xSLOTR_SLOTSZ   SAI_xSLOTR_SLOTSZ_Msk
	SLOTSZ[1:0] (Slot size).
#define	SAI_xSLOTR_SLOTSZ_0   (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)
	0x00000040
#define	SAI_xSLOTR_SLOTSZ_1   (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)
	0x00000080
#define	SAI_xSLOTR_NBSLOT_Pos   (8U)
#define	SAI_xSLOTR_NBSLOT_Msk   (0xFUL << SAI_xSLOTR_NBSLOT_Pos)
	0x00000F00
#define	SAI_xSLOTR_NBSLOT   SAI_xSLOTR_NBSLOT_Msk
	NBSLOT[3:0] (Number of Slot in audio Frame).
#define	SAI_xSLOTR_NBSLOT_0   (0x1UL << SAI_xSLOTR_NBSLOT_Pos)
	0x00000100
#define	SAI_xSLOTR_NBSLOT_1   (0x2UL << SAI_xSLOTR_NBSLOT_Pos)
	0x00000200
#define	SAI_xSLOTR_NBSLOT_2   (0x4UL << SAI_xSLOTR_NBSLOT_Pos)
	0x00000400
#define	SAI_xSLOTR_NBSLOT_3   (0x8UL << SAI_xSLOTR_NBSLOT_Pos)
	0x00000800
#define	SAI_xSLOTR_SLOTEN_Pos   (16U)
#define	SAI_xSLOTR_SLOTEN_Msk   (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)
	0xFFFF0000
#define	SAI_xSLOTR_SLOTEN   SAI_xSLOTR_SLOTEN_Msk
	SLOTEN[15:0] (Slot Enable).
#define	SAI_xIMR_OVRUDRIE_Pos   (0U)
#define	SAI_xIMR_OVRUDRIE_Msk   (0x1UL << SAI_xIMR_OVRUDRIE_Pos)
	0x00000001
#define	SAI_xIMR_OVRUDRIE   SAI_xIMR_OVRUDRIE_Msk
	Overrun underrun interrupt enable.
#define	SAI_xIMR_MUTEDETIE_Pos   (1U)
#define	SAI_xIMR_MUTEDETIE_Msk   (0x1UL << SAI_xIMR_MUTEDETIE_Pos)
	0x00000002
#define	SAI_xIMR_MUTEDETIE   SAI_xIMR_MUTEDETIE_Msk
	Mute detection interrupt enable.
#define	SAI_xIMR_WCKCFGIE_Pos   (2U)
#define	SAI_xIMR_WCKCFGIE_Msk   (0x1UL << SAI_xIMR_WCKCFGIE_Pos)
	0x00000004
#define	SAI_xIMR_WCKCFGIE   SAI_xIMR_WCKCFGIE_Msk
	Wrong Clock Configuration interrupt enable.
#define	SAI_xIMR_FREQIE_Pos   (3U)
#define	SAI_xIMR_FREQIE_Msk   (0x1UL << SAI_xIMR_FREQIE_Pos)
	0x00000008
#define	SAI_xIMR_FREQIE   SAI_xIMR_FREQIE_Msk
	FIFO request interrupt enable.
#define	SAI_xIMR_CNRDYIE_Pos   (4U)
#define	SAI_xIMR_CNRDYIE_Msk   (0x1UL << SAI_xIMR_CNRDYIE_Pos)
	0x00000010
#define	SAI_xIMR_CNRDYIE   SAI_xIMR_CNRDYIE_Msk
	Codec not ready interrupt enable.
#define	SAI_xIMR_AFSDETIE_Pos   (5U)
#define	SAI_xIMR_AFSDETIE_Msk   (0x1UL << SAI_xIMR_AFSDETIE_Pos)
	0x00000020
#define	SAI_xIMR_AFSDETIE   SAI_xIMR_AFSDETIE_Msk
	Anticipated frame synchronization detection interrupt enable.
#define	SAI_xIMR_LFSDETIE_Pos   (6U)
#define	SAI_xIMR_LFSDETIE_Msk   (0x1UL << SAI_xIMR_LFSDETIE_Pos)
	0x00000040
#define	SAI_xIMR_LFSDETIE   SAI_xIMR_LFSDETIE_Msk
	Late frame synchronization detection interrupt enable.
#define	SAI_xSR_OVRUDR_Pos   (0U)
#define	SAI_xSR_OVRUDR_Msk   (0x1UL << SAI_xSR_OVRUDR_Pos)
	0x00000001
#define	SAI_xSR_OVRUDR   SAI_xSR_OVRUDR_Msk
	Overrun underrun.
#define	SAI_xSR_MUTEDET_Pos   (1U)
#define	SAI_xSR_MUTEDET_Msk   (0x1UL << SAI_xSR_MUTEDET_Pos)
	0x00000002
#define	SAI_xSR_MUTEDET   SAI_xSR_MUTEDET_Msk
	Mute detection.
#define	SAI_xSR_WCKCFG_Pos   (2U)
#define	SAI_xSR_WCKCFG_Msk   (0x1UL << SAI_xSR_WCKCFG_Pos)
	0x00000004
#define	SAI_xSR_WCKCFG   SAI_xSR_WCKCFG_Msk
	Wrong Clock Configuration.
#define	SAI_xSR_FREQ_Pos   (3U)
#define	SAI_xSR_FREQ_Msk   (0x1UL << SAI_xSR_FREQ_Pos)
	0x00000008
#define	SAI_xSR_FREQ   SAI_xSR_FREQ_Msk
	FIFO request.
#define	SAI_xSR_CNRDY_Pos   (4U)
#define	SAI_xSR_CNRDY_Msk   (0x1UL << SAI_xSR_CNRDY_Pos)
	0x00000010
#define	SAI_xSR_CNRDY   SAI_xSR_CNRDY_Msk
	Codec not ready.
#define	SAI_xSR_AFSDET_Pos   (5U)
#define	SAI_xSR_AFSDET_Msk   (0x1UL << SAI_xSR_AFSDET_Pos)
	0x00000020
#define	SAI_xSR_AFSDET   SAI_xSR_AFSDET_Msk
	Anticipated frame synchronization detection.
#define	SAI_xSR_LFSDET_Pos   (6U)
#define	SAI_xSR_LFSDET_Msk   (0x1UL << SAI_xSR_LFSDET_Pos)
	0x00000040
#define	SAI_xSR_LFSDET   SAI_xSR_LFSDET_Msk
	Late frame synchronization detection.
#define	SAI_xSR_FLVL_Pos   (16U)
#define	SAI_xSR_FLVL_Msk   (0x7UL << SAI_xSR_FLVL_Pos)
	0x00070000
#define	SAI_xSR_FLVL   SAI_xSR_FLVL_Msk
	FLVL[2:0] (FIFO Level Threshold).
#define	SAI_xSR_FLVL_0   (0x1UL << SAI_xSR_FLVL_Pos)
	0x00010000
#define	SAI_xSR_FLVL_1   (0x2UL << SAI_xSR_FLVL_Pos)
	0x00020000
#define	SAI_xSR_FLVL_2   (0x4UL << SAI_xSR_FLVL_Pos)
	0x00040000
#define	SAI_xCLRFR_COVRUDR_Pos   (0U)
#define	SAI_xCLRFR_COVRUDR_Msk   (0x1UL << SAI_xCLRFR_COVRUDR_Pos)
	0x00000001
#define	SAI_xCLRFR_COVRUDR   SAI_xCLRFR_COVRUDR_Msk
	Clear Overrun underrun.
#define	SAI_xCLRFR_CMUTEDET_Pos   (1U)
#define	SAI_xCLRFR_CMUTEDET_Msk   (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)
	0x00000002
#define	SAI_xCLRFR_CMUTEDET   SAI_xCLRFR_CMUTEDET_Msk
	Clear Mute detection.
#define	SAI_xCLRFR_CWCKCFG_Pos   (2U)
#define	SAI_xCLRFR_CWCKCFG_Msk   (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)
	0x00000004
#define	SAI_xCLRFR_CWCKCFG   SAI_xCLRFR_CWCKCFG_Msk
	Clear Wrong Clock Configuration.
#define	SAI_xCLRFR_CFREQ_Pos   (3U)
#define	SAI_xCLRFR_CFREQ_Msk   (0x1UL << SAI_xCLRFR_CFREQ_Pos)
	0x00000008
#define	SAI_xCLRFR_CFREQ   SAI_xCLRFR_CFREQ_Msk
	Clear FIFO request.
#define	SAI_xCLRFR_CCNRDY_Pos   (4U)
#define	SAI_xCLRFR_CCNRDY_Msk   (0x1UL << SAI_xCLRFR_CCNRDY_Pos)
	0x00000010
#define	SAI_xCLRFR_CCNRDY   SAI_xCLRFR_CCNRDY_Msk
	Clear Codec not ready.
#define	SAI_xCLRFR_CAFSDET_Pos   (5U)
#define	SAI_xCLRFR_CAFSDET_Msk   (0x1UL << SAI_xCLRFR_CAFSDET_Pos)
	0x00000020
#define	SAI_xCLRFR_CAFSDET   SAI_xCLRFR_CAFSDET_Msk
	Clear Anticipated frame synchronization detection.
#define	SAI_xCLRFR_CLFSDET_Pos   (6U)
#define	SAI_xCLRFR_CLFSDET_Msk   (0x1UL << SAI_xCLRFR_CLFSDET_Pos)
	0x00000040
#define	SAI_xCLRFR_CLFSDET   SAI_xCLRFR_CLFSDET_Msk
	Clear Late frame synchronization detection.
#define	SAI_xDR_DATA_Pos   (0U)
#define	SAI_xDR_DATA_Msk   (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)
	0xFFFFFFFF
#define	SAI_xDR_DATA   SAI_xDR_DATA_Msk
#define	SAI_PDMCR_PDMEN_Pos   (0U)
#define	SAI_PDMCR_PDMEN_Msk   (0x1UL << SAI_PDMCR_PDMEN_Pos)
	0x00000001
#define	SAI_PDMCR_PDMEN   SAI_PDMCR_PDMEN_Msk
	PDM Enable.
#define	SAI_PDMCR_MICNBR_Pos   (4U)
#define	SAI_PDMCR_MICNBR_Msk   (0x3UL << SAI_PDMCR_MICNBR_Pos)
	0x00000030
#define	SAI_PDMCR_MICNBR   SAI_PDMCR_MICNBR_Msk
	Number of microphones.
#define	SAI_PDMCR_MICNBR_0   (0x1UL << SAI_PDMCR_MICNBR_Pos)
	0x00000010
#define	SAI_PDMCR_MICNBR_1   (0x2UL << SAI_PDMCR_MICNBR_Pos)
	0x00000020
#define	SAI_PDMCR_CKEN1_Pos   (8U)
#define	SAI_PDMCR_CKEN1_Msk   (0x1UL << SAI_PDMCR_CKEN1_Pos)
	0x00000100
#define	SAI_PDMCR_CKEN1   SAI_PDMCR_CKEN1_Msk
	Clock enable of bitstream clock number 1.
#define	SAI_PDMCR_CKEN2_Pos   (9U)
#define	SAI_PDMCR_CKEN2_Msk   (0x1UL << SAI_PDMCR_CKEN2_Pos)
	0x00000200
#define	SAI_PDMCR_CKEN2   SAI_PDMCR_CKEN2_Msk
	Clock enable of bitstream clock number 2.
#define	SAI_PDMCR_CKEN3_Pos   (10U)
#define	SAI_PDMCR_CKEN3_Msk   (0x1UL << SAI_PDMCR_CKEN3_Pos)
	0x00000400
#define	SAI_PDMCR_CKEN3   SAI_PDMCR_CKEN3_Msk
	Clock enable of bitstream clock number 3.
#define	SAI_PDMCR_CKEN4_Pos   (11U)
#define	SAI_PDMCR_CKEN4_Msk   (0x1UL << SAI_PDMCR_CKEN4_Pos)
	0x00000800
#define	SAI_PDMCR_CKEN4   SAI_PDMCR_CKEN4_Msk
	Clock enable of bitstream clock number 4.
#define	SAI_PDMDLY_DLYM1L_Pos   (0U)
#define	SAI_PDMDLY_DLYM1L_Msk   (0x7UL << SAI_PDMDLY_DLYM1L_Pos)
	0x00000007
#define	SAI_PDMDLY_DLYM1L   SAI_PDMDLY_DLYM1L_Msk
	DLYM1L[2:0] (Delay line adjust for left microphone of pair 1).
#define	SAI_PDMDLY_DLYM1L_0   (0x1UL << SAI_PDMDLY_DLYM1L_Pos)
	0x00000001
#define	SAI_PDMDLY_DLYM1L_1   (0x2UL << SAI_PDMDLY_DLYM1L_Pos)
	0x00000002
#define	SAI_PDMDLY_DLYM1L_2   (0x4UL << SAI_PDMDLY_DLYM1L_Pos)
	0x00000004
#define	SAI_PDMDLY_DLYM1R_Pos   (4U)
#define	SAI_PDMDLY_DLYM1R_Msk   (0x7UL << SAI_PDMDLY_DLYM1R_Pos)
	0x00000070
#define	SAI_PDMDLY_DLYM1R   SAI_PDMDLY_DLYM1R_Msk
	DLYM1R[2:0] (Delay line adjust for right microphone of pair 1).
#define	SAI_PDMDLY_DLYM1R_0   (0x1UL << SAI_PDMDLY_DLYM1R_Pos)
	0x00000010
#define	SAI_PDMDLY_DLYM1R_1   (0x2UL << SAI_PDMDLY_DLYM1R_Pos)
	0x00000020
#define	SAI_PDMDLY_DLYM1R_2   (0x4UL << SAI_PDMDLY_DLYM1R_Pos)
	0x00000040
#define	SAI_PDMDLY_DLYM2L_Pos   (8U)
#define	SAI_PDMDLY_DLYM2L_Msk   (0x7UL << SAI_PDMDLY_DLYM2L_Pos)
	0x00000700
#define	SAI_PDMDLY_DLYM2L   SAI_PDMDLY_DLYM2L_Msk
	DLYM2L[2:0] (Delay line adjust for left microphone of pair 2).
#define	SAI_PDMDLY_DLYM2L_0   (0x1UL << SAI_PDMDLY_DLYM2L_Pos)
	0x00000100
#define	SAI_PDMDLY_DLYM2L_1   (0x2UL << SAI_PDMDLY_DLYM2L_Pos)
	0x00000200
#define	SAI_PDMDLY_DLYM2L_2   (0x4UL << SAI_PDMDLY_DLYM2L_Pos)
	0x00000400
#define	SAI_PDMDLY_DLYM2R_Pos   (12U)
#define	SAI_PDMDLY_DLYM2R_Msk   (0x7UL << SAI_PDMDLY_DLYM2R_Pos)
	0x00007000
#define	SAI_PDMDLY_DLYM2R   SAI_PDMDLY_DLYM2R_Msk
	DLYM2R[2:0] (Delay line adjust for right microphone of pair 2).
#define	SAI_PDMDLY_DLYM2R_0   (0x1UL << SAI_PDMDLY_DLYM2R_Pos)
	0x00001000
#define	SAI_PDMDLY_DLYM2R_1   (0x2UL << SAI_PDMDLY_DLYM2R_Pos)
	0x00002000
#define	SAI_PDMDLY_DLYM2R_2   (0x4UL << SAI_PDMDLY_DLYM2R_Pos)
	0x00004000
#define	SAI_PDMDLY_DLYM3L_Pos   (16U)
#define	SAI_PDMDLY_DLYM3L_Msk   (0x7UL << SAI_PDMDLY_DLYM3L_Pos)
	0x00070000
#define	SAI_PDMDLY_DLYM3L   SAI_PDMDLY_DLYM3L_Msk
	DLYM3L[2:0] (Delay line adjust for left microphone of pair 3).
#define	SAI_PDMDLY_DLYM3L_0   (0x1UL << SAI_PDMDLY_DLYM3L_Pos)
	0x00010000
#define	SAI_PDMDLY_DLYM3L_1   (0x2UL << SAI_PDMDLY_DLYM3L_Pos)
	0x00020000
#define	SAI_PDMDLY_DLYM3L_2   (0x4UL << SAI_PDMDLY_DLYM3L_Pos)
	0x00040000
#define	SAI_PDMDLY_DLYM3R_Pos   (20U)
#define	SAI_PDMDLY_DLYM3R_Msk   (0x7UL << SAI_PDMDLY_DLYM3R_Pos)
	0x00700000
#define	SAI_PDMDLY_DLYM3R   SAI_PDMDLY_DLYM3R_Msk
	DLYM3R[2:0] (Delay line adjust for right microphone of pair 3).
#define	SAI_PDMDLY_DLYM3R_0   (0x1UL << SAI_PDMDLY_DLYM3R_Pos)
	0x00100000
#define	SAI_PDMDLY_DLYM3R_1   (0x2UL << SAI_PDMDLY_DLYM3R_Pos)
	0x00200000
#define	SAI_PDMDLY_DLYM3R_2   (0x4UL << SAI_PDMDLY_DLYM3R_Pos)
	0x00400000
#define	SAI_PDMDLY_DLYM4L_Pos   (24U)
#define	SAI_PDMDLY_DLYM4L_Msk   (0x7UL << SAI_PDMDLY_DLYM4L_Pos)
	0x07000000
#define	SAI_PDMDLY_DLYM4L   SAI_PDMDLY_DLYM4L_Msk
	DLYM4L[2:0] (Delay line adjust for left microphone of pair 4).
#define	SAI_PDMDLY_DLYM4L_0   (0x1UL << SAI_PDMDLY_DLYM4L_Pos)
	0x01000000
#define	SAI_PDMDLY_DLYM4L_1   (0x2UL << SAI_PDMDLY_DLYM4L_Pos)
	0x02000000
#define	SAI_PDMDLY_DLYM4L_2   (0x4UL << SAI_PDMDLY_DLYM4L_Pos)
	0x04000000
#define	SAI_PDMDLY_DLYM4R_Pos   (28U)
#define	SAI_PDMDLY_DLYM4R_Msk   (0x7UL << SAI_PDMDLY_DLYM4R_Pos)
	0x70000000
#define	SAI_PDMDLY_DLYM4R   SAI_PDMDLY_DLYM4R_Msk
	DLYM4R[2:0] (Delay line adjust for right microphone of pair 4).
#define	SAI_PDMDLY_DLYM4R_0   (0x1UL << SAI_PDMDLY_DLYM4R_Pos)
	0x10000000
#define	SAI_PDMDLY_DLYM4R_1   (0x2UL << SAI_PDMDLY_DLYM4R_Pos)
	0x20000000
#define	SAI_PDMDLY_DLYM4R_2   (0x4UL << SAI_PDMDLY_DLYM4R_Pos)
	0x40000000
#define	SDMMC_POWER_PWRCTRL_Pos   (0U)
#define	SDMMC_POWER_PWRCTRL_Msk   (0x3UL << SDMMC_POWER_PWRCTRL_Pos)
	0x00000003
#define	SDMMC_POWER_PWRCTRL   SDMMC_POWER_PWRCTRL_Msk
	PWRCTRL[1:0] bits (Power supply control bits).
#define	SDMMC_POWER_PWRCTRL_0   (0x1UL << SDMMC_POWER_PWRCTRL_Pos)
	0x00000001
#define	SDMMC_POWER_PWRCTRL_1   (0x2UL << SDMMC_POWER_PWRCTRL_Pos)
	0x00000002
#define	SDMMC_POWER_VSWITCH_Pos   (2U)
#define	SDMMC_POWER_VSWITCH_Msk   (0x1UL << SDMMC_POWER_VSWITCH_Pos)
	0x00000004
#define	SDMMC_POWER_VSWITCH   SDMMC_POWER_VSWITCH_Msk
	Voltage switch sequence start.
#define	SDMMC_POWER_VSWITCHEN_Pos   (3U)
#define	SDMMC_POWER_VSWITCHEN_Msk   (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)
	0x00000008
#define	SDMMC_POWER_VSWITCHEN   SDMMC_POWER_VSWITCHEN_Msk
	Voltage switch procedure enable.
#define	SDMMC_POWER_DIRPOL_Pos   (4U)
#define	SDMMC_POWER_DIRPOL_Msk   (0x1UL << SDMMC_POWER_DIRPOL_Pos)
	0x00000010
#define	SDMMC_POWER_DIRPOL   SDMMC_POWER_DIRPOL_Msk
	Data and Command direction signals polarity selection.
#define	SDMMC_CLKCR_CLKDIV_Pos   (0U)
#define	SDMMC_CLKCR_CLKDIV_Msk   (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)
	0x000003FF
#define	SDMMC_CLKCR_CLKDIV   SDMMC_CLKCR_CLKDIV_Msk
	Clock divide factor.
#define	SDMMC_CLKCR_PWRSAV_Pos   (12U)
#define	SDMMC_CLKCR_PWRSAV_Msk   (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)
	0x00001000
#define	SDMMC_CLKCR_PWRSAV   SDMMC_CLKCR_PWRSAV_Msk
	Power saving configuration bit.
#define	SDMMC_CLKCR_WIDBUS_Pos   (14U)
#define	SDMMC_CLKCR_WIDBUS_Msk   (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)
	0x0000C000
#define	SDMMC_CLKCR_WIDBUS   SDMMC_CLKCR_WIDBUS_Msk
	WIDBUS[1:0] bits (Wide bus mode enable bit).
#define	SDMMC_CLKCR_WIDBUS_0   (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)
	0x00004000
#define	SDMMC_CLKCR_WIDBUS_1   (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)
	0x00008000
#define	SDMMC_CLKCR_NEGEDGE_Pos   (16U)
#define	SDMMC_CLKCR_NEGEDGE_Msk   (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)
	0x00010000
#define	SDMMC_CLKCR_NEGEDGE   SDMMC_CLKCR_NEGEDGE_Msk
	SDMMC_CK dephasing selection bit.
#define	SDMMC_CLKCR_HWFC_EN_Pos   (17U)
#define	SDMMC_CLKCR_HWFC_EN_Msk   (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)
	0x00020000
#define	SDMMC_CLKCR_HWFC_EN   SDMMC_CLKCR_HWFC_EN_Msk
	HW Flow Control enable.
#define	SDMMC_CLKCR_DDR_Pos   (18U)
#define	SDMMC_CLKCR_DDR_Msk   (0x1UL << SDMMC_CLKCR_DDR_Pos)
	0x00040000
#define	SDMMC_CLKCR_DDR   SDMMC_CLKCR_DDR_Msk
	Data rate signaling selection.
#define	SDMMC_CLKCR_BUSSPEED_Pos   (19U)
#define	SDMMC_CLKCR_BUSSPEED_Msk   (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)
	0x00080000
#define	SDMMC_CLKCR_BUSSPEED   SDMMC_CLKCR_BUSSPEED_Msk
	Bus speed mode selection.
#define	SDMMC_CLKCR_SELCLKRX_Pos   (20U)
#define	SDMMC_CLKCR_SELCLKRX_Msk   (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)
	0x00300000
#define	SDMMC_CLKCR_SELCLKRX   SDMMC_CLKCR_SELCLKRX_Msk
	SELCLKRX[1:0] bits (Receive clock selection).
#define	SDMMC_CLKCR_SELCLKRX_0   (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)
	0x00100000
#define	SDMMC_CLKCR_SELCLKRX_1   (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)
	0x00200000
#define	SDMMC_ARG_CMDARG_Pos   (0U)
#define	SDMMC_ARG_CMDARG_Msk   (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)
	0xFFFFFFFF
#define	SDMMC_ARG_CMDARG   SDMMC_ARG_CMDARG_Msk
	Command argument.
#define	SDMMC_CMD_CMDINDEX_Pos   (0U)
#define	SDMMC_CMD_CMDINDEX_Msk   (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)
	0x0000003F
#define	SDMMC_CMD_CMDINDEX   SDMMC_CMD_CMDINDEX_Msk
	Command Index.
#define	SDMMC_CMD_CMDTRANS_Pos   (6U)
#define	SDMMC_CMD_CMDTRANS_Msk   (0x1UL << SDMMC_CMD_CMDTRANS_Pos)
	0x00000040
#define	SDMMC_CMD_CMDTRANS   SDMMC_CMD_CMDTRANS_Msk
	CPSM Treats command as a Data Transfer.
#define	SDMMC_CMD_CMDSTOP_Pos   (7U)
#define	SDMMC_CMD_CMDSTOP_Msk   (0x1UL << SDMMC_CMD_CMDSTOP_Pos)
	0x00000080
#define	SDMMC_CMD_CMDSTOP   SDMMC_CMD_CMDSTOP_Msk
	CPSM Treats command as a Stop.
#define	SDMMC_CMD_WAITRESP_Pos   (8U)
#define	SDMMC_CMD_WAITRESP_Msk   (0x3UL << SDMMC_CMD_WAITRESP_Pos)
	0x00000300
#define	SDMMC_CMD_WAITRESP   SDMMC_CMD_WAITRESP_Msk
	WAITRESP[1:0] bits (Wait for response bits).
#define	SDMMC_CMD_WAITRESP_0   (0x1UL << SDMMC_CMD_WAITRESP_Pos)
	0x00000100
#define	SDMMC_CMD_WAITRESP_1   (0x2UL << SDMMC_CMD_WAITRESP_Pos)
	0x00000200
#define	SDMMC_CMD_WAITINT_Pos   (10U)
#define	SDMMC_CMD_WAITINT_Msk   (0x1UL << SDMMC_CMD_WAITINT_Pos)
	0x00000400
#define	SDMMC_CMD_WAITINT   SDMMC_CMD_WAITINT_Msk
	CPSM Waits for Interrupt Request.
#define	SDMMC_CMD_WAITPEND_Pos   (11U)
#define	SDMMC_CMD_WAITPEND_Msk   (0x1UL << SDMMC_CMD_WAITPEND_Pos)
	0x00000800
#define	SDMMC_CMD_WAITPEND   SDMMC_CMD_WAITPEND_Msk
	CPSM Waits for ends of data transfer (CmdPend internal signal).
#define	SDMMC_CMD_CPSMEN_Pos   (12U)
#define	SDMMC_CMD_CPSMEN_Msk   (0x1UL << SDMMC_CMD_CPSMEN_Pos)
	0x00001000
#define	SDMMC_CMD_CPSMEN   SDMMC_CMD_CPSMEN_Msk
	Command path state machine (CPSM) Enable bit.
#define	SDMMC_CMD_DTHOLD_Pos   (13U)
#define	SDMMC_CMD_DTHOLD_Msk   (0x1UL << SDMMC_CMD_DTHOLD_Pos)
	0x00002000
#define	SDMMC_CMD_DTHOLD   SDMMC_CMD_DTHOLD_Msk
	Hold new data block transmission and reception in the DPSM.
#define	SDMMC_CMD_BOOTMODE_Pos   (14U)
#define	SDMMC_CMD_BOOTMODE_Msk   (0x1UL << SDMMC_CMD_BOOTMODE_Pos)
	0x00004000
#define	SDMMC_CMD_BOOTMODE   SDMMC_CMD_BOOTMODE_Msk
	Boot mode.
#define	SDMMC_CMD_BOOTEN_Pos   (15U)
#define	SDMMC_CMD_BOOTEN_Msk   (0x1UL << SDMMC_CMD_BOOTEN_Pos)
	0x00008000
#define	SDMMC_CMD_BOOTEN   SDMMC_CMD_BOOTEN_Msk
	Enable Boot mode procedure.
#define	SDMMC_CMD_CMDSUSPEND_Pos   (16U)
#define	SDMMC_CMD_CMDSUSPEND_Msk   (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)
	0x00010000
#define	SDMMC_CMD_CMDSUSPEND   SDMMC_CMD_CMDSUSPEND_Msk
	CPSM Treats command as a Suspend or Resume command.
#define	SDMMC_RESPCMD_RESPCMD_Pos   (0U)
#define	SDMMC_RESPCMD_RESPCMD_Msk   (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)
	0x0000003F
#define	SDMMC_RESPCMD_RESPCMD   SDMMC_RESPCMD_RESPCMD_Msk
	Response command index.
#define	SDMMC_RESP0_CARDSTATUS0_Pos   (0U)
#define	SDMMC_RESP0_CARDSTATUS0_Msk   (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos)
	0xFFFFFFFF
#define	SDMMC_RESP0_CARDSTATUS0   SDMMC_RESP0_CARDSTATUS0_Msk
	Card Status.
#define	SDMMC_RESP1_CARDSTATUS1_Pos   (0U)
#define	SDMMC_RESP1_CARDSTATUS1_Msk   (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos)
	0xFFFFFFFF
#define	SDMMC_RESP1_CARDSTATUS1   SDMMC_RESP1_CARDSTATUS1_Msk
	Card Status.
#define	SDMMC_RESP2_CARDSTATUS2_Pos   (0U)
#define	SDMMC_RESP2_CARDSTATUS2_Msk   (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos)
	0xFFFFFFFF
#define	SDMMC_RESP2_CARDSTATUS2   SDMMC_RESP2_CARDSTATUS2_Msk
	Card Status.
#define	SDMMC_RESP3_CARDSTATUS3_Pos   (0U)
#define	SDMMC_RESP3_CARDSTATUS3_Msk   (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos)
	0xFFFFFFFF
#define	SDMMC_RESP3_CARDSTATUS3   SDMMC_RESP3_CARDSTATUS3_Msk
	Card Status.
#define	SDMMC_RESP4_CARDSTATUS4_Pos   (0U)
#define	SDMMC_RESP4_CARDSTATUS4_Msk   (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos)
	0xFFFFFFFF
#define	SDMMC_RESP4_CARDSTATUS4   SDMMC_RESP4_CARDSTATUS4_Msk
	Card Status.
#define	SDMMC_DTIMER_DATATIME_Pos   (0U)
#define	SDMMC_DTIMER_DATATIME_Msk   (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos)
	0xFFFFFFFF
#define	SDMMC_DTIMER_DATATIME   SDMMC_DTIMER_DATATIME_Msk
	Data timeout period.
#define	SDMMC_DLEN_DATALENGTH_Pos   (0U)
#define	SDMMC_DLEN_DATALENGTH_Msk   (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos)
	0x01FFFFFF
#define	SDMMC_DLEN_DATALENGTH   SDMMC_DLEN_DATALENGTH_Msk
	Data length value.
#define	SDMMC_DCTRL_DTEN_Pos   (0U)
#define	SDMMC_DCTRL_DTEN_Msk   (0x1UL << SDMMC_DCTRL_DTEN_Pos)
	0x00000001
#define	SDMMC_DCTRL_DTEN   SDMMC_DCTRL_DTEN_Msk
	Data transfer enabled bit.
#define	SDMMC_DCTRL_DTDIR_Pos   (1U)
#define	SDMMC_DCTRL_DTDIR_Msk   (0x1UL << SDMMC_DCTRL_DTDIR_Pos)
	0x00000002
#define	SDMMC_DCTRL_DTDIR   SDMMC_DCTRL_DTDIR_Msk
	Data transfer direction selection.
#define	SDMMC_DCTRL_DTMODE_Pos   (2U)
#define	SDMMC_DCTRL_DTMODE_Msk   (0x3UL << SDMMC_DCTRL_DTMODE_Pos)
	0x0000000C
#define	SDMMC_DCTRL_DTMODE   SDMMC_DCTRL_DTMODE_Msk
	DTMODE[1:0] Data transfer mode selection.
#define	SDMMC_DCTRL_DTMODE_0   (0x1UL << SDMMC_DCTRL_DTMODE_Pos)
	0x00000004
#define	SDMMC_DCTRL_DTMODE_1   (0x2UL << SDMMC_DCTRL_DTMODE_Pos)
	0x00000008
#define	SDMMC_DCTRL_DBLOCKSIZE_Pos   (4U)
#define	SDMMC_DCTRL_DBLOCKSIZE_Msk   (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
	0x000000F0
#define	SDMMC_DCTRL_DBLOCKSIZE   SDMMC_DCTRL_DBLOCKSIZE_Msk
	DBLOCKSIZE[3:0] bits (Data block size).
#define	SDMMC_DCTRL_DBLOCKSIZE_0   (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
	0x00000010
#define	SDMMC_DCTRL_DBLOCKSIZE_1   (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
	0x00000020
#define	SDMMC_DCTRL_DBLOCKSIZE_2   (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
	0x00000040
#define	SDMMC_DCTRL_DBLOCKSIZE_3   (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
	0x00000080
#define	SDMMC_DCTRL_RWSTART_Pos   (8U)
#define	SDMMC_DCTRL_RWSTART_Msk   (0x1UL << SDMMC_DCTRL_RWSTART_Pos)
	0x00000100
#define	SDMMC_DCTRL_RWSTART   SDMMC_DCTRL_RWSTART_Msk
	Read wait start.
#define	SDMMC_DCTRL_RWSTOP_Pos   (9U)
#define	SDMMC_DCTRL_RWSTOP_Msk   (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)
	0x00000200
#define	SDMMC_DCTRL_RWSTOP   SDMMC_DCTRL_RWSTOP_Msk
	Read wait stop.
#define	SDMMC_DCTRL_RWMOD_Pos   (10U)
#define	SDMMC_DCTRL_RWMOD_Msk   (0x1UL << SDMMC_DCTRL_RWMOD_Pos)
	0x00000400
#define	SDMMC_DCTRL_RWMOD   SDMMC_DCTRL_RWMOD_Msk
	Read wait mode.
#define	SDMMC_DCTRL_SDIOEN_Pos   (11U)
#define	SDMMC_DCTRL_SDIOEN_Msk   (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)
	0x00000800
#define	SDMMC_DCTRL_SDIOEN   SDMMC_DCTRL_SDIOEN_Msk
	SD I/O enable functions.
#define	SDMMC_DCTRL_BOOTACKEN_Pos   (12U)
#define	SDMMC_DCTRL_BOOTACKEN_Msk   (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)
	0x00001000
#define	SDMMC_DCTRL_BOOTACKEN   SDMMC_DCTRL_BOOTACKEN_Msk
	Enable the reception of the Boot Acknowledgment.
#define	SDMMC_DCTRL_FIFORST_Pos   (13U)
#define	SDMMC_DCTRL_FIFORST_Msk   (0x1UL << SDMMC_DCTRL_FIFORST_Pos)
	0x00002000
#define	SDMMC_DCTRL_FIFORST   SDMMC_DCTRL_FIFORST_Msk
	FIFO reset.
#define	SDMMC_DCOUNT_DATACOUNT_Pos   (0U)
#define	SDMMC_DCOUNT_DATACOUNT_Msk   (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos)
	0x01FFFFFF
#define	SDMMC_DCOUNT_DATACOUNT   SDMMC_DCOUNT_DATACOUNT_Msk
	Data count value.
#define	SDMMC_STA_CCRCFAIL_Pos   (0U)
#define	SDMMC_STA_CCRCFAIL_Msk   (0x1UL << SDMMC_STA_CCRCFAIL_Pos)
	0x00000001
#define	SDMMC_STA_CCRCFAIL   SDMMC_STA_CCRCFAIL_Msk
	Command response received (CRC check failed).
#define	SDMMC_STA_DCRCFAIL_Pos   (1U)
#define	SDMMC_STA_DCRCFAIL_Msk   (0x1UL << SDMMC_STA_DCRCFAIL_Pos)
	0x00000002
#define	SDMMC_STA_DCRCFAIL   SDMMC_STA_DCRCFAIL_Msk
	Data block sent/received (CRC check failed).
#define	SDMMC_STA_CTIMEOUT_Pos   (2U)
#define	SDMMC_STA_CTIMEOUT_Msk   (0x1UL << SDMMC_STA_CTIMEOUT_Pos)
	0x00000004
#define	SDMMC_STA_CTIMEOUT   SDMMC_STA_CTIMEOUT_Msk
	Command response timeout.
#define	SDMMC_STA_DTIMEOUT_Pos   (3U)
#define	SDMMC_STA_DTIMEOUT_Msk   (0x1UL << SDMMC_STA_DTIMEOUT_Pos)
	0x00000008
#define	SDMMC_STA_DTIMEOUT   SDMMC_STA_DTIMEOUT_Msk
	Data timeout.
#define	SDMMC_STA_TXUNDERR_Pos   (4U)
#define	SDMMC_STA_TXUNDERR_Msk   (0x1UL << SDMMC_STA_TXUNDERR_Pos)
	0x00000010
#define	SDMMC_STA_TXUNDERR   SDMMC_STA_TXUNDERR_Msk
	Transmit FIFO underrun error.
#define	SDMMC_STA_RXOVERR_Pos   (5U)
#define	SDMMC_STA_RXOVERR_Msk   (0x1UL << SDMMC_STA_RXOVERR_Pos)
	0x00000020
#define	SDMMC_STA_RXOVERR   SDMMC_STA_RXOVERR_Msk
	Received FIFO overrun error.
#define	SDMMC_STA_CMDREND_Pos   (6U)
#define	SDMMC_STA_CMDREND_Msk   (0x1UL << SDMMC_STA_CMDREND_Pos)
	0x00000040
#define	SDMMC_STA_CMDREND   SDMMC_STA_CMDREND_Msk
	Command response received (CRC check passed).
#define	SDMMC_STA_CMDSENT_Pos   (7U)
#define	SDMMC_STA_CMDSENT_Msk   (0x1UL << SDMMC_STA_CMDSENT_Pos)
	0x00000080
#define	SDMMC_STA_CMDSENT   SDMMC_STA_CMDSENT_Msk
	Command sent (no response required).
#define	SDMMC_STA_DATAEND_Pos   (8U)
#define	SDMMC_STA_DATAEND_Msk   (0x1UL << SDMMC_STA_DATAEND_Pos)
	0x00000100
#define	SDMMC_STA_DATAEND   SDMMC_STA_DATAEND_Msk
	Data end (data counter, SDIDCOUNT, is zero).
#define	SDMMC_STA_DHOLD_Pos   (9U)
#define	SDMMC_STA_DHOLD_Msk   (0x1UL << SDMMC_STA_DHOLD_Pos)
	0x00000200
#define	SDMMC_STA_DHOLD   SDMMC_STA_DHOLD_Msk
	Data transfer Hold.
#define	SDMMC_STA_DBCKEND_Pos   (10U)
#define	SDMMC_STA_DBCKEND_Msk   (0x1UL << SDMMC_STA_DBCKEND_Pos)
	0x00000400
#define	SDMMC_STA_DBCKEND   SDMMC_STA_DBCKEND_Msk
	Data block sent/received (CRC check passed).
#define	SDMMC_STA_DABORT_Pos   (11U)
#define	SDMMC_STA_DABORT_Msk   (0x1UL << SDMMC_STA_DABORT_Pos)
	0x00000800
#define	SDMMC_STA_DABORT   SDMMC_STA_DABORT_Msk
	Data transfer aborted by CMD12.
#define	SDMMC_STA_DPSMACT_Pos   (12U)
#define	SDMMC_STA_DPSMACT_Msk   (0x1UL << SDMMC_STA_DPSMACT_Pos)
	0x00001000
#define	SDMMC_STA_DPSMACT   SDMMC_STA_DPSMACT_Msk
	Data path state machine active.
#define	SDMMC_STA_CPSMACT_Pos   (13U)
#define	SDMMC_STA_CPSMACT_Msk   (0x1UL << SDMMC_STA_CPSMACT_Pos)
	0x00002000
#define	SDMMC_STA_CPSMACT   SDMMC_STA_CPSMACT_Msk
	Command path state machine active.
#define	SDMMC_STA_TXFIFOHE_Pos   (14U)
#define	SDMMC_STA_TXFIFOHE_Msk   (0x1UL << SDMMC_STA_TXFIFOHE_Pos)
	0x00004000
#define	SDMMC_STA_TXFIFOHE   SDMMC_STA_TXFIFOHE_Msk
	Transmit FIFO Half Empty: at least 8 words can be written into the FIFO.
#define	SDMMC_STA_RXFIFOHF_Pos   (15U)
#define	SDMMC_STA_RXFIFOHF_Msk   (0x1UL << SDMMC_STA_RXFIFOHF_Pos)
	0x00008000
#define	SDMMC_STA_RXFIFOHF   SDMMC_STA_RXFIFOHF_Msk
	Receive FIFO Half Full: there are at least 8 words in the FIFO.
#define	SDMMC_STA_TXFIFOF_Pos   (16U)
#define	SDMMC_STA_TXFIFOF_Msk   (0x1UL << SDMMC_STA_TXFIFOF_Pos)
	0x00010000
#define	SDMMC_STA_TXFIFOF   SDMMC_STA_TXFIFOF_Msk
	Transmit FIFO full.
#define	SDMMC_STA_RXFIFOF_Pos   (17U)
#define	SDMMC_STA_RXFIFOF_Msk   (0x1UL << SDMMC_STA_RXFIFOF_Pos)
	0x00020000
#define	SDMMC_STA_RXFIFOF   SDMMC_STA_RXFIFOF_Msk
	Receive FIFO full.
#define	SDMMC_STA_TXFIFOE_Pos   (18U)
#define	SDMMC_STA_TXFIFOE_Msk   (0x1UL << SDMMC_STA_TXFIFOE_Pos)
	0x00040000
#define	SDMMC_STA_TXFIFOE   SDMMC_STA_TXFIFOE_Msk
	Transmit FIFO empty.
#define	SDMMC_STA_RXFIFOE_Pos   (19U)
#define	SDMMC_STA_RXFIFOE_Msk   (0x1UL << SDMMC_STA_RXFIFOE_Pos)
	0x00080000
#define	SDMMC_STA_RXFIFOE   SDMMC_STA_RXFIFOE_Msk
	Receive FIFO empty.
#define	SDMMC_STA_BUSYD0_Pos   (20U)
#define	SDMMC_STA_BUSYD0_Msk   (0x1UL << SDMMC_STA_BUSYD0_Pos)
	0x00100000
#define	SDMMC_STA_BUSYD0   SDMMC_STA_BUSYD0_Msk
	Inverted value of SDMMC_D0 line (Busy).
#define	SDMMC_STA_BUSYD0END_Pos   (21U)
#define	SDMMC_STA_BUSYD0END_Msk   (0x1UL << SDMMC_STA_BUSYD0END_Pos)
	0x00200000
#define	SDMMC_STA_BUSYD0END   SDMMC_STA_BUSYD0END_Msk
	End of SDMMC_D0 Busy following a CMD response detected.
#define	SDMMC_STA_SDIOIT_Pos   (22U)
#define	SDMMC_STA_SDIOIT_Msk   (0x1UL << SDMMC_STA_SDIOIT_Pos)
	0x00400000
#define	SDMMC_STA_SDIOIT   SDMMC_STA_SDIOIT_Msk
	SDIO interrupt received.
#define	SDMMC_STA_ACKFAIL_Pos   (23U)
#define	SDMMC_STA_ACKFAIL_Msk   (0x1UL << SDMMC_STA_ACKFAIL_Pos)
	0x00800000
#define	SDMMC_STA_ACKFAIL   SDMMC_STA_ACKFAIL_Msk
	Boot Acknowledgment received (BootAck check fail).
#define	SDMMC_STA_ACKTIMEOUT_Pos   (24U)
#define	SDMMC_STA_ACKTIMEOUT_Msk   (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)
	0x01000000
#define	SDMMC_STA_ACKTIMEOUT   SDMMC_STA_ACKTIMEOUT_Msk
	Boot Acknowledgment timeout.
#define	SDMMC_STA_VSWEND_Pos   (25U)
#define	SDMMC_STA_VSWEND_Msk   (0x1UL << SDMMC_STA_VSWEND_Pos)
	0x02000000
#define	SDMMC_STA_VSWEND   SDMMC_STA_VSWEND_Msk
	Voltage switch critical timing section completion.
#define	SDMMC_STA_CKSTOP_Pos   (26U)
#define	SDMMC_STA_CKSTOP_Msk   (0x1UL << SDMMC_STA_CKSTOP_Pos)
	0x04000000
#define	SDMMC_STA_CKSTOP   SDMMC_STA_CKSTOP_Msk
	SDMMC_CK stopped in Voltage switch procedure.
#define	SDMMC_STA_IDMATE_Pos   (27U)
#define	SDMMC_STA_IDMATE_Msk   (0x1UL << SDMMC_STA_IDMATE_Pos)
	0x08000000
#define	SDMMC_STA_IDMATE   SDMMC_STA_IDMATE_Msk
	IDMA transfer error.
#define	SDMMC_STA_IDMABTC_Pos   (28U)
#define	SDMMC_STA_IDMABTC_Msk   (0x1UL << SDMMC_STA_IDMABTC_Pos)
	0x10000000
#define	SDMMC_STA_IDMABTC   SDMMC_STA_IDMABTC_Msk
	IDMA buffer transfer complete.
#define	SDMMC_ICR_CCRCFAILC_Pos   (0U)
#define	SDMMC_ICR_CCRCFAILC_Msk   (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)
	0x00000001
#define	SDMMC_ICR_CCRCFAILC   SDMMC_ICR_CCRCFAILC_Msk
	CCRCFAIL flag clear bit.
#define	SDMMC_ICR_DCRCFAILC_Pos   (1U)
#define	SDMMC_ICR_DCRCFAILC_Msk   (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)
	0x00000002
#define	SDMMC_ICR_DCRCFAILC   SDMMC_ICR_DCRCFAILC_Msk
	DCRCFAIL flag clear bit.
#define	SDMMC_ICR_CTIMEOUTC_Pos   (2U)
#define	SDMMC_ICR_CTIMEOUTC_Msk   (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)
	0x00000004
#define	SDMMC_ICR_CTIMEOUTC   SDMMC_ICR_CTIMEOUTC_Msk
	CTIMEOUT flag clear bit.
#define	SDMMC_ICR_DTIMEOUTC_Pos   (3U)
#define	SDMMC_ICR_DTIMEOUTC_Msk   (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)
	0x00000008
#define	SDMMC_ICR_DTIMEOUTC   SDMMC_ICR_DTIMEOUTC_Msk
	DTIMEOUT flag clear bit.
#define	SDMMC_ICR_TXUNDERRC_Pos   (4U)
#define	SDMMC_ICR_TXUNDERRC_Msk   (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)
	0x00000010
#define	SDMMC_ICR_TXUNDERRC   SDMMC_ICR_TXUNDERRC_Msk
	TXUNDERR flag clear bit.
#define	SDMMC_ICR_RXOVERRC_Pos   (5U)
#define	SDMMC_ICR_RXOVERRC_Msk   (0x1UL << SDMMC_ICR_RXOVERRC_Pos)
	0x00000020
#define	SDMMC_ICR_RXOVERRC   SDMMC_ICR_RXOVERRC_Msk
	RXOVERR flag clear bit.
#define	SDMMC_ICR_CMDRENDC_Pos   (6U)
#define	SDMMC_ICR_CMDRENDC_Msk   (0x1UL << SDMMC_ICR_CMDRENDC_Pos)
	0x00000040
#define	SDMMC_ICR_CMDRENDC   SDMMC_ICR_CMDRENDC_Msk
	CMDREND flag clear bit.
#define	SDMMC_ICR_CMDSENTC_Pos   (7U)
#define	SDMMC_ICR_CMDSENTC_Msk   (0x1UL << SDMMC_ICR_CMDSENTC_Pos)
	0x00000080
#define	SDMMC_ICR_CMDSENTC   SDMMC_ICR_CMDSENTC_Msk
	CMDSENT flag clear bit.
#define	SDMMC_ICR_DATAENDC_Pos   (8U)
#define	SDMMC_ICR_DATAENDC_Msk   (0x1UL << SDMMC_ICR_DATAENDC_Pos)
	0x00000100
#define	SDMMC_ICR_DATAENDC   SDMMC_ICR_DATAENDC_Msk
	DATAEND flag clear bit.
#define	SDMMC_ICR_DHOLDC_Pos   (9U)
#define	SDMMC_ICR_DHOLDC_Msk   (0x1UL << SDMMC_ICR_DHOLDC_Pos)
	0x00000200
#define	SDMMC_ICR_DHOLDC   SDMMC_ICR_DHOLDC_Msk
	DHOLD flag clear bit.
#define	SDMMC_ICR_DBCKENDC_Pos   (10U)
#define	SDMMC_ICR_DBCKENDC_Msk   (0x1UL << SDMMC_ICR_DBCKENDC_Pos)
	0x00000400
#define	SDMMC_ICR_DBCKENDC   SDMMC_ICR_DBCKENDC_Msk
	DBCKEND flag clear bit.
#define	SDMMC_ICR_DABORTC_Pos   (11U)
#define	SDMMC_ICR_DABORTC_Msk   (0x1UL << SDMMC_ICR_DABORTC_Pos)
	0x00000800
#define	SDMMC_ICR_DABORTC   SDMMC_ICR_DABORTC_Msk
	DABORTC flag clear bit.
#define	SDMMC_ICR_BUSYD0ENDC_Pos   (21U)
#define	SDMMC_ICR_BUSYD0ENDC_Msk   (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)
	0x00200000
#define	SDMMC_ICR_BUSYD0ENDC   SDMMC_ICR_BUSYD0ENDC_Msk
	BUSYD0ENDC flag clear bit.
#define	SDMMC_ICR_SDIOITC_Pos   (22U)
#define	SDMMC_ICR_SDIOITC_Msk   (0x1UL << SDMMC_ICR_SDIOITC_Pos)
	0x00400000
#define	SDMMC_ICR_SDIOITC   SDMMC_ICR_SDIOITC_Msk
	SDIOIT flag clear bit.
#define	SDMMC_ICR_ACKFAILC_Pos   (23U)
#define	SDMMC_ICR_ACKFAILC_Msk   (0x1UL << SDMMC_ICR_ACKFAILC_Pos)
	0x00800000
#define	SDMMC_ICR_ACKFAILC   SDMMC_ICR_ACKFAILC_Msk
	ACKFAILC flag clear bit.
#define	SDMMC_ICR_ACKTIMEOUTC_Pos   (24U)
#define	SDMMC_ICR_ACKTIMEOUTC_Msk   (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)
	0x01000000
#define	SDMMC_ICR_ACKTIMEOUTC   SDMMC_ICR_ACKTIMEOUTC_Msk
	ACKTIMEOUTC flag clear bit.
#define	SDMMC_ICR_VSWENDC_Pos   (25U)
#define	SDMMC_ICR_VSWENDC_Msk   (0x1UL << SDMMC_ICR_VSWENDC_Pos)
	0x02000000
#define	SDMMC_ICR_VSWENDC   SDMMC_ICR_VSWENDC_Msk
	VSWENDC flag clear bit.
#define	SDMMC_ICR_CKSTOPC_Pos   (26U)
#define	SDMMC_ICR_CKSTOPC_Msk   (0x1UL << SDMMC_ICR_CKSTOPC_Pos)
	0x04000000
#define	SDMMC_ICR_CKSTOPC   SDMMC_ICR_CKSTOPC_Msk
	CKSTOPC flag clear bit.
#define	SDMMC_ICR_IDMATEC_Pos   (27U)
#define	SDMMC_ICR_IDMATEC_Msk   (0x1UL << SDMMC_ICR_IDMATEC_Pos)
	0x08000000
#define	SDMMC_ICR_IDMATEC   SDMMC_ICR_IDMATEC_Msk
	IDMATEC flag clear bit.
#define	SDMMC_ICR_IDMABTCC_Pos   (28U)
#define	SDMMC_ICR_IDMABTCC_Msk   (0x1UL << SDMMC_ICR_IDMABTCC_Pos)
	0x10000000
#define	SDMMC_ICR_IDMABTCC   SDMMC_ICR_IDMABTCC_Msk
	IDMABTCC flag clear bit.
#define	SDMMC_MASK_CCRCFAILIE_Pos   (0U)
#define	SDMMC_MASK_CCRCFAILIE_Msk   (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)
	0x00000001
#define	SDMMC_MASK_CCRCFAILIE   SDMMC_MASK_CCRCFAILIE_Msk
	Command CRC Fail Interrupt Enable.
#define	SDMMC_MASK_DCRCFAILIE_Pos   (1U)
#define	SDMMC_MASK_DCRCFAILIE_Msk   (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)
	0x00000002
#define	SDMMC_MASK_DCRCFAILIE   SDMMC_MASK_DCRCFAILIE_Msk
	Data CRC Fail Interrupt Enable.
#define	SDMMC_MASK_CTIMEOUTIE_Pos   (2U)
#define	SDMMC_MASK_CTIMEOUTIE_Msk   (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)
	0x00000004
#define	SDMMC_MASK_CTIMEOUTIE   SDMMC_MASK_CTIMEOUTIE_Msk
	Command TimeOut Interrupt Enable.
#define	SDMMC_MASK_DTIMEOUTIE_Pos   (3U)
#define	SDMMC_MASK_DTIMEOUTIE_Msk   (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)
	0x00000008
#define	SDMMC_MASK_DTIMEOUTIE   SDMMC_MASK_DTIMEOUTIE_Msk
	Data TimeOut Interrupt Enable.
#define	SDMMC_MASK_TXUNDERRIE_Pos   (4U)
#define	SDMMC_MASK_TXUNDERRIE_Msk   (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)
	0x00000010
#define	SDMMC_MASK_TXUNDERRIE   SDMMC_MASK_TXUNDERRIE_Msk
	Tx FIFO UnderRun Error Interrupt Enable.
#define	SDMMC_MASK_RXOVERRIE_Pos   (5U)
#define	SDMMC_MASK_RXOVERRIE_Msk   (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)
	0x00000020
#define	SDMMC_MASK_RXOVERRIE   SDMMC_MASK_RXOVERRIE_Msk
	Rx FIFO OverRun Error Interrupt Enable.
#define	SDMMC_MASK_CMDRENDIE_Pos   (6U)
#define	SDMMC_MASK_CMDRENDIE_Msk   (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)
	0x00000040
#define	SDMMC_MASK_CMDRENDIE   SDMMC_MASK_CMDRENDIE_Msk
	Command Response Received Interrupt Enable.
#define	SDMMC_MASK_CMDSENTIE_Pos   (7U)
#define	SDMMC_MASK_CMDSENTIE_Msk   (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)
	0x00000080
#define	SDMMC_MASK_CMDSENTIE   SDMMC_MASK_CMDSENTIE_Msk
	Command Sent Interrupt Enable.
#define	SDMMC_MASK_DATAENDIE_Pos   (8U)
#define	SDMMC_MASK_DATAENDIE_Msk   (0x1UL << SDMMC_MASK_DATAENDIE_Pos)
	0x00000100
#define	SDMMC_MASK_DATAENDIE   SDMMC_MASK_DATAENDIE_Msk
	Data End Interrupt Enable.
#define	SDMMC_MASK_DHOLDIE_Pos   (9U)
#define	SDMMC_MASK_DHOLDIE_Msk   (0x1UL << SDMMC_MASK_DHOLDIE_Pos)
	0x00000200
#define	SDMMC_MASK_DHOLDIE   SDMMC_MASK_DHOLDIE_Msk
	Data Hold Interrupt Enable.
#define	SDMMC_MASK_DBCKENDIE_Pos   (10U)
#define	SDMMC_MASK_DBCKENDIE_Msk   (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)
	0x00000400
#define	SDMMC_MASK_DBCKENDIE   SDMMC_MASK_DBCKENDIE_Msk
	Data Block End Interrupt Enable.
#define	SDMMC_MASK_DABORTIE_Pos   (11U)
#define	SDMMC_MASK_DABORTIE_Msk   (0x1UL << SDMMC_MASK_DABORTIE_Pos)
	0x00000800
#define	SDMMC_MASK_DABORTIE   SDMMC_MASK_DABORTIE_Msk
	Data transfer aborted interrupt enable.
#define	SDMMC_MASK_TXFIFOHEIE_Pos   (14U)
#define	SDMMC_MASK_TXFIFOHEIE_Msk   (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)
	0x00004000
#define	SDMMC_MASK_TXFIFOHEIE   SDMMC_MASK_TXFIFOHEIE_Msk
	Tx FIFO Half Empty interrupt Enable.
#define	SDMMC_MASK_RXFIFOHFIE_Pos   (15U)
#define	SDMMC_MASK_RXFIFOHFIE_Msk   (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)
	0x00008000
#define	SDMMC_MASK_RXFIFOHFIE   SDMMC_MASK_RXFIFOHFIE_Msk
	Rx FIFO Half Full interrupt Enable.
#define	SDMMC_MASK_RXFIFOFIE_Pos   (17U)
#define	SDMMC_MASK_RXFIFOFIE_Msk   (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)
	0x00020000
#define	SDMMC_MASK_RXFIFOFIE   SDMMC_MASK_RXFIFOFIE_Msk
	Rx FIFO Full interrupt Enable.
#define	SDMMC_MASK_TXFIFOEIE_Pos   (18U)
#define	SDMMC_MASK_TXFIFOEIE_Msk   (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)
	0x00040000
#define	SDMMC_MASK_TXFIFOEIE   SDMMC_MASK_TXFIFOEIE_Msk
	Tx FIFO Empty interrupt Enable.
#define	SDMMC_MASK_BUSYD0ENDIE_Pos   (21U)
#define	SDMMC_MASK_BUSYD0ENDIE_Msk   (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos)
	0x00200000
#define	SDMMC_MASK_BUSYD0ENDIE   SDMMC_MASK_BUSYD0ENDIE_Msk
	BUSYD0ENDIE interrupt Enable.
#define	SDMMC_MASK_SDIOITIE_Pos   (22U)
#define	SDMMC_MASK_SDIOITIE_Msk   (0x1UL << SDMMC_MASK_SDIOITIE_Pos)
	0x00400000
#define	SDMMC_MASK_SDIOITIE   SDMMC_MASK_SDIOITIE_Msk
	SDMMC Mode Interrupt Received interrupt Enable.
#define	SDMMC_MASK_ACKFAILIE_Pos   (23U)
#define	SDMMC_MASK_ACKFAILIE_Msk   (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)
	0x00800000
#define	SDMMC_MASK_ACKFAILIE   SDMMC_MASK_ACKFAILIE_Msk
	Acknowledgment Fail Interrupt Enable.
#define	SDMMC_MASK_ACKTIMEOUTIE_Pos   (24U)
#define	SDMMC_MASK_ACKTIMEOUTIE_Msk   (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos)
	0x01000000
#define	SDMMC_MASK_ACKTIMEOUTIE   SDMMC_MASK_ACKTIMEOUTIE_Msk
	Acknowledgment timeout Interrupt Enable.
#define	SDMMC_MASK_VSWENDIE_Pos   (25U)
#define	SDMMC_MASK_VSWENDIE_Msk   (0x1UL << SDMMC_MASK_VSWENDIE_Pos)
	0x02000000
#define	SDMMC_MASK_VSWENDIE   SDMMC_MASK_VSWENDIE_Msk
	Voltage switch critical timing section completion Interrupt Enable.
#define	SDMMC_MASK_CKSTOPIE_Pos   (26U)
#define	SDMMC_MASK_CKSTOPIE_Msk   (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)
	0x04000000
#define	SDMMC_MASK_CKSTOPIE   SDMMC_MASK_CKSTOPIE_Msk
	Voltage Switch clock stopped Interrupt Enable.
#define	SDMMC_MASK_IDMABTCIE_Pos   (28U)
#define	SDMMC_MASK_IDMABTCIE_Msk   (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)
	0x10000000
#define	SDMMC_MASK_IDMABTCIE   SDMMC_MASK_IDMABTCIE_Msk
	IDMA buffer transfer complete Interrupt Enable.
#define	SDMMC_ACKTIME_ACKTIME_Pos   (0U)
#define	SDMMC_ACKTIME_ACKTIME_Msk   (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos)
	0x01FFFFFF
#define	SDMMC_ACKTIME_ACKTIME   SDMMC_ACKTIME_ACKTIME_Msk
	Boot acknowledgment timeout period.
#define	SDMMC_FIFO_FIFODATA_Pos   (0U)
#define	SDMMC_FIFO_FIFODATA_Msk   (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos)
	0xFFFFFFFF
#define	SDMMC_FIFO_FIFODATA   SDMMC_FIFO_FIFODATA_Msk
	Receive and transmit FIFO data.
#define	SDMMC_IDMA_IDMAEN_Pos   (0U)
#define	SDMMC_IDMA_IDMAEN_Msk   (0x1UL << SDMMC_IDMA_IDMAEN_Pos)
	0x00000001
#define	SDMMC_IDMA_IDMAEN   SDMMC_IDMA_IDMAEN_Msk
	Enable the internal DMA of the SDMMC peripheral.
#define	SDMMC_IDMA_IDMABMODE_Pos   (1U)
#define	SDMMC_IDMA_IDMABMODE_Msk   (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)
	0x00000002
#define	SDMMC_IDMA_IDMABMODE   SDMMC_IDMA_IDMABMODE_Msk
	Enable double buffer mode for IDMA.
#define	SDMMC_IDMA_IDMABACT_Pos   (2U)
#define	SDMMC_IDMA_IDMABACT_Msk   (0x1UL << SDMMC_IDMA_IDMABACT_Pos)
	0x00000004
#define	SDMMC_IDMA_IDMABACT   SDMMC_IDMA_IDMABACT_Msk
	Uses buffer 1 when double buffer mode is selected.
#define	SDMMC_IDMABSIZE_IDMABNDT_Pos   (5U)
#define	SDMMC_IDMABSIZE_IDMABNDT_Msk   (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos)
	0x00001FE0
#define	SDMMC_IDMABSIZE_IDMABNDT   SDMMC_IDMABSIZE_IDMABNDT_Msk
	Number of transfers per buffer.
#define	SDMMC_IDMABASE0_IDMABASE0   (0xFFFFFFFFU)
	Buffer 0 memory base address.
#define	SDMMC_IDMABASE1_IDMABASE1   (0xFFFFFFFFU)
	Buffer 1 memory base address.
#define	DLYB_CR_DEN_Pos   (0U)
#define	DLYB_CR_DEN_Msk   (0x1UL << DLYB_CR_DEN_Pos)
	0x00000001
#define	DLYB_CR_DEN   DLYB_CR_DEN_Msk
	Delay Block enable.
#define	DLYB_CR_SEN_Pos   (1U)
#define	DLYB_CR_SEN_Msk   (0x1UL << DLYB_CR_SEN_Pos)
	0x00000002
#define	DLYB_CR_SEN   DLYB_CR_SEN_Msk
	Sampler length enable.
#define	DLYB_CFGR_SEL_Pos   (0U)
#define	DLYB_CFGR_SEL_Msk   (0xFUL << DLYB_CFGR_SEL_Pos)
	0x0000000F
#define	DLYB_CFGR_SEL   DLYB_CFGR_SEL_Msk
	Select the phase for the Output clock[3:0].
#define	DLYB_CFGR_SEL_0   (0x1UL << DLYB_CFGR_SEL_Pos)
	0x00000001
#define	DLYB_CFGR_SEL_1   (0x2UL << DLYB_CFGR_SEL_Pos)
	0x00000002
#define	DLYB_CFGR_SEL_2   (0x3UL << DLYB_CFGR_SEL_Pos)
	0x00000003
#define	DLYB_CFGR_SEL_3   (0x8UL << DLYB_CFGR_SEL_Pos)
	0x00000008
#define	DLYB_CFGR_UNIT_Pos   (8U)
#define	DLYB_CFGR_UNIT_Msk   (0x7FUL << DLYB_CFGR_UNIT_Pos)
	0x00007F00
#define	DLYB_CFGR_UNIT   DLYB_CFGR_UNIT_Msk
	Delay Defines the delay of a Unit delay cell[6:0].
#define	DLYB_CFGR_UNIT_0   (0x01UL << DLYB_CFGR_UNIT_Pos)
	0x00000100
#define	DLYB_CFGR_UNIT_1   (0x02UL << DLYB_CFGR_UNIT_Pos)
	0x00000200
#define	DLYB_CFGR_UNIT_2   (0x04UL << DLYB_CFGR_UNIT_Pos)
	0x00000400
#define	DLYB_CFGR_UNIT_3   (0x08UL << DLYB_CFGR_UNIT_Pos)
	0x00000800
#define	DLYB_CFGR_UNIT_4   (0x10UL << DLYB_CFGR_UNIT_Pos)
	0x00001000
#define	DLYB_CFGR_UNIT_5   (0x20UL << DLYB_CFGR_UNIT_Pos)
	0x00002000
#define	DLYB_CFGR_UNIT_6   (0x40UL << DLYB_CFGR_UNIT_Pos)
	0x00004000
#define	DLYB_CFGR_LNG_Pos   (16U)
#define	DLYB_CFGR_LNG_Msk   (0xFFFUL << DLYB_CFGR_LNG_Pos)
	0x0FFF0000
#define	DLYB_CFGR_LNG   DLYB_CFGR_LNG_Msk
	Delay line length value[11:0].
#define	DLYB_CFGR_LNG_0   (0x001UL << DLYB_CFGR_LNG_Pos)
	0x00010000
#define	DLYB_CFGR_LNG_1   (0x002UL << DLYB_CFGR_LNG_Pos)
	0x00020000
#define	DLYB_CFGR_LNG_2   (0x004UL << DLYB_CFGR_LNG_Pos)
	0x00040000
#define	DLYB_CFGR_LNG_3   (0x008UL << DLYB_CFGR_LNG_Pos)
	0x00080000
#define	DLYB_CFGR_LNG_4   (0x010UL << DLYB_CFGR_LNG_Pos)
	0x00100000
#define	DLYB_CFGR_LNG_5   (0x020UL << DLYB_CFGR_LNG_Pos)
	0x00200000
#define	DLYB_CFGR_LNG_6   (0x040UL << DLYB_CFGR_LNG_Pos)
	0x00400000
#define	DLYB_CFGR_LNG_7   (0x080UL << DLYB_CFGR_LNG_Pos)
	0x00800000
#define	DLYB_CFGR_LNG_8   (0x100UL << DLYB_CFGR_LNG_Pos)
	0x01000000
#define	DLYB_CFGR_LNG_9   (0x200UL << DLYB_CFGR_LNG_Pos)
	0x02000000
#define	DLYB_CFGR_LNG_10   (0x400UL << DLYB_CFGR_LNG_Pos)
	0x04000000
#define	DLYB_CFGR_LNG_11   (0x800UL << DLYB_CFGR_LNG_Pos)
	0x08000000
#define	DLYB_CFGR_LNGF_Pos   (31U)
#define	DLYB_CFGR_LNGF_Msk   (0x1UL << DLYB_CFGR_LNGF_Pos)
	0x80000000
#define	DLYB_CFGR_LNGF   DLYB_CFGR_LNGF_Msk
	Length valid flag.
#define	SPI_SPI6I2S_SUPPORT
	SPI6 I2S support feature.
#define	SPI_CR1_SPE_Pos   (0U)
#define	SPI_CR1_SPE_Msk   (0x1UL << SPI_CR1_SPE_Pos)
	0x00000001
#define	SPI_CR1_SPE   SPI_CR1_SPE_Msk
	Serial Peripheral Enable.
#define	SPI_CR1_MASRX_Pos   (8U)
#define	SPI_CR1_MASRX_Msk   (0x1UL << SPI_CR1_MASRX_Pos)
	0x00000100
#define	SPI_CR1_MASRX   SPI_CR1_MASRX_Msk
	Master automatic SUSP in Receive mode.
#define	SPI_CR1_CSTART_Pos   (9U)
#define	SPI_CR1_CSTART_Msk   (0x1UL << SPI_CR1_CSTART_Pos)
	0x00000200
#define	SPI_CR1_CSTART   SPI_CR1_CSTART_Msk
	Master transfer start.
#define	SPI_CR1_CSUSP_Pos   (10U)
#define	SPI_CR1_CSUSP_Msk   (0x1UL << SPI_CR1_CSUSP_Pos)
	0x00000400
#define	SPI_CR1_CSUSP   SPI_CR1_CSUSP_Msk
	Master SUSPend request.
#define	SPI_CR1_HDDIR_Pos   (11U)
#define	SPI_CR1_HDDIR_Msk   (0x1UL << SPI_CR1_HDDIR_Pos)
	0x00000800
#define	SPI_CR1_HDDIR   SPI_CR1_HDDIR_Msk
	Rx/Tx direction at Half-duplex mode.
#define	SPI_CR1_SSI_Pos   (12U)
#define	SPI_CR1_SSI_Msk   (0x1UL << SPI_CR1_SSI_Pos)
	0x00001000
#define	SPI_CR1_SSI   SPI_CR1_SSI_Msk
	Internal SS signal input level.
#define	SPI_CR1_CRC33_17_Pos   (13U)
#define	SPI_CR1_CRC33_17_Msk   (0x1UL << SPI_CR1_CRC33_17_Pos)
	0x00002000
#define	SPI_CR1_CRC33_17   SPI_CR1_CRC33_17_Msk
	32-bit CRC polynomial configuration
#define	SPI_CR1_RCRCINI_Pos   (14U)
#define	SPI_CR1_RCRCINI_Msk   (0x1UL << SPI_CR1_RCRCINI_Pos)
	0x00004000
#define	SPI_CR1_RCRCINI   SPI_CR1_RCRCINI_Msk
	CRC init pattern control for receiver.
#define	SPI_CR1_TCRCINI_Pos   (15U)
#define	SPI_CR1_TCRCINI_Msk   (0x1UL << SPI_CR1_TCRCINI_Pos)
	0x00008000
#define	SPI_CR1_TCRCINI   SPI_CR1_TCRCINI_Msk
	CRC init pattern control for transmitter.
#define	SPI_CR1_IOLOCK_Pos   (16U)
#define	SPI_CR1_IOLOCK_Msk   (0x1UL << SPI_CR1_IOLOCK_Pos)
	0x00010000
#define	SPI_CR1_IOLOCK   SPI_CR1_IOLOCK_Msk
	Locking the AF configuration of associated IOs.
#define	SPI_CR2_TSER_Pos   (16U)
#define	SPI_CR2_TSER_Msk   (0xFFFFUL << SPI_CR2_TSER_Pos)
	0xFFFF0000
#define	SPI_CR2_TSER   SPI_CR2_TSER_Msk
	Number of data transfer extension.
#define	SPI_CR2_TSIZE_Pos   (0U)
#define	SPI_CR2_TSIZE_Msk   (0xFFFFUL << SPI_CR2_TSIZE_Pos)
	0x0000FFFF
#define	SPI_CR2_TSIZE   SPI_CR2_TSIZE_Msk
	Number of data at current transfer.
#define	SPI_CFG1_DSIZE_Pos   (0U)
#define	SPI_CFG1_DSIZE_Msk   (0x1FUL << SPI_CFG1_DSIZE_Pos)
	0x0000001F
#define	SPI_CFG1_DSIZE   SPI_CFG1_DSIZE_Msk
	DSIZE[4:0]: Bits number in single SPI data frame.
#define	SPI_CFG1_DSIZE_0   (0x01UL << SPI_CFG1_DSIZE_Pos)
	0x00000001
#define	SPI_CFG1_DSIZE_1   (0x02UL << SPI_CFG1_DSIZE_Pos)
	0x00000002
#define	SPI_CFG1_DSIZE_2   (0x04UL << SPI_CFG1_DSIZE_Pos)
	0x00000004
#define	SPI_CFG1_DSIZE_3   (0x08UL << SPI_CFG1_DSIZE_Pos)
	0x00000008
#define	SPI_CFG1_DSIZE_4   (0x10UL << SPI_CFG1_DSIZE_Pos)
	0x00000010
#define	SPI_CFG1_FTHLV_Pos   (5U)
#define	SPI_CFG1_FTHLV_Msk   (0xFUL << SPI_CFG1_FTHLV_Pos)
	0x000001E0
#define	SPI_CFG1_FTHLV   SPI_CFG1_FTHLV_Msk
	FTHVL [3:0]: FIFO threshold level.
#define	SPI_CFG1_FTHLV_0   (0x1UL << SPI_CFG1_FTHLV_Pos)
	0x00000020
#define	SPI_CFG1_FTHLV_1   (0x2UL << SPI_CFG1_FTHLV_Pos)
	0x00000040
#define	SPI_CFG1_FTHLV_2   (0x4UL << SPI_CFG1_FTHLV_Pos)
	0x00000080
#define	SPI_CFG1_FTHLV_3   (0x8UL << SPI_CFG1_FTHLV_Pos)
	0x00000100
#define	SPI_CFG1_UDRCFG_Pos   (9U)
#define	SPI_CFG1_UDRCFG_Msk   (0x3UL << SPI_CFG1_UDRCFG_Pos)
	0x00000600
#define	SPI_CFG1_UDRCFG   SPI_CFG1_UDRCFG_Msk
	UDRCFG[1:0]: Behavior of transmitter at underrun.
#define	SPI_CFG1_UDRCFG_0   (0x1UL << SPI_CFG1_UDRCFG_Pos)
	0x00000200
#define	SPI_CFG1_UDRCFG_1   (0x2UL << SPI_CFG1_UDRCFG_Pos)
	0x00000400
#define	SPI_CFG1_UDRDET_Pos   (11U)
#define	SPI_CFG1_UDRDET_Msk   (0x3UL << SPI_CFG1_UDRDET_Pos)
	0x00001800
#define	SPI_CFG1_UDRDET   SPI_CFG1_UDRDET_Msk
	UDRDET[1:0]: Detection of underrun condition.
#define	SPI_CFG1_UDRDET_0   (0x1UL << SPI_CFG1_UDRDET_Pos)
	0x00000800
#define	SPI_CFG1_UDRDET_1   (0x2UL << SPI_CFG1_UDRDET_Pos)
	0x00001000
#define	SPI_CFG1_RXDMAEN_Pos   (14U)
#define	SPI_CFG1_RXDMAEN_Msk   (0x1UL << SPI_CFG1_RXDMAEN_Pos)
	0x00004000
#define	SPI_CFG1_RXDMAEN   SPI_CFG1_RXDMAEN_Msk
	Rx DMA stream enable.
#define	SPI_CFG1_TXDMAEN_Pos   (15U)
#define	SPI_CFG1_TXDMAEN_Msk   (0x1UL << SPI_CFG1_TXDMAEN_Pos)
	0x00008000
#define	SPI_CFG1_TXDMAEN   SPI_CFG1_TXDMAEN_Msk
	Tx DMA stream enable.
#define	SPI_CFG1_CRCSIZE_Pos   (16U)
#define	SPI_CFG1_CRCSIZE_Msk   (0x1FUL << SPI_CFG1_CRCSIZE_Pos)
	0x001F0000
#define	SPI_CFG1_CRCSIZE   SPI_CFG1_CRCSIZE_Msk
	CRCSIZE [4:0]: Length of CRC frame.
#define	SPI_CFG1_CRCSIZE_0   (0x01UL << SPI_CFG1_CRCSIZE_Pos)
	0x00010000
#define	SPI_CFG1_CRCSIZE_1   (0x02UL << SPI_CFG1_CRCSIZE_Pos)
	0x00020000
#define	SPI_CFG1_CRCSIZE_2   (0x04UL << SPI_CFG1_CRCSIZE_Pos)
	0x00040000
#define	SPI_CFG1_CRCSIZE_3   (0x08UL << SPI_CFG1_CRCSIZE_Pos)
	0x00080000
#define	SPI_CFG1_CRCSIZE_4   (0x10UL << SPI_CFG1_CRCSIZE_Pos)
	0x00100000
#define	SPI_CFG1_CRCEN_Pos   (22U)
#define	SPI_CFG1_CRCEN_Msk   (0x1UL << SPI_CFG1_CRCEN_Pos)
	0x00400000
#define	SPI_CFG1_CRCEN   SPI_CFG1_CRCEN_Msk
	Hardware CRC computation enable.
#define	SPI_CFG1_MBR_Pos   (28U)
#define	SPI_CFG1_MBR_Msk   (0x7UL << SPI_CFG1_MBR_Pos)
	0x70000000
#define	SPI_CFG1_MBR   SPI_CFG1_MBR_Msk
	Master baud rate.
#define	SPI_CFG1_MBR_0   (0x1UL << SPI_CFG1_MBR_Pos)
	0x10000000
#define	SPI_CFG1_MBR_1   (0x2UL << SPI_CFG1_MBR_Pos)
	0x20000000
#define	SPI_CFG1_MBR_2   (0x4UL << SPI_CFG1_MBR_Pos)
	0x40000000
#define	SPI_CFG2_MSSI_Pos   (0U)
#define	SPI_CFG2_MSSI_Msk   (0xFUL << SPI_CFG2_MSSI_Pos)
	0x0000000F
#define	SPI_CFG2_MSSI   SPI_CFG2_MSSI_Msk
	Master SS Idleness.
#define	SPI_CFG2_MSSI_0   (0x1UL << SPI_CFG2_MSSI_Pos)
	0x00000001
#define	SPI_CFG2_MSSI_1   (0x2UL << SPI_CFG2_MSSI_Pos)
	0x00000002
#define	SPI_CFG2_MSSI_2   (0x4UL << SPI_CFG2_MSSI_Pos)
	0x00000004
#define	SPI_CFG2_MSSI_3   (0x8UL << SPI_CFG2_MSSI_Pos)
	0x00000008
#define	SPI_CFG2_MIDI_Pos   (4U)
#define	SPI_CFG2_MIDI_Msk   (0xFUL << SPI_CFG2_MIDI_Pos)
	0x000000F0
#define	SPI_CFG2_MIDI   SPI_CFG2_MIDI_Msk
	Master Inter-Data Idleness.
#define	SPI_CFG2_MIDI_0   (0x1UL << SPI_CFG2_MIDI_Pos)
	0x00000010
#define	SPI_CFG2_MIDI_1   (0x2UL << SPI_CFG2_MIDI_Pos)
	0x00000020
#define	SPI_CFG2_MIDI_2   (0x4UL << SPI_CFG2_MIDI_Pos)
	0x00000040
#define	SPI_CFG2_MIDI_3   (0x8UL << SPI_CFG2_MIDI_Pos)
	0x00000080
#define	SPI_CFG2_IOSWP_Pos   (15U)
#define	SPI_CFG2_IOSWP_Msk   (0x1UL << SPI_CFG2_IOSWP_Pos)
	0x00008000
#define	SPI_CFG2_IOSWP   SPI_CFG2_IOSWP_Msk
	Swap functionality of MISO and MOSI pins.
#define	SPI_CFG2_COMM_Pos   (17U)
#define	SPI_CFG2_COMM_Msk   (0x3UL << SPI_CFG2_COMM_Pos)
	0x00060000
#define	SPI_CFG2_COMM   SPI_CFG2_COMM_Msk
	COMM [1:0]: SPI Communication Mode.
#define	SPI_CFG2_COMM_0   (0x1UL << SPI_CFG2_COMM_Pos)
	0x00020000
#define	SPI_CFG2_COMM_1   (0x2UL << SPI_CFG2_COMM_Pos)
	0x00040000
#define	SPI_CFG2_SP_Pos   (19U)
#define	SPI_CFG2_SP_Msk   (0x7UL << SPI_CFG2_SP_Pos)
	0x00380000
#define	SPI_CFG2_SP   SPI_CFG2_SP_Msk
	SP[2:0]: Serial Protocol.
#define	SPI_CFG2_SP_0   (0x1UL << SPI_CFG2_SP_Pos)
	0x00080000
#define	SPI_CFG2_SP_1   (0x2UL << SPI_CFG2_SP_Pos)
	0x00100000
#define	SPI_CFG2_SP_2   (0x4UL << SPI_CFG2_SP_Pos)
	0x00200000
#define	SPI_CFG2_MASTER_Pos   (22U)
#define	SPI_CFG2_MASTER_Msk   (0x1UL << SPI_CFG2_MASTER_Pos)
	0x00400000
#define	SPI_CFG2_MASTER   SPI_CFG2_MASTER_Msk
	SPI Master.
#define	SPI_CFG2_LSBFRST_Pos   (23U)
#define	SPI_CFG2_LSBFRST_Msk   (0x1UL << SPI_CFG2_LSBFRST_Pos)
	0x00800000
#define	SPI_CFG2_LSBFRST   SPI_CFG2_LSBFRST_Msk
	Data frame format.
#define	SPI_CFG2_CPHA_Pos   (24U)
#define	SPI_CFG2_CPHA_Msk   (0x1UL << SPI_CFG2_CPHA_Pos)
	0x01000000
#define	SPI_CFG2_CPHA   SPI_CFG2_CPHA_Msk
	Clock Phase.
#define	SPI_CFG2_CPOL_Pos   (25U)
#define	SPI_CFG2_CPOL_Msk   (0x1UL << SPI_CFG2_CPOL_Pos)
	0x02000000
#define	SPI_CFG2_CPOL   SPI_CFG2_CPOL_Msk
	Clock Polarity.
#define	SPI_CFG2_SSM_Pos   (26U)
#define	SPI_CFG2_SSM_Msk   (0x1UL << SPI_CFG2_SSM_Pos)
	0x04000000
#define	SPI_CFG2_SSM   SPI_CFG2_SSM_Msk
	Software slave management.
#define	SPI_CFG2_SSIOP_Pos   (28U)
#define	SPI_CFG2_SSIOP_Msk   (0x1UL << SPI_CFG2_SSIOP_Pos)
	0x10000000
#define	SPI_CFG2_SSIOP   SPI_CFG2_SSIOP_Msk
	SS input/output polarity.
#define	SPI_CFG2_SSOE_Pos   (29U)
#define	SPI_CFG2_SSOE_Msk   (0x1UL << SPI_CFG2_SSOE_Pos)
	0x20000000
#define	SPI_CFG2_SSOE   SPI_CFG2_SSOE_Msk
	SS output enable.
#define	SPI_CFG2_SSOM_Pos   (30U)
#define	SPI_CFG2_SSOM_Msk   (0x1UL << SPI_CFG2_SSOM_Pos)
	0x40000000
#define	SPI_CFG2_SSOM   SPI_CFG2_SSOM_Msk
	SS output management in master mode.
#define	SPI_CFG2_AFCNTR_Pos   (31U)
#define	SPI_CFG2_AFCNTR_Msk   (0x1UL << SPI_CFG2_AFCNTR_Pos)
	0x80000000
#define	SPI_CFG2_AFCNTR   SPI_CFG2_AFCNTR_Msk
	Alternate function GPIOs control.
#define	SPI_IER_RXPIE_Pos   (0U)
#define	SPI_IER_RXPIE_Msk   (0x1UL << SPI_IER_RXPIE_Pos)
	0x00000001
#define	SPI_IER_RXPIE   SPI_IER_RXPIE_Msk
	RXP Interrupt Enable.
#define	SPI_IER_TXPIE_Pos   (1U)
#define	SPI_IER_TXPIE_Msk   (0x1UL << SPI_IER_TXPIE_Pos)
	0x00000002
#define	SPI_IER_TXPIE   SPI_IER_TXPIE_Msk
	TXP interrupt enable.
#define	SPI_IER_DXPIE_Pos   (2U)
#define	SPI_IER_DXPIE_Msk   (0x1UL << SPI_IER_DXPIE_Pos)
	0x00000004
#define	SPI_IER_DXPIE   SPI_IER_DXPIE_Msk
	DXP interrupt enable.
#define	SPI_IER_EOTIE_Pos   (3U)
#define	SPI_IER_EOTIE_Msk   (0x1UL << SPI_IER_EOTIE_Pos)
	0x00000008
#define	SPI_IER_EOTIE   SPI_IER_EOTIE_Msk
	EOT/SUSP/TXC interrupt enable.
#define	SPI_IER_TXTFIE_Pos   (4U)
#define	SPI_IER_TXTFIE_Msk   (0x1UL << SPI_IER_TXTFIE_Pos)
	0x00000010
#define	SPI_IER_TXTFIE   SPI_IER_TXTFIE_Msk
	TXTF interrupt enable.
#define	SPI_IER_UDRIE_Pos   (5U)
#define	SPI_IER_UDRIE_Msk   (0x1UL << SPI_IER_UDRIE_Pos)
	0x00000020
#define	SPI_IER_UDRIE   SPI_IER_UDRIE_Msk
	UDR interrupt enable.
#define	SPI_IER_OVRIE_Pos   (6U)
#define	SPI_IER_OVRIE_Msk   (0x1UL << SPI_IER_OVRIE_Pos)
	0x00000040
#define	SPI_IER_OVRIE   SPI_IER_OVRIE_Msk
	OVR interrupt enable.
#define	SPI_IER_CRCEIE_Pos   (7U)
#define	SPI_IER_CRCEIE_Msk   (0x1UL << SPI_IER_CRCEIE_Pos)
	0x00000080
#define	SPI_IER_CRCEIE   SPI_IER_CRCEIE_Msk
	CRCE interrupt enable.
#define	SPI_IER_TIFREIE_Pos   (8U)
#define	SPI_IER_TIFREIE_Msk   (0x1UL << SPI_IER_TIFREIE_Pos)
	0x00000100
#define	SPI_IER_TIFREIE   SPI_IER_TIFREIE_Msk
	TI Frame Error interrupt enable.
#define	SPI_IER_MODFIE_Pos   (9U)
#define	SPI_IER_MODFIE_Msk   (0x1UL << SPI_IER_MODFIE_Pos)
	0x00000200
#define	SPI_IER_MODFIE   SPI_IER_MODFIE_Msk
	MODF interrupt enable.
#define	SPI_IER_TSERFIE_Pos   (10U)
#define	SPI_IER_TSERFIE_Msk   (0x1UL << SPI_IER_TSERFIE_Pos)
	0x00000400
#define	SPI_IER_TSERFIE   SPI_IER_TSERFIE_Msk
	TSERF interrupt enable.
#define	SPI_SR_RXP_Pos   (0U)
#define	SPI_SR_RXP_Msk   (0x1UL << SPI_SR_RXP_Pos)
	0x00000001
#define	SPI_SR_RXP   SPI_SR_RXP_Msk
	Rx-Packet available.
#define	SPI_SR_TXP_Pos   (1U)
#define	SPI_SR_TXP_Msk   (0x1UL << SPI_SR_TXP_Pos)
	0x00000002
#define	SPI_SR_TXP   SPI_SR_TXP_Msk
	Tx-Packet space available.
#define	SPI_SR_DXP_Pos   (2U)
#define	SPI_SR_DXP_Msk   (0x1UL << SPI_SR_DXP_Pos)
	0x00000004
#define	SPI_SR_DXP   SPI_SR_DXP_Msk
	Duplex Packet available.
#define	SPI_SR_EOT_Pos   (3U)
#define	SPI_SR_EOT_Msk   (0x1UL << SPI_SR_EOT_Pos)
	0x00000008
#define	SPI_SR_EOT   SPI_SR_EOT_Msk
	Duplex Packet available.
#define	SPI_SR_TXTF_Pos   (4U)
#define	SPI_SR_TXTF_Msk   (0x1UL << SPI_SR_TXTF_Pos)
	0x00000010
#define	SPI_SR_TXTF   SPI_SR_TXTF_Msk
	Transmission Transfer Filled.
#define	SPI_SR_UDR_Pos   (5U)
#define	SPI_SR_UDR_Msk   (0x1UL << SPI_SR_UDR_Pos)
	0x00000020
#define	SPI_SR_UDR   SPI_SR_UDR_Msk
	UDR at Slave transmission.
#define	SPI_SR_OVR_Pos   (6U)
#define	SPI_SR_OVR_Msk   (0x1UL << SPI_SR_OVR_Pos)
	0x00000040
#define	SPI_SR_OVR   SPI_SR_OVR_Msk
	Rx-Packet available.
#define	SPI_SR_CRCE_Pos   (7U)
#define	SPI_SR_CRCE_Msk   (0x1UL << SPI_SR_CRCE_Pos)
	0x00000080
#define	SPI_SR_CRCE   SPI_SR_CRCE_Msk
	CRC Error Detected.
#define	SPI_SR_TIFRE_Pos   (8U)
#define	SPI_SR_TIFRE_Msk   (0x1UL << SPI_SR_TIFRE_Pos)
	0x00000100
#define	SPI_SR_TIFRE   SPI_SR_TIFRE_Msk
	TI frame format error Detected.
#define	SPI_SR_MODF_Pos   (9U)
#define	SPI_SR_MODF_Msk   (0x1UL << SPI_SR_MODF_Pos)
	0x00000200
#define	SPI_SR_MODF   SPI_SR_MODF_Msk
	Mode Fault Detected.
#define	SPI_SR_TSERF_Pos   (10U)
#define	SPI_SR_TSERF_Msk   (0x1UL << SPI_SR_TSERF_Pos)
	0x00000400
#define	SPI_SR_TSERF   SPI_SR_TSERF_Msk
	Number of SPI data to be transacted reloaded.
#define	SPI_SR_SUSP_Pos   (11U)
#define	SPI_SR_SUSP_Msk   (0x1UL << SPI_SR_SUSP_Pos)
	0x00000800
#define	SPI_SR_SUSP   SPI_SR_SUSP_Msk
	SUSP is set by hardware.
#define	SPI_SR_TXC_Pos   (12U)
#define	SPI_SR_TXC_Msk   (0x1UL << SPI_SR_TXC_Pos)
	0x00001000
#define	SPI_SR_TXC   SPI_SR_TXC_Msk
	TxFIFO transmission complete.
#define	SPI_SR_RXPLVL_Pos   (13U)
#define	SPI_SR_RXPLVL_Msk   (0x3UL << SPI_SR_RXPLVL_Pos)
	0x00006000
#define	SPI_SR_RXPLVL   SPI_SR_RXPLVL_Msk
	RxFIFO Packing Level.
#define	SPI_SR_RXPLVL_0   (0x1UL << SPI_SR_RXPLVL_Pos)
	0x00002000
#define	SPI_SR_RXPLVL_1   (0x2UL << SPI_SR_RXPLVL_Pos)
	0x00004000
#define	SPI_SR_RXWNE_Pos   (15U)
#define	SPI_SR_RXWNE_Msk   (0x1UL << SPI_SR_RXWNE_Pos)
	0x00008000
#define	SPI_SR_RXWNE   SPI_SR_RXWNE_Msk
	Rx FIFO Word Not Empty.
#define	SPI_SR_CTSIZE_Pos   (16U)
#define	SPI_SR_CTSIZE_Msk   (0xFFFFUL << SPI_SR_CTSIZE_Pos)
	0xFFFF0000
#define	SPI_SR_CTSIZE   SPI_SR_CTSIZE_Msk
	Number of data frames remaining in TSIZE.
#define	SPI_IFCR_EOTC_Pos   (3U)
#define	SPI_IFCR_EOTC_Msk   (0x1UL << SPI_IFCR_EOTC_Pos)
	0x00000008
#define	SPI_IFCR_EOTC   SPI_IFCR_EOTC_Msk
	End Of Transfer flag clear.
#define	SPI_IFCR_TXTFC_Pos   (4U)
#define	SPI_IFCR_TXTFC_Msk   (0x1UL << SPI_IFCR_TXTFC_Pos)
	0x00000010
#define	SPI_IFCR_TXTFC   SPI_IFCR_TXTFC_Msk
	Transmission Transfer Filled flag clear.
#define	SPI_IFCR_UDRC_Pos   (5U)
#define	SPI_IFCR_UDRC_Msk   (0x1UL << SPI_IFCR_UDRC_Pos)
	0x00000020
#define	SPI_IFCR_UDRC   SPI_IFCR_UDRC_Msk
	Underrun flag clear.
#define	SPI_IFCR_OVRC_Pos   (6U)
#define	SPI_IFCR_OVRC_Msk   (0x1UL << SPI_IFCR_OVRC_Pos)
	0x00000040
#define	SPI_IFCR_OVRC   SPI_IFCR_OVRC_Msk
	Overrun flag clear.
#define	SPI_IFCR_CRCEC_Pos   (7U)
#define	SPI_IFCR_CRCEC_Msk   (0x1UL << SPI_IFCR_CRCEC_Pos)
	0x00000080
#define	SPI_IFCR_CRCEC   SPI_IFCR_CRCEC_Msk
	CRC Error flag clear.
#define	SPI_IFCR_TIFREC_Pos   (8U)
#define	SPI_IFCR_TIFREC_Msk   (0x1UL << SPI_IFCR_TIFREC_Pos)
	0x00000100
#define	SPI_IFCR_TIFREC   SPI_IFCR_TIFREC_Msk
	TI frame format error flag clear.
#define	SPI_IFCR_MODFC_Pos   (9U)
#define	SPI_IFCR_MODFC_Msk   (0x1UL << SPI_IFCR_MODFC_Pos)
	0x00000200
#define	SPI_IFCR_MODFC   SPI_IFCR_MODFC_Msk
	Mode Fault flag clear.
#define	SPI_IFCR_TSERFC_Pos   (10U)
#define	SPI_IFCR_TSERFC_Msk   (0x1UL << SPI_IFCR_TSERFC_Pos)
	0x00000400
#define	SPI_IFCR_TSERFC   SPI_IFCR_TSERFC_Msk
	TSERFC flag clear.
#define	SPI_IFCR_SUSPC_Pos   (11U)
#define	SPI_IFCR_SUSPC_Msk   (0x1UL << SPI_IFCR_SUSPC_Pos)
	0x00000800
#define	SPI_IFCR_SUSPC   SPI_IFCR_SUSPC_Msk
	SUSPend flag clear.
#define	SPI_TXDR_TXDR_Pos   (0U)
#define	SPI_TXDR_TXDR_Msk   (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)
	0xFFFFFFFF
#define	SPI_TXDR_TXDR   SPI_TXDR_TXDR_Msk /* Transmit Data Register */
#define	SPI_RXDR_RXDR_Pos   (0U)
#define	SPI_RXDR_RXDR_Msk   (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)
	0xFFFFFFFF
#define	SPI_RXDR_RXDR   SPI_RXDR_RXDR_Msk /* Receive Data Register */
#define	SPI_CRCPOLY_CRCPOLY_Pos   (0U)
#define	SPI_CRCPOLY_CRCPOLY_Msk   (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)
	0xFFFFFFFF
#define	SPI_CRCPOLY_CRCPOLY   SPI_CRCPOLY_CRCPOLY_Msk /* CRC Polynomial register */
#define	SPI_TXCRC_TXCRC_Pos   (0U)
#define	SPI_TXCRC_TXCRC_Msk   (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)
	0xFFFFFFFF
#define	SPI_TXCRC_TXCRC   SPI_TXCRC_TXCRC_Msk /* CRCRegister for transmitter */
#define	SPI_RXCRC_RXCRC_Pos   (0U)
#define	SPI_RXCRC_RXCRC_Msk   (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)
	0xFFFFFFFF
#define	SPI_RXCRC_RXCRC   SPI_RXCRC_RXCRC_Msk /* CRCRegister for receiver */
#define	SPI_UDRDR_UDRDR_Pos   (0U)
#define	SPI_UDRDR_UDRDR_Msk   (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)
	0xFFFFFFFF
#define	SPI_UDRDR_UDRDR   SPI_UDRDR_UDRDR_Msk /* Data at slave underrun condition */
#define	SPI_I2SCFGR_I2SMOD_Pos   (0U)
#define	SPI_I2SCFGR_I2SMOD_Msk   (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
	0x00000001
#define	SPI_I2SCFGR_I2SMOD   SPI_I2SCFGR_I2SMOD_Msk
	I2S mode selection.
#define	SPI_I2SCFGR_I2SCFG_Pos   (1U)
#define	SPI_I2SCFGR_I2SCFG_Msk   (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)
	0x0000000E
#define	SPI_I2SCFGR_I2SCFG   SPI_I2SCFGR_I2SCFG_Msk
	I2SCFG[2:0] I2S configuration mode.
#define	SPI_I2SCFGR_I2SCFG_0   (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
	0x00000002
#define	SPI_I2SCFGR_I2SCFG_1   (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
	0x00000004
#define	SPI_I2SCFGR_I2SCFG_2   (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)
	0x00000008
#define	SPI_I2SCFGR_I2SSTD_Pos   (4U)
#define	SPI_I2SCFGR_I2SSTD_Msk   (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
	0x00000030
#define	SPI_I2SCFGR_I2SSTD   SPI_I2SCFGR_I2SSTD_Msk
	I2SSTD[1:0] I2S standard selection.
#define	SPI_I2SCFGR_I2SSTD_0   (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
	0x00000010
#define	SPI_I2SCFGR_I2SSTD_1   (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
	0x00000020
#define	SPI_I2SCFGR_PCMSYNC_Pos   (7U)
#define	SPI_I2SCFGR_PCMSYNC_Msk   (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
	0x00000080
#define	SPI_I2SCFGR_PCMSYNC   SPI_I2SCFGR_PCMSYNC_Msk
	PCM frame synchronization.
#define	SPI_I2SCFGR_DATLEN_Pos   (8U)
#define	SPI_I2SCFGR_DATLEN_Msk   (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
	0x00000300
#define	SPI_I2SCFGR_DATLEN   SPI_I2SCFGR_DATLEN_Msk
	DATLEN[1:0] Data length to be transferred.
#define	SPI_I2SCFGR_DATLEN_0   (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
	0x00000100
#define	SPI_I2SCFGR_DATLEN_1   (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
	0x00000200
#define	SPI_I2SCFGR_CHLEN_Pos   (10U)
#define	SPI_I2SCFGR_CHLEN_Msk   (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
	0x00000400
#define	SPI_I2SCFGR_CHLEN   SPI_I2SCFGR_CHLEN_Msk
	Channel length (number of bits per audio channel).
#define	SPI_I2SCFGR_CKPOL_Pos   (11U)
#define	SPI_I2SCFGR_CKPOL_Msk   (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
	0x00000800
#define	SPI_I2SCFGR_CKPOL   SPI_I2SCFGR_CKPOL_Msk
	Steady state clock polarity.
#define	SPI_I2SCFGR_FIXCH_Pos   (12U)
#define	SPI_I2SCFGR_FIXCH_Msk   (0x1UL << SPI_I2SCFGR_FIXCH_Pos)
	0x00001000
#define	SPI_I2SCFGR_FIXCH   SPI_I2SCFGR_FIXCH_Msk
	Fixed channel length in SLAVE.
#define	SPI_I2SCFGR_WSINV_Pos   (13U)
#define	SPI_I2SCFGR_WSINV_Msk   (0x1UL << SPI_I2SCFGR_WSINV_Pos)
	0x00002000
#define	SPI_I2SCFGR_WSINV   SPI_I2SCFGR_WSINV_Msk
	Word select inversion.
#define	SPI_I2SCFGR_DATFMT_Pos   (14U)
#define	SPI_I2SCFGR_DATFMT_Msk   (0x1UL << SPI_I2SCFGR_DATFMT_Pos)
	0x00004000
#define	SPI_I2SCFGR_DATFMT   SPI_I2SCFGR_DATFMT_Msk
	Data format.
#define	SPI_I2SCFGR_I2SDIV_Pos   (16U)
#define	SPI_I2SCFGR_I2SDIV_Msk   (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)
	0x00FF0000
#define	SPI_I2SCFGR_I2SDIV   SPI_I2SCFGR_I2SDIV_Msk
	I2S Linear prescaler.
#define	SPI_I2SCFGR_ODD_Pos   (24U)
#define	SPI_I2SCFGR_ODD_Msk   (0x1UL << SPI_I2SCFGR_ODD_Pos)
	0x01000000
#define	SPI_I2SCFGR_ODD   SPI_I2SCFGR_ODD_Msk
	Odd factor for the prescaler.
#define	SPI_I2SCFGR_MCKOE_Pos   (25U)
#define	SPI_I2SCFGR_MCKOE_Msk   (0x1UL << SPI_I2SCFGR_MCKOE_Pos)
	0x02000000
#define	SPI_I2SCFGR_MCKOE   SPI_I2SCFGR_MCKOE_Msk
	Master Clock Output Enable.
#define	SYSCFG_PMCR_I2C1_FMP_Pos   (0U)
#define	SYSCFG_PMCR_I2C1_FMP_Msk   (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)
	0x00000001
#define	SYSCFG_PMCR_I2C1_FMP   SYSCFG_PMCR_I2C1_FMP_Msk
	I2C1 Fast mode plus.
#define	SYSCFG_PMCR_I2C2_FMP_Pos   (1U)
#define	SYSCFG_PMCR_I2C2_FMP_Msk   (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)
	0x00000002
#define	SYSCFG_PMCR_I2C2_FMP   SYSCFG_PMCR_I2C2_FMP_Msk
	I2C2 Fast mode plus.
#define	SYSCFG_PMCR_I2C3_FMP_Pos   (2U)
#define	SYSCFG_PMCR_I2C3_FMP_Msk   (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)
	0x00000004
#define	SYSCFG_PMCR_I2C3_FMP   SYSCFG_PMCR_I2C3_FMP_Msk
	I2C3 Fast mode plus.
#define	SYSCFG_PMCR_I2C4_FMP_Pos   (3U)
#define	SYSCFG_PMCR_I2C4_FMP_Msk   (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)
	0x00000008
#define	SYSCFG_PMCR_I2C4_FMP   SYSCFG_PMCR_I2C4_FMP_Msk
	I2C4 Fast mode plus.
#define	SYSCFG_PMCR_I2C_PB6_FMP_Pos   (4U)
#define	SYSCFG_PMCR_I2C_PB6_FMP_Msk   (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos)
	0x00000010
#define	SYSCFG_PMCR_I2C_PB6_FMP   SYSCFG_PMCR_I2C_PB6_FMP_Msk
	I2C PB6 Fast mode plus.
#define	SYSCFG_PMCR_I2C_PB7_FMP_Pos   (5U)
#define	SYSCFG_PMCR_I2C_PB7_FMP_Msk   (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos)
	0x00000020
#define	SYSCFG_PMCR_I2C_PB7_FMP   SYSCFG_PMCR_I2C_PB7_FMP_Msk
	I2C PB7 Fast mode plus.
#define	SYSCFG_PMCR_I2C_PB8_FMP_Pos   (6U)
#define	SYSCFG_PMCR_I2C_PB8_FMP_Msk   (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos)
	0x00000040
#define	SYSCFG_PMCR_I2C_PB8_FMP   SYSCFG_PMCR_I2C_PB8_FMP_Msk
	I2C PB8 Fast mode plus.
#define	SYSCFG_PMCR_I2C_PB9_FMP_Pos   (7U)
#define	SYSCFG_PMCR_I2C_PB9_FMP_Msk   (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos)
	0x00000080
#define	SYSCFG_PMCR_I2C_PB9_FMP   SYSCFG_PMCR_I2C_PB9_FMP_Msk
	I2C PB9 Fast mode plus.
#define	SYSCFG_PMCR_BOOSTEN_Pos   (8U)
#define	SYSCFG_PMCR_BOOSTEN_Msk   (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos)
	0x00000100
#define	SYSCFG_PMCR_BOOSTEN   SYSCFG_PMCR_BOOSTEN_Msk
	I/O analog switch voltage booster enable.
#define	SYSCFG_PMCR_BOOSTVDDSEL_Pos   (9U)
#define	SYSCFG_PMCR_BOOSTVDDSEL_Msk   (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos)
	0x00000200
#define	SYSCFG_PMCR_BOOSTVDDSEL   SYSCFG_PMCR_BOOSTVDDSEL_Msk
	Analog switch supply source selection : VDD/VDDA.
#define	SYSCFG_PMCR_I2C5_FMP_Pos   (10U)
#define	SYSCFG_PMCR_I2C5_FMP_Msk   (0x1UL << SYSCFG_PMCR_I2C5_FMP_Pos)
	0x00000400
#define	SYSCFG_PMCR_I2C5_FMP   SYSCFG_PMCR_I2C5_FMP_Msk
	I2C5 Fast mode plus.
#define	SYSCFG_PMCR_EPIS_SEL_Pos   (21U)
#define	SYSCFG_PMCR_EPIS_SEL_Msk   (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos)
	0x00E00000
#define	SYSCFG_PMCR_EPIS_SEL   SYSCFG_PMCR_EPIS_SEL_Msk
	Ethernet PHY Interface Selection.
#define	SYSCFG_PMCR_EPIS_SEL_0   (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos)
	0x00200000
#define	SYSCFG_PMCR_EPIS_SEL_1   (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos)
	0x00400000
#define	SYSCFG_PMCR_EPIS_SEL_2   (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos)
	0x00800000
#define	SYSCFG_PMCR_PA0SO_Pos   (24U)
#define	SYSCFG_PMCR_PA0SO_Msk   (0x1UL << SYSCFG_PMCR_PA0SO_Pos)
	0x01000000
#define	SYSCFG_PMCR_PA0SO   SYSCFG_PMCR_PA0SO_Msk
	PA0 Switch Open.
#define	SYSCFG_PMCR_PA1SO_Pos   (25U)
#define	SYSCFG_PMCR_PA1SO_Msk   (0x1UL << SYSCFG_PMCR_PA1SO_Pos)
	0x02000000
#define	SYSCFG_PMCR_PA1SO   SYSCFG_PMCR_PA1SO_Msk
	PA1 Switch Open.
#define	SYSCFG_PMCR_PC2SO_Pos   (26U)
#define	SYSCFG_PMCR_PC2SO_Msk   (0x1UL << SYSCFG_PMCR_PC2SO_Pos)
	0x04000000
#define	SYSCFG_PMCR_PC2SO   SYSCFG_PMCR_PC2SO_Msk
	PC2 Switch Open.
#define	SYSCFG_PMCR_PC3SO_Pos   (27U)
#define	SYSCFG_PMCR_PC3SO_Msk   (0x1UL << SYSCFG_PMCR_PC3SO_Pos)
	0x08000000
#define	SYSCFG_PMCR_PC3SO   SYSCFG_PMCR_PC3SO_Msk
	PC3 Switch Open.
#define	SYSCFG_EXTICR1_EXTI0_Pos   (0U)
#define	SYSCFG_EXTICR1_EXTI0_Msk   (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
	0x0000000F
#define	SYSCFG_EXTICR1_EXTI0   SYSCFG_EXTICR1_EXTI0_Msk
	EXTI 0 configuration.
#define	SYSCFG_EXTICR1_EXTI1_Pos   (4U)
#define	SYSCFG_EXTICR1_EXTI1_Msk   (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
	0x000000F0
#define	SYSCFG_EXTICR1_EXTI1   SYSCFG_EXTICR1_EXTI1_Msk
	EXTI 1 configuration.
#define	SYSCFG_EXTICR1_EXTI2_Pos   (8U)
#define	SYSCFG_EXTICR1_EXTI2_Msk   (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
	0x00000F00
#define	SYSCFG_EXTICR1_EXTI2   SYSCFG_EXTICR1_EXTI2_Msk
	EXTI 2 configuration.
#define	SYSCFG_EXTICR1_EXTI3_Pos   (12U)
#define	SYSCFG_EXTICR1_EXTI3_Msk   (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
	0x0000F000
#define	SYSCFG_EXTICR1_EXTI3   SYSCFG_EXTICR1_EXTI3_Msk
	EXTI 3 configuration.
#define	SYSCFG_EXTICR1_EXTI0_PA   (0U)
	EXTI0 configuration.
#define	SYSCFG_EXTICR1_EXTI0_PB   (0x00000001U)
	PB[0] pin.
#define	SYSCFG_EXTICR1_EXTI0_PC   (0x00000002U)
	PC[0] pin.
#define	SYSCFG_EXTICR1_EXTI0_PD   (0x00000003U)
	PD[0] pin.
#define	SYSCFG_EXTICR1_EXTI0_PE   (0x00000004U)
	PE[0] pin.
#define	SYSCFG_EXTICR1_EXTI0_PF   (0x00000005U)
	PF[0] pin.
#define	SYSCFG_EXTICR1_EXTI0_PG   (0x00000006U)
	PG[0] pin.
#define	SYSCFG_EXTICR1_EXTI0_PH   (0x00000007U)
	PH[0] pin.
#define	SYSCFG_EXTICR1_EXTI0_PJ   (0x00000009U)
	PJ[0] pin.
#define	SYSCFG_EXTICR1_EXTI0_PK   (0x0000000AU)
	PK[0] pin.
#define	SYSCFG_EXTICR1_EXTI1_PA   (0U)
	EXTI1 configuration.
#define	SYSCFG_EXTICR1_EXTI1_PB   (0x00000010U)
	PB[1] pin.
#define	SYSCFG_EXTICR1_EXTI1_PC   (0x00000020U)
	PC[1] pin.
#define	SYSCFG_EXTICR1_EXTI1_PD   (0x00000030U)
	PD[1] pin.
#define	SYSCFG_EXTICR1_EXTI1_PE   (0x00000040U)
	PE[1] pin.
#define	SYSCFG_EXTICR1_EXTI1_PF   (0x00000050U)
	PF[1] pin.
#define	SYSCFG_EXTICR1_EXTI1_PG   (0x00000060U)
	PG[1] pin.
#define	SYSCFG_EXTICR1_EXTI1_PH   (0x00000070U)
	PH[1] pin.
#define	SYSCFG_EXTICR1_EXTI1_PJ   (0x00000090U)
	PJ[1] pin.
#define	SYSCFG_EXTICR1_EXTI1_PK   (0x000000A0U)
	PK[1] pin.
#define	SYSCFG_EXTICR1_EXTI2_PA   (0U)
	EXTI2 configuration.
#define	SYSCFG_EXTICR1_EXTI2_PB   (0x00000100U)
	PB[2] pin.
#define	SYSCFG_EXTICR1_EXTI2_PC   (0x00000200U)
	PC[2] pin.
#define	SYSCFG_EXTICR1_EXTI2_PD   (0x00000300U)
	PD[2] pin.
#define	SYSCFG_EXTICR1_EXTI2_PE   (0x00000400U)
	PE[2] pin.
#define	SYSCFG_EXTICR1_EXTI2_PF   (0x00000500U)
	PF[2] pin.
#define	SYSCFG_EXTICR1_EXTI2_PG   (0x00000600U)
	PG[2] pin.
#define	SYSCFG_EXTICR1_EXTI2_PH   (0x00000700U)
	PH[2] pin.
#define	SYSCFG_EXTICR1_EXTI2_PJ   (0x00000900U)
	PJ[2] pin.
#define	SYSCFG_EXTICR1_EXTI2_PK   (0x00000A00U)
	PK[2] pin.
#define	SYSCFG_EXTICR1_EXTI3_PA   (0U)
	EXTI3 configuration.
#define	SYSCFG_EXTICR1_EXTI3_PB   (0x00001000U)
	PB[3] pin.
#define	SYSCFG_EXTICR1_EXTI3_PC   (0x00002000U)
	PC[3] pin.
#define	SYSCFG_EXTICR1_EXTI3_PD   (0x00003000U)
	PD[3] pin.
#define	SYSCFG_EXTICR1_EXTI3_PE   (0x00004000U)
	PE[3] pin.
#define	SYSCFG_EXTICR1_EXTI3_PF   (0x00005000U)
	PF[3] pin.
#define	SYSCFG_EXTICR1_EXTI3_PG   (0x00006000U)
	PG[3] pin.
#define	SYSCFG_EXTICR1_EXTI3_PH   (0x00007000U)
	PH[3] pin.
#define	SYSCFG_EXTICR1_EXTI3_PJ   (0x00009000U)
	PJ[3] pin.
#define	SYSCFG_EXTICR1_EXTI3_PK   (0x0000A000U)
	PK[3] pin.
#define	SYSCFG_EXTICR2_EXTI4_Pos   (0U)
#define	SYSCFG_EXTICR2_EXTI4_Msk   (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
	0x0000000F
#define	SYSCFG_EXTICR2_EXTI4   SYSCFG_EXTICR2_EXTI4_Msk
	EXTI 4 configuration.
#define	SYSCFG_EXTICR2_EXTI5_Pos   (4U)
#define	SYSCFG_EXTICR2_EXTI5_Msk   (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
	0x000000F0
#define	SYSCFG_EXTICR2_EXTI5   SYSCFG_EXTICR2_EXTI5_Msk
	EXTI 5 configuration.
#define	SYSCFG_EXTICR2_EXTI6_Pos   (8U)
#define	SYSCFG_EXTICR2_EXTI6_Msk   (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
	0x00000F00
#define	SYSCFG_EXTICR2_EXTI6   SYSCFG_EXTICR2_EXTI6_Msk
	EXTI 6 configuration.
#define	SYSCFG_EXTICR2_EXTI7_Pos   (12U)
#define	SYSCFG_EXTICR2_EXTI7_Msk   (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
	0x0000F000
#define	SYSCFG_EXTICR2_EXTI7   SYSCFG_EXTICR2_EXTI7_Msk
	EXTI 7 configuration.
#define	SYSCFG_EXTICR2_EXTI4_PA   (0U)
	EXTI4 configuration.
#define	SYSCFG_EXTICR2_EXTI4_PB   (0x00000001U)
	PB[4] pin.
#define	SYSCFG_EXTICR2_EXTI4_PC   (0x00000002U)
	PC[4] pin.
#define	SYSCFG_EXTICR2_EXTI4_PD   (0x00000003U)
	PD[4] pin.
#define	SYSCFG_EXTICR2_EXTI4_PE   (0x00000004U)
	PE[4] pin.
#define	SYSCFG_EXTICR2_EXTI4_PF   (0x00000005U)
	PF[4] pin.
#define	SYSCFG_EXTICR2_EXTI4_PG   (0x00000006U)
	PG[4] pin.
#define	SYSCFG_EXTICR2_EXTI4_PH   (0x00000007U)
	PH[4] pin.
#define	SYSCFG_EXTICR2_EXTI4_PJ   (0x00000009U)
	PJ[4] pin.
#define	SYSCFG_EXTICR2_EXTI4_PK   (0x0000000AU)
	PK[4] pin.
#define	SYSCFG_EXTICR2_EXTI5_PA   (0U)
	EXTI5 configuration.
#define	SYSCFG_EXTICR2_EXTI5_PB   (0x00000010U)
	PB[5] pin.
#define	SYSCFG_EXTICR2_EXTI5_PC   (0x00000020U)
	PC[5] pin.
#define	SYSCFG_EXTICR2_EXTI5_PD   (0x00000030U)
	PD[5] pin.
#define	SYSCFG_EXTICR2_EXTI5_PE   (0x00000040U)
	PE[5] pin.
#define	SYSCFG_EXTICR2_EXTI5_PF   (0x00000050U)
	PF[5] pin.
#define	SYSCFG_EXTICR2_EXTI5_PG   (0x00000060U)
	PG[5] pin.
#define	SYSCFG_EXTICR2_EXTI5_PH   (0x00000070U)
	PH[5] pin.
#define	SYSCFG_EXTICR2_EXTI5_PJ   (0x00000090U)
	PJ[5] pin.
#define	SYSCFG_EXTICR2_EXTI5_PK   (0x000000A0U)
	PK[5] pin.
#define	SYSCFG_EXTICR2_EXTI6_PA   (0U)
	EXTI6 configuration.
#define	SYSCFG_EXTICR2_EXTI6_PB   (0x00000100U)
	PB[6] pin.
#define	SYSCFG_EXTICR2_EXTI6_PC   (0x00000200U)
	PC[6] pin.
#define	SYSCFG_EXTICR2_EXTI6_PD   (0x00000300U)
	PD[6] pin.
#define	SYSCFG_EXTICR2_EXTI6_PE   (0x00000400U)
	PE[6] pin.
#define	SYSCFG_EXTICR2_EXTI6_PF   (0x00000500U)
	PF[6] pin.
#define	SYSCFG_EXTICR2_EXTI6_PG   (0x00000600U)
	PG[6] pin.
#define	SYSCFG_EXTICR2_EXTI6_PH   (0x00000700U)
	PH[6] pin.
#define	SYSCFG_EXTICR2_EXTI6_PJ   (0x00000900U)
	PJ[6] pin.
#define	SYSCFG_EXTICR2_EXTI6_PK   (0x00000A00U)
	PK[6] pin.
#define	SYSCFG_EXTICR2_EXTI7_PA   (0U)
	EXTI7 configuration.
#define	SYSCFG_EXTICR2_EXTI7_PB   (0x00001000U)
	PB[7] pin.
#define	SYSCFG_EXTICR2_EXTI7_PC   (0x00002000U)
	PC[7] pin.
#define	SYSCFG_EXTICR2_EXTI7_PD   (0x00003000U)
	PD[7] pin.
#define	SYSCFG_EXTICR2_EXTI7_PE   (0x00004000U)
	PE[7] pin.
#define	SYSCFG_EXTICR2_EXTI7_PF   (0x00005000U)
	PF[7] pin.
#define	SYSCFG_EXTICR2_EXTI7_PG   (0x00006000U)
	PG[7] pin.
#define	SYSCFG_EXTICR2_EXTI7_PH   (0x00007000U)
	PH[7] pin.
#define	SYSCFG_EXTICR2_EXTI7_PJ   (0x00009000U)
	PJ[7] pin.
#define	SYSCFG_EXTICR2_EXTI7_PK   (0x0000A000U)
	PK[7] pin.
#define	SYSCFG_EXTICR3_EXTI8_Pos   (0U)
#define	SYSCFG_EXTICR3_EXTI8_Msk   (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
	0x0000000F
#define	SYSCFG_EXTICR3_EXTI8   SYSCFG_EXTICR3_EXTI8_Msk
	EXTI 8 configuration.
#define	SYSCFG_EXTICR3_EXTI9_Pos   (4U)
#define	SYSCFG_EXTICR3_EXTI9_Msk   (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
	0x000000F0
#define	SYSCFG_EXTICR3_EXTI9   SYSCFG_EXTICR3_EXTI9_Msk
	EXTI 9 configuration.
#define	SYSCFG_EXTICR3_EXTI10_Pos   (8U)
#define	SYSCFG_EXTICR3_EXTI10_Msk   (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
	0x00000F00
#define	SYSCFG_EXTICR3_EXTI10   SYSCFG_EXTICR3_EXTI10_Msk
	EXTI 10 configuration.
#define	SYSCFG_EXTICR3_EXTI11_Pos   (12U)
#define	SYSCFG_EXTICR3_EXTI11_Msk   (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
	0x0000F000
#define	SYSCFG_EXTICR3_EXTI11   SYSCFG_EXTICR3_EXTI11_Msk
	EXTI 11 configuration.
#define	SYSCFG_EXTICR3_EXTI8_PA   (0U)
	EXTI8 configuration.
#define	SYSCFG_EXTICR3_EXTI8_PB   (0x00000001U)
	PB[8] pin.
#define	SYSCFG_EXTICR3_EXTI8_PC   (0x00000002U)
	PC[8] pin.
#define	SYSCFG_EXTICR3_EXTI8_PD   (0x00000003U)
	PD[8] pin.
#define	SYSCFG_EXTICR3_EXTI8_PE   (0x00000004U)
	PE[8] pin.
#define	SYSCFG_EXTICR3_EXTI8_PF   (0x00000005U)
	PF[8] pin.
#define	SYSCFG_EXTICR3_EXTI8_PG   (0x00000006U)
	PG[8] pin.
#define	SYSCFG_EXTICR3_EXTI8_PH   (0x00000007U)
	PH[8] pin.
#define	SYSCFG_EXTICR3_EXTI8_PJ   (0x00000009U)
	PJ[8] pin.
#define	SYSCFG_EXTICR3_EXTI8_PK   (0x0000000AU)
	PK[8] pin.
#define	SYSCFG_EXTICR3_EXTI9_PA   (0U)
	EXTI9 configuration.
#define	SYSCFG_EXTICR3_EXTI9_PB   (0x00000010U)
	PB[9] pin.
#define	SYSCFG_EXTICR3_EXTI9_PC   (0x00000020U)
	PC[9] pin.
#define	SYSCFG_EXTICR3_EXTI9_PD   (0x00000030U)
	PD[9] pin.
#define	SYSCFG_EXTICR3_EXTI9_PE   (0x00000040U)
	PE[9] pin.
#define	SYSCFG_EXTICR3_EXTI9_PF   (0x00000050U)
	PF[9] pin.
#define	SYSCFG_EXTICR3_EXTI9_PG   (0x00000060U)
	PG[9] pin.
#define	SYSCFG_EXTICR3_EXTI9_PH   (0x00000070U)
	PH[9] pin.
#define	SYSCFG_EXTICR3_EXTI9_PJ   (0x00000090U)
	PJ[9] pin.
#define	SYSCFG_EXTICR3_EXTI9_PK   (0x000000A0U)
	PK[9] pin.
#define	SYSCFG_EXTICR3_EXTI10_PA   (0U)
	EXTI10 configuration.
#define	SYSCFG_EXTICR3_EXTI10_PB   (0x00000100U)
	PB[10] pin.
#define	SYSCFG_EXTICR3_EXTI10_PC   (0x00000200U)
	PC[10] pin.
#define	SYSCFG_EXTICR3_EXTI10_PD   (0x00000300U)
	PD[10] pin.
#define	SYSCFG_EXTICR3_EXTI10_PE   (0x00000400U)
	PE[10] pin.
#define	SYSCFG_EXTICR3_EXTI10_PF   (0x00000500U)
	PF[10] pin.
#define	SYSCFG_EXTICR3_EXTI10_PG   (0x00000600U)
	PG[10] pin.
#define	SYSCFG_EXTICR3_EXTI10_PH   (0x00000700U)
	PH[10] pin.
#define	SYSCFG_EXTICR3_EXTI10_PJ   (0x00000900U)
	PJ[10] pin.
#define	SYSCFG_EXTICR3_EXTI10_PK   (0x00000A00U)
	PK[10] pin.
#define	SYSCFG_EXTICR3_EXTI11_PA   (0U)
	EXTI11 configuration.
#define	SYSCFG_EXTICR3_EXTI11_PB   (0x00001000U)
	PB[11] pin.
#define	SYSCFG_EXTICR3_EXTI11_PC   (0x00002000U)
	PC[11] pin.
#define	SYSCFG_EXTICR3_EXTI11_PD   (0x00003000U)
	PD[11] pin.
#define	SYSCFG_EXTICR3_EXTI11_PE   (0x00004000U)
	PE[11] pin.
#define	SYSCFG_EXTICR3_EXTI11_PF   (0x00005000U)
	PF[11] pin.
#define	SYSCFG_EXTICR3_EXTI11_PG   (0x00006000U)
	PG[11] pin.
#define	SYSCFG_EXTICR3_EXTI11_PH   (0x00007000U)
	PH[11] pin.
#define	SYSCFG_EXTICR3_EXTI11_PJ   (0x00009000U)
	PJ[11] pin.
#define	SYSCFG_EXTICR3_EXTI11_PK   (0x0000A000U)
	PK[11] pin.
#define	SYSCFG_EXTICR4_EXTI12_Pos   (0U)
#define	SYSCFG_EXTICR4_EXTI12_Msk   (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
	0x0000000F
#define	SYSCFG_EXTICR4_EXTI12   SYSCFG_EXTICR4_EXTI12_Msk
	EXTI 12 configuration.
#define	SYSCFG_EXTICR4_EXTI13_Pos   (4U)
#define	SYSCFG_EXTICR4_EXTI13_Msk   (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
	0x000000F0
#define	SYSCFG_EXTICR4_EXTI13   SYSCFG_EXTICR4_EXTI13_Msk
	EXTI 13 configuration.
#define	SYSCFG_EXTICR4_EXTI14_Pos   (8U)
#define	SYSCFG_EXTICR4_EXTI14_Msk   (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
	0x00000F00
#define	SYSCFG_EXTICR4_EXTI14   SYSCFG_EXTICR4_EXTI14_Msk
	EXTI 14 configuration.
#define	SYSCFG_EXTICR4_EXTI15_Pos   (12U)
#define	SYSCFG_EXTICR4_EXTI15_Msk   (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
	0x0000F000
#define	SYSCFG_EXTICR4_EXTI15   SYSCFG_EXTICR4_EXTI15_Msk
	EXTI 15 configuration.
#define	SYSCFG_EXTICR4_EXTI12_PA   (0U)
	EXTI12 configuration.
#define	SYSCFG_EXTICR4_EXTI12_PB   (0x00000001U)
	PB[12] pin.
#define	SYSCFG_EXTICR4_EXTI12_PC   (0x00000002U)
	PC[12] pin.
#define	SYSCFG_EXTICR4_EXTI12_PD   (0x00000003U)
	PD[12] pin.
#define	SYSCFG_EXTICR4_EXTI12_PE   (0x00000004U)
	PE[12] pin.
#define	SYSCFG_EXTICR4_EXTI12_PF   (0x00000005U)
	PF[12] pin.
#define	SYSCFG_EXTICR4_EXTI12_PG   (0x00000006U)
	PG[12] pin.
#define	SYSCFG_EXTICR4_EXTI12_PH   (0x00000007U)
	PH[12] pin.
#define	SYSCFG_EXTICR4_EXTI12_PJ   (0x00000009U)
	PJ[12] pin.
#define	SYSCFG_EXTICR4_EXTI12_PK   (0x0000000AU)
	PK[12] pin.
#define	SYSCFG_EXTICR4_EXTI13_PA   (0U)
	EXTI13 configuration.
#define	SYSCFG_EXTICR4_EXTI13_PB   (0x00000010U)
	PB[13] pin.
#define	SYSCFG_EXTICR4_EXTI13_PC   (0x00000020U)
	PC[13] pin.
#define	SYSCFG_EXTICR4_EXTI13_PD   (0x00000030U)
	PD[13] pin.
#define	SYSCFG_EXTICR4_EXTI13_PE   (0x00000040U)
	PE[13] pin.
#define	SYSCFG_EXTICR4_EXTI13_PF   (0x00000050U)
	PF[13] pin.
#define	SYSCFG_EXTICR4_EXTI13_PG   (0x00000060U)
	PG[13] pin.
#define	SYSCFG_EXTICR4_EXTI13_PH   (0x00000070U)
	PH[13] pin.
#define	SYSCFG_EXTICR4_EXTI13_PJ   (0x00000090U)
	PJ[13] pin.
#define	SYSCFG_EXTICR4_EXTI13_PK   (0x000000A0U)
	PK[13] pin.
#define	SYSCFG_EXTICR4_EXTI14_PA   (0U)
	EXTI14 configuration.
#define	SYSCFG_EXTICR4_EXTI14_PB   (0x00000100U)
	PB[14] pin.
#define	SYSCFG_EXTICR4_EXTI14_PC   (0x00000200U)
	PC[14] pin.
#define	SYSCFG_EXTICR4_EXTI14_PD   (0x00000300U)
	PD[14] pin.
#define	SYSCFG_EXTICR4_EXTI14_PE   (0x00000400U)
	PE[14] pin.
#define	SYSCFG_EXTICR4_EXTI14_PF   (0x00000500U)
	PF[14] pin.
#define	SYSCFG_EXTICR4_EXTI14_PG   (0x00000600U)
	PG[14] pin.
#define	SYSCFG_EXTICR4_EXTI14_PH   (0x00000700U)
	PH[14] pin.
#define	SYSCFG_EXTICR4_EXTI14_PJ   (0x00000900U)
	PJ[14] pin.
#define	SYSCFG_EXTICR4_EXTI14_PK   (0x00000A00U)
	PK[14] pin.
#define	SYSCFG_EXTICR4_EXTI15_PA   (0U)
	EXTI15 configuration.
#define	SYSCFG_EXTICR4_EXTI15_PB   (0x00001000U)
	PB[15] pin.
#define	SYSCFG_EXTICR4_EXTI15_PC   (0x00002000U)
	PC[15] pin.
#define	SYSCFG_EXTICR4_EXTI15_PD   (0x00003000U)
	PD[15] pin.
#define	SYSCFG_EXTICR4_EXTI15_PE   (0x00004000U)
	PE[15] pin.
#define	SYSCFG_EXTICR4_EXTI15_PF   (0x00005000U)
	PF[15] pin.
#define	SYSCFG_EXTICR4_EXTI15_PG   (0x00006000U)
	PG[15] pin.
#define	SYSCFG_EXTICR4_EXTI15_PH   (0x00007000U)
	PH[15] pin.
#define	SYSCFG_EXTICR4_EXTI15_PJ   (0x00009000U)
	PJ[15] pin.
#define	SYSCFG_EXTICR4_EXTI15_PK   (0x0000A000U)
	PK[15] pin.
#define	SYSCFG_CFGR_PVDL_Pos   (2U)
#define	SYSCFG_CFGR_PVDL_Msk   (0x1UL << SYSCFG_CFGR_PVDL_Pos)
	0x00000004
#define	SYSCFG_CFGR_PVDL   SYSCFG_CFGR_PVDL_Msk
	PVD lock enable bit.
#define	SYSCFG_CFGR_FLASHL_Pos   (3U)
#define	SYSCFG_CFGR_FLASHL_Msk   (0x1UL << SYSCFG_CFGR_FLASHL_Pos)
	0x00000008
#define	SYSCFG_CFGR_FLASHL   SYSCFG_CFGR_FLASHL_Msk
	FLASH double ECC error lock bit.
#define	SYSCFG_CFGR_CM7L_Pos   (6U)
#define	SYSCFG_CFGR_CM7L_Msk   (0x1UL << SYSCFG_CFGR_CM7L_Pos)
	0x00000040
#define	SYSCFG_CFGR_CM7L   SYSCFG_CFGR_CM7L_Msk
	Cortex-M7 LOCKUP (Hardfault) output enable bit.
#define	SYSCFG_CFGR_BKRAML_Pos   (7U)
#define	SYSCFG_CFGR_BKRAML_Msk   (0x1UL << SYSCFG_CFGR_BKRAML_Pos)
	0x00000080
#define	SYSCFG_CFGR_BKRAML   SYSCFG_CFGR_BKRAML_Msk
	Backup SRAM double ECC error lock bit.
#define	SYSCFG_CFGR_SRAM4L_Pos   (9U)
#define	SYSCFG_CFGR_SRAM4L_Msk   (0x1UL << SYSCFG_CFGR_SRAM4L_Pos)
	0x00000200
#define	SYSCFG_CFGR_SRAM4L   SYSCFG_CFGR_SRAM4L_Msk
	SRAM4 double ECC error lock bit.
#define	SYSCFG_CFGR_SRAM2L_Pos   (11U)
#define	SYSCFG_CFGR_SRAM2L_Msk   (0x1UL << SYSCFG_CFGR_SRAM2L_Pos)
	0x00000800
#define	SYSCFG_CFGR_SRAM2L   SYSCFG_CFGR_SRAM2L_Msk
	SRAM2 double ECC error lock bit.
#define	SYSCFG_CFGR_SRAM1L_Pos   (12U)
#define	SYSCFG_CFGR_SRAM1L_Msk   (0x1UL << SYSCFG_CFGR_SRAM1L_Pos)
	0x00001000
#define	SYSCFG_CFGR_SRAM1L   SYSCFG_CFGR_SRAM1L_Msk
	SRAM1 double ECC error lock bit.
#define	SYSCFG_CFGR_DTCML_Pos   (13U)
#define	SYSCFG_CFGR_DTCML_Msk   (0x1UL << SYSCFG_CFGR_DTCML_Pos)
	0x00002000
#define	SYSCFG_CFGR_DTCML   SYSCFG_CFGR_DTCML_Msk
	DTCM double ECC error lock bit.
#define	SYSCFG_CFGR_ITCML_Pos   (14U)
#define	SYSCFG_CFGR_ITCML_Msk   (0x1UL << SYSCFG_CFGR_ITCML_Pos)
	0x00004000
#define	SYSCFG_CFGR_ITCML   SYSCFG_CFGR_ITCML_Msk
	ITCM double ECC error lock bit.
#define	SYSCFG_CFGR_AXISRAML_Pos   (15U)
#define	SYSCFG_CFGR_AXISRAML_Msk   (0x1UL << SYSCFG_CFGR_AXISRAML_Pos)
	0x00008000
#define	SYSCFG_CFGR_AXISRAML   SYSCFG_CFGR_AXISRAML_Msk
	AXISRAM double ECC error lock bit.
#define	SYSCFG_CCCSR_EN_Pos   (0U)
#define	SYSCFG_CCCSR_EN_Msk   (0x1UL << SYSCFG_CCCSR_EN_Pos)
	0x00000001
#define	SYSCFG_CCCSR_EN   SYSCFG_CCCSR_EN_Msk
	I/O compensation cell enable.
#define	SYSCFG_CCCSR_CS_Pos   (1U)
#define	SYSCFG_CCCSR_CS_Msk   (0x1UL << SYSCFG_CCCSR_CS_Pos)
	0x00000002
#define	SYSCFG_CCCSR_CS   SYSCFG_CCCSR_CS_Msk
	I/O compensation cell code selection.
#define	SYSCFG_CCCSR_READY_Pos   (8U)
#define	SYSCFG_CCCSR_READY_Msk   (0x1UL << SYSCFG_CCCSR_READY_Pos)
	0x00000100
#define	SYSCFG_CCCSR_READY   SYSCFG_CCCSR_READY_Msk
	I/O compensation cell ready flag.
#define	SYSCFG_CCCSR_HSLV_Pos   (16U)
#define	SYSCFG_CCCSR_HSLV_Msk   (0x1UL << SYSCFG_CCCSR_HSLV_Pos)
	0x00010000
#define	SYSCFG_CCCSR_HSLV   SYSCFG_CCCSR_HSLV_Msk
	High-speed at low-voltage.
#define	SYSCFG_CCVR_NCV_Pos   (0U)
#define	SYSCFG_CCVR_NCV_Msk   (0xFUL << SYSCFG_CCVR_NCV_Pos)
	0x0000000F
#define	SYSCFG_CCVR_NCV   SYSCFG_CCVR_NCV_Msk
	NMOS compensation value.
#define	SYSCFG_CCVR_PCV_Pos   (4U)
#define	SYSCFG_CCVR_PCV_Msk   (0xFUL << SYSCFG_CCVR_PCV_Pos)
	0x000000F0
#define	SYSCFG_CCVR_PCV   SYSCFG_CCVR_PCV_Msk
	PMOS compensation value.
#define	SYSCFG_CCCR_NCC_Pos   (0U)
#define	SYSCFG_CCCR_NCC_Msk   (0xFUL << SYSCFG_CCCR_NCC_Pos)
	0x0000000F
#define	SYSCFG_CCCR_NCC   SYSCFG_CCCR_NCC_Msk
	NMOS compensation code.
#define	SYSCFG_CCCR_PCC_Pos   (4U)
#define	SYSCFG_CCCR_PCC_Msk   (0xFUL << SYSCFG_CCCR_PCC_Pos)
	0x000000F0
#define	SYSCFG_CCCR_PCC   SYSCFG_CCCR_PCC_Msk
	PMOS compensation code.
#define	SYSCFG_ADC2ALT_ADC2_ROUT0_Pos   (0U)
#define	SYSCFG_ADC2ALT_ADC2_ROUT0_Msk   (0x1UL << SYSCFG_ADC2ALT_ADC2_ROUT0_Pos)
	0x00000001
#define	SYSCFG_ADC2ALT_ADC2_ROUT0   SYSCFG_ADC2ALT_ADC2_ROUT0_Msk
	VBAT/4 connected to ADC2 V_INP[16].
#define	SYSCFG_ADC2ALT_ADC2_ROUT1_Pos   (1U)
#define	SYSCFG_ADC2ALT_ADC2_ROUT1_Msk   (0x1UL << SYSCFG_ADC2ALT_ADC2_ROUT1_Pos)
	0x00000002
#define	SYSCFG_ADC2ALT_ADC2_ROUT1   SYSCFG_ADC2ALT_ADC2_ROUT1_Msk
	Internal reference voltage (V_REFINT) connected to ADC2 V_INP[17].
#define	SYSCFG_PKGR_PKG_Pos   (0U)
#define	SYSCFG_PKGR_PKG_Msk   (0xFUL << SYSCFG_PKGR_PKG_Pos)
	0x0000000F
#define	SYSCFG_PKGR_PKG   SYSCFG_PKGR_PKG_Msk
	Package type.
#define	SYSCFG_UR0_RDP_Pos   (16U)
#define	SYSCFG_UR0_RDP_Msk   (0xFFUL << SYSCFG_UR0_RDP_Pos)
	0x00FF0000
#define	SYSCFG_UR0_RDP   SYSCFG_UR0_RDP_Msk
	Readout protection.
#define	SYSCFG_UR2_BORH_Pos   (0U)
#define	SYSCFG_UR2_BORH_Msk   (0x3UL << SYSCFG_UR2_BORH_Pos)
	0x00000003
#define	SYSCFG_UR2_BORH   SYSCFG_UR2_BORH_Msk
	Brown Out Reset High level.
#define	SYSCFG_UR2_BORH_0   (0x1UL << SYSCFG_UR2_BORH_Pos)
	0x00000001
#define	SYSCFG_UR2_BORH_1   (0x2UL << SYSCFG_UR2_BORH_Pos)
	0x00000002
#define	SYSCFG_UR2_BOOT_ADD0_Pos   (16U)
#define	SYSCFG_UR2_BOOT_ADD0_Msk   (0xFFFFUL << SYSCFG_UR2_BOOT_ADD0_Pos)
	0xFFFF0000
#define	SYSCFG_UR2_BOOT_ADD0   SYSCFG_UR2_BOOT_ADD0_Msk
	Core Boot Address 0.
#define	SYSCFG_UR3_BOOT_ADD1_Pos   (0U)
#define	SYSCFG_UR3_BOOT_ADD1_Msk   (0xFFFFUL << SYSCFG_UR3_BOOT_ADD1_Pos)
	0x0000FFFF
#define	SYSCFG_UR3_BOOT_ADD1   SYSCFG_UR3_BOOT_ADD1_Msk
	Core Boot Address 1.
#define	SYSCFG_UR4_MEPAD_BANK1_Pos   (16U)
#define	SYSCFG_UR4_MEPAD_BANK1_Msk   (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos)
	0x00010000
#define	SYSCFG_UR4_MEPAD_BANK1   SYSCFG_UR4_MEPAD_BANK1_Msk
	Mass Erase Protected Area Disabled for bank 1.
#define	SYSCFG_UR5_MESAD_BANK1_Pos   (0U)
#define	SYSCFG_UR5_MESAD_BANK1_Msk   (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos)
	0x00000001
#define	SYSCFG_UR5_MESAD_BANK1   SYSCFG_UR5_MESAD_BANK1_Msk
	Mass erase secured area disabled for bank 1.
#define	SYSCFG_UR5_WRPN_BANK1_Pos   (16U)
#define	SYSCFG_UR5_WRPN_BANK1_Msk   (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos)
	0x00FF0000
#define	SYSCFG_UR5_WRPN_BANK1   SYSCFG_UR5_WRPN_BANK1_Msk
	Write protection for flash bank 1.
#define	SYSCFG_UR6_PABEG_BANK1_Pos   (0U)
#define	SYSCFG_UR6_PABEG_BANK1_Msk   (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos)
	0x00000FFF
#define	SYSCFG_UR6_PABEG_BANK1   SYSCFG_UR6_PABEG_BANK1_Msk
	Protected area start address for bank 1.
#define	SYSCFG_UR6_PAEND_BANK1_Pos   (16U)
#define	SYSCFG_UR6_PAEND_BANK1_Msk   (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos)
	0x0FFF0000
#define	SYSCFG_UR6_PAEND_BANK1   SYSCFG_UR6_PAEND_BANK1_Msk
	Protected area end address for bank 1.
#define	SYSCFG_UR7_SABEG_BANK1_Pos   (0U)
#define	SYSCFG_UR7_SABEG_BANK1_Msk   (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos)
	0x00000FFF
#define	SYSCFG_UR7_SABEG_BANK1   SYSCFG_UR7_SABEG_BANK1_Msk
	Secured area start address for bank 1.
#define	SYSCFG_UR7_SAEND_BANK1_Pos   (16U)
#define	SYSCFG_UR7_SAEND_BANK1_Msk   (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos)
	0x0FFF0000
#define	SYSCFG_UR7_SAEND_BANK1   SYSCFG_UR7_SAEND_BANK1_Msk
	Secured area end address for bank 1.
#define	SYSCFG_UR11_IWDG1M_Pos   (16U)
#define	SYSCFG_UR11_IWDG1M_Msk   (0x1UL << SYSCFG_UR11_IWDG1M_Pos)
	0x00010000
#define	SYSCFG_UR11_IWDG1M   SYSCFG_UR11_IWDG1M_Msk
	Independent Watchdog 1 mode (SW or HW).
#define	SYSCFG_UR12_SECURE_Pos   (16U)
#define	SYSCFG_UR12_SECURE_Msk   (0x1UL << SYSCFG_UR12_SECURE_Pos)
	0x00010000
#define	SYSCFG_UR12_SECURE   SYSCFG_UR12_SECURE_Msk
	Secure mode status.
#define	SYSCFG_UR13_SDRS_Pos   (0U)
#define	SYSCFG_UR13_SDRS_Msk   (0x3UL << SYSCFG_UR13_SDRS_Pos)
	0x00000003
#define	SYSCFG_UR13_SDRS   SYSCFG_UR13_SDRS_Msk
	Secured DTCM RAM Size.
#define	SYSCFG_UR13_D1SBRST_Pos   (16U)
#define	SYSCFG_UR13_D1SBRST_Msk   (0x1UL << SYSCFG_UR13_D1SBRST_Pos)
	0x00010000
#define	SYSCFG_UR13_D1SBRST   SYSCFG_UR13_D1SBRST_Msk
	D1 Standby reset.
#define	SYSCFG_UR14_D1STPRST_Pos   (0U)
#define	SYSCFG_UR14_D1STPRST_Msk   (0x1UL << SYSCFG_UR14_D1STPRST_Pos)
	0x00000001
#define	SYSCFG_UR14_D1STPRST   SYSCFG_UR14_D1STPRST_Msk
	D1 Stop Reset.
#define	SYSCFG_UR15_FZIWDGSTB_Pos   (16U)
#define	SYSCFG_UR15_FZIWDGSTB_Msk   (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos)
	0x00010000
#define	SYSCFG_UR15_FZIWDGSTB   SYSCFG_UR15_FZIWDGSTB_Msk
	Freeze independent watchdogs in Standby mode.
#define	SYSCFG_UR16_FZIWDGSTP_Pos   (0U)
#define	SYSCFG_UR16_FZIWDGSTP_Msk   (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos)
	0x00000001
#define	SYSCFG_UR16_FZIWDGSTP   SYSCFG_UR16_FZIWDGSTP_Msk
	Freeze independent watchdogs in Stop mode.
#define	SYSCFG_UR16_PKP_Pos   (16U)
#define	SYSCFG_UR16_PKP_Msk   (0x1UL << SYSCFG_UR16_PKP_Pos)
	0x00010000
#define	SYSCFG_UR16_PKP   SYSCFG_UR16_PKP_Msk
	Private key programmed.
#define	SYSCFG_UR17_IOHSLV_Pos   (0U)
#define	SYSCFG_UR17_IOHSLV_Msk   (0x1UL << SYSCFG_UR17_IOHSLV_Pos)
	0x00000001
#define	SYSCFG_UR17_IOHSLV   SYSCFG_UR17_IOHSLV_Msk
	I/O high speed / low voltage.
#define	SYSCFG_UR17_TCM_AXI_CFG_Pos   (16U)
#define	SYSCFG_UR17_TCM_AXI_CFG_Msk   (0x3UL << SYSCFG_UR17_TCM_AXI_CFG_Pos)
	0x00030000
#define	SYSCFG_UR17_TCM_AXI_CFG   SYSCFG_UR17_TCM_AXI_CFG_Msk
	ITCM-RAM / AXI-SRAM size.
#define	SYSCFG_UR18_CPU_FREQ_BOOST_Pos   (0U)
#define	SYSCFG_UR18_CPU_FREQ_BOOST_Msk   (0x1UL << SYSCFG_UR18_CPU_FREQ_BOOST_Pos)
	0x00000001
#define	SYSCFG_UR18_CPU_FREQ_BOOST   SYSCFG_UR18_CPU_FREQ_BOOST_Msk
	CPU maximum frequency boost enable.
#define	DTS_CFGR1_TS1_EN_Pos   (0U)
#define	DTS_CFGR1_TS1_EN_Msk   (0x1UL << DTS_CFGR1_TS1_EN_Pos)
	0x00000001
#define	DTS_CFGR1_TS1_EN   DTS_CFGR1_TS1_EN_Msk
	DTS Enable.
#define	DTS_CFGR1_TS1_START_Pos   (4U)
#define	DTS_CFGR1_TS1_START_Msk   (0x1UL << DTS_CFGR1_TS1_START_Pos)
	0x00000010
#define	DTS_CFGR1_TS1_START   DTS_CFGR1_TS1_START_Msk
	Proceed to a frequency measurement on DTS.
#define	DTS_CFGR1_TS1_INTRIG_SEL_Pos   (8U)
#define	DTS_CFGR1_TS1_INTRIG_SEL_Msk   (0xFUL << DTS_CFGR1_TS1_INTRIG_SEL_Pos)
	0x00000F00
#define	DTS_CFGR1_TS1_INTRIG_SEL   DTS_CFGR1_TS1_INTRIG_SEL_Msk
	Input triggers selection bits [3:0] for DTS.
#define	DTS_CFGR1_TS1_INTRIG_SEL_0   (0x1UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos)
	0x00000100
#define	DTS_CFGR1_TS1_INTRIG_SEL_1   (0x2UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos)
	0x00000200
#define	DTS_CFGR1_TS1_INTRIG_SEL_2   (0x4UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos)
	0x00000400
#define	DTS_CFGR1_TS1_INTRIG_SEL_3   (0x8UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos)
	0x00000800
#define	DTS_CFGR1_TS1_SMP_TIME_Pos   (16U)
#define	DTS_CFGR1_TS1_SMP_TIME_Msk   (0xFUL << DTS_CFGR1_TS1_SMP_TIME_Pos)
	0x000F0000
#define	DTS_CFGR1_TS1_SMP_TIME   DTS_CFGR1_TS1_SMP_TIME_Msk
	Sample time [3:0] for DTS.
#define	DTS_CFGR1_TS1_SMP_TIME_0   (0x1UL << DTS_CFGR1_TS1_SMP_TIME_Pos)
	0x00010000
#define	DTS_CFGR1_TS1_SMP_TIME_1   (0x2UL << DTS_CFGR1_TS1_SMP_TIME_Pos)
	0x00020000
#define	DTS_CFGR1_TS1_SMP_TIME_2   (0x4UL << DTS_CFGR1_TS1_SMP_TIME_Pos)
	0x00040000
#define	DTS_CFGR1_TS1_SMP_TIME_3   (0x8UL << DTS_CFGR1_TS1_SMP_TIME_Pos)
	0x00080000
#define	DTS_CFGR1_REFCLK_SEL_Pos   (20U)
#define	DTS_CFGR1_REFCLK_SEL_Msk   (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos)
	0x00100000
#define	DTS_CFGR1_REFCLK_SEL   DTS_CFGR1_REFCLK_SEL_Msk
	Reference Clock Selection.
#define	DTS_CFGR1_Q_MEAS_OPT_Pos   (21U)
#define	DTS_CFGR1_Q_MEAS_OPT_Msk   (0x1UL << DTS_CFGR1_Q_MEAS_OPT_Pos)
	0x00200000
#define	DTS_CFGR1_Q_MEAS_OPT   DTS_CFGR1_Q_MEAS_OPT_Msk
	Quick measure option bit.
#define	DTS_CFGR1_HSREF_CLK_DIV_Pos   (24U)
#define	DTS_CFGR1_HSREF_CLK_DIV_Msk   (0x7FUL << DTS_CFGR1_HSREF_CLK_DIV_Pos)
	0x7F000000
#define	DTS_CFGR1_HSREF_CLK_DIV   DTS_CFGR1_HSREF_CLK_DIV_Msk
	High Speed Clock Divider Ratio [6:0].
#define	DTS_T0VALR1_TS1_FMT0_Pos   (0U)
#define	DTS_T0VALR1_TS1_FMT0_Msk   (0xFFFFUL << DTS_T0VALR1_TS1_FMT0_Pos)
	0x0000FFFF
#define	DTS_T0VALR1_TS1_FMT0   DTS_T0VALR1_TS1_FMT0_Msk
	Engineering value of the measured frequency at T0 for DTS.
#define	DTS_T0VALR1_TS1_T0_Pos   (16U)
#define	DTS_T0VALR1_TS1_T0_Msk   (0x3UL << DTS_T0VALR1_TS1_T0_Pos)
	0x00030000
#define	DTS_T0VALR1_TS1_T0   DTS_T0VALR1_TS1_T0_Msk
	Engineering value of the DTSerature T0 for DTS.
#define	DTS_RAMPVALR_TS1_RAMP_COEFF_Pos   (0U)
#define	DTS_RAMPVALR_TS1_RAMP_COEFF_Msk   (0xFFFFUL << DTS_RAMPVALR_TS1_RAMP_COEFF_Pos)
	0x0000FFFF
#define	DTS_RAMPVALR_TS1_RAMP_COEFF   DTS_RAMPVALR_TS1_RAMP_COEFF_Msk
	Engineering value of the ramp coefficient for DTS.
#define	DTS_ITR1_TS1_LITTHD_Pos   (0U)
#define	DTS_ITR1_TS1_LITTHD_Msk   (0xFFFFUL << DTS_ITR1_TS1_LITTHD_Pos)
	0x0000FFFF
#define	DTS_ITR1_TS1_LITTHD   DTS_ITR1_TS1_LITTHD_Msk
	Low interrupt threshold[15:0] for DTS.
#define	DTS_ITR1_TS1_HITTHD_Pos   (16U)
#define	DTS_ITR1_TS1_HITTHD_Msk   (0xFFFFUL << DTS_ITR1_TS1_HITTHD_Pos)
	0xFFFF0000
#define	DTS_ITR1_TS1_HITTHD   DTS_ITR1_TS1_HITTHD_Msk
	High interrupt threshold[15:0] for DTS.
#define	DTS_DR_TS1_MFREQ_Pos   (0U)
#define	DTS_DR_TS1_MFREQ_Msk   (0xFFFFUL << DTS_DR_TS1_MFREQ_Pos)
	0x0000FFFF
#define	DTS_DR_TS1_MFREQ   DTS_DR_TS1_MFREQ_Msk
	Measured Frequency[15:0] for DTS.
#define	DTS_SR_TS1_ITEF_Pos   (0U)
#define	DTS_SR_TS1_ITEF_Msk   (0x1UL << DTS_SR_TS1_ITEF_Pos)
	0x00000001
#define	DTS_SR_TS1_ITEF   DTS_SR_TS1_ITEF_Msk
	Interrupt flag for end of measure for DTS.
#define	DTS_SR_TS1_ITLF_Pos   (1U)
#define	DTS_SR_TS1_ITLF_Msk   (0x1UL << DTS_SR_TS1_ITLF_Pos)
	0x00000002
#define	DTS_SR_TS1_ITLF   DTS_SR_TS1_ITLF_Msk
	Interrupt flag for low threshold for DTS.
#define	DTS_SR_TS1_ITHF_Pos   (2U)
#define	DTS_SR_TS1_ITHF_Msk   (0x1UL << DTS_SR_TS1_ITHF_Pos)
	0x00000004
#define	DTS_SR_TS1_ITHF   DTS_SR_TS1_ITHF_Msk
	Interrupt flag for high threshold for DTS.
#define	DTS_SR_TS1_AITEF_Pos   (4U)
#define	DTS_SR_TS1_AITEF_Msk   (0x1UL << DTS_SR_TS1_AITEF_Pos)
	0x00000010
#define	DTS_SR_TS1_AITEF   DTS_SR_TS1_AITEF_Msk
	Asynchronous interrupt flag for end of measure for DTS.
#define	DTS_SR_TS1_AITLF_Pos   (5U)
#define	DTS_SR_TS1_AITLF_Msk   (0x1UL << DTS_SR_TS1_AITLF_Pos)
	0x00000020
#define	DTS_SR_TS1_AITLF   DTS_SR_TS1_AITLF_Msk
	Asynchronous interrupt flag for low threshold for DTS.
#define	DTS_SR_TS1_AITHF_Pos   (6U)
#define	DTS_SR_TS1_AITHF_Msk   (0x1UL << DTS_SR_TS1_AITHF_Pos)
	0x00000040
#define	DTS_SR_TS1_AITHF   DTS_SR_TS1_AITHF_Msk
	Asynchronous interrupt flag for high threshold for DTS.
#define	DTS_SR_TS1_RDY_Pos   (15U)
#define	DTS_SR_TS1_RDY_Msk   (0x1UL << DTS_SR_TS1_RDY_Pos)
	0x00008000
#define	DTS_SR_TS1_RDY   DTS_SR_TS1_RDY_Msk
	DTS ready flag.
#define	DTS_ITENR_TS1_ITEEN_Pos   (0U)
#define	DTS_ITENR_TS1_ITEEN_Msk   (0x1UL << DTS_ITENR_TS1_ITEEN_Pos)
	0x00000001
#define	DTS_ITENR_TS1_ITEEN   DTS_ITENR_TS1_ITEEN_Msk
	Enable interrupt flag for end of measure for DTS.
#define	DTS_ITENR_TS1_ITLEN_Pos   (1U)
#define	DTS_ITENR_TS1_ITLEN_Msk   (0x1UL << DTS_ITENR_TS1_ITLEN_Pos)
	0x00000002
#define	DTS_ITENR_TS1_ITLEN   DTS_ITENR_TS1_ITLEN_Msk
	Enable interrupt flag for low threshold for DTS.
#define	DTS_ITENR_TS1_ITHEN_Pos   (2U)
#define	DTS_ITENR_TS1_ITHEN_Msk   (0x1UL << DTS_ITENR_TS1_ITHEN_Pos)
	0x00000004
#define	DTS_ITENR_TS1_ITHEN   DTS_ITENR_TS1_ITHEN_Msk
	Enable interrupt flag for high threshold for DTS.
#define	DTS_ITENR_TS1_AITEEN_Pos   (4U)
#define	DTS_ITENR_TS1_AITEEN_Msk   (0x1UL << DTS_ITENR_TS1_AITEEN_Pos)
	0x00000010
#define	DTS_ITENR_TS1_AITEEN   DTS_ITENR_TS1_AITEEN_Msk
	Enable asynchronous interrupt flag for end of measure for DTS.
#define	DTS_ITENR_TS1_AITLEN_Pos   (5U)
#define	DTS_ITENR_TS1_AITLEN_Msk   (0x1UL << DTS_ITENR_TS1_AITLEN_Pos)
	0x00000020
#define	DTS_ITENR_TS1_AITLEN   DTS_ITENR_TS1_AITLEN_Msk
	Enable Asynchronous interrupt flag for low threshold for DTS.
#define	DTS_ITENR_TS1_AITHEN_Pos   (6U)
#define	DTS_ITENR_TS1_AITHEN_Msk   (0x1UL << DTS_ITENR_TS1_AITHEN_Pos)
	0x00000040
#define	DTS_ITENR_TS1_AITHEN   DTS_ITENR_TS1_AITHEN_Msk
	Enable asynchronous interrupt flag for high threshold for DTS.
#define	DTS_ICIFR_TS1_CITEF_Pos   (0U)
#define	DTS_ICIFR_TS1_CITEF_Msk   (0x1UL << DTS_ICIFR_TS1_CITEF_Pos)
	0x00000001
#define	DTS_ICIFR_TS1_CITEF   DTS_ICIFR_TS1_CITEF_Msk
	Clear the IT flag for End Of Measure for DTS.
#define	DTS_ICIFR_TS1_CITLF_Pos   (1U)
#define	DTS_ICIFR_TS1_CITLF_Msk   (0x1UL << DTS_ICIFR_TS1_CITLF_Pos)
	0x00000002
#define	DTS_ICIFR_TS1_CITLF   DTS_ICIFR_TS1_CITLF_Msk
	Clear the IT flag for low threshold for DTS.
#define	DTS_ICIFR_TS1_CITHF_Pos   (2U)
#define	DTS_ICIFR_TS1_CITHF_Msk   (0x1UL << DTS_ICIFR_TS1_CITHF_Pos)
	0x00000004
#define	DTS_ICIFR_TS1_CITHF   DTS_ICIFR_TS1_CITHF_Msk
	Clear the IT flag for high threshold on DTS.
#define	DTS_ICIFR_TS1_CAITEF_Pos   (4U)
#define	DTS_ICIFR_TS1_CAITEF_Msk   (0x1UL << DTS_ICIFR_TS1_CAITEF_Pos)
	0x00000010
#define	DTS_ICIFR_TS1_CAITEF   DTS_ICIFR_TS1_CAITEF_Msk
	Clear the asynchronous IT flag for End Of Measure for DTS.
#define	DTS_ICIFR_TS1_CAITLF_Pos   (5U)
#define	DTS_ICIFR_TS1_CAITLF_Msk   (0x1UL << DTS_ICIFR_TS1_CAITLF_Pos)
	0x00000020
#define	DTS_ICIFR_TS1_CAITLF   DTS_ICIFR_TS1_CAITLF_Msk
	Clear the asynchronous IT flag for low threshold for DTS.
#define	DTS_ICIFR_TS1_CAITHF_Pos   (6U)
#define	DTS_ICIFR_TS1_CAITHF_Msk   (0x1UL << DTS_ICIFR_TS1_CAITHF_Pos)
	0x00000040
#define	DTS_ICIFR_TS1_CAITHF   DTS_ICIFR_TS1_CAITHF_Msk
	Clear the asynchronous IT flag for high threshold on DTS.
#define	TIM_BREAK_INPUT_SUPPORT
	TIM Break input feature.
#define	TIM_CR1_CEN_Pos   (0U)
#define	TIM_CR1_CEN_Msk   (0x1UL << TIM_CR1_CEN_Pos)
	0x00000001
#define	TIM_CR1_CEN   TIM_CR1_CEN_Msk
	Counter enable.
#define	TIM_CR1_UDIS_Pos   (1U)
#define	TIM_CR1_UDIS_Msk   (0x1UL << TIM_CR1_UDIS_Pos)
	0x00000002
#define	TIM_CR1_UDIS   TIM_CR1_UDIS_Msk
	Update disable.
#define	TIM_CR1_URS_Pos   (2U)
#define	TIM_CR1_URS_Msk   (0x1UL << TIM_CR1_URS_Pos)
	0x00000004
#define	TIM_CR1_URS   TIM_CR1_URS_Msk
	Update request source.
#define	TIM_CR1_OPM_Pos   (3U)
#define	TIM_CR1_OPM_Msk   (0x1UL << TIM_CR1_OPM_Pos)
	0x00000008
#define	TIM_CR1_OPM   TIM_CR1_OPM_Msk
	One pulse mode.
#define	TIM_CR1_DIR_Pos   (4U)
#define	TIM_CR1_DIR_Msk   (0x1UL << TIM_CR1_DIR_Pos)
	0x00000010
#define	TIM_CR1_DIR   TIM_CR1_DIR_Msk
	Direction.
#define	TIM_CR1_CMS_Pos   (5U)
#define	TIM_CR1_CMS_Msk   (0x3UL << TIM_CR1_CMS_Pos)
	0x00000060
#define	TIM_CR1_CMS   TIM_CR1_CMS_Msk
	CMS[1:0] bits (Center-aligned mode selection).
#define	TIM_CR1_CMS_0   (0x1UL << TIM_CR1_CMS_Pos)
	0x00000020
#define	TIM_CR1_CMS_1   (0x2UL << TIM_CR1_CMS_Pos)
	0x00000040
#define	TIM_CR1_ARPE_Pos   (7U)
#define	TIM_CR1_ARPE_Msk   (0x1UL << TIM_CR1_ARPE_Pos)
	0x00000080
#define	TIM_CR1_ARPE   TIM_CR1_ARPE_Msk
	Auto-reload preload enable.
#define	TIM_CR1_CKD_Pos   (8U)
#define	TIM_CR1_CKD_Msk   (0x3UL << TIM_CR1_CKD_Pos)
	0x00000300
#define	TIM_CR1_CKD   TIM_CR1_CKD_Msk
	CKD[1:0] bits (clock division).
#define	TIM_CR1_CKD_0   (0x1UL << TIM_CR1_CKD_Pos)
	0x00000100
#define	TIM_CR1_CKD_1   (0x2UL << TIM_CR1_CKD_Pos)
	0x00000200
#define	TIM_CR1_UIFREMAP_Pos   (11U)
#define	TIM_CR1_UIFREMAP_Msk   (0x1UL << TIM_CR1_UIFREMAP_Pos)
	0x00000800
#define	TIM_CR1_UIFREMAP   TIM_CR1_UIFREMAP_Msk
	Update interrupt flag remap.
#define	TIM_CR2_CCPC_Pos   (0U)
#define	TIM_CR2_CCPC_Msk   (0x1UL << TIM_CR2_CCPC_Pos)
	0x00000001
#define	TIM_CR2_CCPC   TIM_CR2_CCPC_Msk
	Capture/Compare Preloaded Control.
#define	TIM_CR2_CCUS_Pos   (2U)
#define	TIM_CR2_CCUS_Msk   (0x1UL << TIM_CR2_CCUS_Pos)
	0x00000004
#define	TIM_CR2_CCUS   TIM_CR2_CCUS_Msk
	Capture/Compare Control Update Selection.
#define	TIM_CR2_CCDS_Pos   (3U)
#define	TIM_CR2_CCDS_Msk   (0x1UL << TIM_CR2_CCDS_Pos)
	0x00000008
#define	TIM_CR2_CCDS   TIM_CR2_CCDS_Msk
	Capture/Compare DMA Selection.
#define	TIM_CR2_MMS_Pos   (4U)
#define	TIM_CR2_MMS_Msk   (0x7UL << TIM_CR2_MMS_Pos)
	0x00000070
#define	TIM_CR2_MMS   TIM_CR2_MMS_Msk
	MMS[2:0] bits (Master Mode Selection).
#define	TIM_CR2_MMS_0   (0x1UL << TIM_CR2_MMS_Pos)
	0x00000010
#define	TIM_CR2_MMS_1   (0x2UL << TIM_CR2_MMS_Pos)
	0x00000020
#define	TIM_CR2_MMS_2   (0x4UL << TIM_CR2_MMS_Pos)
	0x00000040
#define	TIM_CR2_TI1S_Pos   (7U)
#define	TIM_CR2_TI1S_Msk   (0x1UL << TIM_CR2_TI1S_Pos)
	0x00000080
#define	TIM_CR2_TI1S   TIM_CR2_TI1S_Msk
	TI1 Selection.
#define	TIM_CR2_OIS1_Pos   (8U)
#define	TIM_CR2_OIS1_Msk   (0x1UL << TIM_CR2_OIS1_Pos)
	0x00000100
#define	TIM_CR2_OIS1   TIM_CR2_OIS1_Msk
	Output Idle state 1 (OC1 output).
#define	TIM_CR2_OIS1N_Pos   (9U)
#define	TIM_CR2_OIS1N_Msk   (0x1UL << TIM_CR2_OIS1N_Pos)
	0x00000200
#define	TIM_CR2_OIS1N   TIM_CR2_OIS1N_Msk
	Output Idle state 1 (OC1N output).
#define	TIM_CR2_OIS2_Pos   (10U)
#define	TIM_CR2_OIS2_Msk   (0x1UL << TIM_CR2_OIS2_Pos)
	0x00000400
#define	TIM_CR2_OIS2   TIM_CR2_OIS2_Msk
	Output Idle state 2 (OC2 output).
#define	TIM_CR2_OIS2N_Pos   (11U)
#define	TIM_CR2_OIS2N_Msk   (0x1UL << TIM_CR2_OIS2N_Pos)
	0x00000800
#define	TIM_CR2_OIS2N   TIM_CR2_OIS2N_Msk
	Output Idle state 2 (OC2N output).
#define	TIM_CR2_OIS3_Pos   (12U)
#define	TIM_CR2_OIS3_Msk   (0x1UL << TIM_CR2_OIS3_Pos)
	0x00001000
#define	TIM_CR2_OIS3   TIM_CR2_OIS3_Msk
	Output Idle state 3 (OC3 output).
#define	TIM_CR2_OIS3N_Pos   (13U)
#define	TIM_CR2_OIS3N_Msk   (0x1UL << TIM_CR2_OIS3N_Pos)
	0x00002000
#define	TIM_CR2_OIS3N   TIM_CR2_OIS3N_Msk
	Output Idle state 3 (OC3N output).
#define	TIM_CR2_OIS4_Pos   (14U)
#define	TIM_CR2_OIS4_Msk   (0x1UL << TIM_CR2_OIS4_Pos)
	0x00004000
#define	TIM_CR2_OIS4   TIM_CR2_OIS4_Msk
	Output Idle state 4 (OC4 output).
#define	TIM_CR2_OIS5_Pos   (16U)
#define	TIM_CR2_OIS5_Msk   (0x1UL << TIM_CR2_OIS5_Pos)
	0x00010000
#define	TIM_CR2_OIS5   TIM_CR2_OIS5_Msk
	Output Idle state 4 (OC4 output).
#define	TIM_CR2_OIS6_Pos   (18U)
#define	TIM_CR2_OIS6_Msk   (0x1UL << TIM_CR2_OIS6_Pos)
	0x00040000
#define	TIM_CR2_OIS6   TIM_CR2_OIS6_Msk
	Output Idle state 4 (OC4 output).
#define	TIM_CR2_MMS2_Pos   (20U)
#define	TIM_CR2_MMS2_Msk   (0xFUL << TIM_CR2_MMS2_Pos)
	0x00F00000
#define	TIM_CR2_MMS2   TIM_CR2_MMS2_Msk
	MMS[2:0] bits (Master Mode Selection).
#define	TIM_CR2_MMS2_0   (0x1UL << TIM_CR2_MMS2_Pos)
	0x00100000
#define	TIM_CR2_MMS2_1   (0x2UL << TIM_CR2_MMS2_Pos)
	0x00200000
#define	TIM_CR2_MMS2_2   (0x4UL << TIM_CR2_MMS2_Pos)
	0x00400000
#define	TIM_CR2_MMS2_3   (0x8UL << TIM_CR2_MMS2_Pos)
	0x00800000
#define	TIM_SMCR_SMS_Pos   (0U)
#define	TIM_SMCR_SMS_Msk   (0x10007UL << TIM_SMCR_SMS_Pos)
	0x00010007
#define	TIM_SMCR_SMS   TIM_SMCR_SMS_Msk
	SMS[2:0] bits (Slave mode selection).
#define	TIM_SMCR_SMS_0   (0x00001UL << TIM_SMCR_SMS_Pos)
	0x00000001
#define	TIM_SMCR_SMS_1   (0x00002UL << TIM_SMCR_SMS_Pos)
	0x00000002
#define	TIM_SMCR_SMS_2   (0x00004UL << TIM_SMCR_SMS_Pos)
	0x00000004
#define	TIM_SMCR_SMS_3   (0x10000UL << TIM_SMCR_SMS_Pos)
	0x00010000
#define	TIM_SMCR_TS_Pos   (4U)
#define	TIM_SMCR_TS_Msk   (0x30007UL << TIM_SMCR_TS_Pos)
	0x00300070
#define	TIM_SMCR_TS   TIM_SMCR_TS_Msk
	TS[4:0] bits (Trigger selection).
#define	TIM_SMCR_TS_0   (0x00001UL << TIM_SMCR_TS_Pos)
	0x00000010
#define	TIM_SMCR_TS_1   (0x00002UL << TIM_SMCR_TS_Pos)
	0x00000020
#define	TIM_SMCR_TS_2   (0x00004UL << TIM_SMCR_TS_Pos)
	0x00000040
#define	TIM_SMCR_TS_3   (0x10000UL << TIM_SMCR_TS_Pos)
	0x00100000
#define	TIM_SMCR_TS_4   (0x20000UL << TIM_SMCR_TS_Pos)
	0x00200000
#define	TIM_SMCR_MSM_Pos   (7U)
#define	TIM_SMCR_MSM_Msk   (0x1UL << TIM_SMCR_MSM_Pos)
	0x00000080
#define	TIM_SMCR_MSM   TIM_SMCR_MSM_Msk
	Master/slave mode.
#define	TIM_SMCR_ETF_Pos   (8U)
#define	TIM_SMCR_ETF_Msk   (0xFUL << TIM_SMCR_ETF_Pos)
	0x00000F00
#define	TIM_SMCR_ETF   TIM_SMCR_ETF_Msk
	ETF[3:0] bits (External trigger filter).
#define	TIM_SMCR_ETF_0   (0x1UL << TIM_SMCR_ETF_Pos)
	0x00000100
#define	TIM_SMCR_ETF_1   (0x2UL << TIM_SMCR_ETF_Pos)
	0x00000200
#define	TIM_SMCR_ETF_2   (0x4UL << TIM_SMCR_ETF_Pos)
	0x00000400
#define	TIM_SMCR_ETF_3   (0x8UL << TIM_SMCR_ETF_Pos)
	0x00000800
#define	TIM_SMCR_ETPS_Pos   (12U)
#define	TIM_SMCR_ETPS_Msk   (0x3UL << TIM_SMCR_ETPS_Pos)
	0x00003000
#define	TIM_SMCR_ETPS   TIM_SMCR_ETPS_Msk
	ETPS[1:0] bits (External trigger prescaler).
#define	TIM_SMCR_ETPS_0   (0x1UL << TIM_SMCR_ETPS_Pos)
	0x00001000
#define	TIM_SMCR_ETPS_1   (0x2UL << TIM_SMCR_ETPS_Pos)
	0x00002000
#define	TIM_SMCR_ECE_Pos   (14U)
#define	TIM_SMCR_ECE_Msk   (0x1UL << TIM_SMCR_ECE_Pos)
	0x00004000
#define	TIM_SMCR_ECE   TIM_SMCR_ECE_Msk
	External clock enable.
#define	TIM_SMCR_ETP_Pos   (15U)
#define	TIM_SMCR_ETP_Msk   (0x1UL << TIM_SMCR_ETP_Pos)
	0x00008000
#define	TIM_SMCR_ETP   TIM_SMCR_ETP_Msk
	External trigger polarity.
#define	TIM_DIER_UIE_Pos   (0U)
#define	TIM_DIER_UIE_Msk   (0x1UL << TIM_DIER_UIE_Pos)
	0x00000001
#define	TIM_DIER_UIE   TIM_DIER_UIE_Msk
	Update interrupt enable.
#define	TIM_DIER_CC1IE_Pos   (1U)
#define	TIM_DIER_CC1IE_Msk   (0x1UL << TIM_DIER_CC1IE_Pos)
	0x00000002
#define	TIM_DIER_CC1IE   TIM_DIER_CC1IE_Msk
	Capture/Compare 1 interrupt enable.
#define	TIM_DIER_CC2IE_Pos   (2U)
#define	TIM_DIER_CC2IE_Msk   (0x1UL << TIM_DIER_CC2IE_Pos)
	0x00000004
#define	TIM_DIER_CC2IE   TIM_DIER_CC2IE_Msk
	Capture/Compare 2 interrupt enable.
#define	TIM_DIER_CC3IE_Pos   (3U)
#define	TIM_DIER_CC3IE_Msk   (0x1UL << TIM_DIER_CC3IE_Pos)
	0x00000008
#define	TIM_DIER_CC3IE   TIM_DIER_CC3IE_Msk
	Capture/Compare 3 interrupt enable.
#define	TIM_DIER_CC4IE_Pos   (4U)
#define	TIM_DIER_CC4IE_Msk   (0x1UL << TIM_DIER_CC4IE_Pos)
	0x00000010
#define	TIM_DIER_CC4IE   TIM_DIER_CC4IE_Msk
	Capture/Compare 4 interrupt enable.
#define	TIM_DIER_COMIE_Pos   (5U)
#define	TIM_DIER_COMIE_Msk   (0x1UL << TIM_DIER_COMIE_Pos)
	0x00000020
#define	TIM_DIER_COMIE   TIM_DIER_COMIE_Msk
	COM interrupt enable.
#define	TIM_DIER_TIE_Pos   (6U)
#define	TIM_DIER_TIE_Msk   (0x1UL << TIM_DIER_TIE_Pos)
	0x00000040
#define	TIM_DIER_TIE   TIM_DIER_TIE_Msk
	Trigger interrupt enable.
#define	TIM_DIER_BIE_Pos   (7U)
#define	TIM_DIER_BIE_Msk   (0x1UL << TIM_DIER_BIE_Pos)
	0x00000080
#define	TIM_DIER_BIE   TIM_DIER_BIE_Msk
	Break interrupt enable.
#define	TIM_DIER_UDE_Pos   (8U)
#define	TIM_DIER_UDE_Msk   (0x1UL << TIM_DIER_UDE_Pos)
	0x00000100
#define	TIM_DIER_UDE   TIM_DIER_UDE_Msk
	Update DMA request enable.
#define	TIM_DIER_CC1DE_Pos   (9U)
#define	TIM_DIER_CC1DE_Msk   (0x1UL << TIM_DIER_CC1DE_Pos)
	0x00000200
#define	TIM_DIER_CC1DE   TIM_DIER_CC1DE_Msk
	Capture/Compare 1 DMA request enable.
#define	TIM_DIER_CC2DE_Pos   (10U)
#define	TIM_DIER_CC2DE_Msk   (0x1UL << TIM_DIER_CC2DE_Pos)
	0x00000400
#define	TIM_DIER_CC2DE   TIM_DIER_CC2DE_Msk
	Capture/Compare 2 DMA request enable.
#define	TIM_DIER_CC3DE_Pos   (11U)
#define	TIM_DIER_CC3DE_Msk   (0x1UL << TIM_DIER_CC3DE_Pos)
	0x00000800
#define	TIM_DIER_CC3DE   TIM_DIER_CC3DE_Msk
	Capture/Compare 3 DMA request enable.
#define	TIM_DIER_CC4DE_Pos   (12U)
#define	TIM_DIER_CC4DE_Msk   (0x1UL << TIM_DIER_CC4DE_Pos)
	0x00001000
#define	TIM_DIER_CC4DE   TIM_DIER_CC4DE_Msk
	Capture/Compare 4 DMA request enable.
#define	TIM_DIER_COMDE_Pos   (13U)
#define	TIM_DIER_COMDE_Msk   (0x1UL << TIM_DIER_COMDE_Pos)
	0x00002000
#define	TIM_DIER_COMDE   TIM_DIER_COMDE_Msk
	COM DMA request enable.
#define	TIM_DIER_TDE_Pos   (14U)
#define	TIM_DIER_TDE_Msk   (0x1UL << TIM_DIER_TDE_Pos)
	0x00004000
#define	TIM_DIER_TDE   TIM_DIER_TDE_Msk
	Trigger DMA request enable.
#define	TIM_SR_UIF_Pos   (0U)
#define	TIM_SR_UIF_Msk   (0x1UL << TIM_SR_UIF_Pos)
	0x00000001
#define	TIM_SR_UIF   TIM_SR_UIF_Msk
	Update interrupt Flag.
#define	TIM_SR_CC1IF_Pos   (1U)
#define	TIM_SR_CC1IF_Msk   (0x1UL << TIM_SR_CC1IF_Pos)
	0x00000002
#define	TIM_SR_CC1IF   TIM_SR_CC1IF_Msk
	Capture/Compare 1 interrupt Flag.
#define	TIM_SR_CC2IF_Pos   (2U)
#define	TIM_SR_CC2IF_Msk   (0x1UL << TIM_SR_CC2IF_Pos)
	0x00000004
#define	TIM_SR_CC2IF   TIM_SR_CC2IF_Msk
	Capture/Compare 2 interrupt Flag.
#define	TIM_SR_CC3IF_Pos   (3U)
#define	TIM_SR_CC3IF_Msk   (0x1UL << TIM_SR_CC3IF_Pos)
	0x00000008
#define	TIM_SR_CC3IF   TIM_SR_CC3IF_Msk
	Capture/Compare 3 interrupt Flag.
#define	TIM_SR_CC4IF_Pos   (4U)
#define	TIM_SR_CC4IF_Msk   (0x1UL << TIM_SR_CC4IF_Pos)
	0x00000010
#define	TIM_SR_CC4IF   TIM_SR_CC4IF_Msk
	Capture/Compare 4 interrupt Flag.
#define	TIM_SR_COMIF_Pos   (5U)
#define	TIM_SR_COMIF_Msk   (0x1UL << TIM_SR_COMIF_Pos)
	0x00000020
#define	TIM_SR_COMIF   TIM_SR_COMIF_Msk
	COM interrupt Flag.
#define	TIM_SR_TIF_Pos   (6U)
#define	TIM_SR_TIF_Msk   (0x1UL << TIM_SR_TIF_Pos)
	0x00000040
#define	TIM_SR_TIF   TIM_SR_TIF_Msk
	Trigger interrupt Flag.
#define	TIM_SR_BIF_Pos   (7U)
#define	TIM_SR_BIF_Msk   (0x1UL << TIM_SR_BIF_Pos)
	0x00000080
#define	TIM_SR_BIF   TIM_SR_BIF_Msk
	Break interrupt Flag.
#define	TIM_SR_B2IF_Pos   (8U)
#define	TIM_SR_B2IF_Msk   (0x1UL << TIM_SR_B2IF_Pos)
	0x00000100
#define	TIM_SR_B2IF   TIM_SR_B2IF_Msk
	Break2 interrupt Flag.
#define	TIM_SR_CC1OF_Pos   (9U)
#define	TIM_SR_CC1OF_Msk   (0x1UL << TIM_SR_CC1OF_Pos)
	0x00000200
#define	TIM_SR_CC1OF   TIM_SR_CC1OF_Msk
	Capture/Compare 1 Overcapture Flag.
#define	TIM_SR_CC2OF_Pos   (10U)
#define	TIM_SR_CC2OF_Msk   (0x1UL << TIM_SR_CC2OF_Pos)
	0x00000400
#define	TIM_SR_CC2OF   TIM_SR_CC2OF_Msk
	Capture/Compare 2 Overcapture Flag.
#define	TIM_SR_CC3OF_Pos   (11U)
#define	TIM_SR_CC3OF_Msk   (0x1UL << TIM_SR_CC3OF_Pos)
	0x00000800
#define	TIM_SR_CC3OF   TIM_SR_CC3OF_Msk
	Capture/Compare 3 Overcapture Flag.
#define	TIM_SR_CC4OF_Pos   (12U)
#define	TIM_SR_CC4OF_Msk   (0x1UL << TIM_SR_CC4OF_Pos)
	0x00001000
#define	TIM_SR_CC4OF   TIM_SR_CC4OF_Msk
	Capture/Compare 4 Overcapture Flag.
#define	TIM_SR_CC5IF_Pos   (16U)
#define	TIM_SR_CC5IF_Msk   (0x1UL << TIM_SR_CC5IF_Pos)
	0x00010000
#define	TIM_SR_CC5IF   TIM_SR_CC5IF_Msk
	Capture/Compare 5 interrupt Flag.
#define	TIM_SR_CC6IF_Pos   (17U)
#define	TIM_SR_CC6IF_Msk   (0x1UL << TIM_SR_CC6IF_Pos)
	0x00020000
#define	TIM_SR_CC6IF   TIM_SR_CC6IF_Msk
	Capture/Compare 6 interrupt Flag.
#define	TIM_SR_SBIF_Pos   (13U)
#define	TIM_SR_SBIF_Msk   (0x1UL << TIM_SR_SBIF_Pos)
	0x00002000
#define	TIM_SR_SBIF   TIM_SR_SBIF_Msk
	System Break Flag.
#define	TIM_EGR_UG_Pos   (0U)
#define	TIM_EGR_UG_Msk   (0x1UL << TIM_EGR_UG_Pos)
	0x00000001
#define	TIM_EGR_UG   TIM_EGR_UG_Msk
	Update Generation.
#define	TIM_EGR_CC1G_Pos   (1U)
#define	TIM_EGR_CC1G_Msk   (0x1UL << TIM_EGR_CC1G_Pos)
	0x00000002
#define	TIM_EGR_CC1G   TIM_EGR_CC1G_Msk
	Capture/Compare 1 Generation.
#define	TIM_EGR_CC2G_Pos   (2U)
#define	TIM_EGR_CC2G_Msk   (0x1UL << TIM_EGR_CC2G_Pos)
	0x00000004
#define	TIM_EGR_CC2G   TIM_EGR_CC2G_Msk
	Capture/Compare 2 Generation.
#define	TIM_EGR_CC3G_Pos   (3U)
#define	TIM_EGR_CC3G_Msk   (0x1UL << TIM_EGR_CC3G_Pos)
	0x00000008
#define	TIM_EGR_CC3G   TIM_EGR_CC3G_Msk
	Capture/Compare 3 Generation.
#define	TIM_EGR_CC4G_Pos   (4U)
#define	TIM_EGR_CC4G_Msk   (0x1UL << TIM_EGR_CC4G_Pos)
	0x00000010
#define	TIM_EGR_CC4G   TIM_EGR_CC4G_Msk
	Capture/Compare 4 Generation.
#define	TIM_EGR_COMG_Pos   (5U)
#define	TIM_EGR_COMG_Msk   (0x1UL << TIM_EGR_COMG_Pos)
	0x00000020
#define	TIM_EGR_COMG   TIM_EGR_COMG_Msk
	Capture/Compare Control Update Generation.
#define	TIM_EGR_TG_Pos   (6U)
#define	TIM_EGR_TG_Msk   (0x1UL << TIM_EGR_TG_Pos)
	0x00000040
#define	TIM_EGR_TG   TIM_EGR_TG_Msk
	Trigger Generation.
#define	TIM_EGR_BG_Pos   (7U)
#define	TIM_EGR_BG_Msk   (0x1UL << TIM_EGR_BG_Pos)
	0x00000080
#define	TIM_EGR_BG   TIM_EGR_BG_Msk
	Break Generation.
#define	TIM_EGR_B2G_Pos   (8U)
#define	TIM_EGR_B2G_Msk   (0x1UL << TIM_EGR_B2G_Pos)
	0x00000100
#define	TIM_EGR_B2G   TIM_EGR_B2G_Msk
	Break Generation.
#define	TIM_CCMR1_CC1S_Pos   (0U)
#define	TIM_CCMR1_CC1S_Msk   (0x3UL << TIM_CCMR1_CC1S_Pos)
	0x00000003
#define	TIM_CCMR1_CC1S   TIM_CCMR1_CC1S_Msk
	CC1S[1:0] bits (Capture/Compare 1 Selection).
#define	TIM_CCMR1_CC1S_0   (0x1UL << TIM_CCMR1_CC1S_Pos)
	0x00000001
#define	TIM_CCMR1_CC1S_1   (0x2UL << TIM_CCMR1_CC1S_Pos)
	0x00000002
#define	TIM_CCMR1_OC1FE_Pos   (2U)
#define	TIM_CCMR1_OC1FE_Msk   (0x1UL << TIM_CCMR1_OC1FE_Pos)
	0x00000004
#define	TIM_CCMR1_OC1FE   TIM_CCMR1_OC1FE_Msk
	Output Compare 1 Fast enable.
#define	TIM_CCMR1_OC1PE_Pos   (3U)
#define	TIM_CCMR1_OC1PE_Msk   (0x1UL << TIM_CCMR1_OC1PE_Pos)
	0x00000008
#define	TIM_CCMR1_OC1PE   TIM_CCMR1_OC1PE_Msk
	Output Compare 1 Preload enable.
#define	TIM_CCMR1_OC1M_Pos   (4U)
#define	TIM_CCMR1_OC1M_Msk   (0x1007UL << TIM_CCMR1_OC1M_Pos)
	0x00010070
#define	TIM_CCMR1_OC1M   TIM_CCMR1_OC1M_Msk
	OC1M[2:0] bits (Output Compare 1 Mode).
#define	TIM_CCMR1_OC1M_0   (0x0001UL << TIM_CCMR1_OC1M_Pos)
	0x00000010
#define	TIM_CCMR1_OC1M_1   (0x0002UL << TIM_CCMR1_OC1M_Pos)
	0x00000020
#define	TIM_CCMR1_OC1M_2   (0x0004UL << TIM_CCMR1_OC1M_Pos)
	0x00000040
#define	TIM_CCMR1_OC1M_3   (0x1000UL << TIM_CCMR1_OC1M_Pos)
	0x00010000
#define	TIM_CCMR1_OC1CE_Pos   (7U)
#define	TIM_CCMR1_OC1CE_Msk   (0x1UL << TIM_CCMR1_OC1CE_Pos)
	0x00000080
#define	TIM_CCMR1_OC1CE   TIM_CCMR1_OC1CE_Msk
	Output Compare 1Clear Enable.
#define	TIM_CCMR1_CC2S_Pos   (8U)
#define	TIM_CCMR1_CC2S_Msk   (0x3UL << TIM_CCMR1_CC2S_Pos)
	0x00000300
#define	TIM_CCMR1_CC2S   TIM_CCMR1_CC2S_Msk
	CC2S[1:0] bits (Capture/Compare 2 Selection).
#define	TIM_CCMR1_CC2S_0   (0x1UL << TIM_CCMR1_CC2S_Pos)
	0x00000100
#define	TIM_CCMR1_CC2S_1   (0x2UL << TIM_CCMR1_CC2S_Pos)
	0x00000200
#define	TIM_CCMR1_OC2FE_Pos   (10U)
#define	TIM_CCMR1_OC2FE_Msk   (0x1UL << TIM_CCMR1_OC2FE_Pos)
	0x00000400
#define	TIM_CCMR1_OC2FE   TIM_CCMR1_OC2FE_Msk
	Output Compare 2 Fast enable.
#define	TIM_CCMR1_OC2PE_Pos   (11U)
#define	TIM_CCMR1_OC2PE_Msk   (0x1UL << TIM_CCMR1_OC2PE_Pos)
	0x00000800
#define	TIM_CCMR1_OC2PE   TIM_CCMR1_OC2PE_Msk
	Output Compare 2 Preload enable.
#define	TIM_CCMR1_OC2M_Pos   (12U)
#define	TIM_CCMR1_OC2M_Msk   (0x1007UL << TIM_CCMR1_OC2M_Pos)
	0x01007000
#define	TIM_CCMR1_OC2M   TIM_CCMR1_OC2M_Msk
	OC2M[2:0] bits (Output Compare 2 Mode).
#define	TIM_CCMR1_OC2M_0   (0x0001UL << TIM_CCMR1_OC2M_Pos)
	0x00001000
#define	TIM_CCMR1_OC2M_1   (0x0002UL << TIM_CCMR1_OC2M_Pos)
	0x00002000
#define	TIM_CCMR1_OC2M_2   (0x0004UL << TIM_CCMR1_OC2M_Pos)
	0x00004000
#define	TIM_CCMR1_OC2M_3   (0x1000UL << TIM_CCMR1_OC2M_Pos)
	0x01000000
#define	TIM_CCMR1_OC2CE_Pos   (15U)
#define	TIM_CCMR1_OC2CE_Msk   (0x1UL << TIM_CCMR1_OC2CE_Pos)
	0x00008000
#define	TIM_CCMR1_OC2CE   TIM_CCMR1_OC2CE_Msk
	Output Compare 2 Clear Enable.
#define	TIM_CCMR1_IC1PSC_Pos   (2U)
#define	TIM_CCMR1_IC1PSC_Msk   (0x3UL << TIM_CCMR1_IC1PSC_Pos)
	0x0000000C
#define	TIM_CCMR1_IC1PSC   TIM_CCMR1_IC1PSC_Msk
	IC1PSC[1:0] bits (Input Capture 1 Prescaler).
#define	TIM_CCMR1_IC1PSC_0   (0x1UL << TIM_CCMR1_IC1PSC_Pos)
	0x00000004
#define	TIM_CCMR1_IC1PSC_1   (0x2UL << TIM_CCMR1_IC1PSC_Pos)
	0x00000008
#define	TIM_CCMR1_IC1F_Pos   (4U)
#define	TIM_CCMR1_IC1F_Msk   (0xFUL << TIM_CCMR1_IC1F_Pos)
	0x000000F0
#define	TIM_CCMR1_IC1F   TIM_CCMR1_IC1F_Msk
	IC1F[3:0] bits (Input Capture 1 Filter).
#define	TIM_CCMR1_IC1F_0   (0x1UL << TIM_CCMR1_IC1F_Pos)
	0x00000010
#define	TIM_CCMR1_IC1F_1   (0x2UL << TIM_CCMR1_IC1F_Pos)
	0x00000020
#define	TIM_CCMR1_IC1F_2   (0x4UL << TIM_CCMR1_IC1F_Pos)
	0x00000040
#define	TIM_CCMR1_IC1F_3   (0x8UL << TIM_CCMR1_IC1F_Pos)
	0x00000080
#define	TIM_CCMR1_IC2PSC_Pos   (10U)
#define	TIM_CCMR1_IC2PSC_Msk   (0x3UL << TIM_CCMR1_IC2PSC_Pos)
	0x00000C00
#define	TIM_CCMR1_IC2PSC   TIM_CCMR1_IC2PSC_Msk
	IC2PSC[1:0] bits (Input Capture 2 Prescaler).
#define	TIM_CCMR1_IC2PSC_0   (0x1UL << TIM_CCMR1_IC2PSC_Pos)
	0x00000400
#define	TIM_CCMR1_IC2PSC_1   (0x2UL << TIM_CCMR1_IC2PSC_Pos)
	0x00000800
#define	TIM_CCMR1_IC2F_Pos   (12U)
#define	TIM_CCMR1_IC2F_Msk   (0xFUL << TIM_CCMR1_IC2F_Pos)
	0x0000F000
#define	TIM_CCMR1_IC2F   TIM_CCMR1_IC2F_Msk
	IC2F[3:0] bits (Input Capture 2 Filter).
#define	TIM_CCMR1_IC2F_0   (0x1UL << TIM_CCMR1_IC2F_Pos)
	0x00001000
#define	TIM_CCMR1_IC2F_1   (0x2UL << TIM_CCMR1_IC2F_Pos)
	0x00002000
#define	TIM_CCMR1_IC2F_2   (0x4UL << TIM_CCMR1_IC2F_Pos)
	0x00004000
#define	TIM_CCMR1_IC2F_3   (0x8UL << TIM_CCMR1_IC2F_Pos)
	0x00008000
#define	TIM_CCMR2_CC3S_Pos   (0U)
#define	TIM_CCMR2_CC3S_Msk   (0x3UL << TIM_CCMR2_CC3S_Pos)
	0x00000003
#define	TIM_CCMR2_CC3S   TIM_CCMR2_CC3S_Msk
	CC3S[1:0] bits (Capture/Compare 3 Selection).
#define	TIM_CCMR2_CC3S_0   (0x1UL << TIM_CCMR2_CC3S_Pos)
	0x00000001
#define	TIM_CCMR2_CC3S_1   (0x2UL << TIM_CCMR2_CC3S_Pos)
	0x00000002
#define	TIM_CCMR2_OC3FE_Pos   (2U)
#define	TIM_CCMR2_OC3FE_Msk   (0x1UL << TIM_CCMR2_OC3FE_Pos)
	0x00000004
#define	TIM_CCMR2_OC3FE   TIM_CCMR2_OC3FE_Msk
	Output Compare 3 Fast enable.
#define	TIM_CCMR2_OC3PE_Pos   (3U)
#define	TIM_CCMR2_OC3PE_Msk   (0x1UL << TIM_CCMR2_OC3PE_Pos)
	0x00000008
#define	TIM_CCMR2_OC3PE   TIM_CCMR2_OC3PE_Msk
	Output Compare 3 Preload enable.
#define	TIM_CCMR2_OC3M_Pos   (4U)
#define	TIM_CCMR2_OC3M_Msk   (0x1007UL << TIM_CCMR2_OC3M_Pos)
	0x00010070
#define	TIM_CCMR2_OC3M   TIM_CCMR2_OC3M_Msk
	OC3M[3:0] bits (Output Compare 3 Mode).
#define	TIM_CCMR2_OC3M_0   (0x1UL << TIM_CCMR2_OC3M_Pos)
	0x00000010
#define	TIM_CCMR2_OC3M_1   (0x2UL << TIM_CCMR2_OC3M_Pos)
	0x00000020
#define	TIM_CCMR2_OC3M_2   (0x4UL << TIM_CCMR2_OC3M_Pos)
	0x00000040
#define	TIM_CCMR2_OC3M_3   (0x1000UL << TIM_CCMR2_OC3M_Pos)
	0x00010000
#define	TIM_CCMR2_OC3CE_Pos   (7U)
#define	TIM_CCMR2_OC3CE_Msk   (0x1UL << TIM_CCMR2_OC3CE_Pos)
	0x00000080
#define	TIM_CCMR2_OC3CE   TIM_CCMR2_OC3CE_Msk
	Output Compare 3 Clear Enable.
#define	TIM_CCMR2_CC4S_Pos   (8U)
#define	TIM_CCMR2_CC4S_Msk   (0x3UL << TIM_CCMR2_CC4S_Pos)
	0x00000300
#define	TIM_CCMR2_CC4S   TIM_CCMR2_CC4S_Msk
	CC4S[1:0] bits (Capture/Compare 4 Selection).
#define	TIM_CCMR2_CC4S_0   (0x1UL << TIM_CCMR2_CC4S_Pos)
	0x00000100
#define	TIM_CCMR2_CC4S_1   (0x2UL << TIM_CCMR2_CC4S_Pos)
	0x00000200
#define	TIM_CCMR2_OC4FE_Pos   (10U)
#define	TIM_CCMR2_OC4FE_Msk   (0x1UL << TIM_CCMR2_OC4FE_Pos)
	0x00000400
#define	TIM_CCMR2_OC4FE   TIM_CCMR2_OC4FE_Msk
	Output Compare 4 Fast enable.
#define	TIM_CCMR2_OC4PE_Pos   (11U)
#define	TIM_CCMR2_OC4PE_Msk   (0x1UL << TIM_CCMR2_OC4PE_Pos)
	0x00000800
#define	TIM_CCMR2_OC4PE   TIM_CCMR2_OC4PE_Msk
	Output Compare 4 Preload enable.
#define	TIM_CCMR2_OC4M_Pos   (12U)
#define	TIM_CCMR2_OC4M_Msk   (0x1007UL << TIM_CCMR2_OC4M_Pos)
	0x01007000
#define	TIM_CCMR2_OC4M   TIM_CCMR2_OC4M_Msk
	OC4M[3:0] bits (Output Compare 4 Mode).
#define	TIM_CCMR2_OC4M_0   (0x1UL << TIM_CCMR2_OC4M_Pos)
	0x00001000
#define	TIM_CCMR2_OC4M_1   (0x2UL << TIM_CCMR2_OC4M_Pos)
	0x00002000
#define	TIM_CCMR2_OC4M_2   (0x4UL << TIM_CCMR2_OC4M_Pos)
	0x00004000
#define	TIM_CCMR2_OC4M_3   (0x1000UL << TIM_CCMR2_OC4M_Pos)
	0x01000000
#define	TIM_CCMR2_OC4CE_Pos   (15U)
#define	TIM_CCMR2_OC4CE_Msk   (0x1UL << TIM_CCMR2_OC4CE_Pos)
	0x00008000
#define	TIM_CCMR2_OC4CE   TIM_CCMR2_OC4CE_Msk
	Output Compare 4 Clear Enable.
#define	TIM_CCMR2_IC3PSC_Pos   (2U)
#define	TIM_CCMR2_IC3PSC_Msk   (0x3UL << TIM_CCMR2_IC3PSC_Pos)
	0x0000000C
#define	TIM_CCMR2_IC3PSC   TIM_CCMR2_IC3PSC_Msk
	IC3PSC[1:0] bits (Input Capture 3 Prescaler).
#define	TIM_CCMR2_IC3PSC_0   (0x1UL << TIM_CCMR2_IC3PSC_Pos)
	0x00000004
#define	TIM_CCMR2_IC3PSC_1   (0x2UL << TIM_CCMR2_IC3PSC_Pos)
	0x00000008
#define	TIM_CCMR2_IC3F_Pos   (4U)
#define	TIM_CCMR2_IC3F_Msk   (0xFUL << TIM_CCMR2_IC3F_Pos)
	0x000000F0
#define	TIM_CCMR2_IC3F   TIM_CCMR2_IC3F_Msk
	IC3F[3:0] bits (Input Capture 3 Filter).
#define	TIM_CCMR2_IC3F_0   (0x1UL << TIM_CCMR2_IC3F_Pos)
	0x00000010
#define	TIM_CCMR2_IC3F_1   (0x2UL << TIM_CCMR2_IC3F_Pos)
	0x00000020
#define	TIM_CCMR2_IC3F_2   (0x4UL << TIM_CCMR2_IC3F_Pos)
	0x00000040
#define	TIM_CCMR2_IC3F_3   (0x8UL << TIM_CCMR2_IC3F_Pos)
	0x00000080
#define	TIM_CCMR2_IC4PSC_Pos   (10U)
#define	TIM_CCMR2_IC4PSC_Msk   (0x3UL << TIM_CCMR2_IC4PSC_Pos)
	0x00000C00
#define	TIM_CCMR2_IC4PSC   TIM_CCMR2_IC4PSC_Msk
	IC4PSC[1:0] bits (Input Capture 4 Prescaler).
#define	TIM_CCMR2_IC4PSC_0   (0x1UL << TIM_CCMR2_IC4PSC_Pos)
	0x00000400
#define	TIM_CCMR2_IC4PSC_1   (0x2UL << TIM_CCMR2_IC4PSC_Pos)
	0x00000800
#define	TIM_CCMR2_IC4F_Pos   (12U)
#define	TIM_CCMR2_IC4F_Msk   (0xFUL << TIM_CCMR2_IC4F_Pos)
	0x0000F000
#define	TIM_CCMR2_IC4F   TIM_CCMR2_IC4F_Msk
	IC4F[3:0] bits (Input Capture 4 Filter).
#define	TIM_CCMR2_IC4F_0   (0x1UL << TIM_CCMR2_IC4F_Pos)
	0x00001000
#define	TIM_CCMR2_IC4F_1   (0x2UL << TIM_CCMR2_IC4F_Pos)
	0x00002000
#define	TIM_CCMR2_IC4F_2   (0x4UL << TIM_CCMR2_IC4F_Pos)
	0x00004000
#define	TIM_CCMR2_IC4F_3   (0x8UL << TIM_CCMR2_IC4F_Pos)
	0x00008000
#define	TIM_CCER_CC1E_Pos   (0U)
#define	TIM_CCER_CC1E_Msk   (0x1UL << TIM_CCER_CC1E_Pos)
	0x00000001
#define	TIM_CCER_CC1E   TIM_CCER_CC1E_Msk
	Capture/Compare 1 output enable.
#define	TIM_CCER_CC1P_Pos   (1U)
#define	TIM_CCER_CC1P_Msk   (0x1UL << TIM_CCER_CC1P_Pos)
	0x00000002
#define	TIM_CCER_CC1P   TIM_CCER_CC1P_Msk
	Capture/Compare 1 output Polarity.
#define	TIM_CCER_CC1NE_Pos   (2U)
#define	TIM_CCER_CC1NE_Msk   (0x1UL << TIM_CCER_CC1NE_Pos)
	0x00000004
#define	TIM_CCER_CC1NE   TIM_CCER_CC1NE_Msk
	Capture/Compare 1 Complementary output enable.
#define	TIM_CCER_CC1NP_Pos   (3U)
#define	TIM_CCER_CC1NP_Msk   (0x1UL << TIM_CCER_CC1NP_Pos)
	0x00000008
#define	TIM_CCER_CC1NP   TIM_CCER_CC1NP_Msk
	Capture/Compare 1 Complementary output Polarity.
#define	TIM_CCER_CC2E_Pos   (4U)
#define	TIM_CCER_CC2E_Msk   (0x1UL << TIM_CCER_CC2E_Pos)
	0x00000010
#define	TIM_CCER_CC2E   TIM_CCER_CC2E_Msk
	Capture/Compare 2 output enable.
#define	TIM_CCER_CC2P_Pos   (5U)
#define	TIM_CCER_CC2P_Msk   (0x1UL << TIM_CCER_CC2P_Pos)
	0x00000020
#define	TIM_CCER_CC2P   TIM_CCER_CC2P_Msk
	Capture/Compare 2 output Polarity.
#define	TIM_CCER_CC2NE_Pos   (6U)
#define	TIM_CCER_CC2NE_Msk   (0x1UL << TIM_CCER_CC2NE_Pos)
	0x00000040
#define	TIM_CCER_CC2NE   TIM_CCER_CC2NE_Msk
	Capture/Compare 2 Complementary output enable.
#define	TIM_CCER_CC2NP_Pos   (7U)
#define	TIM_CCER_CC2NP_Msk   (0x1UL << TIM_CCER_CC2NP_Pos)
	0x00000080
#define	TIM_CCER_CC2NP   TIM_CCER_CC2NP_Msk
	Capture/Compare 2 Complementary output Polarity.
#define	TIM_CCER_CC3E_Pos   (8U)
#define	TIM_CCER_CC3E_Msk   (0x1UL << TIM_CCER_CC3E_Pos)
	0x00000100
#define	TIM_CCER_CC3E   TIM_CCER_CC3E_Msk
	Capture/Compare 3 output enable.
#define	TIM_CCER_CC3P_Pos   (9U)
#define	TIM_CCER_CC3P_Msk   (0x1UL << TIM_CCER_CC3P_Pos)
	0x00000200
#define	TIM_CCER_CC3P   TIM_CCER_CC3P_Msk
	Capture/Compare 3 output Polarity.
#define	TIM_CCER_CC3NE_Pos   (10U)
#define	TIM_CCER_CC3NE_Msk   (0x1UL << TIM_CCER_CC3NE_Pos)
	0x00000400
#define	TIM_CCER_CC3NE   TIM_CCER_CC3NE_Msk
	Capture/Compare 3 Complementary output enable.
#define	TIM_CCER_CC3NP_Pos   (11U)
#define	TIM_CCER_CC3NP_Msk   (0x1UL << TIM_CCER_CC3NP_Pos)
	0x00000800
#define	TIM_CCER_CC3NP   TIM_CCER_CC3NP_Msk
	Capture/Compare 3 Complementary output Polarity.
#define	TIM_CCER_CC4E_Pos   (12U)
#define	TIM_CCER_CC4E_Msk   (0x1UL << TIM_CCER_CC4E_Pos)
	0x00001000
#define	TIM_CCER_CC4E   TIM_CCER_CC4E_Msk
	Capture/Compare 4 output enable.
#define	TIM_CCER_CC4P_Pos   (13U)
#define	TIM_CCER_CC4P_Msk   (0x1UL << TIM_CCER_CC4P_Pos)
	0x00002000
#define	TIM_CCER_CC4P   TIM_CCER_CC4P_Msk
	Capture/Compare 4 output Polarity.
#define	TIM_CCER_CC4NP_Pos   (15U)
#define	TIM_CCER_CC4NP_Msk   (0x1UL << TIM_CCER_CC4NP_Pos)
	0x00008000
#define	TIM_CCER_CC4NP   TIM_CCER_CC4NP_Msk
	Capture/Compare 4 Complementary output Polarity.
#define	TIM_CCER_CC5E_Pos   (16U)
#define	TIM_CCER_CC5E_Msk   (0x1UL << TIM_CCER_CC5E_Pos)
	0x00010000
#define	TIM_CCER_CC5E   TIM_CCER_CC5E_Msk
	Capture/Compare 5 output enable.
#define	TIM_CCER_CC5P_Pos   (17U)
#define	TIM_CCER_CC5P_Msk   (0x1UL << TIM_CCER_CC5P_Pos)
	0x00020000
#define	TIM_CCER_CC5P   TIM_CCER_CC5P_Msk
	Capture/Compare 5 output Polarity.
#define	TIM_CCER_CC6E_Pos   (20U)
#define	TIM_CCER_CC6E_Msk   (0x1UL << TIM_CCER_CC6E_Pos)
	0x00100000
#define	TIM_CCER_CC6E   TIM_CCER_CC6E_Msk
	Capture/Compare 6 output enable.
#define	TIM_CCER_CC6P_Pos   (21U)
#define	TIM_CCER_CC6P_Msk   (0x1UL << TIM_CCER_CC6P_Pos)
	0x00200000
#define	TIM_CCER_CC6P   TIM_CCER_CC6P_Msk
	Capture/Compare 6 output Polarity.
#define	TIM_CNT_CNT_Pos   (0U)
#define	TIM_CNT_CNT_Msk   (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
	0xFFFFFFFF
#define	TIM_CNT_CNT   TIM_CNT_CNT_Msk
	Counter Value.
#define	TIM_CNT_UIFCPY_Pos   (31U)
#define	TIM_CNT_UIFCPY_Msk   (0x1UL << TIM_CNT_UIFCPY_Pos)
	0x80000000
#define	TIM_CNT_UIFCPY   TIM_CNT_UIFCPY_Msk
	Update interrupt flag copy.
#define	TIM_PSC_PSC_Pos   (0U)
#define	TIM_PSC_PSC_Msk   (0xFFFFUL << TIM_PSC_PSC_Pos)
	0x0000FFFF
#define	TIM_PSC_PSC   TIM_PSC_PSC_Msk
	Prescaler Value.
#define	TIM_ARR_ARR_Pos   (0U)
#define	TIM_ARR_ARR_Msk   (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
	0xFFFFFFFF
#define	TIM_ARR_ARR   TIM_ARR_ARR_Msk
	actual auto-reload Value
#define	TIM_RCR_REP_Pos   (0U)
#define	TIM_RCR_REP_Msk   (0xFFUL << TIM_RCR_REP_Pos)
	0x000000FF
#define	TIM_RCR_REP   TIM_RCR_REP_Msk
	Repetition Counter Value.
#define	TIM_CCR1_CCR1_Pos   (0U)
#define	TIM_CCR1_CCR1_Msk   (0xFFFFUL << TIM_CCR1_CCR1_Pos)
	0x0000FFFF
#define	TIM_CCR1_CCR1   TIM_CCR1_CCR1_Msk
	Capture/Compare 1 Value.
#define	TIM_CCR2_CCR2_Pos   (0U)
#define	TIM_CCR2_CCR2_Msk   (0xFFFFUL << TIM_CCR2_CCR2_Pos)
	0x0000FFFF
#define	TIM_CCR2_CCR2   TIM_CCR2_CCR2_Msk
	Capture/Compare 2 Value.
#define	TIM_CCR3_CCR3_Pos   (0U)
#define	TIM_CCR3_CCR3_Msk   (0xFFFFUL << TIM_CCR3_CCR3_Pos)
	0x0000FFFF
#define	TIM_CCR3_CCR3   TIM_CCR3_CCR3_Msk
	Capture/Compare 3 Value.
#define	TIM_CCR4_CCR4_Pos   (0U)
#define	TIM_CCR4_CCR4_Msk   (0xFFFFUL << TIM_CCR4_CCR4_Pos)
	0x0000FFFF
#define	TIM_CCR4_CCR4   TIM_CCR4_CCR4_Msk
	Capture/Compare 4 Value.
#define	TIM_CCR5_CCR5_Pos   (0U)
#define	TIM_CCR5_CCR5_Msk   (0xFFFFUL << TIM_CCR5_CCR5_Pos)
	0xFFFF
#define	TIM_CCR5_CCR5   TIM_CCR5_CCR5_Msk
	Capture/Compare 5 Value.
#define	TIM_CCR5_GC5C1_Pos   (29U)
#define	TIM_CCR5_GC5C1_Msk   (0x1UL << TIM_CCR5_GC5C1_Pos)
	0x20000000
#define	TIM_CCR5_GC5C1   TIM_CCR5_GC5C1_Msk
	Group Channel 5 and Channel 1.
#define	TIM_CCR5_GC5C2_Pos   (30U)
#define	TIM_CCR5_GC5C2_Msk   (0x1UL << TIM_CCR5_GC5C2_Pos)
	0x40000000
#define	TIM_CCR5_GC5C2   TIM_CCR5_GC5C2_Msk
	Group Channel 5 and Channel 2.
#define	TIM_CCR5_GC5C3_Pos   (31U)
#define	TIM_CCR5_GC5C3_Msk   (0x1UL << TIM_CCR5_GC5C3_Pos)
	0x80000000
#define	TIM_CCR5_GC5C3   TIM_CCR5_GC5C3_Msk
	Group Channel 5 and Channel 3.
#define	TIM_CCR6_CCR6_Pos   (0U)
#define	TIM_CCR6_CCR6_Msk   (0xFFFFUL << TIM_CCR6_CCR6_Pos)
	0x0000FFFF
#define	TIM_CCR6_CCR6   TIM_CCR6_CCR6_Msk
	Capture/Compare 6 Value.
#define	TIM_BDTR_DTG_Pos   (0U)
#define	TIM_BDTR_DTG_Msk   (0xFFUL << TIM_BDTR_DTG_Pos)
	0x000000FF
#define	TIM_BDTR_DTG   TIM_BDTR_DTG_Msk
	DTG[0:7] bits (Dead-Time Generator set-up).
#define	TIM_BDTR_DTG_0   (0x01UL << TIM_BDTR_DTG_Pos)
	0x00000001
#define	TIM_BDTR_DTG_1   (0x02UL << TIM_BDTR_DTG_Pos)
	0x00000002
#define	TIM_BDTR_DTG_2   (0x04UL << TIM_BDTR_DTG_Pos)
	0x00000004
#define	TIM_BDTR_DTG_3   (0x08UL << TIM_BDTR_DTG_Pos)
	0x00000008
#define	TIM_BDTR_DTG_4   (0x10UL << TIM_BDTR_DTG_Pos)
	0x00000010
#define	TIM_BDTR_DTG_5   (0x20UL << TIM_BDTR_DTG_Pos)
	0x00000020
#define	TIM_BDTR_DTG_6   (0x40UL << TIM_BDTR_DTG_Pos)
	0x00000040
#define	TIM_BDTR_DTG_7   (0x80UL << TIM_BDTR_DTG_Pos)
	0x00000080
#define	TIM_BDTR_LOCK_Pos   (8U)
#define	TIM_BDTR_LOCK_Msk   (0x3UL << TIM_BDTR_LOCK_Pos)
	0x00000300
#define	TIM_BDTR_LOCK   TIM_BDTR_LOCK_Msk
	LOCK[1:0] bits (Lock Configuration).
#define	TIM_BDTR_LOCK_0   (0x1UL << TIM_BDTR_LOCK_Pos)
	0x00000100
#define	TIM_BDTR_LOCK_1   (0x2UL << TIM_BDTR_LOCK_Pos)
	0x00000200
#define	TIM_BDTR_OSSI_Pos   (10U)
#define	TIM_BDTR_OSSI_Msk   (0x1UL << TIM_BDTR_OSSI_Pos)
	0x00000400
#define	TIM_BDTR_OSSI   TIM_BDTR_OSSI_Msk
	Off-State Selection for Idle mode.
#define	TIM_BDTR_OSSR_Pos   (11U)
#define	TIM_BDTR_OSSR_Msk   (0x1UL << TIM_BDTR_OSSR_Pos)
	0x00000800
#define	TIM_BDTR_OSSR   TIM_BDTR_OSSR_Msk
	Off-State Selection for Run mode.
#define	TIM_BDTR_BKE_Pos   (12U)
#define	TIM_BDTR_BKE_Msk   (0x1UL << TIM_BDTR_BKE_Pos)
	0x00001000
#define	TIM_BDTR_BKE   TIM_BDTR_BKE_Msk
	Break enable for Break1.
#define	TIM_BDTR_BKP_Pos   (13U)
#define	TIM_BDTR_BKP_Msk   (0x1UL << TIM_BDTR_BKP_Pos)
	0x00002000
#define	TIM_BDTR_BKP   TIM_BDTR_BKP_Msk
	Break Polarity for Break1.
#define	TIM_BDTR_AOE_Pos   (14U)
#define	TIM_BDTR_AOE_Msk   (0x1UL << TIM_BDTR_AOE_Pos)
	0x00004000
#define	TIM_BDTR_AOE   TIM_BDTR_AOE_Msk
	Automatic Output enable.
#define	TIM_BDTR_MOE_Pos   (15U)
#define	TIM_BDTR_MOE_Msk   (0x1UL << TIM_BDTR_MOE_Pos)
	0x00008000
#define	TIM_BDTR_MOE   TIM_BDTR_MOE_Msk
	Main Output enable.
#define	TIM_BDTR_BKF_Pos   (16U)
#define	TIM_BDTR_BKF_Msk   (0xFUL << TIM_BDTR_BKF_Pos)
	0x000F0000
#define	TIM_BDTR_BKF   TIM_BDTR_BKF_Msk
	Break Filter for Break1.
#define	TIM_BDTR_BK2F_Pos   (20U)
#define	TIM_BDTR_BK2F_Msk   (0xFUL << TIM_BDTR_BK2F_Pos)
	0x00F00000
#define	TIM_BDTR_BK2F   TIM_BDTR_BK2F_Msk
	Break Filter for Break2.
#define	TIM_BDTR_BK2E_Pos   (24U)
#define	TIM_BDTR_BK2E_Msk   (0x1UL << TIM_BDTR_BK2E_Pos)
	0x01000000
#define	TIM_BDTR_BK2E   TIM_BDTR_BK2E_Msk
	Break enable for Break2.
#define	TIM_BDTR_BK2P_Pos   (25U)
#define	TIM_BDTR_BK2P_Msk   (0x1UL << TIM_BDTR_BK2P_Pos)
	0x02000000
#define	TIM_BDTR_BK2P   TIM_BDTR_BK2P_Msk
	Break Polarity for Break2.
#define	TIM_BDTR_BKDSRM_Pos   (26U)
#define	TIM_BDTR_BKDSRM_Msk   (0x1UL << TIM_BDTR_BKDSRM_Pos)
	0x04000000
#define	TIM_BDTR_BKDSRM   TIM_BDTR_BKDSRM_Msk
	Break Disarm.
#define	TIM_BDTR_BK2DSRM_Pos   (27U)
#define	TIM_BDTR_BK2DSRM_Msk   (0x1UL << TIM_BDTR_BK2DSRM_Pos)
	0x08000000
#define	TIM_BDTR_BK2DSRM   TIM_BDTR_BK2DSRM_Msk
	Break2 Disarm.
#define	TIM_BDTR_BKBID_Pos   (28U)
#define	TIM_BDTR_BKBID_Msk   (0x1UL << TIM_BDTR_BKBID_Pos)
	0x10000000
#define	TIM_BDTR_BKBID   TIM_BDTR_BKBID_Msk
	Break Bidirectional.
#define	TIM_BDTR_BK2BID_Pos   (29U)
#define	TIM_BDTR_BK2BID_Msk   (0x1UL << TIM_BDTR_BK2BID_Pos)
	0x20000000
#define	TIM_BDTR_BK2BID   TIM_BDTR_BK2BID_Msk
	Break2 Bidirectional.
#define	TIM_DCR_DBA_Pos   (0U)
#define	TIM_DCR_DBA_Msk   (0x1FUL << TIM_DCR_DBA_Pos)
	0x0000001F
#define	TIM_DCR_DBA   TIM_DCR_DBA_Msk
	DBA[4:0] bits (DMA Base Address).
#define	TIM_DCR_DBA_0   (0x01UL << TIM_DCR_DBA_Pos)
	0x00000001
#define	TIM_DCR_DBA_1   (0x02UL << TIM_DCR_DBA_Pos)
	0x00000002
#define	TIM_DCR_DBA_2   (0x04UL << TIM_DCR_DBA_Pos)
	0x00000004
#define	TIM_DCR_DBA_3   (0x08UL << TIM_DCR_DBA_Pos)
	0x00000008
#define	TIM_DCR_DBA_4   (0x10UL << TIM_DCR_DBA_Pos)
	0x00000010
#define	TIM_DCR_DBL_Pos   (8U)
#define	TIM_DCR_DBL_Msk   (0x1FUL << TIM_DCR_DBL_Pos)
	0x00001F00
#define	TIM_DCR_DBL   TIM_DCR_DBL_Msk
	DBL[4:0] bits (DMA Burst Length).
#define	TIM_DCR_DBL_0   (0x01UL << TIM_DCR_DBL_Pos)
	0x00000100
#define	TIM_DCR_DBL_1   (0x02UL << TIM_DCR_DBL_Pos)
	0x00000200
#define	TIM_DCR_DBL_2   (0x04UL << TIM_DCR_DBL_Pos)
	0x00000400
#define	TIM_DCR_DBL_3   (0x08UL << TIM_DCR_DBL_Pos)
	0x00000800
#define	TIM_DCR_DBL_4   (0x10UL << TIM_DCR_DBL_Pos)
	0x00001000
#define	TIM_DMAR_DMAB_Pos   (0U)
#define	TIM_DMAR_DMAB_Msk   (0xFFFFUL << TIM_DMAR_DMAB_Pos)
	0x0000FFFF
#define	TIM_DMAR_DMAB   TIM_DMAR_DMAB_Msk
	DMA register for burst accesses.
#define	TIM_CCMR3_OC5FE_Pos   (2U)
#define	TIM_CCMR3_OC5FE_Msk   (0x1UL << TIM_CCMR3_OC5FE_Pos)
	0x00000004
#define	TIM_CCMR3_OC5FE   TIM_CCMR3_OC5FE_Msk
	Output Compare 5 Fast enable.
#define	TIM_CCMR3_OC5PE_Pos   (3U)
#define	TIM_CCMR3_OC5PE_Msk   (0x1UL << TIM_CCMR3_OC5PE_Pos)
	0x00000008
#define	TIM_CCMR3_OC5PE   TIM_CCMR3_OC5PE_Msk
	Output Compare 5 Preload enable.
#define	TIM_CCMR3_OC5M_Pos   (4U)
#define	TIM_CCMR3_OC5M_Msk   (0x1007UL << TIM_CCMR3_OC5M_Pos)
	0x00010070
#define	TIM_CCMR3_OC5M   TIM_CCMR3_OC5M_Msk
	OC5M[3:0] bits (Output Compare 5 Mode).
#define	TIM_CCMR3_OC5M_0   (0x1UL << TIM_CCMR3_OC5M_Pos)
	0x00000010
#define	TIM_CCMR3_OC5M_1   (0x2UL << TIM_CCMR3_OC5M_Pos)
	0x00000020
#define	TIM_CCMR3_OC5M_2   (0x4UL << TIM_CCMR3_OC5M_Pos)
	0x00000040
#define	TIM_CCMR3_OC5M_3   (0x1000UL << TIM_CCMR3_OC5M_Pos)
	0x00010000
#define	TIM_CCMR3_OC5CE_Pos   (7U)
#define	TIM_CCMR3_OC5CE_Msk   (0x1UL << TIM_CCMR3_OC5CE_Pos)
	0x00000080
#define	TIM_CCMR3_OC5CE   TIM_CCMR3_OC5CE_Msk
	Output Compare 5 Clear Enable.
#define	TIM_CCMR3_OC6FE_Pos   (10U)
#define	TIM_CCMR3_OC6FE_Msk   (0x1UL << TIM_CCMR3_OC6FE_Pos)
	0x00000400
#define	TIM_CCMR3_OC6FE   TIM_CCMR3_OC6FE_Msk
	Output Compare 4 Fast enable.
#define	TIM_CCMR3_OC6PE_Pos   (11U)
#define	TIM_CCMR3_OC6PE_Msk   (0x1UL << TIM_CCMR3_OC6PE_Pos)
	0x00000800
#define	TIM_CCMR3_OC6PE   TIM_CCMR3_OC6PE_Msk
	Output Compare 4 Preload enable.
#define	TIM_CCMR3_OC6M_Pos   (12U)
#define	TIM_CCMR3_OC6M_Msk   (0x1007UL << TIM_CCMR3_OC6M_Pos)
	0x01007000
#define	TIM_CCMR3_OC6M   TIM_CCMR3_OC6M_Msk
	OC4M[3:0] bits (Output Compare 4 Mode).
#define	TIM_CCMR3_OC6M_0   (0x1UL << TIM_CCMR3_OC6M_Pos)
	0x00001000
#define	TIM_CCMR3_OC6M_1   (0x2UL << TIM_CCMR3_OC6M_Pos)
	0x00002000
#define	TIM_CCMR3_OC6M_2   (0x4UL << TIM_CCMR3_OC6M_Pos)
	0x00004000
#define	TIM_CCMR3_OC6M_3   (0x1000UL << TIM_CCMR3_OC6M_Pos)
	0x01000000
#define	TIM_CCMR3_OC6CE_Pos   (15U)
#define	TIM_CCMR3_OC6CE_Msk   (0x1UL << TIM_CCMR3_OC6CE_Pos)
	0x00008000
#define	TIM_CCMR3_OC6CE   TIM_CCMR3_OC6CE_Msk
	Output Compare 4 Clear Enable.
#define	TIM1_AF1_BKINE_Pos   (0U)
#define	TIM1_AF1_BKINE_Msk   (0x1UL << TIM1_AF1_BKINE_Pos)
	0x00000001
#define	TIM1_AF1_BKINE   TIM1_AF1_BKINE_Msk
	BKINE Break input enable bit.
#define	TIM1_AF1_BKCMP1E_Pos   (1U)
#define	TIM1_AF1_BKCMP1E_Msk   (0x1UL << TIM1_AF1_BKCMP1E_Pos)
	0x00000002
#define	TIM1_AF1_BKCMP1E   TIM1_AF1_BKCMP1E_Msk
	BKCMP1E Break Compare1 Enable bit.
#define	TIM1_AF1_BKCMP2E_Pos   (2U)
#define	TIM1_AF1_BKCMP2E_Msk   (0x1UL << TIM1_AF1_BKCMP2E_Pos)
	0x00000004
#define	TIM1_AF1_BKCMP2E   TIM1_AF1_BKCMP2E_Msk
	BKCMP1E Break Compare2 Enable bit.
#define	TIM1_AF1_BKDF1BK0E_Pos   (8U)
#define	TIM1_AF1_BKDF1BK0E_Msk   (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)
	0x00000100
#define	TIM1_AF1_BKDF1BK0E   TIM1_AF1_BKDF1BK0E_Msk
	BKDF1BK0E Break input DFSDM Break 0.
#define	TIM1_AF1_BKINP_Pos   (9U)
#define	TIM1_AF1_BKINP_Msk   (0x1UL << TIM1_AF1_BKINP_Pos)
	0x00000200
#define	TIM1_AF1_BKINP   TIM1_AF1_BKINP_Msk
	BRKINP Break input polarity.
#define	TIM1_AF1_BKCMP1P_Pos   (10U)
#define	TIM1_AF1_BKCMP1P_Msk   (0x1UL << TIM1_AF1_BKCMP1P_Pos)
	0x00000400
#define	TIM1_AF1_BKCMP1P   TIM1_AF1_BKCMP1P_Msk
	BKCMP1P Break COMP1 input polarity.
#define	TIM1_AF1_BKCMP2P_Pos   (11U)
#define	TIM1_AF1_BKCMP2P_Msk   (0x1UL << TIM1_AF1_BKCMP2P_Pos)
	0x00000800
#define	TIM1_AF1_BKCMP2P   TIM1_AF1_BKCMP2P_Msk
	BKCMP2P Break COMP2 input polarity.
#define	TIM1_AF1_ETRSEL_Pos   (14U)
#define	TIM1_AF1_ETRSEL_Msk   (0xFUL << TIM1_AF1_ETRSEL_Pos)
	0x0003C000
#define	TIM1_AF1_ETRSEL   TIM1_AF1_ETRSEL_Msk
	ETRSEL[3:0] bits (TIM1 ETRSEL).
#define	TIM1_AF1_ETRSEL_0   (0x1UL << TIM1_AF1_ETRSEL_Pos)
	0x00004000
#define	TIM1_AF1_ETRSEL_1   (0x2UL << TIM1_AF1_ETRSEL_Pos)
	0x00008000
#define	TIM1_AF1_ETRSEL_2   (0x4UL << TIM1_AF1_ETRSEL_Pos)
	0x00010000
#define	TIM1_AF1_ETRSEL_3   (0x8UL << TIM1_AF1_ETRSEL_Pos)
	0x00020000
#define	TIM1_AF2_BK2INE_Pos   (0U)
#define	TIM1_AF2_BK2INE_Msk   (0x1UL << TIM1_AF2_BK2INE_Pos)
	0x00000001
#define	TIM1_AF2_BK2INE   TIM1_AF2_BK2INE_Msk
	BK2INE Break input 2 enable bit.
#define	TIM1_AF2_BK2CMP1E_Pos   (1U)
#define	TIM1_AF2_BK2CMP1E_Msk   (0x1UL << TIM1_AF2_BK2CMP1E_Pos)
	0x00000002
#define	TIM1_AF2_BK2CMP1E   TIM1_AF2_BK2CMP1E_Msk
	BK2CMP1E Break2 Compare1 Enable bit.
#define	TIM1_AF2_BK2CMP2E_Pos   (2U)
#define	TIM1_AF2_BK2CMP2E_Msk   (0x1UL << TIM1_AF2_BK2CMP2E_Pos)
	0x00000004
#define	TIM1_AF2_BK2CMP2E   TIM1_AF2_BK2CMP2E_Msk
	BK2CMP1E Break2 Compare2 Enable bit.
#define	TIM1_AF2_BK2DFBK1E_Pos   (8U)
#define	TIM1_AF2_BK2DFBK1E_Msk   (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)
	0x00000100
#define	TIM1_AF2_BK2DFBK1E   TIM1_AF2_BK2DFBK1E_Msk
	BK2DFBK1E Break input2 DFSDM Break 1.
#define	TIM1_AF2_BK2INP_Pos   (9U)
#define	TIM1_AF2_BK2INP_Msk   (0x1UL << TIM1_AF2_BK2INP_Pos)
	0x00000200
#define	TIM1_AF2_BK2INP   TIM1_AF2_BK2INP_Msk
	BRKINP Break2 input polarity.
#define	TIM1_AF2_BK2CMP1P_Pos   (10U)
#define	TIM1_AF2_BK2CMP1P_Msk   (0x1UL << TIM1_AF2_BK2CMP1P_Pos)
	0x00000400
#define	TIM1_AF2_BK2CMP1P   TIM1_AF2_BK2CMP1P_Msk
	BKCMP1P Break2 COMP1 input polarity.
#define	TIM1_AF2_BK2CMP2P_Pos   (11U)
#define	TIM1_AF2_BK2CMP2P_Msk   (0x1UL << TIM1_AF2_BK2CMP2P_Pos)
	0x00000800
#define	TIM1_AF2_BK2CMP2P   TIM1_AF2_BK2CMP2P_Msk
	BKCMP2P Break2 COMP2 input polarity.
#define	TIM_TISEL_TI1SEL_Pos   (0U)
#define	TIM_TISEL_TI1SEL_Msk   (0xFUL << TIM_TISEL_TI1SEL_Pos)
	0x0000000F
#define	TIM_TISEL_TI1SEL   TIM_TISEL_TI1SEL_Msk
	TI1SEL[3:0] bits (TIM TI1 SEL).
#define	TIM_TISEL_TI1SEL_0   (0x1UL << TIM_TISEL_TI1SEL_Pos)
	0x00000001
#define	TIM_TISEL_TI1SEL_1   (0x2UL << TIM_TISEL_TI1SEL_Pos)
	0x00000002
#define	TIM_TISEL_TI1SEL_2   (0x4UL << TIM_TISEL_TI1SEL_Pos)
	0x00000004
#define	TIM_TISEL_TI1SEL_3   (0x8UL << TIM_TISEL_TI1SEL_Pos)
	0x00000008
#define	TIM_TISEL_TI2SEL_Pos   (8U)
#define	TIM_TISEL_TI2SEL_Msk   (0xFUL << TIM_TISEL_TI2SEL_Pos)
	0x00000F00
#define	TIM_TISEL_TI2SEL   TIM_TISEL_TI2SEL_Msk
	TI2SEL[3:0] bits (TIM TI2 SEL).
#define	TIM_TISEL_TI2SEL_0   (0x1UL << TIM_TISEL_TI2SEL_Pos)
	0x00000100
#define	TIM_TISEL_TI2SEL_1   (0x2UL << TIM_TISEL_TI2SEL_Pos)
	0x00000200
#define	TIM_TISEL_TI2SEL_2   (0x4UL << TIM_TISEL_TI2SEL_Pos)
	0x00000400
#define	TIM_TISEL_TI2SEL_3   (0x8UL << TIM_TISEL_TI2SEL_Pos)
	0x00000800
#define	TIM_TISEL_TI3SEL_Pos   (16U)
#define	TIM_TISEL_TI3SEL_Msk   (0xFUL << TIM_TISEL_TI3SEL_Pos)
	0x000F0000
#define	TIM_TISEL_TI3SEL   TIM_TISEL_TI3SEL_Msk
	TI3SEL[3:0] bits (TIM TI3 SEL).
#define	TIM_TISEL_TI3SEL_0   (0x1UL << TIM_TISEL_TI3SEL_Pos)
	0x00010000
#define	TIM_TISEL_TI3SEL_1   (0x2UL << TIM_TISEL_TI3SEL_Pos)
	0x00020000
#define	TIM_TISEL_TI3SEL_2   (0x4UL << TIM_TISEL_TI3SEL_Pos)
	0x00040000
#define	TIM_TISEL_TI3SEL_3   (0x8UL << TIM_TISEL_TI3SEL_Pos)
	0x00080000
#define	TIM_TISEL_TI4SEL_Pos   (24U)
#define	TIM_TISEL_TI4SEL_Msk   (0xFUL << TIM_TISEL_TI4SEL_Pos)
	0x0F000000
#define	TIM_TISEL_TI4SEL   TIM_TISEL_TI4SEL_Msk
	TI4SEL[3:0] bits (TIM TI4 SEL).
#define	TIM_TISEL_TI4SEL_0   (0x1UL << TIM_TISEL_TI4SEL_Pos)
	0x01000000
#define	TIM_TISEL_TI4SEL_1   (0x2UL << TIM_TISEL_TI4SEL_Pos)
	0x02000000
#define	TIM_TISEL_TI4SEL_2   (0x4UL << TIM_TISEL_TI4SEL_Pos)
	0x04000000
#define	TIM_TISEL_TI4SEL_3   (0x8UL << TIM_TISEL_TI4SEL_Pos)
	0x08000000
#define	TIM8_AF1_BKINE_Pos   (0U)
#define	TIM8_AF1_BKINE_Msk   (0x1UL << TIM8_AF1_BKINE_Pos)
	0x00000001
#define	TIM8_AF1_BKINE   TIM8_AF1_BKINE_Msk
	BKINE Break input enable bit.
#define	TIM8_AF1_BKCMP1E_Pos   (1U)
#define	TIM8_AF1_BKCMP1E_Msk   (0x1UL << TIM8_AF1_BKCMP1E_Pos)
	0x00000002
#define	TIM8_AF1_BKCMP1E   TIM8_AF1_BKCMP1E_Msk
	BKCMP1E Break Compare1 Enable bit.
#define	TIM8_AF1_BKCMP2E_Pos   (2U)
#define	TIM8_AF1_BKCMP2E_Msk   (0x1UL << TIM8_AF1_BKCMP2E_Pos)
	0x00000004
#define	TIM8_AF1_BKCMP2E   TIM8_AF1_BKCMP2E_Msk
	BKCMP1E Break Compare2 Enable bit.
#define	TIM8_AF1_BKDFBK2E_Pos   (8U)
#define	TIM8_AF1_BKDFBK2E_Msk   (0x1UL << TIM8_AF1_BKDFBK2E_Pos)
	0x00000100
#define	TIM8_AF1_BKDFBK2E   TIM8_AF1_BKDFBK2E_Msk
	BKDFBK2E Break input DFSDM Break 2.
#define	TIM8_AF1_BKINP_Pos   (9U)
#define	TIM8_AF1_BKINP_Msk   (0x1UL << TIM8_AF1_BKINP_Pos)
	0x00000200
#define	TIM8_AF1_BKINP   TIM8_AF1_BKINP_Msk
	BRKINP Break input polarity.
#define	TIM8_AF1_BKCMP1P_Pos   (10U)
#define	TIM8_AF1_BKCMP1P_Msk   (0x1UL << TIM8_AF1_BKCMP1P_Pos)
	0x00000400
#define	TIM8_AF1_BKCMP1P   TIM8_AF1_BKCMP1P_Msk
	BKCMP1P Break COMP1 input polarity.
#define	TIM8_AF1_BKCMP2P_Pos   (11U)
#define	TIM8_AF1_BKCMP2P_Msk   (0x1UL << TIM8_AF1_BKCMP2P_Pos)
	0x00000800
#define	TIM8_AF1_BKCMP2P   TIM8_AF1_BKCMP2P_Msk
	BKCMP2P Break COMP2 input polarity.
#define	TIM8_AF1_ETRSEL_Pos   (14U)
#define	TIM8_AF1_ETRSEL_Msk   (0xFUL << TIM8_AF1_ETRSEL_Pos)
	0x0003C000
#define	TIM8_AF1_ETRSEL   TIM8_AF1_ETRSEL_Msk
	ETRSEL[3:0] bits (TIM8 ETRSEL).
#define	TIM8_AF1_ETRSEL_0   (0x1UL << TIM8_AF1_ETRSEL_Pos)
	0x00004000
#define	TIM8_AF1_ETRSEL_1   (0x2UL << TIM8_AF1_ETRSEL_Pos)
	0x00008000
#define	TIM8_AF1_ETRSEL_2   (0x4UL << TIM8_AF1_ETRSEL_Pos)
	0x00010000
#define	TIM8_AF1_ETRSEL_3   (0x8UL << TIM8_AF1_ETRSEL_Pos)
	0x00020000
#define	TIM8_AF2_BK2INE_Pos   (0U)
#define	TIM8_AF2_BK2INE_Msk   (0x1UL << TIM8_AF2_BK2INE_Pos)
	0x00000001
#define	TIM8_AF2_BK2INE   TIM8_AF2_BK2INE_Msk
	BK2INE Break input 2 enable bit.
#define	TIM8_AF2_BK2CMP1E_Pos   (1U)
#define	TIM8_AF2_BK2CMP1E_Msk   (0x1UL << TIM8_AF2_BK2CMP1E_Pos)
	0x00000002
#define	TIM8_AF2_BK2CMP1E   TIM8_AF2_BK2CMP1E_Msk
	BK2CMP1E Break2 Compare1 Enable bit.
#define	TIM8_AF2_BK2CMP2E_Pos   (2U)
#define	TIM8_AF2_BK2CMP2E_Msk   (0x1UL << TIM8_AF2_BK2CMP2E_Pos)
	0x00000004
#define	TIM8_AF2_BK2CMP2E   TIM8_AF2_BK2CMP2E_Msk
	BK2CMP1E Break2 Compare2 Enable bit.
#define	TIM8_AF2_BK2DFBK3E_Pos   (8U)
#define	TIM8_AF2_BK2DFBK3E_Msk   (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)
	0x00000100
#define	TIM8_AF2_BK2DFBK3E   TIM8_AF2_BK2DFBK3E_Msk
	BK2DFBK1E Break input2 DFSDM Break 3.
#define	TIM8_AF2_BK2INP_Pos   (9U)
#define	TIM8_AF2_BK2INP_Msk   (0x1UL << TIM8_AF2_BK2INP_Pos)
	0x00000200
#define	TIM8_AF2_BK2INP   TIM8_AF2_BK2INP_Msk
	BRKINP Break2 input polarity.
#define	TIM8_AF2_BK2CMP1P_Pos   (10U)
#define	TIM8_AF2_BK2CMP1P_Msk   (0x1UL << TIM8_AF2_BK2CMP1P_Pos)
	0x00000400
#define	TIM8_AF2_BK2CMP1P   TIM8_AF2_BK2CMP1P_Msk
	BKCMP1P Break2 COMP1 input polarity.
#define	TIM8_AF2_BK2CMP2P_Pos   (11U)
#define	TIM8_AF2_BK2CMP2P_Msk   (0x1UL << TIM8_AF2_BK2CMP2P_Pos)
	0x00000800
#define	TIM8_AF2_BK2CMP2P   TIM8_AF2_BK2CMP2P_Msk
	BKCMP2P Break2 COMP2 input polarity.
#define	TIM2_AF1_ETRSEL_Pos   (14U)
#define	TIM2_AF1_ETRSEL_Msk   (0xFUL << TIM2_AF1_ETRSEL_Pos)
	0x0003C000
#define	TIM2_AF1_ETRSEL   TIM2_AF1_ETRSEL_Msk
	ETRSEL[3:0] bits (TIM2 ETRSEL).
#define	TIM2_AF1_ETRSEL_0   (0x1UL << TIM2_AF1_ETRSEL_Pos)
	0x00004000
#define	TIM2_AF1_ETRSEL_1   (0x2UL << TIM2_AF1_ETRSEL_Pos)
	0x00008000
#define	TIM2_AF1_ETRSEL_2   (0x4UL << TIM2_AF1_ETRSEL_Pos)
	0x00010000
#define	TIM2_AF1_ETRSEL_3   (0x8UL << TIM2_AF1_ETRSEL_Pos)
	0x00020000
#define	TIM3_AF1_ETRSEL_Pos   (14U)
#define	TIM3_AF1_ETRSEL_Msk   (0xFUL << TIM3_AF1_ETRSEL_Pos)
	0x0003C000
#define	TIM3_AF1_ETRSEL   TIM3_AF1_ETRSEL_Msk
	ETRSEL[3:0] bits (TIM3 ETRSEL).
#define	TIM3_AF1_ETRSEL_0   (0x1UL << TIM3_AF1_ETRSEL_Pos)
	0x00004000
#define	TIM3_AF1_ETRSEL_1   (0x2UL << TIM3_AF1_ETRSEL_Pos)
	0x00008000
#define	TIM3_AF1_ETRSEL_2   (0x4UL << TIM3_AF1_ETRSEL_Pos)
	0x00010000
#define	TIM3_AF1_ETRSEL_3   (0x8UL << TIM3_AF1_ETRSEL_Pos)
	0x00020000
#define	TIM5_AF1_ETRSEL_Pos   (14U)
#define	TIM5_AF1_ETRSEL_Msk   (0xFUL << TIM5_AF1_ETRSEL_Pos)
	0x0003C000
#define	TIM5_AF1_ETRSEL   TIM5_AF1_ETRSEL_Msk
	ETRSEL[3:0] bits (TIM5 ETRSEL).
#define	TIM5_AF1_ETRSEL_0   (0x1UL << TIM5_AF1_ETRSEL_Pos)
	0x00004000
#define	TIM5_AF1_ETRSEL_1   (0x2UL << TIM5_AF1_ETRSEL_Pos)
	0x00008000
#define	TIM5_AF1_ETRSEL_2   (0x4UL << TIM5_AF1_ETRSEL_Pos)
	0x00010000
#define	TIM5_AF1_ETRSEL_3   (0x8UL << TIM5_AF1_ETRSEL_Pos)
	0x00020000
#define	TIM15_AF1_BKINE_Pos   (0U)
#define	TIM15_AF1_BKINE_Msk   (0x1UL << TIM15_AF1_BKINE_Pos)
	0x00000001
#define	TIM15_AF1_BKINE   TIM15_AF1_BKINE_Msk
	BKINE Break input enable bit.
#define	TIM15_AF1_BKCMP1E_Pos   (1U)
#define	TIM15_AF1_BKCMP1E_Msk   (0x1UL << TIM15_AF1_BKCMP1E_Pos)
	0x00000002
#define	TIM15_AF1_BKCMP1E   TIM15_AF1_BKCMP1E_Msk
	BKCMP1E Break Compare1 Enable bit.
#define	TIM15_AF1_BKCMP2E_Pos   (2U)
#define	TIM15_AF1_BKCMP2E_Msk   (0x1UL << TIM15_AF1_BKCMP2E_Pos)
	0x00000004
#define	TIM15_AF1_BKCMP2E   TIM15_AF1_BKCMP2E_Msk
	BKCMP1E Break Compare2 Enable bit.
#define	TIM15_AF1_BKDF1BK2E_Pos   (8U)
#define	TIM15_AF1_BKDF1BK2E_Msk   (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)
	0x00000100
#define	TIM15_AF1_BKDF1BK2E   TIM15_AF1_BKDF1BK2E_Msk
	BRK dfsdm1_break[0] enable.
#define	TIM15_AF1_BKINP_Pos   (9U)
#define	TIM15_AF1_BKINP_Msk   (0x1UL << TIM15_AF1_BKINP_Pos)
	0x00000200
#define	TIM15_AF1_BKINP   TIM15_AF1_BKINP_Msk
	BRKINP Break input polarity.
#define	TIM15_AF1_BKCMP1P_Pos   (10U)
#define	TIM15_AF1_BKCMP1P_Msk   (0x1UL << TIM15_AF1_BKCMP1P_Pos)
	0x00000400
#define	TIM15_AF1_BKCMP1P   TIM15_AF1_BKCMP1P_Msk
	BKCMP1P Break COMP1 input polarity.
#define	TIM15_AF1_BKCMP2P_Pos   (11U)
#define	TIM15_AF1_BKCMP2P_Msk   (0x1UL << TIM15_AF1_BKCMP2P_Pos)
	0x00000800
#define	TIM15_AF1_BKCMP2P   TIM15_AF1_BKCMP2P_Msk
	BKCMP2P Break COMP2 input polarity.
#define	TIM16_AF1_BKINE_Pos   (0U)
#define	TIM16_AF1_BKINE_Msk   (0x1UL << TIM16_AF1_BKINE_Pos)
	0x00000001
#define	TIM16_AF1_BKINE   TIM16_AF1_BKINE_Msk
	BKINE Break input enable bit.
#define	TIM16_AF1_BKCMP1E_Pos   (1U)
#define	TIM16_AF1_BKCMP1E_Msk   (0x1UL << TIM16_AF1_BKCMP1E_Pos)
	0x00000002
#define	TIM16_AF1_BKCMP1E   TIM16_AF1_BKCMP1E_Msk
	BKCMP1E Break Compare1 Enable bit.
#define	TIM16_AF1_BKCMP2E_Pos   (2U)
#define	TIM16_AF1_BKCMP2E_Msk   (0x1UL << TIM16_AF1_BKCMP2E_Pos)
	0x00000004
#define	TIM16_AF1_BKCMP2E   TIM16_AF1_BKCMP2E_Msk
	BKCMP1E Break Compare2 Enable bit.
#define	TIM16_AF1_BKDF1BK2E_Pos   (8U)
#define	TIM16_AF1_BKDF1BK2E_Msk   (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)
	0x00000100
#define	TIM16_AF1_BKDF1BK2E   TIM16_AF1_BKDF1BK2E_Msk
	BRK dfsdm1_break[1] enable.
#define	TIM16_AF1_BKINP_Pos   (9U)
#define	TIM16_AF1_BKINP_Msk   (0x1UL << TIM16_AF1_BKINP_Pos)
	0x00000200
#define	TIM16_AF1_BKINP   TIM16_AF1_BKINP_Msk
	BRKINP Break input polarity.
#define	TIM16_AF1_BKCMP1P_Pos   (10U)
#define	TIM16_AF1_BKCMP1P_Msk   (0x1UL << TIM16_AF1_BKCMP1P_Pos)
	0x00000400
#define	TIM16_AF1_BKCMP1P   TIM16_AF1_BKCMP1P_Msk
	BKCMP1P Break COMP1 input polarity.
#define	TIM16_AF1_BKCMP2P_Pos   (11U)
#define	TIM16_AF1_BKCMP2P_Msk   (0x1UL << TIM16_AF1_BKCMP2P_Pos)
	0x00000800
#define	TIM16_AF1_BKCMP2P   TIM16_AF1_BKCMP2P_Msk
	BKCMP2P Break COMP2 input polarity.
#define	TIM17_AF1_BKINE_Pos   (0U)
#define	TIM17_AF1_BKINE_Msk   (0x1UL << TIM17_AF1_BKINE_Pos)
	0x00000001
#define	TIM17_AF1_BKINE   TIM17_AF1_BKINE_Msk
	BKINE Break input enable bit.
#define	TIM17_AF1_BKCMP1E_Pos   (1U)
#define	TIM17_AF1_BKCMP1E_Msk   (0x1UL << TIM17_AF1_BKCMP1E_Pos)
	0x00000002
#define	TIM17_AF1_BKCMP1E   TIM17_AF1_BKCMP1E_Msk
	BKCMP1E Break Compare1 Enable bit.
#define	TIM17_AF1_BKCMP2E_Pos   (2U)
#define	TIM17_AF1_BKCMP2E_Msk   (0x1UL << TIM17_AF1_BKCMP2E_Pos)
	0x00000004
#define	TIM17_AF1_BKCMP2E   TIM17_AF1_BKCMP2E_Msk
	BKCMP1E Break Compare2 Enable bit.
#define	TIM17_AF1_BKDF1BK2E_Pos   (8U)
#define	TIM17_AF1_BKDF1BK2E_Msk   (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)
	0x00000100
#define	TIM17_AF1_BKDF1BK2E   TIM17_AF1_BKDF1BK2E_Msk
	BRK dfsdm1_break[2] enable.
#define	TIM17_AF1_BKINP_Pos   (9U)
#define	TIM17_AF1_BKINP_Msk   (0x1UL << TIM17_AF1_BKINP_Pos)
	0x00000200
#define	TIM17_AF1_BKINP   TIM17_AF1_BKINP_Msk
	BRKINP Break input polarity.
#define	TIM17_AF1_BKCMP1P_Pos   (10U)
#define	TIM17_AF1_BKCMP1P_Msk   (0x1UL << TIM17_AF1_BKCMP1P_Pos)
	0x00000400
#define	TIM17_AF1_BKCMP1P   TIM17_AF1_BKCMP1P_Msk
	BKCMP1P Break COMP1 input polarity.
#define	TIM17_AF1_BKCMP2P_Pos   (11U)
#define	TIM17_AF1_BKCMP2P_Msk   (0x1UL << TIM17_AF1_BKCMP2P_Pos)
	0x00000800
#define	TIM17_AF1_BKCMP2P   TIM17_AF1_BKCMP2P_Msk
	BKCMP2P Break COMP2 input polarity.
#define	LPTIM_ISR_CMPM_Pos   (0U)
#define	LPTIM_ISR_CMPM_Msk   (0x1UL << LPTIM_ISR_CMPM_Pos)
	0x00000001
#define	LPTIM_ISR_CMPM   LPTIM_ISR_CMPM_Msk
	Compare match.
#define	LPTIM_ISR_ARRM_Pos   (1U)
#define	LPTIM_ISR_ARRM_Msk   (0x1UL << LPTIM_ISR_ARRM_Pos)
	0x00000002
#define	LPTIM_ISR_ARRM   LPTIM_ISR_ARRM_Msk
	Autoreload match.
#define	LPTIM_ISR_EXTTRIG_Pos   (2U)
#define	LPTIM_ISR_EXTTRIG_Msk   (0x1UL << LPTIM_ISR_EXTTRIG_Pos)
	0x00000004
#define	LPTIM_ISR_EXTTRIG   LPTIM_ISR_EXTTRIG_Msk
	External trigger edge event.
#define	LPTIM_ISR_CMPOK_Pos   (3U)
#define	LPTIM_ISR_CMPOK_Msk   (0x1UL << LPTIM_ISR_CMPOK_Pos)
	0x00000008
#define	LPTIM_ISR_CMPOK   LPTIM_ISR_CMPOK_Msk
	Compare register update OK.
#define	LPTIM_ISR_ARROK_Pos   (4U)
#define	LPTIM_ISR_ARROK_Msk   (0x1UL << LPTIM_ISR_ARROK_Pos)
	0x00000010
#define	LPTIM_ISR_ARROK   LPTIM_ISR_ARROK_Msk
	Autoreload register update OK.
#define	LPTIM_ISR_UP_Pos   (5U)
#define	LPTIM_ISR_UP_Msk   (0x1UL << LPTIM_ISR_UP_Pos)
	0x00000020
#define	LPTIM_ISR_UP   LPTIM_ISR_UP_Msk
	Counter direction change down to up.
#define	LPTIM_ISR_DOWN_Pos   (6U)
#define	LPTIM_ISR_DOWN_Msk   (0x1UL << LPTIM_ISR_DOWN_Pos)
	0x00000040
#define	LPTIM_ISR_DOWN   LPTIM_ISR_DOWN_Msk
	Counter direction change up to down.
#define	LPTIM_ICR_CMPMCF_Pos   (0U)
#define	LPTIM_ICR_CMPMCF_Msk   (0x1UL << LPTIM_ICR_CMPMCF_Pos)
	0x00000001
#define	LPTIM_ICR_CMPMCF   LPTIM_ICR_CMPMCF_Msk
	Compare match Clear Flag.
#define	LPTIM_ICR_ARRMCF_Pos   (1U)
#define	LPTIM_ICR_ARRMCF_Msk   (0x1UL << LPTIM_ICR_ARRMCF_Pos)
	0x00000002
#define	LPTIM_ICR_ARRMCF   LPTIM_ICR_ARRMCF_Msk
	Autoreload match Clear Flag.
#define	LPTIM_ICR_EXTTRIGCF_Pos   (2U)
#define	LPTIM_ICR_EXTTRIGCF_Msk   (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)
	0x00000004
#define	LPTIM_ICR_EXTTRIGCF   LPTIM_ICR_EXTTRIGCF_Msk
	External trigger edge event Clear Flag.
#define	LPTIM_ICR_CMPOKCF_Pos   (3U)
#define	LPTIM_ICR_CMPOKCF_Msk   (0x1UL << LPTIM_ICR_CMPOKCF_Pos)
	0x00000008
#define	LPTIM_ICR_CMPOKCF   LPTIM_ICR_CMPOKCF_Msk
	Compare register update OK Clear Flag.
#define	LPTIM_ICR_ARROKCF_Pos   (4U)
#define	LPTIM_ICR_ARROKCF_Msk   (0x1UL << LPTIM_ICR_ARROKCF_Pos)
	0x00000010
#define	LPTIM_ICR_ARROKCF   LPTIM_ICR_ARROKCF_Msk
	Autoreload register update OK Clear Flag.
#define	LPTIM_ICR_UPCF_Pos   (5U)
#define	LPTIM_ICR_UPCF_Msk   (0x1UL << LPTIM_ICR_UPCF_Pos)
	0x00000020
#define	LPTIM_ICR_UPCF   LPTIM_ICR_UPCF_Msk
	Counter direction change down to up Clear Flag.
#define	LPTIM_ICR_DOWNCF_Pos   (6U)
#define	LPTIM_ICR_DOWNCF_Msk   (0x1UL << LPTIM_ICR_DOWNCF_Pos)
	0x00000040
#define	LPTIM_ICR_DOWNCF   LPTIM_ICR_DOWNCF_Msk
	Counter direction change up to down Clear Flag.
#define	LPTIM_IER_CMPMIE_Pos   (0U)
#define	LPTIM_IER_CMPMIE_Msk   (0x1UL << LPTIM_IER_CMPMIE_Pos)
	0x00000001
#define	LPTIM_IER_CMPMIE   LPTIM_IER_CMPMIE_Msk
	Compare match Interrupt Enable.
#define	LPTIM_IER_ARRMIE_Pos   (1U)
#define	LPTIM_IER_ARRMIE_Msk   (0x1UL << LPTIM_IER_ARRMIE_Pos)
	0x00000002
#define	LPTIM_IER_ARRMIE   LPTIM_IER_ARRMIE_Msk
	Autoreload match Interrupt Enable.
#define	LPTIM_IER_EXTTRIGIE_Pos   (2U)
#define	LPTIM_IER_EXTTRIGIE_Msk   (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)
	0x00000004
#define	LPTIM_IER_EXTTRIGIE   LPTIM_IER_EXTTRIGIE_Msk
	External trigger edge event Interrupt Enable.
#define	LPTIM_IER_CMPOKIE_Pos   (3U)
#define	LPTIM_IER_CMPOKIE_Msk   (0x1UL << LPTIM_IER_CMPOKIE_Pos)
	0x00000008
#define	LPTIM_IER_CMPOKIE   LPTIM_IER_CMPOKIE_Msk
	Compare register update OK Interrupt Enable.
#define	LPTIM_IER_ARROKIE_Pos   (4U)
#define	LPTIM_IER_ARROKIE_Msk   (0x1UL << LPTIM_IER_ARROKIE_Pos)
	0x00000010
#define	LPTIM_IER_ARROKIE   LPTIM_IER_ARROKIE_Msk
	Autoreload register update OK Interrupt Enable.
#define	LPTIM_IER_UPIE_Pos   (5U)
#define	LPTIM_IER_UPIE_Msk   (0x1UL << LPTIM_IER_UPIE_Pos)
	0x00000020
#define	LPTIM_IER_UPIE   LPTIM_IER_UPIE_Msk
	Counter direction change down to up Interrupt Enable.
#define	LPTIM_IER_DOWNIE_Pos   (6U)
#define	LPTIM_IER_DOWNIE_Msk   (0x1UL << LPTIM_IER_DOWNIE_Pos)
	0x00000040
#define	LPTIM_IER_DOWNIE   LPTIM_IER_DOWNIE_Msk
	Counter direction change up to down Interrupt Enable.
#define	LPTIM_CFGR_CKSEL_Pos   (0U)
#define	LPTIM_CFGR_CKSEL_Msk   (0x1UL << LPTIM_CFGR_CKSEL_Pos)
	0x00000001
#define	LPTIM_CFGR_CKSEL   LPTIM_CFGR_CKSEL_Msk
	Clock selector.
#define	LPTIM_CFGR_CKPOL_Pos   (1U)
#define	LPTIM_CFGR_CKPOL_Msk   (0x3UL << LPTIM_CFGR_CKPOL_Pos)
	0x00000006
#define	LPTIM_CFGR_CKPOL   LPTIM_CFGR_CKPOL_Msk
	CKPOL[1:0] bits (Clock polarity).
#define	LPTIM_CFGR_CKPOL_0   (0x1UL << LPTIM_CFGR_CKPOL_Pos)
	0x00000002
#define	LPTIM_CFGR_CKPOL_1   (0x2UL << LPTIM_CFGR_CKPOL_Pos)
	0x00000004
#define	LPTIM_CFGR_CKFLT_Pos   (3U)
#define	LPTIM_CFGR_CKFLT_Msk   (0x3UL << LPTIM_CFGR_CKFLT_Pos)
	0x00000018
#define	LPTIM_CFGR_CKFLT   LPTIM_CFGR_CKFLT_Msk
	CKFLT[1:0] bits (Configurable digital filter for external clock).
#define	LPTIM_CFGR_CKFLT_0   (0x1UL << LPTIM_CFGR_CKFLT_Pos)
	0x00000008
#define	LPTIM_CFGR_CKFLT_1   (0x2UL << LPTIM_CFGR_CKFLT_Pos)
	0x00000010
#define	LPTIM_CFGR_TRGFLT_Pos   (6U)
#define	LPTIM_CFGR_TRGFLT_Msk   (0x3UL << LPTIM_CFGR_TRGFLT_Pos)
	0x000000C0
#define	LPTIM_CFGR_TRGFLT   LPTIM_CFGR_TRGFLT_Msk
	TRGFLT[1:0] bits (Configurable digital filter for trigger).
#define	LPTIM_CFGR_TRGFLT_0   (0x1UL << LPTIM_CFGR_TRGFLT_Pos)
	0x00000040
#define	LPTIM_CFGR_TRGFLT_1   (0x2UL << LPTIM_CFGR_TRGFLT_Pos)
	0x00000080
#define	LPTIM_CFGR_PRESC_Pos   (9U)
#define	LPTIM_CFGR_PRESC_Msk   (0x7UL << LPTIM_CFGR_PRESC_Pos)
	0x00000E00
#define	LPTIM_CFGR_PRESC   LPTIM_CFGR_PRESC_Msk
	PRESC[2:0] bits (Clock prescaler).
#define	LPTIM_CFGR_PRESC_0   (0x1UL << LPTIM_CFGR_PRESC_Pos)
	0x00000200
#define	LPTIM_CFGR_PRESC_1   (0x2UL << LPTIM_CFGR_PRESC_Pos)
	0x00000400
#define	LPTIM_CFGR_PRESC_2   (0x4UL << LPTIM_CFGR_PRESC_Pos)
	0x00000800
#define	LPTIM_CFGR_TRIGSEL_Pos   (13U)
#define	LPTIM_CFGR_TRIGSEL_Msk   (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)
	0x0000E000
#define	LPTIM_CFGR_TRIGSEL   LPTIM_CFGR_TRIGSEL_Msk
	TRIGSEL[2:0]] bits (Trigger selector).
#define	LPTIM_CFGR_TRIGSEL_0   (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)
	0x00002000
#define	LPTIM_CFGR_TRIGSEL_1   (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)
	0x00004000
#define	LPTIM_CFGR_TRIGSEL_2   (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)
	0x00008000
#define	LPTIM_CFGR_TRIGEN_Pos   (17U)
#define	LPTIM_CFGR_TRIGEN_Msk   (0x3UL << LPTIM_CFGR_TRIGEN_Pos)
	0x00060000
#define	LPTIM_CFGR_TRIGEN   LPTIM_CFGR_TRIGEN_Msk
	TRIGEN[1:0] bits (Trigger enable and polarity).
#define	LPTIM_CFGR_TRIGEN_0   (0x1UL << LPTIM_CFGR_TRIGEN_Pos)
	0x00020000
#define	LPTIM_CFGR_TRIGEN_1   (0x2UL << LPTIM_CFGR_TRIGEN_Pos)
	0x00040000
#define	LPTIM_CFGR_TIMOUT_Pos   (19U)
#define	LPTIM_CFGR_TIMOUT_Msk   (0x1UL << LPTIM_CFGR_TIMOUT_Pos)
	0x00080000
#define	LPTIM_CFGR_TIMOUT   LPTIM_CFGR_TIMOUT_Msk
	Timout enable.
#define	LPTIM_CFGR_WAVE_Pos   (20U)
#define	LPTIM_CFGR_WAVE_Msk   (0x1UL << LPTIM_CFGR_WAVE_Pos)
	0x00100000
#define	LPTIM_CFGR_WAVE   LPTIM_CFGR_WAVE_Msk
	Waveform shape.
#define	LPTIM_CFGR_WAVPOL_Pos   (21U)
#define	LPTIM_CFGR_WAVPOL_Msk   (0x1UL << LPTIM_CFGR_WAVPOL_Pos)
	0x00200000
#define	LPTIM_CFGR_WAVPOL   LPTIM_CFGR_WAVPOL_Msk
	Waveform shape polarity.
#define	LPTIM_CFGR_PRELOAD_Pos   (22U)
#define	LPTIM_CFGR_PRELOAD_Msk   (0x1UL << LPTIM_CFGR_PRELOAD_Pos)
	0x00400000
#define	LPTIM_CFGR_PRELOAD   LPTIM_CFGR_PRELOAD_Msk
	Reg update mode.
#define	LPTIM_CFGR_COUNTMODE_Pos   (23U)
#define	LPTIM_CFGR_COUNTMODE_Msk   (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)
	0x00800000
#define	LPTIM_CFGR_COUNTMODE   LPTIM_CFGR_COUNTMODE_Msk
	Counter mode enable.
#define	LPTIM_CFGR_ENC_Pos   (24U)
#define	LPTIM_CFGR_ENC_Msk   (0x1UL << LPTIM_CFGR_ENC_Pos)
	0x01000000
#define	LPTIM_CFGR_ENC   LPTIM_CFGR_ENC_Msk
	Encoder mode enable.
#define	LPTIM_CR_ENABLE_Pos   (0U)
#define	LPTIM_CR_ENABLE_Msk   (0x1UL << LPTIM_CR_ENABLE_Pos)
	0x00000001
#define	LPTIM_CR_ENABLE   LPTIM_CR_ENABLE_Msk
	LPTIMer enable.
#define	LPTIM_CR_SNGSTRT_Pos   (1U)
#define	LPTIM_CR_SNGSTRT_Msk   (0x40001UL << LPTIM_CR_SNGSTRT_Pos)
	0x00080002
#define	LPTIM_CR_SNGSTRT   LPTIM_CR_SNGSTRT_Msk
	Timer start in single mode.
#define	LPTIM_CR_CNTSTRT_Pos   (2U)
#define	LPTIM_CR_CNTSTRT_Msk   (0x1UL << LPTIM_CR_CNTSTRT_Pos)
	0x00000004
#define	LPTIM_CR_CNTSTRT   LPTIM_CR_CNTSTRT_Msk
	Timer start in continuous mode.
#define	LPTIM_CR_COUNTRST_Pos   (3U)
#define	LPTIM_CR_COUNTRST_Msk   (0x1UL << LPTIM_CR_COUNTRST_Pos)
	0x00000008
#define	LPTIM_CR_COUNTRST   LPTIM_CR_COUNTRST_Msk
	Timer Counter reset in synchronous mode.
#define	LPTIM_CR_RSTARE_Pos   (4U)
#define	LPTIM_CR_RSTARE_Msk   (0x1UL << LPTIM_CR_RSTARE_Pos)
	0x00000010
#define	LPTIM_CR_RSTARE   LPTIM_CR_RSTARE_Msk
	Timer Counter reset after read enable (asynchronously).
#define	LPTIM_CMP_CMP_Pos   (0U)
#define	LPTIM_CMP_CMP_Msk   (0xFFFFUL << LPTIM_CMP_CMP_Pos)
	0x0000FFFF
#define	LPTIM_CMP_CMP   LPTIM_CMP_CMP_Msk
	Compare register.
#define	LPTIM_ARR_ARR_Pos   (0U)
#define	LPTIM_ARR_ARR_Msk   (0xFFFFUL << LPTIM_ARR_ARR_Pos)
	0x0000FFFF
#define	LPTIM_ARR_ARR   LPTIM_ARR_ARR_Msk
	Auto reload register.
#define	LPTIM_CNT_CNT_Pos   (0U)
#define	LPTIM_CNT_CNT_Msk   (0xFFFFUL << LPTIM_CNT_CNT_Pos)
	0x0000FFFF
#define	LPTIM_CNT_CNT   LPTIM_CNT_CNT_Msk
	Counter register.
#define	LPTIM_CFGR2_IN1SEL_Pos   (0U)
#define	LPTIM_CFGR2_IN1SEL_Msk   (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)
	0x00000003
#define	LPTIM_CFGR2_IN1SEL   LPTIM_CFGR2_IN1SEL_Msk
	IN1SEL[1:0] bits (Remap selection).
#define	LPTIM_CFGR2_IN1SEL_0   (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)
	0x00000001
#define	LPTIM_CFGR2_IN1SEL_1   (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)
	0x00000002
#define	LPTIM_CFGR2_IN2SEL_Pos   (4U)
#define	LPTIM_CFGR2_IN2SEL_Msk   (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)
	0x00000030
#define	LPTIM_CFGR2_IN2SEL   LPTIM_CFGR2_IN2SEL_Msk
	IN2SEL[5:4] bits (Remap selection).
#define	LPTIM_CFGR2_IN2SEL_0   (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)
	0x00000010
#define	LPTIM_CFGR2_IN2SEL_1   (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)
	0x00000020
#define	OCTOSPI_CR_EN_Pos   (0U)
#define	OCTOSPI_CR_EN_Msk   (0x1UL << OCTOSPI_CR_EN_Pos)
	0x00000001
#define	OCTOSPI_CR_EN   OCTOSPI_CR_EN_Msk
	Enable.
#define	OCTOSPI_CR_ABORT_Pos   (1U)
#define	OCTOSPI_CR_ABORT_Msk   (0x1UL << OCTOSPI_CR_ABORT_Pos)
	0x00000002
#define	OCTOSPI_CR_ABORT   OCTOSPI_CR_ABORT_Msk
	Abort request.
#define	OCTOSPI_CR_DMAEN_Pos   (2U)
#define	OCTOSPI_CR_DMAEN_Msk   (0x1UL << OCTOSPI_CR_DMAEN_Pos)
	0x00000004
#define	OCTOSPI_CR_DMAEN   OCTOSPI_CR_DMAEN_Msk
	DMA Enable.
#define	OCTOSPI_CR_TCEN_Pos   (3U)
#define	OCTOSPI_CR_TCEN_Msk   (0x1UL << OCTOSPI_CR_TCEN_Pos)
	0x00000008
#define	OCTOSPI_CR_TCEN   OCTOSPI_CR_TCEN_Msk
	Timeout Counter Enable.
#define	OCTOSPI_CR_DQM_Pos   (6U)
#define	OCTOSPI_CR_DQM_Msk   (0x1UL << OCTOSPI_CR_DQM_Pos)
	0x00000040
#define	OCTOSPI_CR_DQM   OCTOSPI_CR_DQM_Msk
	Dual-Quad Mode.
#define	OCTOSPI_CR_FSEL_Pos   (7U)
#define	OCTOSPI_CR_FSEL_Msk   (0x1UL << OCTOSPI_CR_FSEL_Pos)
	0x00000080
#define	OCTOSPI_CR_FSEL   OCTOSPI_CR_FSEL_Msk
	Flash Select.
#define	OCTOSPI_CR_FTHRES_Pos   (8U)
#define	OCTOSPI_CR_FTHRES_Msk   (0x1FUL << OCTOSPI_CR_FTHRES_Pos)
	0x00001F00
#define	OCTOSPI_CR_FTHRES   OCTOSPI_CR_FTHRES_Msk
	FIFO Threshold Level.
#define	OCTOSPI_CR_TEIE_Pos   (16U)
#define	OCTOSPI_CR_TEIE_Msk   (0x1UL << OCTOSPI_CR_TEIE_Pos)
	0x00010000
#define	OCTOSPI_CR_TEIE   OCTOSPI_CR_TEIE_Msk
	Transfer Error Interrupt Enable.
#define	OCTOSPI_CR_TCIE_Pos   (17U)
#define	OCTOSPI_CR_TCIE_Msk   (0x1UL << OCTOSPI_CR_TCIE_Pos)
	0x00020000
#define	OCTOSPI_CR_TCIE   OCTOSPI_CR_TCIE_Msk
	Transfer Complete Interrupt Enable.
#define	OCTOSPI_CR_FTIE_Pos   (18U)
#define	OCTOSPI_CR_FTIE_Msk   (0x1UL << OCTOSPI_CR_FTIE_Pos)
	0x00040000
#define	OCTOSPI_CR_FTIE   OCTOSPI_CR_FTIE_Msk
	FIFO Threshold Interrupt Enable.
#define	OCTOSPI_CR_SMIE_Pos   (19U)
#define	OCTOSPI_CR_SMIE_Msk   (0x1UL << OCTOSPI_CR_SMIE_Pos)
	0x00080000
#define	OCTOSPI_CR_SMIE   OCTOSPI_CR_SMIE_Msk
	Status Match Interrupt Enable.
#define	OCTOSPI_CR_TOIE_Pos   (20U)
#define	OCTOSPI_CR_TOIE_Msk   (0x1UL << OCTOSPI_CR_TOIE_Pos)
	0x00100000
#define	OCTOSPI_CR_TOIE   OCTOSPI_CR_TOIE_Msk
	TimeOut Interrupt Enable.
#define	OCTOSPI_CR_APMS_Pos   (22U)
#define	OCTOSPI_CR_APMS_Msk   (0x1UL << OCTOSPI_CR_APMS_Pos)
	0x00400000
#define	OCTOSPI_CR_APMS   OCTOSPI_CR_APMS_Msk
	Automatic Poll Mode Stop.
#define	OCTOSPI_CR_PMM_Pos   (23U)
#define	OCTOSPI_CR_PMM_Msk   (0x1UL << OCTOSPI_CR_PMM_Pos)
	0x00800000
#define	OCTOSPI_CR_PMM   OCTOSPI_CR_PMM_Msk
	Polling Match Mode.
#define	OCTOSPI_CR_FMODE_Pos   (28U)
#define	OCTOSPI_CR_FMODE_Msk   (0x3UL << OCTOSPI_CR_FMODE_Pos)
	0x30000000
#define	OCTOSPI_CR_FMODE   OCTOSPI_CR_FMODE_Msk
	Functional Mode.
#define	OCTOSPI_CR_FMODE_0   (0x1UL << OCTOSPI_CR_FMODE_Pos)
	0x10000000
#define	OCTOSPI_CR_FMODE_1   (0x2UL << OCTOSPI_CR_FMODE_Pos)
	0x20000000
#define	OCTOSPI_DCR1_CKMODE_Pos   (0U)
#define	OCTOSPI_DCR1_CKMODE_Msk   (0x1UL << OCTOSPI_DCR1_CKMODE_Pos)
	0x00000001
#define	OCTOSPI_DCR1_CKMODE   OCTOSPI_DCR1_CKMODE_Msk
	Mode 0 / Mode 3.
#define	OCTOSPI_DCR1_FRCK_Pos   (1U)
#define	OCTOSPI_DCR1_FRCK_Msk   (0x1UL << OCTOSPI_DCR1_FRCK_Pos)
	0x00000002
#define	OCTOSPI_DCR1_FRCK   OCTOSPI_DCR1_FRCK_Msk
	Free Running Clock.
#define	OCTOSPI_DCR1_DLYBYP_Pos   (3U)
#define	OCTOSPI_DCR1_DLYBYP_Msk   (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)
	0x00000008
#define	OCTOSPI_DCR1_DLYBYP   OCTOSPI_DCR1_DLYBYP_Msk
	Delay Block.
#define	OCTOSPI_DCR1_CSHT_Pos   (8U)
#define	OCTOSPI_DCR1_CSHT_Msk   (0x7UL << OCTOSPI_DCR1_CSHT_Pos)
	0x00000700
#define	OCTOSPI_DCR1_CSHT   OCTOSPI_DCR1_CSHT_Msk
	Chip Select High Time.
#define	OCTOSPI_DCR1_DEVSIZE_Pos   (16U)
#define	OCTOSPI_DCR1_DEVSIZE_Msk   (0x1FUL << OCTOSPI_DCR1_DEVSIZE_Pos)
	0x001F0000
#define	OCTOSPI_DCR1_DEVSIZE   OCTOSPI_DCR1_DEVSIZE_Msk
	Device Size.
#define	OCTOSPI_DCR1_MTYP_Pos   (24U)
#define	OCTOSPI_DCR1_MTYP_Msk   (0x7UL << OCTOSPI_DCR1_MTYP_Pos)
	0x07000000
#define	OCTOSPI_DCR1_MTYP   OCTOSPI_DCR1_MTYP_Msk
	Memory Type.
#define	OCTOSPI_DCR1_MTYP_0   (0x1UL << OCTOSPI_DCR1_MTYP_Pos)
	0x01000000
#define	OCTOSPI_DCR1_MTYP_1   (0x2UL << OCTOSPI_DCR1_MTYP_Pos)
	0x02000000
#define	OCTOSPI_DCR1_MTYP_2   (0x4UL << OCTOSPI_DCR1_MTYP_Pos)
	0x04000000
#define	OCTOSPI_DCR1_CKCSHT_Pos   (4U)
#define	OCTOSPI_DCR1_CKCSHT_Msk   (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)
	0x00000070
#define	OCTOSPI_DCR1_CKCSHT   OCTOSPI_DCR1_CKCSHT_Msk
	Clocked Chip Select High Time.
#define	OCTOSPI_DCR2_PRESCALER_Pos   (0U)
#define	OCTOSPI_DCR2_PRESCALER_Msk   (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)
	0x000000FF
#define	OCTOSPI_DCR2_PRESCALER   OCTOSPI_DCR2_PRESCALER_Msk
	Clock prescaler.
#define	OCTOSPI_DCR2_WRAPSIZE_Pos   (16U)
#define	OCTOSPI_DCR2_WRAPSIZE_Msk   (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos)
	0x00070000
#define	OCTOSPI_DCR2_WRAPSIZE   OCTOSPI_DCR2_WRAPSIZE_Msk
	Wrap Size.
#define	OCTOSPI_DCR2_WRAPSIZE_0   (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos)
	0x00010000
#define	OCTOSPI_DCR2_WRAPSIZE_1   (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos)
	0x00020000
#define	OCTOSPI_DCR2_WRAPSIZE_2   (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos)
	0x00040000
#define	OCTOSPI_DCR3_MAXTRAN_Pos   (0U)
#define	OCTOSPI_DCR3_MAXTRAN_Msk   (0xFFUL << OCTOSPI_DCR3_MAXTRAN_Pos)
	0x000000FF
#define	OCTOSPI_DCR3_MAXTRAN   OCTOSPI_DCR3_MAXTRAN_Msk
	Maximum Transfer.
#define	OCTOSPI_DCR3_CSBOUND_Pos   (16U)
#define	OCTOSPI_DCR3_CSBOUND_Msk   (0x1FUL << OCTOSPI_DCR3_CSBOUND_Pos)
	0x001F0000
#define	OCTOSPI_DCR3_CSBOUND   OCTOSPI_DCR3_CSBOUND_Msk
	CS Boundary.
#define	OCTOSPI_DCR4_REFRESH_Pos   (0U)
#define	OCTOSPI_DCR4_REFRESH_Msk   (0xFFFFFFFFUL << OCTOSPI_DCR4_REFRESH_Pos)
	0xFFFFFFFF
#define	OCTOSPI_DCR4_REFRESH   OCTOSPI_DCR4_REFRESH_Msk
	Refresh rate.
#define	OCTOSPI_SR_TEF_Pos   (0U)
#define	OCTOSPI_SR_TEF_Msk   (0x1UL << OCTOSPI_SR_TEF_Pos)
	0x00000001
#define	OCTOSPI_SR_TEF   OCTOSPI_SR_TEF_Msk
	Transfer Error Flag.
#define	OCTOSPI_SR_TCF_Pos   (1U)
#define	OCTOSPI_SR_TCF_Msk   (0x1UL << OCTOSPI_SR_TCF_Pos)
	0x00000002
#define	OCTOSPI_SR_TCF   OCTOSPI_SR_TCF_Msk
	Transfer Complete Flag.
#define	OCTOSPI_SR_FTF_Pos   (2U)
#define	OCTOSPI_SR_FTF_Msk   (0x1UL << OCTOSPI_SR_FTF_Pos)
	0x00000004
#define	OCTOSPI_SR_FTF   OCTOSPI_SR_FTF_Msk
	FIFO Threshold Flag.
#define	OCTOSPI_SR_SMF_Pos   (3U)
#define	OCTOSPI_SR_SMF_Msk   (0x1UL << OCTOSPI_SR_SMF_Pos)
	0x00000008
#define	OCTOSPI_SR_SMF   OCTOSPI_SR_SMF_Msk
	Status Match Flag.
#define	OCTOSPI_SR_TOF_Pos   (4U)
#define	OCTOSPI_SR_TOF_Msk   (0x1UL << OCTOSPI_SR_TOF_Pos)
	0x00000010
#define	OCTOSPI_SR_TOF   OCTOSPI_SR_TOF_Msk
	Timeout Flag.
#define	OCTOSPI_SR_BUSY_Pos   (5U)
#define	OCTOSPI_SR_BUSY_Msk   (0x1UL << OCTOSPI_SR_BUSY_Pos)
	0x00000020
#define	OCTOSPI_SR_BUSY   OCTOSPI_SR_BUSY_Msk
	Busy.
#define	OCTOSPI_SR_FLEVEL_Pos   (8U)
#define	OCTOSPI_SR_FLEVEL_Msk   (0x3FUL << OCTOSPI_SR_FLEVEL_Pos)
	0x00003F00
#define	OCTOSPI_SR_FLEVEL   OCTOSPI_SR_FLEVEL_Msk
	FIFO Level.
#define	OCTOSPI_FCR_CTEF_Pos   (0U)
#define	OCTOSPI_FCR_CTEF_Msk   (0x1UL << OCTOSPI_FCR_CTEF_Pos)
	0x00000001
#define	OCTOSPI_FCR_CTEF   OCTOSPI_FCR_CTEF_Msk
	Clear Transfer Error Flag.
#define	OCTOSPI_FCR_CTCF_Pos   (1U)
#define	OCTOSPI_FCR_CTCF_Msk   (0x1UL << OCTOSPI_FCR_CTCF_Pos)
	0x00000002
#define	OCTOSPI_FCR_CTCF   OCTOSPI_FCR_CTCF_Msk
	Clear Transfer Complete Flag.
#define	OCTOSPI_FCR_CSMF_Pos   (3U)
#define	OCTOSPI_FCR_CSMF_Msk   (0x1UL << OCTOSPI_FCR_CSMF_Pos)
	0x00000008
#define	OCTOSPI_FCR_CSMF   OCTOSPI_FCR_CSMF_Msk
	Clear Status Match Flag.
#define	OCTOSPI_FCR_CTOF_Pos   (4U)
#define	OCTOSPI_FCR_CTOF_Msk   (0x1UL << OCTOSPI_FCR_CTOF_Pos)
	0x00000010
#define	OCTOSPI_FCR_CTOF   OCTOSPI_FCR_CTOF_Msk
	Clear Timeout Flag.
#define	OCTOSPI_DLR_DL_Pos   (0U)
#define	OCTOSPI_DLR_DL_Msk   (0xFFFFFFFFUL << OCTOSPI_DLR_DL_Pos)
	0xFFFFFFFF
#define	OCTOSPI_DLR_DL   OCTOSPI_DLR_DL_Msk
	Data Length.
#define	OCTOSPI_AR_ADDRESS_Pos   (0U)
#define	OCTOSPI_AR_ADDRESS_Msk   (0xFFFFFFFFUL << OCTOSPI_AR_ADDRESS_Pos)
	0xFFFFFFFF
#define	OCTOSPI_AR_ADDRESS   OCTOSPI_AR_ADDRESS_Msk
	Address.
#define	OCTOSPI_DR_DATA_Pos   (0U)
#define	OCTOSPI_DR_DATA_Msk   (0xFFFFFFFFUL << OCTOSPI_DR_DATA_Pos)
	0xFFFFFFFF
#define	OCTOSPI_DR_DATA   OCTOSPI_DR_DATA_Msk
	Data.
#define	OCTOSPI_PSMKR_MASK_Pos   (0U)
#define	OCTOSPI_PSMKR_MASK_Msk   (0xFFFFFFFFUL << OCTOSPI_PSMKR_MASK_Pos)
	0xFFFFFFFF
#define	OCTOSPI_PSMKR_MASK   OCTOSPI_PSMKR_MASK_Msk
	Status mask.
#define	OCTOSPI_PSMAR_MATCH_Pos   (0U)
#define	OCTOSPI_PSMAR_MATCH_Msk   (0xFFFFFFFFUL << OCTOSPI_PSMAR_MATCH_Pos)
	0xFFFFFFFF
#define	OCTOSPI_PSMAR_MATCH   OCTOSPI_PSMAR_MATCH_Msk
	Status match.
#define	OCTOSPI_PIR_INTERVAL_Pos   (0U)
#define	OCTOSPI_PIR_INTERVAL_Msk   (0xFFFFUL << OCTOSPI_PIR_INTERVAL_Pos)
	0x0000FFFF
#define	OCTOSPI_PIR_INTERVAL   OCTOSPI_PIR_INTERVAL_Msk
	Polling Interval.
#define	OCTOSPI_CCR_IMODE_Pos   (0U)
#define	OCTOSPI_CCR_IMODE_Msk   (0x7UL << OCTOSPI_CCR_IMODE_Pos)
	0x00000007
#define	OCTOSPI_CCR_IMODE   OCTOSPI_CCR_IMODE_Msk
	Instruction Mode.
#define	OCTOSPI_CCR_IMODE_0   (0x1UL << OCTOSPI_CCR_IMODE_Pos)
	0x00000001
#define	OCTOSPI_CCR_IMODE_1   (0x2UL << OCTOSPI_CCR_IMODE_Pos)
	0x00000002
#define	OCTOSPI_CCR_IMODE_2   (0x4UL << OCTOSPI_CCR_IMODE_Pos)
	0x00000004
#define	OCTOSPI_CCR_IDTR_Pos   (3U)
#define	OCTOSPI_CCR_IDTR_Msk   (0x1UL << OCTOSPI_CCR_IDTR_Pos)
	0x00000008
#define	OCTOSPI_CCR_IDTR   OCTOSPI_CCR_IDTR_Msk
	Instruction Double Transfer Rate.
#define	OCTOSPI_CCR_ISIZE_Pos   (4U)
#define	OCTOSPI_CCR_ISIZE_Msk   (0x3UL << OCTOSPI_CCR_ISIZE_Pos)
	0x00000030
#define	OCTOSPI_CCR_ISIZE   OCTOSPI_CCR_ISIZE_Msk
	Instruction Size.
#define	OCTOSPI_CCR_ISIZE_0   (0x1UL << OCTOSPI_CCR_ISIZE_Pos)
	0x00000010
#define	OCTOSPI_CCR_ISIZE_1   (0x2UL << OCTOSPI_CCR_ISIZE_Pos)
	0x00000020
#define	OCTOSPI_CCR_ADMODE_Pos   (8U)
#define	OCTOSPI_CCR_ADMODE_Msk   (0x7UL << OCTOSPI_CCR_ADMODE_Pos)
	0x00000700
#define	OCTOSPI_CCR_ADMODE   OCTOSPI_CCR_ADMODE_Msk
	Address Mode.
#define	OCTOSPI_CCR_ADMODE_0   (0x1UL << OCTOSPI_CCR_ADMODE_Pos)
	0x00000100
#define	OCTOSPI_CCR_ADMODE_1   (0x2UL << OCTOSPI_CCR_ADMODE_Pos)
	0x00000200
#define	OCTOSPI_CCR_ADMODE_2   (0x4UL << OCTOSPI_CCR_ADMODE_Pos)
	0x00000400
#define	OCTOSPI_CCR_ADDTR_Pos   (11U)
#define	OCTOSPI_CCR_ADDTR_Msk   (0x1UL << OCTOSPI_CCR_ADDTR_Pos)
	0x00000800
#define	OCTOSPI_CCR_ADDTR   OCTOSPI_CCR_ADDTR_Msk
	Address Double Transfer Rate.
#define	OCTOSPI_CCR_ADSIZE_Pos   (12U)
#define	OCTOSPI_CCR_ADSIZE_Msk   (0x3UL << OCTOSPI_CCR_ADSIZE_Pos)
	0x00003000
#define	OCTOSPI_CCR_ADSIZE   OCTOSPI_CCR_ADSIZE_Msk
	Address Size.
#define	OCTOSPI_CCR_ADSIZE_0   (0x1UL << OCTOSPI_CCR_ADSIZE_Pos)
	0x00001000
#define	OCTOSPI_CCR_ADSIZE_1   (0x2UL << OCTOSPI_CCR_ADSIZE_Pos)
	0x00002000
#define	OCTOSPI_CCR_ABMODE_Pos   (16U)
#define	OCTOSPI_CCR_ABMODE_Msk   (0x7UL << OCTOSPI_CCR_ABMODE_Pos)
	0x00070000
#define	OCTOSPI_CCR_ABMODE   OCTOSPI_CCR_ABMODE_Msk
	Alternate Bytes Mode.
#define	OCTOSPI_CCR_ABMODE_0   (0x1UL << OCTOSPI_CCR_ABMODE_Pos)
	0x00010000
#define	OCTOSPI_CCR_ABMODE_1   (0x2UL << OCTOSPI_CCR_ABMODE_Pos)
	0x00020000
#define	OCTOSPI_CCR_ABMODE_2   (0x4UL << OCTOSPI_CCR_ABMODE_Pos)
	0x00040000
#define	OCTOSPI_CCR_ABDTR_Pos   (19U)
#define	OCTOSPI_CCR_ABDTR_Msk   (0x1UL << OCTOSPI_CCR_ABDTR_Pos)
	0x00080000
#define	OCTOSPI_CCR_ABDTR   OCTOSPI_CCR_ABDTR_Msk
	Alternate Bytes Double Transfer Rate.
#define	OCTOSPI_CCR_ABSIZE_Pos   (20U)
#define	OCTOSPI_CCR_ABSIZE_Msk   (0x3UL << OCTOSPI_CCR_ABSIZE_Pos)
	0x00300000
#define	OCTOSPI_CCR_ABSIZE   OCTOSPI_CCR_ABSIZE_Msk
	Alternate Bytes Size.
#define	OCTOSPI_CCR_ABSIZE_0   (0x1UL << OCTOSPI_CCR_ABSIZE_Pos)
	0x00100000
#define	OCTOSPI_CCR_ABSIZE_1   (0x2UL << OCTOSPI_CCR_ABSIZE_Pos)
	0x00200000
#define	OCTOSPI_CCR_DMODE_Pos   (24U)
#define	OCTOSPI_CCR_DMODE_Msk   (0x7UL << OCTOSPI_CCR_DMODE_Pos)
	0x07000000
#define	OCTOSPI_CCR_DMODE   OCTOSPI_CCR_DMODE_Msk
	Data Mode.
#define	OCTOSPI_CCR_DMODE_0   (0x1UL << OCTOSPI_CCR_DMODE_Pos)
	0x01000000
#define	OCTOSPI_CCR_DMODE_1   (0x2UL << OCTOSPI_CCR_DMODE_Pos)
	0x02000000
#define	OCTOSPI_CCR_DMODE_2   (0x4UL << OCTOSPI_CCR_DMODE_Pos)
	0x04000000
#define	OCTOSPI_CCR_DDTR_Pos   (27U)
#define	OCTOSPI_CCR_DDTR_Msk   (0x1UL << OCTOSPI_CCR_DDTR_Pos)
	0x08000000
#define	OCTOSPI_CCR_DDTR   OCTOSPI_CCR_DDTR_Msk
	Data Double Transfer Rate.
#define	OCTOSPI_CCR_DQSE_Pos   (29U)
#define	OCTOSPI_CCR_DQSE_Msk   (0x1UL << OCTOSPI_CCR_DQSE_Pos)
	0x20000000
#define	OCTOSPI_CCR_DQSE   OCTOSPI_CCR_DQSE_Msk
	DQS Enable.
#define	OCTOSPI_CCR_SIOO_Pos   (31U)
#define	OCTOSPI_CCR_SIOO_Msk   (0x1UL << OCTOSPI_CCR_SIOO_Pos)
	0x80000000
#define	OCTOSPI_CCR_SIOO   OCTOSPI_CCR_SIOO_Msk
	Send Instruction Only Once Mode.
#define	OCTOSPI_TCR_DCYC_Pos   (0U)
#define	OCTOSPI_TCR_DCYC_Msk   (0x1FUL << OCTOSPI_TCR_DCYC_Pos)
	0x0000001F
#define	OCTOSPI_TCR_DCYC   OCTOSPI_TCR_DCYC_Msk
	Number of Dummy Cycles.
#define	OCTOSPI_TCR_DHQC_Pos   (28U)
#define	OCTOSPI_TCR_DHQC_Msk   (0x1UL << OCTOSPI_TCR_DHQC_Pos)
	0x10000000
#define	OCTOSPI_TCR_DHQC   OCTOSPI_TCR_DHQC_Msk
	Delay Hold Quarter Cycle.
#define	OCTOSPI_TCR_SSHIFT_Pos   (30U)
#define	OCTOSPI_TCR_SSHIFT_Msk   (0x1UL << OCTOSPI_TCR_SSHIFT_Pos)
	0x40000000
#define	OCTOSPI_TCR_SSHIFT   OCTOSPI_TCR_SSHIFT_Msk
	Sample Shift.
#define	OCTOSPI_IR_INSTRUCTION_Pos   (0U)
#define	OCTOSPI_IR_INSTRUCTION_Msk   (0xFFFFFFFFUL << OCTOSPI_IR_INSTRUCTION_Pos)
	0xFFFFFFFF
#define	OCTOSPI_IR_INSTRUCTION   OCTOSPI_IR_INSTRUCTION_Msk
	Instruction.
#define	OCTOSPI_ABR_ALTERNATE_Pos   (0U)
#define	OCTOSPI_ABR_ALTERNATE_Msk   (0xFFFFFFFFUL << OCTOSPI_ABR_ALTERNATE_Pos)
	0xFFFFFFFF
#define	OCTOSPI_ABR_ALTERNATE   OCTOSPI_ABR_ALTERNATE_Msk
	Alternate Bytes.
#define	OCTOSPI_LPTR_TIMEOUT_Pos   (0U)
#define	OCTOSPI_LPTR_TIMEOUT_Msk   (0xFFFFUL << OCTOSPI_LPTR_TIMEOUT_Pos)
	0x0000FFFF
#define	OCTOSPI_LPTR_TIMEOUT   OCTOSPI_LPTR_TIMEOUT_Msk
	Timeout period.
#define	OCTOSPI_WPCCR_IMODE_Pos   (0U)
#define	OCTOSPI_WPCCR_IMODE_Msk   (0x7UL << OCTOSPI_WPCCR_IMODE_Pos)
	0x00000007
#define	OCTOSPI_WPCCR_IMODE   OCTOSPI_WPCCR_IMODE_Msk
	Instruction Mode.
#define	OCTOSPI_WPCCR_IMODE_0   (0x1UL << OCTOSPI_WPCCR_IMODE_Pos)
	0x00000001
#define	OCTOSPI_WPCCR_IMODE_1   (0x2UL << OCTOSPI_WPCCR_IMODE_Pos)
	0x00000002
#define	OCTOSPI_WPCCR_IMODE_2   (0x4UL << OCTOSPI_WPCCR_IMODE_Pos)
	0x00000004
#define	OCTOSPI_WPCCR_IDTR_Pos   (3U)
#define	OCTOSPI_WPCCR_IDTR_Msk   (0x1UL << OCTOSPI_WPCCR_IDTR_Pos)
	0x00000008
#define	OCTOSPI_WPCCR_IDTR   OCTOSPI_WPCCR_IDTR_Msk
	Instruction Double Transfer Rate.
#define	OCTOSPI_WPCCR_ISIZE_Pos   (4U)
#define	OCTOSPI_WPCCR_ISIZE_Msk   (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos)
	0x00000030
#define	OCTOSPI_WPCCR_ISIZE   OCTOSPI_WPCCR_ISIZE_Msk
	Instruction Size.
#define	OCTOSPI_WPCCR_ISIZE_0   (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos)
	0x00000010
#define	OCTOSPI_WPCCR_ISIZE_1   (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos)
	0x00000020
#define	OCTOSPI_WPCCR_ADMODE_Pos   (8U)
#define	OCTOSPI_WPCCR_ADMODE_Msk   (0x7UL << OCTOSPI_WPCCR_ADMODE_Pos)
	0x00000700
#define	OCTOSPI_WPCCR_ADMODE   OCTOSPI_WPCCR_ADMODE_Msk
	Address Mode.
#define	OCTOSPI_WPCCR_ADMODE_0   (0x1UL << OCTOSPI_WPCCR_ADMODE_Pos)
	0x00000100
#define	OCTOSPI_WPCCR_ADMODE_1   (0x2UL << OCTOSPI_WPCCR_ADMODE_Pos)
	0x00000200
#define	OCTOSPI_WPCCR_ADMODE_2   (0x4UL << OCTOSPI_WPCCR_ADMODE_Pos)
	0x00000400
#define	OCTOSPI_WPCCR_ADDTR_Pos   (11U)
#define	OCTOSPI_WPCCR_ADDTR_Msk   (0x1UL << OCTOSPI_WPCCR_ADDTR_Pos)
	0x00000800
#define	OCTOSPI_WPCCR_ADDTR   OCTOSPI_WPCCR_ADDTR_Msk
	Address Double Transfer Rate.
#define	OCTOSPI_WPCCR_ADSIZE_Pos   (12U)
#define	OCTOSPI_WPCCR_ADSIZE_Msk   (0x3UL << OCTOSPI_WPCCR_ADSIZE_Pos)
	0x00003000
#define	OCTOSPI_WPCCR_ADSIZE   OCTOSPI_WPCCR_ADSIZE_Msk
	Address Size.
#define	OCTOSPI_WPCCR_ADSIZE_0   (0x1UL << OCTOSPI_WPCCR_ADSIZE_Pos)
	0x00001000
#define	OCTOSPI_WPCCR_ADSIZE_1   (0x2UL << OCTOSPI_WPCCR_ADSIZE_Pos)
	0x00002000
#define	OCTOSPI_WPCCR_ABMODE_Pos   (16U)
#define	OCTOSPI_WPCCR_ABMODE_Msk   (0x7UL << OCTOSPI_WPCCR_ABMODE_Pos)
	0x00070000
#define	OCTOSPI_WPCCR_ABMODE   OCTOSPI_WPCCR_ABMODE_Msk
	Alternate Bytes Mode.
#define	OCTOSPI_WPCCR_ABMODE_0   (0x1UL << OCTOSPI_WPCCR_ABMODE_Pos)
	0x00010000
#define	OCTOSPI_WPCCR_ABMODE_1   (0x2UL << OCTOSPI_WPCCR_ABMODE_Pos)
	0x00020000
#define	OCTOSPI_WPCCR_ABMODE_2   (0x4UL << OCTOSPI_WPCCR_ABMODE_Pos)
	0x00040000
#define	OCTOSPI_WPCCR_ABDTR_Pos   (19U)
#define	OCTOSPI_WPCCR_ABDTR_Msk   (0x1UL << OCTOSPI_WPCCR_ABDTR_Pos)
	0x00080000
#define	OCTOSPI_WPCCR_ABDTR   OCTOSPI_WPCCR_ABDTR_Msk
	Alternate Bytes Double Transfer Rate.
#define	OCTOSPI_WPCCR_ABSIZE_Pos   (20U)
#define	OCTOSPI_WPCCR_ABSIZE_Msk   (0x3UL << OCTOSPI_WPCCR_ABSIZE_Pos)
	0x00300000
#define	OCTOSPI_WPCCR_ABSIZE   OCTOSPI_WPCCR_ABSIZE_Msk
	Alternate Bytes Size.
#define	OCTOSPI_WPCCR_ABSIZE_0   (0x1UL << OCTOSPI_WPCCR_ABSIZE_Pos)
	0x00100000
#define	OCTOSPI_WPCCR_ABSIZE_1   (0x2UL << OCTOSPI_WPCCR_ABSIZE_Pos)
	0x00200000
#define	OCTOSPI_WPCCR_DMODE_Pos   (24U)
#define	OCTOSPI_WPCCR_DMODE_Msk   (0x7UL << OCTOSPI_WPCCR_DMODE_Pos)
	0x07000000
#define	OCTOSPI_WPCCR_DMODE   OCTOSPI_WPCCR_DMODE_Msk
	Data Mode.
#define	OCTOSPI_WPCCR_DMODE_0   (0x1UL << OCTOSPI_WPCCR_DMODE_Pos)
	0x01000000
#define	OCTOSPI_WPCCR_DMODE_1   (0x2UL << OCTOSPI_WPCCR_DMODE_Pos)
	0x02000000
#define	OCTOSPI_WPCCR_DMODE_2   (0x4UL << OCTOSPI_WPCCR_DMODE_Pos)
	0x04000000
#define	OCTOSPI_WPCCR_DDTR_Pos   (27U)
#define	OCTOSPI_WPCCR_DDTR_Msk   (0x1UL << OCTOSPI_WPCCR_DDTR_Pos)
	0x08000000
#define	OCTOSPI_WPCCR_DDTR   OCTOSPI_WPCCR_DDTR_Msk
	Data Double Transfer Rate.
#define	OCTOSPI_WPCCR_DQSE_Pos   (29U)
#define	OCTOSPI_WPCCR_DQSE_Msk   (0x1UL << OCTOSPI_WPCCR_DQSE_Pos)
	0x20000000
#define	OCTOSPI_WPCCR_DQSE   OCTOSPI_WPCCR_DQSE_Msk
	DQS Enable.
#define	OCTOSPI_WPCCR_SIOO_Pos   (31U)
#define	OCTOSPI_WPCCR_SIOO_Msk   (0x1UL << OCTOSPI_WPCCR_SIOO_Pos)
	0x80000000
#define	OCTOSPI_WPCCR_SIOO   OCTOSPI_WPCCR_SIOO_Msk
	Send Instruction Only Once Mode.
#define	OCTOSPI_WPTCR_DCYC_Pos   (0U)
#define	OCTOSPI_WPTCR_DCYC_Msk   (0x1FUL << OCTOSPI_WPTCR_DCYC_Pos)
	0x0000001F
#define	OCTOSPI_WPTCR_DCYC   OCTOSPI_WPTCR_DCYC_Msk
	Number of Dummy Cycles.
#define	OCTOSPI_WPTCR_DHQC_Pos   (28U)
#define	OCTOSPI_WPTCR_DHQC_Msk   (0x1UL << OCTOSPI_WPTCR_DHQC_Pos)
	0x10000000
#define	OCTOSPI_WPTCR_DHQC   OCTOSPI_WPTCR_DHQC_Msk
	Delay Hold Quarter Cycle.
#define	OCTOSPI_WPTCR_SSHIFT_Pos   (30U)
#define	OCTOSPI_WPTCR_SSHIFT_Msk   (0x1UL << OCTOSPI_WPTCR_SSHIFT_Pos)
	0x40000000
#define	OCTOSPI_WPTCR_SSHIFT   OCTOSPI_WPTCR_SSHIFT_Msk
	Sample Shift.
#define	OCTOSPI_WPIR_INSTRUCTION_Pos   (0U)
#define	OCTOSPI_WPIR_INSTRUCTION_Msk   (0xFFFFFFFFUL << OCTOSPI_WPIR_INSTRUCTION_Pos)
	0xFFFFFFFF
#define	OCTOSPI_WPIR_INSTRUCTION   OCTOSPI_WPIR_INSTRUCTION_Msk
	Instruction.
#define	OCTOSPI_WPABR_ALTERNATE_Pos   (0U)
#define	OCTOSPI_WPABR_ALTERNATE_Msk   (0xFFFFFFFFUL << OCTOSPI_WPABR_ALTERNATE_Pos)
	0xFFFFFFFF
#define	OCTOSPI_WPABR_ALTERNATE   OCTOSPI_WPABR_ALTERNATE_Msk
	Alternate Bytes.
#define	OCTOSPI_WCCR_IMODE_Pos   (0U)
#define	OCTOSPI_WCCR_IMODE_Msk   (0x7UL << OCTOSPI_WCCR_IMODE_Pos)
	0x00000007
#define	OCTOSPI_WCCR_IMODE   OCTOSPI_WCCR_IMODE_Msk
	Instruction Mode.
#define	OCTOSPI_WCCR_IMODE_0   (0x1UL << OCTOSPI_WCCR_IMODE_Pos)
	0x00000001
#define	OCTOSPI_WCCR_IMODE_1   (0x2UL << OCTOSPI_WCCR_IMODE_Pos)
	0x00000002
#define	OCTOSPI_WCCR_IMODE_2   (0x4UL << OCTOSPI_WCCR_IMODE_Pos)
	0x00000004
#define	OCTOSPI_WCCR_IDTR_Pos   (3U)
#define	OCTOSPI_WCCR_IDTR_Msk   (0x1UL << OCTOSPI_WCCR_IDTR_Pos)
	0x00000008
#define	OCTOSPI_WCCR_IDTR   OCTOSPI_WCCR_IDTR_Msk
	Instruction Double Transfer Rate.
#define	OCTOSPI_WCCR_ISIZE_Pos   (4U)
#define	OCTOSPI_WCCR_ISIZE_Msk   (0x3UL << OCTOSPI_WCCR_ISIZE_Pos)
	0x00000030
#define	OCTOSPI_WCCR_ISIZE   OCTOSPI_WCCR_ISIZE_Msk
	Instruction Size.
#define	OCTOSPI_WCCR_ISIZE_0   (0x1UL << OCTOSPI_WCCR_ISIZE_Pos)
	0x00000010
#define	OCTOSPI_WCCR_ISIZE_1   (0x2UL << OCTOSPI_WCCR_ISIZE_Pos)
	0x00000020
#define	OCTOSPI_WCCR_ADMODE_Pos   (8U)
#define	OCTOSPI_WCCR_ADMODE_Msk   (0x7UL << OCTOSPI_WCCR_ADMODE_Pos)
	0x00000700
#define	OCTOSPI_WCCR_ADMODE   OCTOSPI_WCCR_ADMODE_Msk
	Address Mode.
#define	OCTOSPI_WCCR_ADMODE_0   (0x1UL << OCTOSPI_WCCR_ADMODE_Pos)
	0x00000100
#define	OCTOSPI_WCCR_ADMODE_1   (0x2UL << OCTOSPI_WCCR_ADMODE_Pos)
	0x00000200
#define	OCTOSPI_WCCR_ADMODE_2   (0x4UL << OCTOSPI_WCCR_ADMODE_Pos)
	0x00000400
#define	OCTOSPI_WCCR_ADDTR_Pos   (11U)
#define	OCTOSPI_WCCR_ADDTR_Msk   (0x1UL << OCTOSPI_WCCR_ADDTR_Pos)
	0x00000800
#define	OCTOSPI_WCCR_ADDTR   OCTOSPI_WCCR_ADDTR_Msk
	Address Double Transfer Rate.
#define	OCTOSPI_WCCR_ADSIZE_Pos   (12U)
#define	OCTOSPI_WCCR_ADSIZE_Msk   (0x3UL << OCTOSPI_WCCR_ADSIZE_Pos)
	0x00003000
#define	OCTOSPI_WCCR_ADSIZE   OCTOSPI_WCCR_ADSIZE_Msk
	Address Size.
#define	OCTOSPI_WCCR_ADSIZE_0   (0x1UL << OCTOSPI_WCCR_ADSIZE_Pos)
	0x00001000
#define	OCTOSPI_WCCR_ADSIZE_1   (0x2UL << OCTOSPI_WCCR_ADSIZE_Pos)
	0x00002000
#define	OCTOSPI_WCCR_ABMODE_Pos   (16U)
#define	OCTOSPI_WCCR_ABMODE_Msk   (0x7UL << OCTOSPI_WCCR_ABMODE_Pos)
	0x00070000
#define	OCTOSPI_WCCR_ABMODE   OCTOSPI_WCCR_ABMODE_Msk
	Alternate Bytes Mode.
#define	OCTOSPI_WCCR_ABMODE_0   (0x1UL << OCTOSPI_WCCR_ABMODE_Pos)
	0x00010000
#define	OCTOSPI_WCCR_ABMODE_1   (0x2UL << OCTOSPI_WCCR_ABMODE_Pos)
	0x00020000
#define	OCTOSPI_WCCR_ABMODE_2   (0x4UL << OCTOSPI_WCCR_ABMODE_Pos)
	0x00040000
#define	OCTOSPI_WCCR_ABDTR_Pos   (19U)
#define	OCTOSPI_WCCR_ABDTR_Msk   (0x1UL << OCTOSPI_WCCR_ABDTR_Pos)
	0x00080000
#define	OCTOSPI_WCCR_ABDTR   OCTOSPI_WCCR_ABDTR_Msk
	Alternate Bytes Double Transfer Rate.
#define	OCTOSPI_WCCR_ABSIZE_Pos   (20U)
#define	OCTOSPI_WCCR_ABSIZE_Msk   (0x3UL << OCTOSPI_WCCR_ABSIZE_Pos)
	0x00300000
#define	OCTOSPI_WCCR_ABSIZE   OCTOSPI_WCCR_ABSIZE_Msk
	Alternate Bytes Size.
#define	OCTOSPI_WCCR_ABSIZE_0   (0x1UL << OCTOSPI_WCCR_ABSIZE_Pos)
	0x00100000
#define	OCTOSPI_WCCR_ABSIZE_1   (0x2UL << OCTOSPI_WCCR_ABSIZE_Pos)
	0x00200000
#define	OCTOSPI_WCCR_DMODE_Pos   (24U)
#define	OCTOSPI_WCCR_DMODE_Msk   (0x7UL << OCTOSPI_WCCR_DMODE_Pos)
	0x07000000
#define	OCTOSPI_WCCR_DMODE   OCTOSPI_WCCR_DMODE_Msk
	Data Mode.
#define	OCTOSPI_WCCR_DMODE_0   (0x1UL << OCTOSPI_WCCR_DMODE_Pos)
	0x01000000
#define	OCTOSPI_WCCR_DMODE_1   (0x2UL << OCTOSPI_WCCR_DMODE_Pos)
	0x02000000
#define	OCTOSPI_WCCR_DMODE_2   (0x4UL << OCTOSPI_WCCR_DMODE_Pos)
	0x04000000
#define	OCTOSPI_WCCR_DDTR_Pos   (27U)
#define	OCTOSPI_WCCR_DDTR_Msk   (0x1UL << OCTOSPI_WCCR_DDTR_Pos)
	0x08000000
#define	OCTOSPI_WCCR_DDTR   OCTOSPI_WCCR_DDTR_Msk
	Data Double Transfer Rate.
#define	OCTOSPI_WCCR_DQSE_Pos   (29U)
#define	OCTOSPI_WCCR_DQSE_Msk   (0x1UL << OCTOSPI_WCCR_DQSE_Pos)
	0x20000000
#define	OCTOSPI_WCCR_DQSE   OCTOSPI_WCCR_DQSE_Msk
	DQS Enable.
#define	OCTOSPI_WCCR_SIOO_Pos   (31U)
#define	OCTOSPI_WCCR_SIOO_Msk   (0x1UL << OCTOSPI_WCCR_SIOO_Pos)
	0x80000000
#define	OCTOSPI_WCCR_SIOO   OCTOSPI_WCCR_SIOO_Msk
	Send Instruction Only Once Mode.
#define	OCTOSPI_WTCR_DCYC_Pos   (0U)
#define	OCTOSPI_WTCR_DCYC_Msk   (0x1FUL << OCTOSPI_WTCR_DCYC_Pos)
	0x0000001F
#define	OCTOSPI_WTCR_DCYC   OCTOSPI_WTCR_DCYC_Msk
	Number of Dummy Cycles.
#define	OCTOSPI_WIR_INSTRUCTION_Pos   (0U)
#define	OCTOSPI_WIR_INSTRUCTION_Msk   (0xFFFFFFFFUL << OCTOSPI_WIR_INSTRUCTION_Pos)
	0xFFFFFFFF
#define	OCTOSPI_WIR_INSTRUCTION   OCTOSPI_WIR_INSTRUCTION_Msk
	Instruction.
#define	OCTOSPI_WABR_ALTERNATE_Pos   (0U)
#define	OCTOSPI_WABR_ALTERNATE_Msk   (0xFFFFFFFFUL << OCTOSPI_WABR_ALTERNATE_Pos)
	0xFFFFFFFF
#define	OCTOSPI_WABR_ALTERNATE   OCTOSPI_WABR_ALTERNATE_Msk
	Alternate Bytes.
#define	OCTOSPI_HLCR_LM_Pos   (0U)
#define	OCTOSPI_HLCR_LM_Msk   (0x1UL << OCTOSPI_HLCR_LM_Pos)
	0x00000001
#define	OCTOSPI_HLCR_LM   OCTOSPI_HLCR_LM_Msk
	Latency Mode.
#define	OCTOSPI_HLCR_WZL_Pos   (1U)
#define	OCTOSPI_HLCR_WZL_Msk   (0x1UL << OCTOSPI_HLCR_WZL_Pos)
	0x00000002
#define	OCTOSPI_HLCR_WZL   OCTOSPI_HLCR_WZL_Msk
	Write Zero Latency.
#define	OCTOSPI_HLCR_TACC_Pos   (8U)
#define	OCTOSPI_HLCR_TACC_Msk   (0xFFUL << OCTOSPI_HLCR_TACC_Pos)
	0x0000FF00
#define	OCTOSPI_HLCR_TACC   OCTOSPI_HLCR_TACC_Msk
	Access Time.
#define	OCTOSPI_HLCR_TRWR_Pos   (16U)
#define	OCTOSPI_HLCR_TRWR_Msk   (0xFFUL << OCTOSPI_HLCR_TRWR_Pos)
	0x00FF0000
#define	OCTOSPI_HLCR_TRWR   OCTOSPI_HLCR_TRWR_Msk
	Read Write Recovery Time.
#define	OCTOSPI_VER_VER_Pos   (0U)
#define	OCTOSPI_VER_VER_Msk   (0xFFUL << OCTOSPI_VER_VER_Pos)
	0x000000FF
#define	OCTOSPI_VER_VER   OCTOSPI_VER_VER_Msk
	Version.
#define	OCTOSPI_ID_ID_Pos   (0U)
#define	OCTOSPI_ID_ID_Msk   (0xFFFFFFFFUL << OCTOSPI_ID_ID_Pos)
	0xFFFFFFFF
#define	OCTOSPI_ID_ID   OCTOSPI_ID_ID_Msk
	Identification.
#define	OCTOSPI_MID_MID_Pos   (0U)
#define	OCTOSPI_MID_MID_Msk   (0xFFFFFFFFUL << OCTOSPI_MID_MID_Pos)
	0xFFFFFFFF
#define	OCTOSPI_MID_MID   OCTOSPI_MID_MID_Msk
	Magic ID.
#define	OCTOSPIM_CR_MUXEN_Pos   (0U)
#define	OCTOSPIM_CR_MUXEN_Msk   (0x1UL << OCTOSPIM_CR_MUXEN_Pos)
	0x00000001
#define	OCTOSPIM_CR_MUXEN   OCTOSPIM_CR_MUXEN_Msk
	Multiplexed mode enable.
#define	OCTOSPIM_CR_REQ2ACK_TIME_Pos   (16U)
#define	OCTOSPIM_CR_REQ2ACK_TIME_Msk   (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos
	0x00FF0000
#define	OCTOSPIM_CR_REQ2ACK_TIME   OCTOSPIM_CR_REQ2ACK_TIME_Msk
	REQ to ACK time.
#define	OCTOSPIM_PCR_CLKEN_Pos   (0U)
#define	OCTOSPIM_PCR_CLKEN_Msk   (0x1UL << OCTOSPIM_PCR_CLKEN_Pos)
	0x00000001
#define	OCTOSPIM_PCR_CLKEN   OCTOSPIM_PCR_CLKEN_Msk
	CLK/CLKn Enable for Port n.
#define	OCTOSPIM_PCR_CLKSRC_Pos   (1U)
#define	OCTOSPIM_PCR_CLKSRC_Msk   (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos)
	0x00000002
#define	OCTOSPIM_PCR_CLKSRC   OCTOSPIM_PCR_CLKSRC_Msk
	CLK/CLKn Source for Port n.
#define	OCTOSPIM_PCR_DQSEN_Pos   (4U)
#define	OCTOSPIM_PCR_DQSEN_Msk   (0x1UL << OCTOSPIM_PCR_DQSEN_Pos)
	0x00000010
#define	OCTOSPIM_PCR_DQSEN   OCTOSPIM_PCR_DQSEN_Msk
	DQS Enable for Port n.
#define	OCTOSPIM_PCR_DQSSRC_Pos   (5U)
#define	OCTOSPIM_PCR_DQSSRC_Msk   (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos)
	0x00000020
#define	OCTOSPIM_PCR_DQSSRC   OCTOSPIM_PCR_DQSSRC_Msk
	DQS Source for Port n.
#define	OCTOSPIM_PCR_NCSEN_Pos   (8U)
#define	OCTOSPIM_PCR_NCSEN_Msk   (0x1UL << OCTOSPIM_PCR_NCSEN_Pos)
	0x00000100
#define	OCTOSPIM_PCR_NCSEN   OCTOSPIM_PCR_NCSEN_Msk
	nCS Enable for Port n
#define	OCTOSPIM_PCR_NCSSRC_Pos   (9U)
#define	OCTOSPIM_PCR_NCSSRC_Msk   (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos)
	0x00000200
#define	OCTOSPIM_PCR_NCSSRC   OCTOSPIM_PCR_NCSSRC_Msk
	nCS Source for Port n
#define	OCTOSPIM_PCR_IOLEN_Pos   (16U)
#define	OCTOSPIM_PCR_IOLEN_Msk   (0x1UL << OCTOSPIM_PCR_IOLEN_Pos)
	0x00010000
#define	OCTOSPIM_PCR_IOLEN   OCTOSPIM_PCR_IOLEN_Msk
	IO[3:0] Enable for Port n.
#define	OCTOSPIM_PCR_IOLSRC_Pos   (17U)
#define	OCTOSPIM_PCR_IOLSRC_Msk   (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos)
	0x00060000
#define	OCTOSPIM_PCR_IOLSRC   OCTOSPIM_PCR_IOLSRC_Msk
	IO[3:0] Source for Port n.
#define	OCTOSPIM_PCR_IOLSRC_0   (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos)
	0x00020000
#define	OCTOSPIM_PCR_IOLSRC_1   (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos)
	0x00040000
#define	OCTOSPIM_PCR_IOHEN_Pos   (24U)
#define	OCTOSPIM_PCR_IOHEN_Msk   (0x1UL << OCTOSPIM_PCR_IOHEN_Pos)
	0x01000000
#define	OCTOSPIM_PCR_IOHEN   OCTOSPIM_PCR_IOHEN_Msk
	IO[7:4] Enable for Port n.
#define	OCTOSPIM_PCR_IOHSRC_Pos   (25U)
#define	OCTOSPIM_PCR_IOHSRC_Msk   (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos)
	0x06000000
#define	OCTOSPIM_PCR_IOHSRC   OCTOSPIM_PCR_IOHSRC_Msk
	IO[7:4] Source for Port n.
#define	OCTOSPIM_PCR_IOHSRC_0   (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos)
	0x02000000
#define	OCTOSPIM_PCR_IOHSRC_1   (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos)
	0x04000000
#define	COMP_SR_C1VAL_Pos   (0U)
#define	COMP_SR_C1VAL_Msk   (0x1UL << COMP_SR_C1VAL_Pos)
	0x00000001
#define	COMP_SR_C1VAL   COMP_SR_C1VAL_Msk
#define	COMP_SR_C2VAL_Pos   (1U)
#define	COMP_SR_C2VAL_Msk   (0x1UL << COMP_SR_C2VAL_Pos)
	0x00000002
#define	COMP_SR_C2VAL   COMP_SR_C2VAL_Msk
#define	COMP_SR_C1IF_Pos   (16U)
#define	COMP_SR_C1IF_Msk   (0x1UL << COMP_SR_C1IF_Pos)
	0x00010000
#define	COMP_SR_C1IF   COMP_SR_C1IF_Msk
#define	COMP_SR_C2IF_Pos   (17U)
#define	COMP_SR_C2IF_Msk   (0x1UL << COMP_SR_C2IF_Pos)
	0x00020000
#define	COMP_SR_C2IF   COMP_SR_C2IF_Msk
#define	COMP_ICFR_C1IF_Pos   (16U)
#define	COMP_ICFR_C1IF_Msk   (0x1UL << COMP_ICFR_C1IF_Pos)
	0x00010000
#define	COMP_ICFR_C1IF   COMP_ICFR_C1IF_Msk
#define	COMP_ICFR_C2IF_Pos   (17U)
#define	COMP_ICFR_C2IF_Msk   (0x1UL << COMP_ICFR_C2IF_Pos)
	0x00020000
#define	COMP_ICFR_C2IF   COMP_ICFR_C2IF_Msk
#define	COMP_OR_AFOPA6_Pos   (0U)
#define	COMP_OR_AFOPA6_Msk   (0x1UL << COMP_OR_AFOPA6_Pos)
	0x00000001
#define	COMP_OR_AFOPA6   COMP_OR_AFOPA6_Msk
#define	COMP_OR_AFOPA8_Pos   (1U)
#define	COMP_OR_AFOPA8_Msk   (0x1UL << COMP_OR_AFOPA8_Pos)
	0x00000002
#define	COMP_OR_AFOPA8   COMP_OR_AFOPA8_Msk
#define	COMP_OR_AFOPB12_Pos   (2U)
#define	COMP_OR_AFOPB12_Msk   (0x1UL << COMP_OR_AFOPB12_Pos)
	0x00000004
#define	COMP_OR_AFOPB12   COMP_OR_AFOPB12_Msk
#define	COMP_OR_AFOPE6_Pos   (3U)
#define	COMP_OR_AFOPE6_Msk   (0x1UL << COMP_OR_AFOPE6_Pos)
	0x00000008
#define	COMP_OR_AFOPE6   COMP_OR_AFOPE6_Msk
#define	COMP_OR_AFOPE15_Pos   (4U)
#define	COMP_OR_AFOPE15_Msk   (0x1UL << COMP_OR_AFOPE15_Pos)
	0x00000010
#define	COMP_OR_AFOPE15   COMP_OR_AFOPE15_Msk
#define	COMP_OR_AFOPG2_Pos   (5U)
#define	COMP_OR_AFOPG2_Msk   (0x1UL << COMP_OR_AFOPG2_Pos)
	0x00000020
#define	COMP_OR_AFOPG2   COMP_OR_AFOPG2_Msk
#define	COMP_OR_AFOPG3_Pos   (6U)
#define	COMP_OR_AFOPG3_Msk   (0x1UL << COMP_OR_AFOPG3_Pos)
	0x00000040
#define	COMP_OR_AFOPG3   COMP_OR_AFOPG3_Msk
#define	COMP_OR_AFOPG4_Pos   (7U)
#define	COMP_OR_AFOPG4_Msk   (0x1UL << COMP_OR_AFOPG4_Pos)
	0x00000080
#define	COMP_OR_AFOPG4   COMP_OR_AFOPG4_Msk
#define	COMP_OR_AFOPI1_Pos   (8U)
#define	COMP_OR_AFOPI1_Msk   (0x1UL << COMP_OR_AFOPI1_Pos)
	0x00000100
#define	COMP_OR_AFOPI1   COMP_OR_AFOPI1_Msk
#define	COMP_OR_AFOPI4_Pos   (9U)
#define	COMP_OR_AFOPI4_Msk   (0x1UL << COMP_OR_AFOPI4_Pos)
	0x00000200
#define	COMP_OR_AFOPI4   COMP_OR_AFOPI4_Msk
#define	COMP_OR_AFOPK2_Pos   (10U)
#define	COMP_OR_AFOPK2_Msk   (0x1UL << COMP_OR_AFOPK2_Pos)
	0x00000400
#define	COMP_OR_AFOPK2   COMP_OR_AFOPK2_Msk
	****************** Bit definition for COMP_CFGRx register
#define	COMP_CFGRx_EN_Pos   (0U)
#define	COMP_CFGRx_EN_Msk   (0x1UL << COMP_CFGRx_EN_Pos)
	0x00000001
#define	COMP_CFGRx_EN   COMP_CFGRx_EN_Msk
	COMPx enable bit.
#define	COMP_CFGRx_BRGEN_Pos   (1U)
#define	COMP_CFGRx_BRGEN_Msk   (0x1UL << COMP_CFGRx_BRGEN_Pos)
	0x00000002
#define	COMP_CFGRx_BRGEN   COMP_CFGRx_BRGEN_Msk
	COMPx Scaler bridge enable.
#define	COMP_CFGRx_SCALEN_Pos   (2U)
#define	COMP_CFGRx_SCALEN_Msk   (0x1UL << COMP_CFGRx_SCALEN_Pos)
	0x00000004
#define	COMP_CFGRx_SCALEN   COMP_CFGRx_SCALEN_Msk
	COMPx Voltage scaler enable bit.
#define	COMP_CFGRx_POLARITY_Pos   (3U)
#define	COMP_CFGRx_POLARITY_Msk   (0x1UL << COMP_CFGRx_POLARITY_Pos)
	0x00000008
#define	COMP_CFGRx_POLARITY   COMP_CFGRx_POLARITY_Msk
	COMPx polarity selection bit.
#define	COMP_CFGRx_WINMODE_Pos   (4U)
#define	COMP_CFGRx_WINMODE_Msk   (0x1UL << COMP_CFGRx_WINMODE_Pos)
	0x00000010
#define	COMP_CFGRx_WINMODE   COMP_CFGRx_WINMODE_Msk
	COMPx Windows mode selection bit.
#define	COMP_CFGRx_ITEN_Pos   (6U)
#define	COMP_CFGRx_ITEN_Msk   (0x1UL << COMP_CFGRx_ITEN_Pos)
	0x00000040
#define	COMP_CFGRx_ITEN   COMP_CFGRx_ITEN_Msk
	COMPx interrupt enable.
#define	COMP_CFGRx_HYST_Pos   (8U)
#define	COMP_CFGRx_HYST_Msk   (0x3UL << COMP_CFGRx_HYST_Pos)
	0x00000300
#define	COMP_CFGRx_HYST   COMP_CFGRx_HYST_Msk
	COMPx hysteresis selection bits.
#define	COMP_CFGRx_HYST_0   (0x1UL << COMP_CFGRx_HYST_Pos)
	0x00000100
#define	COMP_CFGRx_HYST_1   (0x2UL << COMP_CFGRx_HYST_Pos)
	0x00000200
#define	COMP_CFGRx_PWRMODE_Pos   (12U)
#define	COMP_CFGRx_PWRMODE_Msk   (0x3UL << COMP_CFGRx_PWRMODE_Pos)
	0x00003000
#define	COMP_CFGRx_PWRMODE   COMP_CFGRx_PWRMODE_Msk
	COMPx Power Mode of the comparator.
#define	COMP_CFGRx_PWRMODE_0   (0x1UL << COMP_CFGRx_PWRMODE_Pos)
	0x00001000
#define	COMP_CFGRx_PWRMODE_1   (0x2UL << COMP_CFGRx_PWRMODE_Pos)
	0x00002000
#define	COMP_CFGRx_INMSEL_Pos   (16U)
#define	COMP_CFGRx_INMSEL_Msk   (0x7UL << COMP_CFGRx_INMSEL_Pos)
	0x00070000
#define	COMP_CFGRx_INMSEL   COMP_CFGRx_INMSEL_Msk
	COMPx input minus selection bit.
#define	COMP_CFGRx_INMSEL_0   (0x1UL << COMP_CFGRx_INMSEL_Pos)
	0x00010000
#define	COMP_CFGRx_INMSEL_1   (0x2UL << COMP_CFGRx_INMSEL_Pos)
	0x00020000
#define	COMP_CFGRx_INMSEL_2   (0x4UL << COMP_CFGRx_INMSEL_Pos)
	0x00040000
#define	COMP_CFGRx_INPSEL_Pos   (20U)
#define	COMP_CFGRx_INPSEL_Msk   (0x1UL << COMP_CFGRx_INPSEL_Pos)
	0x00100000
#define	COMP_CFGRx_INPSEL   COMP_CFGRx_INPSEL_Msk
	COMPx input plus selection bit.
#define	COMP_CFGRx_BLANKING_Pos   (24U)
#define	COMP_CFGRx_BLANKING_Msk   (0xFUL << COMP_CFGRx_BLANKING_Pos)
	0x0F000000
#define	COMP_CFGRx_BLANKING   COMP_CFGRx_BLANKING_Msk
	COMPx blanking source selection bits.
#define	COMP_CFGRx_BLANKING_0   (0x1UL << COMP_CFGRx_BLANKING_Pos)
	0x01000000
#define	COMP_CFGRx_BLANKING_1   (0x2UL << COMP_CFGRx_BLANKING_Pos)
	0x02000000
#define	COMP_CFGRx_BLANKING_2   (0x4UL << COMP_CFGRx_BLANKING_Pos)
	0x04000000
#define	COMP_CFGRx_LOCK_Pos   (31U)
#define	COMP_CFGRx_LOCK_Msk   (0x1UL << COMP_CFGRx_LOCK_Pos)
	0x80000000
#define	COMP_CFGRx_LOCK   COMP_CFGRx_LOCK_Msk
	COMPx Lock Bit.
#define	USART_CR1_UE_Pos   (0U)
#define	USART_CR1_UE_Msk   (0x1UL << USART_CR1_UE_Pos)
	0x00000001
#define	USART_CR1_UE   USART_CR1_UE_Msk
	USART Enable.
#define	USART_CR1_UESM_Pos   (1U)
#define	USART_CR1_UESM_Msk   (0x1UL << USART_CR1_UESM_Pos)
	0x00000002
#define	USART_CR1_UESM   USART_CR1_UESM_Msk
	USART Enable in STOP Mode.
#define	USART_CR1_RE_Pos   (2U)
#define	USART_CR1_RE_Msk   (0x1UL << USART_CR1_RE_Pos)
	0x00000004
#define	USART_CR1_RE   USART_CR1_RE_Msk
	Receiver Enable.
#define	USART_CR1_TE_Pos   (3U)
#define	USART_CR1_TE_Msk   (0x1UL << USART_CR1_TE_Pos)
	0x00000008
#define	USART_CR1_TE   USART_CR1_TE_Msk
	Transmitter Enable.
#define	USART_CR1_IDLEIE_Pos   (4U)
#define	USART_CR1_IDLEIE_Msk   (0x1UL << USART_CR1_IDLEIE_Pos)
	0x00000010
#define	USART_CR1_IDLEIE   USART_CR1_IDLEIE_Msk
	IDLE Interrupt Enable.
#define	USART_CR1_RXNEIE_RXFNEIE_Pos   (5U)
#define	USART_CR1_RXNEIE_RXFNEIE_Msk   (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos)
	0x00000020
#define	USART_CR1_RXNEIE_RXFNEIE   USART_CR1_RXNEIE_RXFNEIE_Msk
	RXNE and RX FIFO Not Empty Interrupt Enable.
#define	USART_CR1_TCIE_Pos   (6U)
#define	USART_CR1_TCIE_Msk   (0x1UL << USART_CR1_TCIE_Pos)
	0x00000040
#define	USART_CR1_TCIE   USART_CR1_TCIE_Msk
	Transmission Complete Interrupt Enable.
#define	USART_CR1_TXEIE_TXFNFIE_Pos   (7U)
#define	USART_CR1_TXEIE_TXFNFIE_Msk   (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos)
	0x00000080
#define	USART_CR1_TXEIE_TXFNFIE   USART_CR1_TXEIE_TXFNFIE_Msk
	TXE and TX FIFO Not Full Interrupt Enable.
#define	USART_CR1_PEIE_Pos   (8U)
#define	USART_CR1_PEIE_Msk   (0x1UL << USART_CR1_PEIE_Pos)
	0x00000100
#define	USART_CR1_PEIE   USART_CR1_PEIE_Msk
	PE Interrupt Enable.
#define	USART_CR1_PS_Pos   (9U)
#define	USART_CR1_PS_Msk   (0x1UL << USART_CR1_PS_Pos)
	0x00000200
#define	USART_CR1_PS   USART_CR1_PS_Msk
	Parity Selection.
#define	USART_CR1_PCE_Pos   (10U)
#define	USART_CR1_PCE_Msk   (0x1UL << USART_CR1_PCE_Pos)
	0x00000400
#define	USART_CR1_PCE   USART_CR1_PCE_Msk
	Parity Control Enable.
#define	USART_CR1_WAKE_Pos   (11U)
#define	USART_CR1_WAKE_Msk   (0x1UL << USART_CR1_WAKE_Pos)
	0x00000800
#define	USART_CR1_WAKE   USART_CR1_WAKE_Msk
	Receiver Wakeup method.
#define	USART_CR1_M_Pos   (12U)
#define	USART_CR1_M_Msk   (0x10001UL << USART_CR1_M_Pos)
	0x10001000
#define	USART_CR1_M   USART_CR1_M_Msk
	Word length.
#define	USART_CR1_M0_Pos   (12U)
#define	USART_CR1_M0_Msk   (0x1UL << USART_CR1_M0_Pos)
	0x00001000
#define	USART_CR1_M0   USART_CR1_M0_Msk
	Word length - Bit 0.
#define	USART_CR1_MME_Pos   (13U)
#define	USART_CR1_MME_Msk   (0x1UL << USART_CR1_MME_Pos)
	0x00002000
#define	USART_CR1_MME   USART_CR1_MME_Msk
	Mute Mode Enable.
#define	USART_CR1_CMIE_Pos   (14U)
#define	USART_CR1_CMIE_Msk   (0x1UL << USART_CR1_CMIE_Pos)
	0x00004000
#define	USART_CR1_CMIE   USART_CR1_CMIE_Msk
	Character match interrupt enable.
#define	USART_CR1_OVER8_Pos   (15U)
#define	USART_CR1_OVER8_Msk   (0x1UL << USART_CR1_OVER8_Pos)
	0x00008000
#define	USART_CR1_OVER8   USART_CR1_OVER8_Msk
	Oversampling by 8-bit or 16-bit mode.
#define	USART_CR1_DEDT_Pos   (16U)
#define	USART_CR1_DEDT_Msk   (0x1FUL << USART_CR1_DEDT_Pos)
	0x001F0000
#define	USART_CR1_DEDT   USART_CR1_DEDT_Msk
	DEDT[4:0] bits (Driver Enable Deassertion Time).
#define	USART_CR1_DEDT_0   (0x01UL << USART_CR1_DEDT_Pos)
	0x00010000
#define	USART_CR1_DEDT_1   (0x02UL << USART_CR1_DEDT_Pos)
	0x00020000
#define	USART_CR1_DEDT_2   (0x04UL << USART_CR1_DEDT_Pos)
	0x00040000
#define	USART_CR1_DEDT_3   (0x08UL << USART_CR1_DEDT_Pos)
	0x00080000
#define	USART_CR1_DEDT_4   (0x10UL << USART_CR1_DEDT_Pos)
	0x00100000
#define	USART_CR1_DEAT_Pos   (21U)
#define	USART_CR1_DEAT_Msk   (0x1FUL << USART_CR1_DEAT_Pos)
	0x03E00000
#define	USART_CR1_DEAT   USART_CR1_DEAT_Msk
	DEAT[4:0] bits (Driver Enable Assertion Time).
#define	USART_CR1_DEAT_0   (0x01UL << USART_CR1_DEAT_Pos)
	0x00200000
#define	USART_CR1_DEAT_1   (0x02UL << USART_CR1_DEAT_Pos)
	0x00400000
#define	USART_CR1_DEAT_2   (0x04UL << USART_CR1_DEAT_Pos)
	0x00800000
#define	USART_CR1_DEAT_3   (0x08UL << USART_CR1_DEAT_Pos)
	0x01000000
#define	USART_CR1_DEAT_4   (0x10UL << USART_CR1_DEAT_Pos)
	0x02000000
#define	USART_CR1_RTOIE_Pos   (26U)
#define	USART_CR1_RTOIE_Msk   (0x1UL << USART_CR1_RTOIE_Pos)
	0x04000000
#define	USART_CR1_RTOIE   USART_CR1_RTOIE_Msk
	Receive Time Out interrupt enable.
#define	USART_CR1_EOBIE_Pos   (27U)
#define	USART_CR1_EOBIE_Msk   (0x1UL << USART_CR1_EOBIE_Pos)
	0x08000000
#define	USART_CR1_EOBIE   USART_CR1_EOBIE_Msk
	End of Block interrupt enable.
#define	USART_CR1_M1_Pos   (28U)
#define	USART_CR1_M1_Msk   (0x1UL << USART_CR1_M1_Pos)
	0x10000000
#define	USART_CR1_M1   USART_CR1_M1_Msk
	Word length - Bit 1.
#define	USART_CR1_FIFOEN_Pos   (29U)
#define	USART_CR1_FIFOEN_Msk   (0x1UL << USART_CR1_FIFOEN_Pos)
	0x20000000
#define	USART_CR1_FIFOEN   USART_CR1_FIFOEN_Msk
	FIFO mode enable.
#define	USART_CR1_TXFEIE_Pos   (30U)
#define	USART_CR1_TXFEIE_Msk   (0x1UL << USART_CR1_TXFEIE_Pos)
	0x40000000
#define	USART_CR1_TXFEIE   USART_CR1_TXFEIE_Msk
	TXFIFO empty interrupt enable.
#define	USART_CR1_RXFFIE_Pos   (31U)
#define	USART_CR1_RXFFIE_Msk   (0x1UL << USART_CR1_RXFFIE_Pos)
	0x80000000
#define	USART_CR1_RXFFIE   USART_CR1_RXFFIE_Msk
	RXFIFO Full interrupt enable.
#define	USART_CR1_RXNEIE   USART_CR1_RXNEIE_RXFNEIE
#define	USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE
#define	USART_CR2_SLVEN_Pos   (0U)
#define	USART_CR2_SLVEN_Msk   (0x1UL << USART_CR2_SLVEN_Pos)
	0x00000001
#define	USART_CR2_SLVEN   USART_CR2_SLVEN_Msk
	Synchronous Slave mode Enable.
#define	USART_CR2_DIS_NSS_Pos   (3U)
#define	USART_CR2_DIS_NSS_Msk   (0x1UL << USART_CR2_DIS_NSS_Pos)
	0x00000008
#define	USART_CR2_DIS_NSS   USART_CR2_DIS_NSS_Msk
	Negative Slave Select (NSS) pin management.
#define	USART_CR2_ADDM7_Pos   (4U)
#define	USART_CR2_ADDM7_Msk   (0x1UL << USART_CR2_ADDM7_Pos)
	0x00000010
#define	USART_CR2_ADDM7   USART_CR2_ADDM7_Msk
	7-bit or 4-bit Address Detection
#define	USART_CR2_LBDL_Pos   (5U)
#define	USART_CR2_LBDL_Msk   (0x1UL << USART_CR2_LBDL_Pos)
	0x00000020
#define	USART_CR2_LBDL   USART_CR2_LBDL_Msk
	LIN Break Detection Length.
#define	USART_CR2_LBDIE_Pos   (6U)
#define	USART_CR2_LBDIE_Msk   (0x1UL << USART_CR2_LBDIE_Pos)
	0x00000040
#define	USART_CR2_LBDIE   USART_CR2_LBDIE_Msk
	LIN Break Detection Interrupt Enable.
#define	USART_CR2_LBCL_Pos   (8U)
#define	USART_CR2_LBCL_Msk   (0x1UL << USART_CR2_LBCL_Pos)
	0x00000100
#define	USART_CR2_LBCL   USART_CR2_LBCL_Msk
	Last Bit Clock pulse.
#define	USART_CR2_CPHA_Pos   (9U)
#define	USART_CR2_CPHA_Msk   (0x1UL << USART_CR2_CPHA_Pos)
	0x00000200
#define	USART_CR2_CPHA   USART_CR2_CPHA_Msk
	Clock Phase.
#define	USART_CR2_CPOL_Pos   (10U)
#define	USART_CR2_CPOL_Msk   (0x1UL << USART_CR2_CPOL_Pos)
	0x00000400
#define	USART_CR2_CPOL   USART_CR2_CPOL_Msk
	Clock Polarity.
#define	USART_CR2_CLKEN_Pos   (11U)
#define	USART_CR2_CLKEN_Msk   (0x1UL << USART_CR2_CLKEN_Pos)
	0x00000800
#define	USART_CR2_CLKEN   USART_CR2_CLKEN_Msk
	Clock Enable.
#define	USART_CR2_STOP_Pos   (12U)
#define	USART_CR2_STOP_Msk   (0x3UL << USART_CR2_STOP_Pos)
	0x00003000
#define	USART_CR2_STOP   USART_CR2_STOP_Msk
	STOP[1:0] bits (STOP bits).
#define	USART_CR2_STOP_0   (0x1UL << USART_CR2_STOP_Pos)
	0x00001000
#define	USART_CR2_STOP_1   (0x2UL << USART_CR2_STOP_Pos)
	0x00002000
#define	USART_CR2_LINEN_Pos   (14U)
#define	USART_CR2_LINEN_Msk   (0x1UL << USART_CR2_LINEN_Pos)
	0x00004000
#define	USART_CR2_LINEN   USART_CR2_LINEN_Msk
	LIN mode enable.
#define	USART_CR2_SWAP_Pos   (15U)
#define	USART_CR2_SWAP_Msk   (0x1UL << USART_CR2_SWAP_Pos)
	0x00008000
#define	USART_CR2_SWAP   USART_CR2_SWAP_Msk
	SWAP TX/RX pins.
#define	USART_CR2_RXINV_Pos   (16U)
#define	USART_CR2_RXINV_Msk   (0x1UL << USART_CR2_RXINV_Pos)
	0x00010000
#define	USART_CR2_RXINV   USART_CR2_RXINV_Msk
	RX pin active level inversion.
#define	USART_CR2_TXINV_Pos   (17U)
#define	USART_CR2_TXINV_Msk   (0x1UL << USART_CR2_TXINV_Pos)
	0x00020000
#define	USART_CR2_TXINV   USART_CR2_TXINV_Msk
	TX pin active level inversion.
#define	USART_CR2_DATAINV_Pos   (18U)
#define	USART_CR2_DATAINV_Msk   (0x1UL << USART_CR2_DATAINV_Pos)
	0x00040000
#define	USART_CR2_DATAINV   USART_CR2_DATAINV_Msk
	Binary data inversion.
#define	USART_CR2_MSBFIRST_Pos   (19U)
#define	USART_CR2_MSBFIRST_Msk   (0x1UL << USART_CR2_MSBFIRST_Pos)
	0x00080000
#define	USART_CR2_MSBFIRST   USART_CR2_MSBFIRST_Msk
	Most Significant Bit First.
#define	USART_CR2_ABREN_Pos   (20U)
#define	USART_CR2_ABREN_Msk   (0x1UL << USART_CR2_ABREN_Pos)
	0x00100000
#define	USART_CR2_ABREN   USART_CR2_ABREN_Msk
	Auto Baud-Rate Enable.
#define	USART_CR2_ABRMODE_Pos   (21U)
#define	USART_CR2_ABRMODE_Msk   (0x3UL << USART_CR2_ABRMODE_Pos)
	0x00600000
#define	USART_CR2_ABRMODE   USART_CR2_ABRMODE_Msk
	ABRMOD[1:0] bits (Auto Baud-Rate Mode).
#define	USART_CR2_ABRMODE_0   (0x1UL << USART_CR2_ABRMODE_Pos)
	0x00200000
#define	USART_CR2_ABRMODE_1   (0x2UL << USART_CR2_ABRMODE_Pos)
	0x00400000
#define	USART_CR2_RTOEN_Pos   (23U)
#define	USART_CR2_RTOEN_Msk   (0x1UL << USART_CR2_RTOEN_Pos)
	0x00800000
#define	USART_CR2_RTOEN   USART_CR2_RTOEN_Msk
	Receiver Time-Out enable.
#define	USART_CR2_ADD_Pos   (24U)
#define	USART_CR2_ADD_Msk   (0xFFUL << USART_CR2_ADD_Pos)
	0xFF000000
#define	USART_CR2_ADD   USART_CR2_ADD_Msk
	Address of the USART node.
#define	USART_CR3_EIE_Pos   (0U)
#define	USART_CR3_EIE_Msk   (0x1UL << USART_CR3_EIE_Pos)
	0x00000001
#define	USART_CR3_EIE   USART_CR3_EIE_Msk
	Error Interrupt Enable.
#define	USART_CR3_IREN_Pos   (1U)
#define	USART_CR3_IREN_Msk   (0x1UL << USART_CR3_IREN_Pos)
	0x00000002
#define	USART_CR3_IREN   USART_CR3_IREN_Msk
	IrDA mode Enable.
#define	USART_CR3_IRLP_Pos   (2U)
#define	USART_CR3_IRLP_Msk   (0x1UL << USART_CR3_IRLP_Pos)
	0x00000004
#define	USART_CR3_IRLP   USART_CR3_IRLP_Msk
	IrDA Low-Power.
#define	USART_CR3_HDSEL_Pos   (3U)
#define	USART_CR3_HDSEL_Msk   (0x1UL << USART_CR3_HDSEL_Pos)
	0x00000008
#define	USART_CR3_HDSEL   USART_CR3_HDSEL_Msk
	Half-Duplex Selection.
#define	USART_CR3_NACK_Pos   (4U)
#define	USART_CR3_NACK_Msk   (0x1UL << USART_CR3_NACK_Pos)
	0x00000010
#define	USART_CR3_NACK   USART_CR3_NACK_Msk
	SmartCard NACK enable.
#define	USART_CR3_SCEN_Pos   (5U)
#define	USART_CR3_SCEN_Msk   (0x1UL << USART_CR3_SCEN_Pos)
	0x00000020
#define	USART_CR3_SCEN   USART_CR3_SCEN_Msk
	SmartCard mode enable.
#define	USART_CR3_DMAR_Pos   (6U)
#define	USART_CR3_DMAR_Msk   (0x1UL << USART_CR3_DMAR_Pos)
	0x00000040
#define	USART_CR3_DMAR   USART_CR3_DMAR_Msk
	DMA Enable Receiver.
#define	USART_CR3_DMAT_Pos   (7U)
#define	USART_CR3_DMAT_Msk   (0x1UL << USART_CR3_DMAT_Pos)
	0x00000080
#define	USART_CR3_DMAT   USART_CR3_DMAT_Msk
	DMA Enable Transmitter.
#define	USART_CR3_RTSE_Pos   (8U)
#define	USART_CR3_RTSE_Msk   (0x1UL << USART_CR3_RTSE_Pos)
	0x00000100
#define	USART_CR3_RTSE   USART_CR3_RTSE_Msk
	RTS Enable.
#define	USART_CR3_CTSE_Pos   (9U)
#define	USART_CR3_CTSE_Msk   (0x1UL << USART_CR3_CTSE_Pos)
	0x00000200
#define	USART_CR3_CTSE   USART_CR3_CTSE_Msk
	CTS Enable.
#define	USART_CR3_CTSIE_Pos   (10U)
#define	USART_CR3_CTSIE_Msk   (0x1UL << USART_CR3_CTSIE_Pos)
	0x00000400
#define	USART_CR3_CTSIE   USART_CR3_CTSIE_Msk
	CTS Interrupt Enable.
#define	USART_CR3_ONEBIT_Pos   (11U)
#define	USART_CR3_ONEBIT_Msk   (0x1UL << USART_CR3_ONEBIT_Pos)
	0x00000800
#define	USART_CR3_ONEBIT   USART_CR3_ONEBIT_Msk
	One sample bit method enable.
#define	USART_CR3_OVRDIS_Pos   (12U)
#define	USART_CR3_OVRDIS_Msk   (0x1UL << USART_CR3_OVRDIS_Pos)
	0x00001000
#define	USART_CR3_OVRDIS   USART_CR3_OVRDIS_Msk
	Overrun Disable.
#define	USART_CR3_DDRE_Pos   (13U)
#define	USART_CR3_DDRE_Msk   (0x1UL << USART_CR3_DDRE_Pos)
	0x00002000
#define	USART_CR3_DDRE   USART_CR3_DDRE_Msk
	DMA Disable on Reception Error.
#define	USART_CR3_DEM_Pos   (14U)
#define	USART_CR3_DEM_Msk   (0x1UL << USART_CR3_DEM_Pos)
	0x00004000
#define	USART_CR3_DEM   USART_CR3_DEM_Msk
	Driver Enable Mode.
#define	USART_CR3_DEP_Pos   (15U)
#define	USART_CR3_DEP_Msk   (0x1UL << USART_CR3_DEP_Pos)
	0x00008000
#define	USART_CR3_DEP   USART_CR3_DEP_Msk
	Driver Enable Polarity Selection.
#define	USART_CR3_SCARCNT_Pos   (17U)
#define	USART_CR3_SCARCNT_Msk   (0x7UL << USART_CR3_SCARCNT_Pos)
	0x000E0000
#define	USART_CR3_SCARCNT   USART_CR3_SCARCNT_Msk
	SCARCNT[2:0] bits (SmartCard Auto-Retry Count).
#define	USART_CR3_SCARCNT_0   (0x1UL << USART_CR3_SCARCNT_Pos)
	0x00020000
#define	USART_CR3_SCARCNT_1   (0x2UL << USART_CR3_SCARCNT_Pos)
	0x00040000
#define	USART_CR3_SCARCNT_2   (0x4UL << USART_CR3_SCARCNT_Pos)
	0x00080000
#define	USART_CR3_WUS_Pos   (20U)
#define	USART_CR3_WUS_Msk   (0x3UL << USART_CR3_WUS_Pos)
	0x00300000
#define	USART_CR3_WUS   USART_CR3_WUS_Msk
	WUS[1:0] bits (Wake UP Interrupt Flag Selection).
#define	USART_CR3_WUS_0   (0x1UL << USART_CR3_WUS_Pos)
	0x00100000
#define	USART_CR3_WUS_1   (0x2UL << USART_CR3_WUS_Pos)
	0x00200000
#define	USART_CR3_WUFIE_Pos   (22U)
#define	USART_CR3_WUFIE_Msk   (0x1UL << USART_CR3_WUFIE_Pos)
	0x00400000
#define	USART_CR3_WUFIE   USART_CR3_WUFIE_Msk
	Wake Up Interrupt Enable.
#define	USART_CR3_TXFTIE_Pos   (23U)
#define	USART_CR3_TXFTIE_Msk   (0x1UL << USART_CR3_TXFTIE_Pos)
	0x00800000
#define	USART_CR3_TXFTIE   USART_CR3_TXFTIE_Msk
	TXFIFO threshold interrupt enable.
#define	USART_CR3_TCBGTIE_Pos   (24U)
#define	USART_CR3_TCBGTIE_Msk   (0x1UL << USART_CR3_TCBGTIE_Pos)
	0x01000000
#define	USART_CR3_TCBGTIE   USART_CR3_TCBGTIE_Msk
	Transmission Complete before guard time, interrupt enable.
#define	USART_CR3_RXFTCFG_Pos   (25U)
#define	USART_CR3_RXFTCFG_Msk   (0x7UL << USART_CR3_RXFTCFG_Pos)
	0x0E000000
#define	USART_CR3_RXFTCFG   USART_CR3_RXFTCFG_Msk
	RXFTCFG [2:0]Receive FIFO threshold configuration.
#define	USART_CR3_RXFTCFG_0   (0x1UL << USART_CR3_RXFTCFG_Pos)
	0x02000000
#define	USART_CR3_RXFTCFG_1   (0x2UL << USART_CR3_RXFTCFG_Pos)
	0x04000000
#define	USART_CR3_RXFTCFG_2   (0x4UL << USART_CR3_RXFTCFG_Pos)
	0x08000000
#define	USART_CR3_RXFTIE_Pos   (28U)
#define	USART_CR3_RXFTIE_Msk   (0x1UL << USART_CR3_RXFTIE_Pos)
	0x10000000
#define	USART_CR3_RXFTIE   USART_CR3_RXFTIE_Msk
	RXFIFO threshold interrupt enable.
#define	USART_CR3_TXFTCFG_Pos   (29U)
#define	USART_CR3_TXFTCFG_Msk   (0x7UL << USART_CR3_TXFTCFG_Pos)
	0xE0000000
#define	USART_CR3_TXFTCFG   USART_CR3_TXFTCFG_Msk
	TXFIFO [2:0] threshold configuration.
#define	USART_CR3_TXFTCFG_0   (0x1UL << USART_CR3_TXFTCFG_Pos)
	0x20000000
#define	USART_CR3_TXFTCFG_1   (0x2UL << USART_CR3_TXFTCFG_Pos)
	0x40000000
#define	USART_CR3_TXFTCFG_2   (0x4UL << USART_CR3_TXFTCFG_Pos)
	0x80000000
#define	USART_BRR_DIV_FRACTION_Pos   (0U)
#define	USART_BRR_DIV_FRACTION_Msk   (0xFUL << USART_BRR_DIV_FRACTION_Pos)
	0x0000000F
#define	USART_BRR_DIV_FRACTION   USART_BRR_DIV_FRACTION_Msk
	Fraction of USARTDIV.
#define	USART_BRR_DIV_MANTISSA_Pos   (4U)
#define	USART_BRR_DIV_MANTISSA_Msk   (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)
	0x0000FFF0
#define	USART_BRR_DIV_MANTISSA   USART_BRR_DIV_MANTISSA_Msk
	Mantissa of USARTDIV.
#define	USART_GTPR_PSC_Pos   (0U)
#define	USART_GTPR_PSC_Msk   (0xFFUL << USART_GTPR_PSC_Pos)
	0x000000FF
#define	USART_GTPR_PSC   USART_GTPR_PSC_Msk
	PSC[7:0] bits (Prescaler value).
#define	USART_GTPR_GT_Pos   (8U)
#define	USART_GTPR_GT_Msk   (0xFFUL << USART_GTPR_GT_Pos)
	0x0000FF00
#define	USART_GTPR_GT   USART_GTPR_GT_Msk
	GT[7:0] bits (Guard time value).
#define	USART_RTOR_RTO_Pos   (0U)
#define	USART_RTOR_RTO_Msk   (0xFFFFFFUL << USART_RTOR_RTO_Pos)
	0x00FFFFFF
#define	USART_RTOR_RTO   USART_RTOR_RTO_Msk
	Receiver Time Out Value.
#define	USART_RTOR_BLEN_Pos   (24U)
#define	USART_RTOR_BLEN_Msk   (0xFFUL << USART_RTOR_BLEN_Pos)
	0xFF000000
#define	USART_RTOR_BLEN   USART_RTOR_BLEN_Msk
	Block Length.
#define	USART_RQR_ABRRQ_Pos   (0U)
#define	USART_RQR_ABRRQ_Msk   (0x1UL << USART_RQR_ABRRQ_Pos)
	0x00000001
#define	USART_RQR_ABRRQ   USART_RQR_ABRRQ_Msk
	Auto-Baud Rate Request.
#define	USART_RQR_SBKRQ_Pos   (1U)
#define	USART_RQR_SBKRQ_Msk   (0x1UL << USART_RQR_SBKRQ_Pos)
	0x00000002
#define	USART_RQR_SBKRQ   USART_RQR_SBKRQ_Msk
	Send Break Request.
#define	USART_RQR_MMRQ_Pos   (2U)
#define	USART_RQR_MMRQ_Msk   (0x1UL << USART_RQR_MMRQ_Pos)
	0x00000004
#define	USART_RQR_MMRQ   USART_RQR_MMRQ_Msk
	Mute Mode Request.
#define	USART_RQR_RXFRQ_Pos   (3U)
#define	USART_RQR_RXFRQ_Msk   (0x1UL << USART_RQR_RXFRQ_Pos)
	0x00000008
#define	USART_RQR_RXFRQ   USART_RQR_RXFRQ_Msk
	Receive Data flush Request.
#define	USART_RQR_TXFRQ_Pos   (4U)
#define	USART_RQR_TXFRQ_Msk   (0x1UL << USART_RQR_TXFRQ_Pos)
	0x00000010
#define	USART_RQR_TXFRQ   USART_RQR_TXFRQ_Msk
	Transmit data flush Request.
#define	USART_ISR_PE_Pos   (0U)
#define	USART_ISR_PE_Msk   (0x1UL << USART_ISR_PE_Pos)
	0x00000001
#define	USART_ISR_PE   USART_ISR_PE_Msk
	Parity Error.
#define	USART_ISR_FE_Pos   (1U)
#define	USART_ISR_FE_Msk   (0x1UL << USART_ISR_FE_Pos)
	0x00000002
#define	USART_ISR_FE   USART_ISR_FE_Msk
	Framing Error.
#define	USART_ISR_NE_Pos   (2U)
#define	USART_ISR_NE_Msk   (0x1UL << USART_ISR_NE_Pos)
	0x00000004
#define	USART_ISR_NE   USART_ISR_NE_Msk
	Noise detected Flag.
#define	USART_ISR_ORE_Pos   (3U)
#define	USART_ISR_ORE_Msk   (0x1UL << USART_ISR_ORE_Pos)
	0x00000008
#define	USART_ISR_ORE   USART_ISR_ORE_Msk
	OverRun Error.
#define	USART_ISR_IDLE_Pos   (4U)
#define	USART_ISR_IDLE_Msk   (0x1UL << USART_ISR_IDLE_Pos)
	0x00000010
#define	USART_ISR_IDLE   USART_ISR_IDLE_Msk
	IDLE line detected.
#define	USART_ISR_RXNE_RXFNE_Pos   (5U)
#define	USART_ISR_RXNE_RXFNE_Msk   (0x1UL << USART_ISR_RXNE_RXFNE_Pos)
	0x00000020
#define	USART_ISR_RXNE_RXFNE   USART_ISR_RXNE_RXFNE_Msk
	Read Data Register or RX FIFO Not Empty.
#define	USART_ISR_TC_Pos   (6U)
#define	USART_ISR_TC_Msk   (0x1UL << USART_ISR_TC_Pos)
	0x00000040
#define	USART_ISR_TC   USART_ISR_TC_Msk
	Transmission Complete.
#define	USART_ISR_TXE_TXFNF_Pos   (7U)
#define	USART_ISR_TXE_TXFNF_Msk   (0x1UL << USART_ISR_TXE_TXFNF_Pos)
	0x00000080
#define	USART_ISR_TXE_TXFNF   USART_ISR_TXE_TXFNF_Msk
	Transmit Data Register Empty or TX FIFO Not Full Flag.
#define	USART_ISR_LBDF_Pos   (8U)
#define	USART_ISR_LBDF_Msk   (0x1UL << USART_ISR_LBDF_Pos)
	0x00000100
#define	USART_ISR_LBDF   USART_ISR_LBDF_Msk
	LIN Break Detection Flag.
#define	USART_ISR_CTSIF_Pos   (9U)
#define	USART_ISR_CTSIF_Msk   (0x1UL << USART_ISR_CTSIF_Pos)
	0x00000200
#define	USART_ISR_CTSIF   USART_ISR_CTSIF_Msk
	CTS interrupt flag.
#define	USART_ISR_CTS_Pos   (10U)
#define	USART_ISR_CTS_Msk   (0x1UL << USART_ISR_CTS_Pos)
	0x00000400
#define	USART_ISR_CTS   USART_ISR_CTS_Msk
	CTS flag.
#define	USART_ISR_RTOF_Pos   (11U)
#define	USART_ISR_RTOF_Msk   (0x1UL << USART_ISR_RTOF_Pos)
	0x00000800
#define	USART_ISR_RTOF   USART_ISR_RTOF_Msk
	Receiver Time Out.
#define	USART_ISR_EOBF_Pos   (12U)
#define	USART_ISR_EOBF_Msk   (0x1UL << USART_ISR_EOBF_Pos)
	0x00001000
#define	USART_ISR_EOBF   USART_ISR_EOBF_Msk
	End Of Block Flag.
#define	USART_ISR_UDR_Pos   (13U)
#define	USART_ISR_UDR_Msk   (0x1UL << USART_ISR_UDR_Pos)
	0x00002000
#define	USART_ISR_UDR   USART_ISR_UDR_Msk
	SPI slave underrun error flag.
#define	USART_ISR_ABRE_Pos   (14U)
#define	USART_ISR_ABRE_Msk   (0x1UL << USART_ISR_ABRE_Pos)
	0x00004000
#define	USART_ISR_ABRE   USART_ISR_ABRE_Msk
	Auto-Baud Rate Error.
#define	USART_ISR_ABRF_Pos   (15U)
#define	USART_ISR_ABRF_Msk   (0x1UL << USART_ISR_ABRF_Pos)
	0x00008000
#define	USART_ISR_ABRF   USART_ISR_ABRF_Msk
	Auto-Baud Rate Flag.
#define	USART_ISR_BUSY_Pos   (16U)
#define	USART_ISR_BUSY_Msk   (0x1UL << USART_ISR_BUSY_Pos)
	0x00010000
#define	USART_ISR_BUSY   USART_ISR_BUSY_Msk
	Busy Flag.
#define	USART_ISR_CMF_Pos   (17U)
#define	USART_ISR_CMF_Msk   (0x1UL << USART_ISR_CMF_Pos)
	0x00020000
#define	USART_ISR_CMF   USART_ISR_CMF_Msk
	Character Match Flag.
#define	USART_ISR_SBKF_Pos   (18U)
#define	USART_ISR_SBKF_Msk   (0x1UL << USART_ISR_SBKF_Pos)
	0x00040000
#define	USART_ISR_SBKF   USART_ISR_SBKF_Msk
	Send Break Flag.
#define	USART_ISR_RWU_Pos   (19U)
#define	USART_ISR_RWU_Msk   (0x1UL << USART_ISR_RWU_Pos)
	0x00080000
#define	USART_ISR_RWU   USART_ISR_RWU_Msk
	Receive Wake Up from mute mode Flag.
#define	USART_ISR_WUF_Pos   (20U)
#define	USART_ISR_WUF_Msk   (0x1UL << USART_ISR_WUF_Pos)
	0x00100000
#define	USART_ISR_WUF   USART_ISR_WUF_Msk
	Wake Up from stop mode Flag.
#define	USART_ISR_TEACK_Pos   (21U)
#define	USART_ISR_TEACK_Msk   (0x1UL << USART_ISR_TEACK_Pos)
	0x00200000
#define	USART_ISR_TEACK   USART_ISR_TEACK_Msk
	Transmit Enable Acknowledge Flag.
#define	USART_ISR_REACK_Pos   (22U)
#define	USART_ISR_REACK_Msk   (0x1UL << USART_ISR_REACK_Pos)
	0x00400000
#define	USART_ISR_REACK   USART_ISR_REACK_Msk
	Receive Enable Acknowledge Flag.
#define	USART_ISR_TXFE_Pos   (23U)
#define	USART_ISR_TXFE_Msk   (0x1UL << USART_ISR_TXFE_Pos)
	0x00800000
#define	USART_ISR_TXFE   USART_ISR_TXFE_Msk
	TXFIFO Empty.
#define	USART_ISR_RXFF_Pos   (24U)
#define	USART_ISR_RXFF_Msk   (0x1UL << USART_ISR_RXFF_Pos)
	0x01000000
#define	USART_ISR_RXFF   USART_ISR_RXFF_Msk
	RXFIFO Full Flag.
#define	USART_ISR_TCBGT_Pos   (25U)
#define	USART_ISR_TCBGT_Msk   (0x1UL << USART_ISR_TCBGT_Pos)
	0x02000000
#define	USART_ISR_TCBGT   USART_ISR_TCBGT_Msk
	Transmission complete before guard time Flag.
#define	USART_ISR_RXFT_Pos   (26U)
#define	USART_ISR_RXFT_Msk   (0x1UL << USART_ISR_RXFT_Pos)
	0x04000000
#define	USART_ISR_RXFT   USART_ISR_RXFT_Msk
	RXFIFO threshold Flag.
#define	USART_ISR_TXFT_Pos   (27U)
#define	USART_ISR_TXFT_Msk   (0x1UL << USART_ISR_TXFT_Pos)
	0x08000000
#define	USART_ISR_TXFT   USART_ISR_TXFT_Msk
	TXFIFO threshold Flag.
#define	USART_ICR_PECF_Pos   (0U)
#define	USART_ICR_PECF_Msk   (0x1UL << USART_ICR_PECF_Pos)
	0x00000001
#define	USART_ICR_PECF   USART_ICR_PECF_Msk
	Parity Error Clear Flag.
#define	USART_ICR_FECF_Pos   (1U)
#define	USART_ICR_FECF_Msk   (0x1UL << USART_ICR_FECF_Pos)
	0x00000002
#define	USART_ICR_FECF   USART_ICR_FECF_Msk
	Framing Error Clear Flag.
#define	USART_ICR_NECF_Pos   (2U)
#define	USART_ICR_NECF_Msk   (0x1UL << USART_ICR_NECF_Pos)
	0x00000004
#define	USART_ICR_NECF   USART_ICR_NECF_Msk
	Noise detected Clear Flag.
#define	USART_ICR_ORECF_Pos   (3U)
#define	USART_ICR_ORECF_Msk   (0x1UL << USART_ICR_ORECF_Pos)
	0x00000008
#define	USART_ICR_ORECF   USART_ICR_ORECF_Msk
	OverRun Error Clear Flag.
#define	USART_ICR_IDLECF_Pos   (4U)
#define	USART_ICR_IDLECF_Msk   (0x1UL << USART_ICR_IDLECF_Pos)
	0x00000010
#define	USART_ICR_IDLECF   USART_ICR_IDLECF_Msk
	IDLE line detected Clear Flag.
#define	USART_ICR_TXFECF_Pos   (5U)
#define	USART_ICR_TXFECF_Msk   (0x1UL << USART_ICR_TXFECF_Pos)
	0x00000020
#define	USART_ICR_TXFECF   USART_ICR_TXFECF_Msk
	TXFIFO empty clear flag.
#define	USART_ICR_TCCF_Pos   (6U)
#define	USART_ICR_TCCF_Msk   (0x1UL << USART_ICR_TCCF_Pos)
	0x00000040
#define	USART_ICR_TCCF   USART_ICR_TCCF_Msk
	Transmission Complete Clear Flag.
#define	USART_ICR_TCBGTCF_Pos   (7U)
#define	USART_ICR_TCBGTCF_Msk   (0x1UL << USART_ICR_TCBGTCF_Pos)
	0x00000080
#define	USART_ICR_TCBGTCF   USART_ICR_TCBGTCF_Msk
	Transmission complete before guard time Clear Flag.
#define	USART_ICR_LBDCF_Pos   (8U)
#define	USART_ICR_LBDCF_Msk   (0x1UL << USART_ICR_LBDCF_Pos)
	0x00000100
#define	USART_ICR_LBDCF   USART_ICR_LBDCF_Msk
	LIN Break Detection Clear Flag.
#define	USART_ICR_CTSCF_Pos   (9U)
#define	USART_ICR_CTSCF_Msk   (0x1UL << USART_ICR_CTSCF_Pos)
	0x00000200
#define	USART_ICR_CTSCF   USART_ICR_CTSCF_Msk
	CTS Interrupt Clear Flag.
#define	USART_ICR_RTOCF_Pos   (11U)
#define	USART_ICR_RTOCF_Msk   (0x1UL << USART_ICR_RTOCF_Pos)
	0x00000800
#define	USART_ICR_RTOCF   USART_ICR_RTOCF_Msk
	Receiver Time Out Clear Flag.
#define	USART_ICR_EOBCF_Pos   (12U)
#define	USART_ICR_EOBCF_Msk   (0x1UL << USART_ICR_EOBCF_Pos)
	0x00001000
#define	USART_ICR_EOBCF   USART_ICR_EOBCF_Msk
	End Of Block Clear Flag.
#define	USART_ICR_UDRCF_Pos   (13U)
#define	USART_ICR_UDRCF_Msk   (0x1UL << USART_ICR_UDRCF_Pos)
	0x00002000
#define	USART_ICR_UDRCF   USART_ICR_UDRCF_Msk
	SPI slave underrun clear flag.
#define	USART_ICR_CMCF_Pos   (17U)
#define	USART_ICR_CMCF_Msk   (0x1UL << USART_ICR_CMCF_Pos)
	0x00020000
#define	USART_ICR_CMCF   USART_ICR_CMCF_Msk
	Character Match Clear Flag.
#define	USART_ICR_WUCF_Pos   (20U)
#define	USART_ICR_WUCF_Msk   (0x1UL << USART_ICR_WUCF_Pos)
	0x00100000
#define	USART_ICR_WUCF   USART_ICR_WUCF_Msk
	Wake Up from stop mode Clear Flag.
#define	USART_RDR_RDR_Pos   (0U)
#define	USART_RDR_RDR_Msk   (0x1FFUL << USART_RDR_RDR_Pos)
	0x000001FF
#define	USART_RDR_RDR   USART_RDR_RDR_Msk
	RDR[8:0] bits (Receive Data value).
#define	USART_TDR_TDR_Pos   (0U)
#define	USART_TDR_TDR_Msk   (0x1FFUL << USART_TDR_TDR_Pos)
	0x000001FF
#define	USART_TDR_TDR   USART_TDR_TDR_Msk
	TDR[8:0] bits (Transmit Data value).
#define	USART_PRESC_PRESCALER_Pos   (0U)
#define	USART_PRESC_PRESCALER_Msk   (0xFUL << USART_PRESC_PRESCALER_Pos)
	0x0000000F
#define	USART_PRESC_PRESCALER   USART_PRESC_PRESCALER_Msk
	PRESCALER[3:0] bits (Clock prescaler).
#define	USART_PRESC_PRESCALER_0   (0x1UL << USART_PRESC_PRESCALER_Pos)
	0x00000001
#define	USART_PRESC_PRESCALER_1   (0x2UL << USART_PRESC_PRESCALER_Pos)
	0x00000002
#define	USART_PRESC_PRESCALER_2   (0x4UL << USART_PRESC_PRESCALER_Pos)
	0x00000004
#define	USART_PRESC_PRESCALER_3   (0x8UL << USART_PRESC_PRESCALER_Pos)
	0x00000008
#define	SWPMI_CR_RXDMA_Pos   (0U)
#define	SWPMI_CR_RXDMA_Msk   (0x1UL << SWPMI_CR_RXDMA_Pos)
	0x00000001
#define	SWPMI_CR_RXDMA   SWPMI_CR_RXDMA_Msk
	Reception DMA enable.
#define	SWPMI_CR_TXDMA_Pos   (1U)
#define	SWPMI_CR_TXDMA_Msk   (0x1UL << SWPMI_CR_TXDMA_Pos)
	0x00000002
#define	SWPMI_CR_TXDMA   SWPMI_CR_TXDMA_Msk
	Transmission DMA enable.
#define	SWPMI_CR_RXMODE_Pos   (2U)
#define	SWPMI_CR_RXMODE_Msk   (0x1UL << SWPMI_CR_RXMODE_Pos)
	0x00000004
#define	SWPMI_CR_RXMODE   SWPMI_CR_RXMODE_Msk
	Reception buffering mode.
#define	SWPMI_CR_TXMODE_Pos   (3U)
#define	SWPMI_CR_TXMODE_Msk   (0x1UL << SWPMI_CR_TXMODE_Pos)
	0x00000008
#define	SWPMI_CR_TXMODE   SWPMI_CR_TXMODE_Msk
	Transmission buffering mode.
#define	SWPMI_CR_LPBK_Pos   (4U)
#define	SWPMI_CR_LPBK_Msk   (0x1UL << SWPMI_CR_LPBK_Pos)
	0x00000010
#define	SWPMI_CR_LPBK   SWPMI_CR_LPBK_Msk
	Loopback mode enable.
#define	SWPMI_CR_SWPACT_Pos   (5U)
#define	SWPMI_CR_SWPACT_Msk   (0x1UL << SWPMI_CR_SWPACT_Pos)
	0x00000020
#define	SWPMI_CR_SWPACT   SWPMI_CR_SWPACT_Msk
	Single wire protocol master interface activate.
#define	SWPMI_CR_DEACT_Pos   (10U)
#define	SWPMI_CR_DEACT_Msk   (0x1UL << SWPMI_CR_DEACT_Pos)
	0x00000400
#define	SWPMI_CR_DEACT   SWPMI_CR_DEACT_Msk
	Single wire protocol master interface deactivate.
#define	SWPMI_CR_SWPEN_Pos   (11U)
#define	SWPMI_CR_SWPEN_Msk   (0x1UL << SWPMI_CR_SWPEN_Pos)
	0x00000800
#define	SWPMI_CR_SWPEN   SWPMI_CR_SWPEN_Msk
	Single wire protocol master transceiver enable.
#define	SWPMI_BRR_BR_Pos   (0U)
#define	SWPMI_BRR_BR_Msk   (0xFFUL << SWPMI_BRR_BR_Pos)
	0x000000FF
#define	SWPMI_BRR_BR   SWPMI_BRR_BR_Msk
	BR[7:0] bits (Bitrate prescaler).
#define	SWPMI_ISR_RXBFF_Pos   (0U)
#define	SWPMI_ISR_RXBFF_Msk   (0x1UL << SWPMI_ISR_RXBFF_Pos)
	0x00000001
#define	SWPMI_ISR_RXBFF   SWPMI_ISR_RXBFF_Msk
	Receive buffer full flag.
#define	SWPMI_ISR_TXBEF_Pos   (1U)
#define	SWPMI_ISR_TXBEF_Msk   (0x1UL << SWPMI_ISR_TXBEF_Pos)
	0x00000002
#define	SWPMI_ISR_TXBEF   SWPMI_ISR_TXBEF_Msk
	Transmit buffer empty flag.
#define	SWPMI_ISR_RXBERF_Pos   (2U)
#define	SWPMI_ISR_RXBERF_Msk   (0x1UL << SWPMI_ISR_RXBERF_Pos)
	0x00000004
#define	SWPMI_ISR_RXBERF   SWPMI_ISR_RXBERF_Msk
	Receive CRC error flag.
#define	SWPMI_ISR_RXOVRF_Pos   (3U)
#define	SWPMI_ISR_RXOVRF_Msk   (0x1UL << SWPMI_ISR_RXOVRF_Pos)
	0x00000008
#define	SWPMI_ISR_RXOVRF   SWPMI_ISR_RXOVRF_Msk
	Receive overrun error flag.
#define	SWPMI_ISR_TXUNRF_Pos   (4U)
#define	SWPMI_ISR_TXUNRF_Msk   (0x1UL << SWPMI_ISR_TXUNRF_Pos)
	0x00000010
#define	SWPMI_ISR_TXUNRF   SWPMI_ISR_TXUNRF_Msk
	Transmit underrun error flag.
#define	SWPMI_ISR_RXNE_Pos   (5U)
#define	SWPMI_ISR_RXNE_Msk   (0x1UL << SWPMI_ISR_RXNE_Pos)
	0x00000020
#define	SWPMI_ISR_RXNE   SWPMI_ISR_RXNE_Msk
	Receive data register not empty.
#define	SWPMI_ISR_TXE_Pos   (6U)
#define	SWPMI_ISR_TXE_Msk   (0x1UL << SWPMI_ISR_TXE_Pos)
	0x00000040
#define	SWPMI_ISR_TXE   SWPMI_ISR_TXE_Msk
	Transmit data register empty.
#define	SWPMI_ISR_TCF_Pos   (7U)
#define	SWPMI_ISR_TCF_Msk   (0x1UL << SWPMI_ISR_TCF_Pos)
	0x00000080
#define	SWPMI_ISR_TCF   SWPMI_ISR_TCF_Msk
	Transfer complete flag.
#define	SWPMI_ISR_SRF_Pos   (8U)
#define	SWPMI_ISR_SRF_Msk   (0x1UL << SWPMI_ISR_SRF_Pos)
	0x00000100
#define	SWPMI_ISR_SRF   SWPMI_ISR_SRF_Msk
	Slave resume flag.
#define	SWPMI_ISR_SUSP_Pos   (9U)
#define	SWPMI_ISR_SUSP_Msk   (0x1UL << SWPMI_ISR_SUSP_Pos)
	0x00000200
#define	SWPMI_ISR_SUSP   SWPMI_ISR_SUSP_Msk
	SUSPEND flag.
#define	SWPMI_ISR_DEACTF_Pos   (10U)
#define	SWPMI_ISR_DEACTF_Msk   (0x1UL << SWPMI_ISR_DEACTF_Pos)
	0x00000400
#define	SWPMI_ISR_DEACTF   SWPMI_ISR_DEACTF_Msk
	DEACTIVATED flag.
#define	SWPMI_ISR_RDYF_Pos   (11U)
#define	SWPMI_ISR_RDYF_Msk   (0x1UL << SWPMI_ISR_RDYF_Pos)
	0x00000800
#define	SWPMI_ISR_RDYF   SWPMI_ISR_RDYF_Msk
	Transceiver ready flag.
#define	SWPMI_ICR_CRXBFF_Pos   (0U)
#define	SWPMI_ICR_CRXBFF_Msk   (0x1UL << SWPMI_ICR_CRXBFF_Pos)
	0x00000001
#define	SWPMI_ICR_CRXBFF   SWPMI_ICR_CRXBFF_Msk
	Clear receive buffer full flag.
#define	SWPMI_ICR_CTXBEF_Pos   (1U)
#define	SWPMI_ICR_CTXBEF_Msk   (0x1UL << SWPMI_ICR_CTXBEF_Pos)
	0x00000002
#define	SWPMI_ICR_CTXBEF   SWPMI_ICR_CTXBEF_Msk
	Clear transmit buffer empty flag.
#define	SWPMI_ICR_CRXBERF_Pos   (2U)
#define	SWPMI_ICR_CRXBERF_Msk   (0x1UL << SWPMI_ICR_CRXBERF_Pos)
	0x00000004
#define	SWPMI_ICR_CRXBERF   SWPMI_ICR_CRXBERF_Msk
	Clear receive CRC error flag.
#define	SWPMI_ICR_CRXOVRF_Pos   (3U)
#define	SWPMI_ICR_CRXOVRF_Msk   (0x1UL << SWPMI_ICR_CRXOVRF_Pos)
	0x00000008
#define	SWPMI_ICR_CRXOVRF   SWPMI_ICR_CRXOVRF_Msk
	Clear receive overrun error flag.
#define	SWPMI_ICR_CTXUNRF_Pos   (4U)
#define	SWPMI_ICR_CTXUNRF_Msk   (0x1UL << SWPMI_ICR_CTXUNRF_Pos)
	0x00000010
#define	SWPMI_ICR_CTXUNRF   SWPMI_ICR_CTXUNRF_Msk
	Clear transmit underrun error flag.
#define	SWPMI_ICR_CTCF_Pos   (7U)
#define	SWPMI_ICR_CTCF_Msk   (0x1UL << SWPMI_ICR_CTCF_Pos)
	0x00000080
#define	SWPMI_ICR_CTCF   SWPMI_ICR_CTCF_Msk
	Clear transfer complete flag.
#define	SWPMI_ICR_CSRF_Pos   (8U)
#define	SWPMI_ICR_CSRF_Msk   (0x1UL << SWPMI_ICR_CSRF_Pos)
	0x00000100
#define	SWPMI_ICR_CSRF   SWPMI_ICR_CSRF_Msk
	Clear slave resume flag.
#define	SWPMI_ICR_CRDYF_Pos   (11U)
#define	SWPMI_ICR_CRDYF_Msk   (0x1UL << SWPMI_ICR_CRDYF_Pos)
	0x00000800
#define	SWPMI_ICR_CRDYF   SWPMI_ICR_CRDYF_Msk
	Clear transceiver ready flag.
#define	SWPMI_IER_RXBFIE_Pos   (0U)
#define	SWPMI_IER_RXBFIE_Msk   (0x1UL << SWPMI_IER_RXBFIE_Pos)
	0x00000001
#define	SWPMI_IER_RXBFIE   SWPMI_IER_RXBFIE_Msk
	Receive buffer full interrupt enable.
#define	SWPMI_IER_TXBEIE_Pos   (1U)
#define	SWPMI_IER_TXBEIE_Msk   (0x1UL << SWPMI_IER_TXBEIE_Pos)
	0x00000002
#define	SWPMI_IER_TXBEIE   SWPMI_IER_TXBEIE_Msk
	Transmit buffer empty interrupt enable.
#define	SWPMI_IER_RXBERIE_Pos   (2U)
#define	SWPMI_IER_RXBERIE_Msk   (0x1UL << SWPMI_IER_RXBERIE_Pos)
	0x00000004
#define	SWPMI_IER_RXBERIE   SWPMI_IER_RXBERIE_Msk
	Receive CRC error interrupt enable.
#define	SWPMI_IER_RXOVRIE_Pos   (3U)
#define	SWPMI_IER_RXOVRIE_Msk   (0x1UL << SWPMI_IER_RXOVRIE_Pos)
	0x00000008
#define	SWPMI_IER_RXOVRIE   SWPMI_IER_RXOVRIE_Msk
	Receive overrun error interrupt enable.
#define	SWPMI_IER_TXUNRIE_Pos   (4U)
#define	SWPMI_IER_TXUNRIE_Msk   (0x1UL << SWPMI_IER_TXUNRIE_Pos)
	0x00000010
#define	SWPMI_IER_TXUNRIE   SWPMI_IER_TXUNRIE_Msk
	Transmit underrun error interrupt enable.
#define	SWPMI_IER_RIE_Pos   (5U)
#define	SWPMI_IER_RIE_Msk   (0x1UL << SWPMI_IER_RIE_Pos)
	0x00000020
#define	SWPMI_IER_RIE   SWPMI_IER_RIE_Msk
	Receive interrupt enable.
#define	SWPMI_IER_TIE_Pos   (6U)
#define	SWPMI_IER_TIE_Msk   (0x1UL << SWPMI_IER_TIE_Pos)
	0x00000040
#define	SWPMI_IER_TIE   SWPMI_IER_TIE_Msk
	Transmit interrupt enable.
#define	SWPMI_IER_TCIE_Pos   (7U)
#define	SWPMI_IER_TCIE_Msk   (0x1UL << SWPMI_IER_TCIE_Pos)
	0x00000080
#define	SWPMI_IER_TCIE   SWPMI_IER_TCIE_Msk
	Transmit complete interrupt enable.
#define	SWPMI_IER_SRIE_Pos   (8U)
#define	SWPMI_IER_SRIE_Msk   (0x1UL << SWPMI_IER_SRIE_Pos)
	0x00000100
#define	SWPMI_IER_SRIE   SWPMI_IER_SRIE_Msk
	Slave resume interrupt enable.
#define	SWPMI_IER_RDYIE_Pos   (11U)
#define	SWPMI_IER_RDYIE_Msk   (0x1UL << SWPMI_IER_RDYIE_Pos)
	0x00000800
#define	SWPMI_IER_RDYIE   SWPMI_IER_RDYIE_Msk
	Transceiver ready interrupt enable.
#define	SWPMI_RFL_RFL_Pos   (0U)
#define	SWPMI_RFL_RFL_Msk   (0x1FUL << SWPMI_RFL_RFL_Pos)
	0x0000001F
#define	SWPMI_RFL_RFL   SWPMI_RFL_RFL_Msk
	RFL[4:0] bits (Receive Frame length).
#define	SWPMI_RFL_RFL_0_1   (0x00000003U)
	RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.).
#define	SWPMI_TDR_TD_Pos   (0U)
#define	SWPMI_TDR_TD_Msk   (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)
	0xFFFFFFFF
#define	SWPMI_TDR_TD   SWPMI_TDR_TD_Msk
	Transmit Data Register.
#define	SWPMI_RDR_RD_Pos   (0U)
#define	SWPMI_RDR_RD_Msk   (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)
	0xFFFFFFFF
#define	SWPMI_RDR_RD   SWPMI_RDR_RD_Msk
	Receive Data Register.
#define	SWPMI_OR_TBYP_Pos   (0U)
#define	SWPMI_OR_TBYP_Msk   (0x1UL << SWPMI_OR_TBYP_Pos)
	0x00000001
#define	SWPMI_OR_TBYP   SWPMI_OR_TBYP_Msk
	SWP Transceiver Bypass.
#define	SWPMI_OR_CLASS_Pos   (1U)
#define	SWPMI_OR_CLASS_Msk   (0x1UL << SWPMI_OR_CLASS_Pos)
	0x00000002
#define	SWPMI_OR_CLASS   SWPMI_OR_CLASS_Msk
	SWP CLASS selection.
#define	WWDG_CR_T_Pos   (0U)
#define	WWDG_CR_T_Msk   (0x7FUL << WWDG_CR_T_Pos)
	0x0000007F
#define	WWDG_CR_T   WWDG_CR_T_Msk
	T[6:0] bits (7-Bit counter (MSB to LSB)).
#define	WWDG_CR_T_0   (0x01UL << WWDG_CR_T_Pos)
	0x00000001
#define	WWDG_CR_T_1   (0x02UL << WWDG_CR_T_Pos)
	0x00000002
#define	WWDG_CR_T_2   (0x04UL << WWDG_CR_T_Pos)
	0x00000004
#define	WWDG_CR_T_3   (0x08UL << WWDG_CR_T_Pos)
	0x00000008
#define	WWDG_CR_T_4   (0x10UL << WWDG_CR_T_Pos)
	0x00000010
#define	WWDG_CR_T_5   (0x20UL << WWDG_CR_T_Pos)
	0x00000020
#define	WWDG_CR_T_6   (0x40UL << WWDG_CR_T_Pos)
	0x00000040
#define	WWDG_CR_WDGA_Pos   (7U)
#define	WWDG_CR_WDGA_Msk   (0x1UL << WWDG_CR_WDGA_Pos)
	0x00000080
#define	WWDG_CR_WDGA   WWDG_CR_WDGA_Msk
	Activation bit.
#define	WWDG_CFR_W_Pos   (0U)
#define	WWDG_CFR_W_Msk   (0x7FUL << WWDG_CFR_W_Pos)
	0x0000007F
#define	WWDG_CFR_W   WWDG_CFR_W_Msk
	W[6:0] bits (7-bit window value).
#define	WWDG_CFR_W_0   (0x01UL << WWDG_CFR_W_Pos)
	0x00000001
#define	WWDG_CFR_W_1   (0x02UL << WWDG_CFR_W_Pos)
	0x00000002
#define	WWDG_CFR_W_2   (0x04UL << WWDG_CFR_W_Pos)
	0x00000004
#define	WWDG_CFR_W_3   (0x08UL << WWDG_CFR_W_Pos)
	0x00000008
#define	WWDG_CFR_W_4   (0x10UL << WWDG_CFR_W_Pos)
	0x00000010
#define	WWDG_CFR_W_5   (0x20UL << WWDG_CFR_W_Pos)
	0x00000020
#define	WWDG_CFR_W_6   (0x40UL << WWDG_CFR_W_Pos)
	0x00000040
#define	WWDG_CFR_EWI_Pos   (9U)
#define	WWDG_CFR_EWI_Msk   (0x1UL << WWDG_CFR_EWI_Pos)
	0x00000200
#define	WWDG_CFR_EWI   WWDG_CFR_EWI_Msk
	Early Wakeup Interrupt.
#define	WWDG_CFR_WDGTB_Pos   (11U)
#define	WWDG_CFR_WDGTB_Msk   (0x7UL << WWDG_CFR_WDGTB_Pos)
	0x00003800
#define	WWDG_CFR_WDGTB   WWDG_CFR_WDGTB_Msk
	WDGTB[2:0] bits (Timer Base).
#define	WWDG_CFR_WDGTB_0   (0x1UL << WWDG_CFR_WDGTB_Pos)
	0x00000800
#define	WWDG_CFR_WDGTB_1   (0x2UL << WWDG_CFR_WDGTB_Pos)
	0x00001000
#define	WWDG_CFR_WDGTB_2   (0x4UL << WWDG_CFR_WDGTB_Pos)
	0x00002000
#define	WWDG_SR_EWIF_Pos   (0U)
#define	WWDG_SR_EWIF_Msk   (0x1UL << WWDG_SR_EWIF_Pos)
	0x00000001
#define	WWDG_SR_EWIF   WWDG_SR_EWIF_Msk
	Early Wakeup Interrupt Flag.
#define	STM32H7_DEV_ID   0x483UL
#define	DBGMCU_IDCODE_DEV_ID_Pos   (0U)
#define	DBGMCU_IDCODE_DEV_ID_Msk   (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
	0x00000FFF
#define	DBGMCU_IDCODE_DEV_ID   DBGMCU_IDCODE_DEV_ID_Msk
#define	DBGMCU_IDCODE_REV_ID_Pos   (16U)
#define	DBGMCU_IDCODE_REV_ID_Msk   (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
	0xFFFF0000
#define	DBGMCU_IDCODE_REV_ID   DBGMCU_IDCODE_REV_ID_Msk
#define	DBGMCU_CR_DBG_SLEEPD1_Pos   (0U)
#define	DBGMCU_CR_DBG_SLEEPD1_Msk   (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos)
	0x00000001
#define	DBGMCU_CR_DBG_SLEEPD1   DBGMCU_CR_DBG_SLEEPD1_Msk
#define	DBGMCU_CR_DBG_STOPD1_Pos   (1U)
#define	DBGMCU_CR_DBG_STOPD1_Msk   (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos)
	0x00000002
#define	DBGMCU_CR_DBG_STOPD1   DBGMCU_CR_DBG_STOPD1_Msk
#define	DBGMCU_CR_DBG_STANDBYD1_Pos   (2U)
#define	DBGMCU_CR_DBG_STANDBYD1_Msk   (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos)
	0x00000004
#define	DBGMCU_CR_DBG_STANDBYD1   DBGMCU_CR_DBG_STANDBYD1_Msk
#define	DBGMCU_CR_DBG_STOPD3_Pos   (7U)
#define	DBGMCU_CR_DBG_STOPD3_Msk   (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos)
	0x00000080
#define	DBGMCU_CR_DBG_STOPD3   DBGMCU_CR_DBG_STOPD3_Msk
#define	DBGMCU_CR_DBG_STANDBYD3_Pos   (8U)
#define	DBGMCU_CR_DBG_STANDBYD3_Msk   (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos)
	0x00000100
#define	DBGMCU_CR_DBG_STANDBYD3   DBGMCU_CR_DBG_STANDBYD3_Msk
#define	DBGMCU_CR_DBG_TRACECKEN_Pos   (20U)
#define	DBGMCU_CR_DBG_TRACECKEN_Msk   (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos)
	0x00100000
#define	DBGMCU_CR_DBG_TRACECKEN   DBGMCU_CR_DBG_TRACECKEN_Msk
#define	DBGMCU_CR_DBG_CKD1EN_Pos   (21U)
#define	DBGMCU_CR_DBG_CKD1EN_Msk   (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos)
	0x00200000
#define	DBGMCU_CR_DBG_CKD1EN   DBGMCU_CR_DBG_CKD1EN_Msk
#define	DBGMCU_CR_DBG_CKD3EN_Pos   (22U)
#define	DBGMCU_CR_DBG_CKD3EN_Msk   (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos)
	0x00400000
#define	DBGMCU_CR_DBG_CKD3EN   DBGMCU_CR_DBG_CKD3EN_Msk
#define	DBGMCU_CR_DBG_TRGOEN_Pos   (28U)
#define	DBGMCU_CR_DBG_TRGOEN_Msk   (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)
	0x10000000
#define	DBGMCU_CR_DBG_TRGOEN   DBGMCU_CR_DBG_TRGOEN_Msk
#define	DBGMCU_APB3FZ1_DBG_WWDG1_Pos   (6U)
#define	DBGMCU_APB3FZ1_DBG_WWDG1_Msk   (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos)
	0x00000040
#define	DBGMCU_APB3FZ1_DBG_WWDG1   DBGMCU_APB3FZ1_DBG_WWDG1_Msk
#define	DBGMCU_APB1LFZ1_DBG_TIM2_Pos   (0U)
#define	DBGMCU_APB1LFZ1_DBG_TIM2_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos)
	0x00000001
#define	DBGMCU_APB1LFZ1_DBG_TIM2   DBGMCU_APB1LFZ1_DBG_TIM2_Msk
#define	DBGMCU_APB1LFZ1_DBG_TIM3_Pos   (1U)
#define	DBGMCU_APB1LFZ1_DBG_TIM3_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos)
	0x00000002
#define	DBGMCU_APB1LFZ1_DBG_TIM3   DBGMCU_APB1LFZ1_DBG_TIM3_Msk
#define	DBGMCU_APB1LFZ1_DBG_TIM4_Pos   (2U)
#define	DBGMCU_APB1LFZ1_DBG_TIM4_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos)
	0x00000004
#define	DBGMCU_APB1LFZ1_DBG_TIM4   DBGMCU_APB1LFZ1_DBG_TIM4_Msk
#define	DBGMCU_APB1LFZ1_DBG_TIM5_Pos   (3U)
#define	DBGMCU_APB1LFZ1_DBG_TIM5_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos)
	0x00000008
#define	DBGMCU_APB1LFZ1_DBG_TIM5   DBGMCU_APB1LFZ1_DBG_TIM5_Msk
#define	DBGMCU_APB1LFZ1_DBG_TIM6_Pos   (4U)
#define	DBGMCU_APB1LFZ1_DBG_TIM6_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos)
	0x00000010
#define	DBGMCU_APB1LFZ1_DBG_TIM6   DBGMCU_APB1LFZ1_DBG_TIM6_Msk
#define	DBGMCU_APB1LFZ1_DBG_TIM7_Pos   (5U)
#define	DBGMCU_APB1LFZ1_DBG_TIM7_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos)
	0x00000020
#define	DBGMCU_APB1LFZ1_DBG_TIM7   DBGMCU_APB1LFZ1_DBG_TIM7_Msk
#define	DBGMCU_APB1LFZ1_DBG_TIM12_Pos   (6U)
#define	DBGMCU_APB1LFZ1_DBG_TIM12_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos)
	0x00000040
#define	DBGMCU_APB1LFZ1_DBG_TIM12   DBGMCU_APB1LFZ1_DBG_TIM12_Msk
#define	DBGMCU_APB1LFZ1_DBG_TIM13_Pos   (7U)
#define	DBGMCU_APB1LFZ1_DBG_TIM13_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos)
	0x00000080
#define	DBGMCU_APB1LFZ1_DBG_TIM13   DBGMCU_APB1LFZ1_DBG_TIM13_Msk
#define	DBGMCU_APB1LFZ1_DBG_TIM14_Pos   (8U)
#define	DBGMCU_APB1LFZ1_DBG_TIM14_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos)
	0x00000100
#define	DBGMCU_APB1LFZ1_DBG_TIM14   DBGMCU_APB1LFZ1_DBG_TIM14_Msk
#define	DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos   (9U)
#define	DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos)
	0x00000200
#define	DBGMCU_APB1LFZ1_DBG_LPTIM1   DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk
#define	DBGMCU_APB1LFZ1_DBG_I2C1_Pos   (21U)
#define	DBGMCU_APB1LFZ1_DBG_I2C1_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos)
	0x00200000
#define	DBGMCU_APB1LFZ1_DBG_I2C1   DBGMCU_APB1LFZ1_DBG_I2C1_Msk
#define	DBGMCU_APB1LFZ1_DBG_I2C2_Pos   (22U)
#define	DBGMCU_APB1LFZ1_DBG_I2C2_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos)
	0x00400000
#define	DBGMCU_APB1LFZ1_DBG_I2C2   DBGMCU_APB1LFZ1_DBG_I2C2_Msk
#define	DBGMCU_APB1LFZ1_DBG_I2C3_Pos   (23U)
#define	DBGMCU_APB1LFZ1_DBG_I2C3_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos)
	0x00800000
#define	DBGMCU_APB1LFZ1_DBG_I2C3   DBGMCU_APB1LFZ1_DBG_I2C3_Msk
#define	DBGMCU_APB1LFZ1_DBG_I2C5_Pos   (25U)
#define	DBGMCU_APB1LFZ1_DBG_I2C5_Msk   (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C5_Pos)
	0x02000000
#define	DBGMCU_APB1LFZ1_DBG_I2C5   DBGMCU_APB1LFZ1_DBG_I2C5_Msk
#define	DBGMCU_APB1HFZ1_DBG_TIM23_Pos   (24U)
#define	DBGMCU_APB1HFZ1_DBG_TIM23_Msk   (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos)
	0x01000000
#define	DBGMCU_APB1HFZ1_DBG_TIM23   DBGMCU_APB1HFZ1_DBG_TIM23_Msk
#define	DBGMCU_APB1HFZ1_DBG_TIM24_Pos   (25U)
#define	DBGMCU_APB1HFZ1_DBG_TIM24_Msk   (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos)
	0x02000000
#define	DBGMCU_APB1HFZ1_DBG_TIM24   DBGMCU_APB1HFZ1_DBG_TIM24_Msk
#define	DBGMCU_APB2FZ1_DBG_TIM1_Pos   (0U)
#define	DBGMCU_APB2FZ1_DBG_TIM1_Msk   (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos)
	0x00000001
#define	DBGMCU_APB2FZ1_DBG_TIM1   DBGMCU_APB2FZ1_DBG_TIM1_Msk
#define	DBGMCU_APB2FZ1_DBG_TIM8_Pos   (1U)
#define	DBGMCU_APB2FZ1_DBG_TIM8_Msk   (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos)
	0x00000002
#define	DBGMCU_APB2FZ1_DBG_TIM8   DBGMCU_APB2FZ1_DBG_TIM8_Msk
#define	DBGMCU_APB2FZ1_DBG_TIM15_Pos   (16U)
#define	DBGMCU_APB2FZ1_DBG_TIM15_Msk   (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos)
	0x00010000
#define	DBGMCU_APB2FZ1_DBG_TIM15   DBGMCU_APB2FZ1_DBG_TIM15_Msk
#define	DBGMCU_APB2FZ1_DBG_TIM16_Pos   (17U)
#define	DBGMCU_APB2FZ1_DBG_TIM16_Msk   (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos)
	0x00020000
#define	DBGMCU_APB2FZ1_DBG_TIM16   DBGMCU_APB2FZ1_DBG_TIM16_Msk
#define	DBGMCU_APB2FZ1_DBG_TIM17_Pos   (18U)
#define	DBGMCU_APB2FZ1_DBG_TIM17_Msk   (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos)
	0x00040000
#define	DBGMCU_APB2FZ1_DBG_TIM17   DBGMCU_APB2FZ1_DBG_TIM17_Msk
#define	DBGMCU_APB4FZ1_DBG_I2C4_Pos   (7U)
#define	DBGMCU_APB4FZ1_DBG_I2C4_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos)
	0x00000080
#define	DBGMCU_APB4FZ1_DBG_I2C4   DBGMCU_APB4FZ1_DBG_I2C4_Msk
#define	DBGMCU_APB4FZ1_DBG_LPTIM2_Pos   (9U)
#define	DBGMCU_APB4FZ1_DBG_LPTIM2_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos)
	0x00000200
#define	DBGMCU_APB4FZ1_DBG_LPTIM2   DBGMCU_APB4FZ1_DBG_LPTIM2_Msk
#define	DBGMCU_APB4FZ1_DBG_LPTIM3_Pos   (10U)
#define	DBGMCU_APB4FZ1_DBG_LPTIM3_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos)
	0x00000400
#define	DBGMCU_APB4FZ1_DBG_LPTIM3   DBGMCU_APB4FZ1_DBG_LPTIM3_Msk
#define	DBGMCU_APB4FZ1_DBG_LPTIM4_Pos   (11U)
#define	DBGMCU_APB4FZ1_DBG_LPTIM4_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos)
	0x00000800
#define	DBGMCU_APB4FZ1_DBG_LPTIM4   DBGMCU_APB4FZ1_DBG_LPTIM4_Msk
#define	DBGMCU_APB4FZ1_DBG_LPTIM5_Pos   (12U)
#define	DBGMCU_APB4FZ1_DBG_LPTIM5_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos)
	0x00001000
#define	DBGMCU_APB4FZ1_DBG_LPTIM5   DBGMCU_APB4FZ1_DBG_LPTIM5_Msk
#define	DBGMCU_APB4FZ1_DBG_RTC_Pos   (16U)
#define	DBGMCU_APB4FZ1_DBG_RTC_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos)
	0x00010000
#define	DBGMCU_APB4FZ1_DBG_RTC   DBGMCU_APB4FZ1_DBG_RTC_Msk
#define	DBGMCU_APB4FZ1_DBG_IWDG1_Pos   (18U)
#define	DBGMCU_APB4FZ1_DBG_IWDG1_Msk   (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos)
	0x00040000
#define	DBGMCU_APB4FZ1_DBG_IWDG1   DBGMCU_APB4FZ1_DBG_IWDG1_Msk
#define	DBGMCU_PIDR4_JEP106CON_Pos   (0U)
#define	DBGMCU_PIDR4_JEP106CON_Msk   (0xFUL << DBGMCU_PIDR4_JEP106CON_Pos)
	0x0000000F
#define	DBGMCU_PIDR4_JEP106CON   DBGMCU_PIDR4_JEP106CON_Msk
#define	DBGMCU_PIDR4_4KCOUNT_Pos   (4U)
#define	DBGMCU_PIDR4_4KCOUNT_Msk   (0xFUL << DBGMCU_PIDR4_4KCOUNT_Pos)
	0x000000F0
#define	DBGMCU_PIDR4_4KCOUNT   DBGMCU_PIDR4_4KCOUNT_Msk
#define	DBGMCU_PIDR0_PARTNUM_Pos   (0U)
#define	DBGMCU_PIDR0_PARTNUM_Msk   (0xFFUL << DBGMCU_PIDR0_PARTNUM_Pos)
	0x000000FF
#define	DBGMCU_PIDR0_PARTNUM   DBGMCU_PIDR0_PARTNUM_Msk
#define	DBGMCU_PIDR1_PARTNUM_Pos   (0U)
#define	DBGMCU_PIDR1_PARTNUM_Msk   (0xFUL << DBGMCU_PIDR1_PARTNUM_Pos)
	0x0000000F
#define	DBGMCU_PIDR1_PARTNUM   DBGMCU_PIDR1_PARTNUM_Msk
#define	DBGMCU_PIDR1_JEP106ID_Pos   (4U)
#define	DBGMCU_PIDR1_JEP106ID_Msk   (0xFUL << DBGMCU_PIDR1_JEP106ID_Pos)
	0x000000F0
#define	DBGMCU_PIDR1_JEP106ID   DBGMCU_PIDR1_JEP106ID_Msk
#define	DBGMCU_PIDR2_JEP106ID_Pos   (0U)
#define	DBGMCU_PIDR2_JEP106ID_Msk   (0x7UL << DBGMCU_PIDR2_JEP106ID_Pos)
	0x00000007
#define	DBGMCU_PIDR2_JEP106ID   DBGMCU_PIDR2_JEP106ID_Msk
#define	DBGMCU_PIDR2_JEDEC_Pos   (3U)
#define	DBGMCU_PIDR2_JEDEC_Msk   (0x1UL << DBGMCU_PIDR2_JEDEC_Pos)
	0x00000008
#define	DBGMCU_PIDR2_JEDEC   DBGMCU_PIDR2_JEDEC_Msk
#define	DBGMCU_PIDR2_REVISION_Pos   (4U)
#define	DBGMCU_PIDR2_REVISION_Msk   (0xFUL << DBGMCU_PIDR2_REVISION_Pos)
	0x000000F0
#define	DBGMCU_PIDR2_REVISION   DBGMCU_PIDR2_REVISION_Msk
#define	DBGMCU_PIDR3_CMOD_Pos   (0U)
#define	DBGMCU_PIDR3_CMOD_Msk   (0xFUL << DBGMCU_PIDR3_CMOD_Pos)
	0x0000000F
#define	DBGMCU_PIDR3_CMOD   DBGMCU_PIDR3_CMOD_Msk
#define	DBGMCU_PIDR3_REVAND_Pos   (4U)
#define	DBGMCU_PIDR3_REVAND_Msk   (0xFUL << DBGMCU_PIDR3_REVAND_Pos)
	0x000000F0
#define	DBGMCU_PIDR3_REVAND   DBGMCU_PIDR3_REVAND_Msk
#define	DBGMCU_CIR0_PREAMBLE_Pos   (0U)
#define	DBGMCU_CIR0_PREAMBLE_Msk   (0xFFUL << DBGMCU_CIR0_PREAMBLE_Pos)
	0x000000FF
#define	DBGMCU_CIR0_PREAMBLE   DBGMCU_CIR0_PREAMBLE_Msk
#define	DBGMCU_CIR1_PREAMBLE_Pos   (0U)
#define	DBGMCU_CIR1_PREAMBLE_Msk   (0xFUL << DBGMCU_CIR1_PREAMBLE_Pos)
	0x0000000F
#define	DBGMCU_CIR1_PREAMBLE   DBGMCU_CIR1_PREAMBLE_Msk
#define	DBGMCU_CIR1_CLASS_Pos   (4U)
#define	DBGMCU_CIR1_CLASS_Msk   (0xFUL << DBGMCU_CIR1_CLASS_Pos)
	0x000000F0
#define	DBGMCU_CIR1_CLASS   DBGMCU_CIR1_CLASS_Msk
#define	DBGMCU_CIR2_PREAMBLE_Pos   (0U)
#define	DBGMCU_CIR2_PREAMBLE_Msk   (0xFFUL << DBGMCU_CIR2_PREAMBLE_Pos)
	0x000000FF
#define	DBGMCU_CIR2_PREAMBLE   DBGMCU_CIR2_PREAMBLE_Msk
#define	DBGMCU_CIR3_PREAMBLE_Pos   (0U)
#define	DBGMCU_CIR3_PREAMBLE_Msk   (0xFFUL << DBGMCU_CIR3_PREAMBLE_Pos)
	0x000000FF
#define	DBGMCU_CIR3_PREAMBLE   DBGMCU_CIR3_PREAMBLE_Msk
#define	RAMECC_IER_GECCDEBWIE_Pos   (3U)
#define	RAMECC_IER_GECCDEBWIE_Msk   (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)
	0x00000008
#define	RAMECC_IER_GECCDEBWIE   RAMECC_IER_GECCDEBWIE_Msk
	Global ECC double error on byte write (BW) interrupt enable.
#define	RAMECC_IER_GECCDEIE_Pos   (2U)
#define	RAMECC_IER_GECCDEIE_Msk   (0x1UL << RAMECC_IER_GECCDEIE_Pos)
	0x00000004
#define	RAMECC_IER_GECCDEIE   RAMECC_IER_GECCDEIE_Msk
	Global ECC double error interrupt enable.
#define	RAMECC_IER_GECCSEIE_Pos   (1U)
#define	RAMECC_IER_GECCSEIE_Msk   (0x1UL << RAMECC_IER_GECCSEIE_Pos)
	0x00000002
#define	RAMECC_IER_GECCSEIE   RAMECC_IER_GECCSEIE_Msk
	Global ECC single error interrupt enable.
#define	RAMECC_IER_GIE_Pos   (0U)
#define	RAMECC_IER_GIE_Msk   (0x1UL << RAMECC_IER_GIE_Pos)
	0x00000001
#define	RAMECC_IER_GIE   RAMECC_IER_GIE_Msk
	Global interrupt enable.
#define	RAMECC_CR_ECCELEN_Pos   (5U)
#define	RAMECC_CR_ECCELEN_Msk   (0x1UL << RAMECC_CR_ECCELEN_Pos)
	0x00000020
#define	RAMECC_CR_ECCELEN   RAMECC_CR_ECCELEN_Msk
	ECC error latching enable.
#define	RAMECC_CR_ECCDEBWIE_Pos   (4U)
#define	RAMECC_CR_ECCDEBWIE_Msk   (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)
	0x00000010
#define	RAMECC_CR_ECCDEBWIE   RAMECC_CR_ECCDEBWIE_Msk
	ECC double error on byte write (BW) interrupt enable.
#define	RAMECC_CR_ECCDEIE_Pos   (3U)
#define	RAMECC_CR_ECCDEIE_Msk   (0x1UL << RAMECC_CR_ECCDEIE_Pos)
	0x00000008
#define	RAMECC_CR_ECCDEIE   RAMECC_CR_ECCDEIE_Msk
	ECC double error interrupt enable.
#define	RAMECC_CR_ECCSEIE_Pos   (2U)
#define	RAMECC_CR_ECCSEIE_Msk   (0x1UL << RAMECC_CR_ECCSEIE_Pos)
	0x00000004
#define	RAMECC_CR_ECCSEIE   RAMECC_CR_ECCSEIE_Msk
	ECC single error interrupt enable.
#define	RAMECC_SR_DEBWDF_Pos   (2U)
#define	RAMECC_SR_DEBWDF_Msk   (0x1UL << RAMECC_SR_DEBWDF_Pos)
	0x00000004
#define	RAMECC_SR_DEBWDF   RAMECC_SR_DEBWDF_Msk
	ECC double error on byte write (BW) detected flag.
#define	RAMECC_SR_DEDF_Pos   (1U)
#define	RAMECC_SR_DEDF_Msk   (0x1UL << RAMECC_SR_DEDF_Pos)
	0x00000002
#define	RAMECC_SR_DEDF   RAMECC_SR_DEDF_Msk
	ECC double error detected flag.
#define	RAMECC_SR_SEDCF_Pos   (0U)
#define	RAMECC_SR_SEDCF_Msk   (0x1UL << RAMECC_SR_SEDCF_Pos)
	0x00000001
#define	RAMECC_SR_SEDCF   RAMECC_SR_SEDCF_Msk
	ECC single error detected and corrected flag.
#define	RAMECC_FAR_FADD_Pos   (0U)
#define	RAMECC_FAR_FADD_Msk   (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)
	0xFFFFFFFF
#define	RAMECC_FAR_FADD   RAMECC_FAR_FADD_Msk
	ECC error failing address.
#define	RAMECC_FAR_FDATAL_Pos   (0U)
#define	RAMECC_FAR_FDATAL_Msk   (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos
	0xFFFFFFFF
#define	RAMECC_FAR_FDATAL   RAMECC_FAR_FDATAL_Msk
	ECC error failing address.
#define	RAMECC_FAR_FDATAH_Pos   (0U)
#define	RAMECC_FAR_FDATAH_Msk   (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos
	0xFFFFFFFF
#define	RAMECC_FAR_FDATAH   RAMECC_FAR_FDATAH_Msk /* Failing data high (64-bit memory) */
#define	RAMECC_FECR_FEC_Pos   (0U)
#define	RAMECC_FECR_FEC_Msk   (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)
	0xFFFFFFFF
#define	RAMECC_FECR_FEC   RAMECC_FECR_FEC_Msk
	Failing error code.
#define	MDIOS_CR_EN_Pos   (0U)
#define	MDIOS_CR_EN_Msk   (0x1UL << MDIOS_CR_EN_Pos)
	0x00000001
#define	MDIOS_CR_EN   MDIOS_CR_EN_Msk
	MDIOS slave peripheral enable.
#define	MDIOS_CR_WRIE_Pos   (1U)
#define	MDIOS_CR_WRIE_Msk   (0x1UL << MDIOS_CR_WRIE_Pos)
	0x00000002
#define	MDIOS_CR_WRIE   MDIOS_CR_WRIE_Msk
	MDIOS slave register write interrupt enable.
#define	MDIOS_CR_RDIE_Pos   (2U)
#define	MDIOS_CR_RDIE_Msk   (0x1UL << MDIOS_CR_RDIE_Pos)
	0x00000004
#define	MDIOS_CR_RDIE   MDIOS_CR_RDIE_Msk
	MDIOS slave register read interrupt enable.
#define	MDIOS_CR_EIE_Pos   (3U)
#define	MDIOS_CR_EIE_Msk   (0x1UL << MDIOS_CR_EIE_Pos)
	0x00000008
#define	MDIOS_CR_EIE   MDIOS_CR_EIE_Msk
	MDIOS slave register error interrupt enable.
#define	MDIOS_CR_DPC_Pos   (7U)
#define	MDIOS_CR_DPC_Msk   (0x1UL << MDIOS_CR_DPC_Pos)
	0x00000080
#define	MDIOS_CR_DPC   MDIOS_CR_DPC_Msk
	MDIOS slave disable preamble check.
#define	MDIOS_CR_PORT_ADDRESS_Pos   (8U)
#define	MDIOS_CR_PORT_ADDRESS_Msk   (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)
	0x00001F00
#define	MDIOS_CR_PORT_ADDRESS   MDIOS_CR_PORT_ADDRESS_Msk
	MDIOS slave port address mask.
#define	MDIOS_CR_PORT_ADDRESS_0   (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)
	0x00000100
#define	MDIOS_CR_PORT_ADDRESS_1   (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)
	0x00000200
#define	MDIOS_CR_PORT_ADDRESS_2   (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)
	0x00000400
#define	MDIOS_CR_PORT_ADDRESS_3   (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)
	0x00000800
#define	MDIOS_CR_PORT_ADDRESS_4   (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)
	0x00001000
#define	MDIOS_SR_PERF_Pos   (0U)
#define	MDIOS_SR_PERF_Msk   (0x1UL << MDIOS_SR_PERF_Pos)
	0x00000001
#define	MDIOS_SR_PERF   MDIOS_SR_PERF_Msk
	MDIOS slave turnaround error flag.
#define	MDIOS_SR_SERF_Pos   (1U)
#define	MDIOS_SR_SERF_Msk   (0x1UL << MDIOS_SR_SERF_Pos)
	0x00000002
#define	MDIOS_SR_SERF   MDIOS_SR_SERF_Msk
	MDIOS slave start error flag.
#define	MDIOS_SR_TERF_Pos   (2U)
#define	MDIOS_SR_TERF_Msk   (0x1UL << MDIOS_SR_TERF_Pos)
	0x00000004
#define	MDIOS_SR_TERF   MDIOS_SR_TERF_Msk
	MDIOS slave preamble error flag.
#define	MDIOS_SR_CPERF_Pos   (0U)
#define	MDIOS_SR_CPERF_Msk   (0x1UL << MDIOS_SR_CPERF_Pos)
	0x00000001
#define	MDIOS_SR_CPERF   MDIOS_SR_CPERF_Msk
	MDIOS slave Clear the turnaround error flag.
#define	MDIOS_SR_CSERF_Pos   (1U)
#define	MDIOS_SR_CSERF_Msk   (0x1UL << MDIOS_SR_CSERF_Pos)
	0x00000002
#define	MDIOS_SR_CSERF   MDIOS_SR_CSERF_Msk
	MDIOS slave Clear the start error flag.
#define	MDIOS_SR_CTERF_Pos   (2U)
#define	MDIOS_SR_CTERF_Msk   (0x1UL << MDIOS_SR_CTERF_Pos)
	0x00000004
#define	MDIOS_SR_CTERF   MDIOS_SR_CTERF_Msk
	MDIOS slave Clear the preamble error flag.
#define	USB_OTG_GOTGCTL_SRQSCS_Pos   (0U)
#define	USB_OTG_GOTGCTL_SRQSCS_Msk   (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
	0x00000001
#define	USB_OTG_GOTGCTL_SRQSCS   USB_OTG_GOTGCTL_SRQSCS_Msk
	Session request success.
#define	USB_OTG_GOTGCTL_SRQ_Pos   (1U)
#define	USB_OTG_GOTGCTL_SRQ_Msk   (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
	0x00000002
#define	USB_OTG_GOTGCTL_SRQ   USB_OTG_GOTGCTL_SRQ_Msk
	Session request.
#define	USB_OTG_GOTGCTL_VBVALOEN_Pos   (2U)
#define	USB_OTG_GOTGCTL_VBVALOEN_Msk   (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos)
	0x00000004
#define	USB_OTG_GOTGCTL_VBVALOEN   USB_OTG_GOTGCTL_VBVALOEN_Msk
	VBUS valid override enable.
#define	USB_OTG_GOTGCTL_VBVALOVAL_Pos   (3U)
#define	USB_OTG_GOTGCTL_VBVALOVAL_Msk   (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos)
	0x00000008
#define	USB_OTG_GOTGCTL_VBVALOVAL   USB_OTG_GOTGCTL_VBVALOVAL_Msk
	VBUS valid override value.
#define	USB_OTG_GOTGCTL_AVALOEN_Pos   (4U)
#define	USB_OTG_GOTGCTL_AVALOEN_Msk   (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos)
	0x00000010
#define	USB_OTG_GOTGCTL_AVALOEN   USB_OTG_GOTGCTL_AVALOEN_Msk
	A-peripheral session valid override enable.
#define	USB_OTG_GOTGCTL_AVALOVAL_Pos   (5U)
#define	USB_OTG_GOTGCTL_AVALOVAL_Msk   (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos)
	0x00000020
#define	USB_OTG_GOTGCTL_AVALOVAL   USB_OTG_GOTGCTL_AVALOVAL_Msk
	A-peripheral session valid override value.
#define	USB_OTG_GOTGCTL_BVALOEN_Pos   (6U)
#define	USB_OTG_GOTGCTL_BVALOEN_Msk   (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos)
	0x00000040
#define	USB_OTG_GOTGCTL_BVALOEN   USB_OTG_GOTGCTL_BVALOEN_Msk
	B-peripheral session valid override enable.
#define	USB_OTG_GOTGCTL_BVALOVAL_Pos   (7U)
#define	USB_OTG_GOTGCTL_BVALOVAL_Msk   (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos)
	0x00000080
#define	USB_OTG_GOTGCTL_BVALOVAL   USB_OTG_GOTGCTL_BVALOVAL_Msk
	B-peripheral session valid override value.
#define	USB_OTG_GOTGCTL_HNGSCS_Pos   (8U)
#define	USB_OTG_GOTGCTL_HNGSCS_Msk   (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
	0x00000100
#define	USB_OTG_GOTGCTL_HNGSCS   USB_OTG_GOTGCTL_HNGSCS_Msk
	Host set HNP enable.
#define	USB_OTG_GOTGCTL_HNPRQ_Pos   (9U)
#define	USB_OTG_GOTGCTL_HNPRQ_Msk   (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
	0x00000200
#define	USB_OTG_GOTGCTL_HNPRQ   USB_OTG_GOTGCTL_HNPRQ_Msk
	HNP request.
#define	USB_OTG_GOTGCTL_HSHNPEN_Pos   (10U)
#define	USB_OTG_GOTGCTL_HSHNPEN_Msk   (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
	0x00000400
#define	USB_OTG_GOTGCTL_HSHNPEN   USB_OTG_GOTGCTL_HSHNPEN_Msk
	Host set HNP enable.
#define	USB_OTG_GOTGCTL_DHNPEN_Pos   (11U)
#define	USB_OTG_GOTGCTL_DHNPEN_Msk   (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
	0x00000800
#define	USB_OTG_GOTGCTL_DHNPEN   USB_OTG_GOTGCTL_DHNPEN_Msk
	Device HNP enabled.
#define	USB_OTG_GOTGCTL_EHEN_Pos   (12U)
#define	USB_OTG_GOTGCTL_EHEN_Msk   (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos)
	0x00001000
#define	USB_OTG_GOTGCTL_EHEN   USB_OTG_GOTGCTL_EHEN_Msk
	Embedded host enable.
#define	USB_OTG_GOTGCTL_CIDSTS_Pos   (16U)
#define	USB_OTG_GOTGCTL_CIDSTS_Msk   (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
	0x00010000
#define	USB_OTG_GOTGCTL_CIDSTS   USB_OTG_GOTGCTL_CIDSTS_Msk
	Connector ID status.
#define	USB_OTG_GOTGCTL_DBCT_Pos   (17U)
#define	USB_OTG_GOTGCTL_DBCT_Msk   (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
	0x00020000
#define	USB_OTG_GOTGCTL_DBCT   USB_OTG_GOTGCTL_DBCT_Msk
	Long/short debounce time.
#define	USB_OTG_GOTGCTL_ASVLD_Pos   (18U)
#define	USB_OTG_GOTGCTL_ASVLD_Msk   (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
	0x00040000
#define	USB_OTG_GOTGCTL_ASVLD   USB_OTG_GOTGCTL_ASVLD_Msk
	A-session valid.
#define	USB_OTG_GOTGCTL_BSESVLD_Pos   (19U)
#define	USB_OTG_GOTGCTL_BSESVLD_Msk   (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos)
	0x00080000
#define	USB_OTG_GOTGCTL_BSESVLD   USB_OTG_GOTGCTL_BSESVLD_Msk
	B-session valid.
#define	USB_OTG_GOTGCTL_OTGVER_Pos   (20U)
#define	USB_OTG_GOTGCTL_OTGVER_Msk   (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos)
	0x00100000
#define	USB_OTG_GOTGCTL_OTGVER   USB_OTG_GOTGCTL_OTGVER_Msk
	OTG version.
#define	USB_OTG_GOTGCTL_CURMOD_Pos   (21U)
#define	USB_OTG_GOTGCTL_CURMOD_Msk   (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos)
	0x00200000
#define	USB_OTG_GOTGCTL_CURMOD   USB_OTG_GOTGCTL_CURMOD_Msk
	Current mode of operation.
#define	USB_OTG_HCFG_FSLSPCS_Pos   (0U)
#define	USB_OTG_HCFG_FSLSPCS_Msk   (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
	0x00000003
#define	USB_OTG_HCFG_FSLSPCS   USB_OTG_HCFG_FSLSPCS_Msk
	FS/LS PHY clock select.
#define	USB_OTG_HCFG_FSLSPCS_0   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
	0x00000001
#define	USB_OTG_HCFG_FSLSPCS_1   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
	0x00000002
#define	USB_OTG_HCFG_FSLSS_Pos   (2U)
#define	USB_OTG_HCFG_FSLSS_Msk   (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
	0x00000004
#define	USB_OTG_HCFG_FSLSS   USB_OTG_HCFG_FSLSS_Msk
	FS- and LS-only support.
#define	USB_OTG_DCFG_DSPD_Pos   (0U)
#define	USB_OTG_DCFG_DSPD_Msk   (0x3UL << USB_OTG_DCFG_DSPD_Pos)
	0x00000003
#define	USB_OTG_DCFG_DSPD   USB_OTG_DCFG_DSPD_Msk
	Device speed.
#define	USB_OTG_DCFG_DSPD_0   (0x1UL << USB_OTG_DCFG_DSPD_Pos)
	0x00000001
#define	USB_OTG_DCFG_DSPD_1   (0x2UL << USB_OTG_DCFG_DSPD_Pos)
	0x00000002
#define	USB_OTG_DCFG_NZLSOHSK_Pos   (2U)
#define	USB_OTG_DCFG_NZLSOHSK_Msk   (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
	0x00000004
#define	USB_OTG_DCFG_NZLSOHSK   USB_OTG_DCFG_NZLSOHSK_Msk
	Nonzero-length status OUT handshake.
#define	USB_OTG_DCFG_DAD_Pos   (4U)
#define	USB_OTG_DCFG_DAD_Msk   (0x7FUL << USB_OTG_DCFG_DAD_Pos)
	0x000007F0
#define	USB_OTG_DCFG_DAD   USB_OTG_DCFG_DAD_Msk
	Device address.
#define	USB_OTG_DCFG_DAD_0   (0x01UL << USB_OTG_DCFG_DAD_Pos)
	0x00000010
#define	USB_OTG_DCFG_DAD_1   (0x02UL << USB_OTG_DCFG_DAD_Pos)
	0x00000020
#define	USB_OTG_DCFG_DAD_2   (0x04UL << USB_OTG_DCFG_DAD_Pos)
	0x00000040
#define	USB_OTG_DCFG_DAD_3   (0x08UL << USB_OTG_DCFG_DAD_Pos)
	0x00000080
#define	USB_OTG_DCFG_DAD_4   (0x10UL << USB_OTG_DCFG_DAD_Pos)
	0x00000100
#define	USB_OTG_DCFG_DAD_5   (0x20UL << USB_OTG_DCFG_DAD_Pos)
	0x00000200
#define	USB_OTG_DCFG_DAD_6   (0x40UL << USB_OTG_DCFG_DAD_Pos)
	0x00000400
#define	USB_OTG_DCFG_PFIVL_Pos   (11U)
#define	USB_OTG_DCFG_PFIVL_Msk   (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
	0x00001800
#define	USB_OTG_DCFG_PFIVL   USB_OTG_DCFG_PFIVL_Msk
	Periodic (micro)frame interval.
#define	USB_OTG_DCFG_PFIVL_0   (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
	0x00000800
#define	USB_OTG_DCFG_PFIVL_1   (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
	0x00001000
#define	USB_OTG_DCFG_XCVRDLY_Pos   (14U)
#define	USB_OTG_DCFG_XCVRDLY_Msk   (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos)
	0x00004000
#define	USB_OTG_DCFG_XCVRDLY   USB_OTG_DCFG_XCVRDLY_Msk
	Transceiver delay.
#define	USB_OTG_DCFG_ERRATIM_Pos   (15U)
#define	USB_OTG_DCFG_ERRATIM_Msk   (0x1UL << USB_OTG_DCFG_ERRATIM_Pos)
	0x00008000
#define	USB_OTG_DCFG_ERRATIM   USB_OTG_DCFG_ERRATIM_Msk
	Erratic error interrupt mask.
#define	USB_OTG_DCFG_PERSCHIVL_Pos   (24U)
#define	USB_OTG_DCFG_PERSCHIVL_Msk   (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
	0x03000000
#define	USB_OTG_DCFG_PERSCHIVL   USB_OTG_DCFG_PERSCHIVL_Msk
	Periodic scheduling interval.
#define	USB_OTG_DCFG_PERSCHIVL_0   (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
	0x01000000
#define	USB_OTG_DCFG_PERSCHIVL_1   (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
	0x02000000
#define	USB_OTG_PCGCR_STPPCLK_Pos   (0U)
#define	USB_OTG_PCGCR_STPPCLK_Msk   (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
	0x00000001
#define	USB_OTG_PCGCR_STPPCLK   USB_OTG_PCGCR_STPPCLK_Msk
	Stop PHY clock.
#define	USB_OTG_PCGCR_GATEHCLK_Pos   (1U)
#define	USB_OTG_PCGCR_GATEHCLK_Msk   (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
	0x00000002
#define	USB_OTG_PCGCR_GATEHCLK   USB_OTG_PCGCR_GATEHCLK_Msk
	Gate HCLK.
#define	USB_OTG_PCGCR_PHYSUSP_Pos   (4U)
#define	USB_OTG_PCGCR_PHYSUSP_Msk   (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
	0x00000010
#define	USB_OTG_PCGCR_PHYSUSP   USB_OTG_PCGCR_PHYSUSP_Msk
	PHY suspended.
#define	USB_OTG_GOTGINT_SEDET_Pos   (2U)
#define	USB_OTG_GOTGINT_SEDET_Msk   (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
	0x00000004
#define	USB_OTG_GOTGINT_SEDET   USB_OTG_GOTGINT_SEDET_Msk
	Session end detected.
#define	USB_OTG_GOTGINT_SRSSCHG_Pos   (8U)
#define	USB_OTG_GOTGINT_SRSSCHG_Msk   (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
	0x00000100
#define	USB_OTG_GOTGINT_SRSSCHG   USB_OTG_GOTGINT_SRSSCHG_Msk
	Session request success status change.
#define	USB_OTG_GOTGINT_HNSSCHG_Pos   (9U)
#define	USB_OTG_GOTGINT_HNSSCHG_Msk   (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
	0x00000200
#define	USB_OTG_GOTGINT_HNSSCHG   USB_OTG_GOTGINT_HNSSCHG_Msk
	Host negotiation success status change.
#define	USB_OTG_GOTGINT_HNGDET_Pos   (17U)
#define	USB_OTG_GOTGINT_HNGDET_Msk   (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
	0x00020000
#define	USB_OTG_GOTGINT_HNGDET   USB_OTG_GOTGINT_HNGDET_Msk
	Host negotiation detected.
#define	USB_OTG_GOTGINT_ADTOCHG_Pos   (18U)
#define	USB_OTG_GOTGINT_ADTOCHG_Msk   (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
	0x00040000
#define	USB_OTG_GOTGINT_ADTOCHG   USB_OTG_GOTGINT_ADTOCHG_Msk
	A-device timeout change.
#define	USB_OTG_GOTGINT_DBCDNE_Pos   (19U)
#define	USB_OTG_GOTGINT_DBCDNE_Msk   (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
	0x00080000
#define	USB_OTG_GOTGINT_DBCDNE   USB_OTG_GOTGINT_DBCDNE_Msk
	Debounce done.
#define	USB_OTG_DCTL_RWUSIG_Pos   (0U)
#define	USB_OTG_DCTL_RWUSIG_Msk   (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
	0x00000001
#define	USB_OTG_DCTL_RWUSIG   USB_OTG_DCTL_RWUSIG_Msk
	Remote wakeup signaling.
#define	USB_OTG_DCTL_SDIS_Pos   (1U)
#define	USB_OTG_DCTL_SDIS_Msk   (0x1UL << USB_OTG_DCTL_SDIS_Pos)
	0x00000002
#define	USB_OTG_DCTL_SDIS   USB_OTG_DCTL_SDIS_Msk
	Soft disconnect.
#define	USB_OTG_DCTL_GINSTS_Pos   (2U)
#define	USB_OTG_DCTL_GINSTS_Msk   (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
	0x00000004
#define	USB_OTG_DCTL_GINSTS   USB_OTG_DCTL_GINSTS_Msk
	Global IN NAK status.
#define	USB_OTG_DCTL_GONSTS_Pos   (3U)
#define	USB_OTG_DCTL_GONSTS_Msk   (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
	0x00000008
#define	USB_OTG_DCTL_GONSTS   USB_OTG_DCTL_GONSTS_Msk
	Global OUT NAK status.
#define	USB_OTG_DCTL_TCTL_Pos   (4U)
#define	USB_OTG_DCTL_TCTL_Msk   (0x7UL << USB_OTG_DCTL_TCTL_Pos)
	0x00000070
#define	USB_OTG_DCTL_TCTL   USB_OTG_DCTL_TCTL_Msk
	Test control.
#define	USB_OTG_DCTL_TCTL_0   (0x1UL << USB_OTG_DCTL_TCTL_Pos)
	0x00000010
#define	USB_OTG_DCTL_TCTL_1   (0x2UL << USB_OTG_DCTL_TCTL_Pos)
	0x00000020
#define	USB_OTG_DCTL_TCTL_2   (0x4UL << USB_OTG_DCTL_TCTL_Pos)
	0x00000040
#define	USB_OTG_DCTL_SGINAK_Pos   (7U)
#define	USB_OTG_DCTL_SGINAK_Msk   (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
	0x00000080
#define	USB_OTG_DCTL_SGINAK   USB_OTG_DCTL_SGINAK_Msk
	Set global IN NAK.
#define	USB_OTG_DCTL_CGINAK_Pos   (8U)
#define	USB_OTG_DCTL_CGINAK_Msk   (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
	0x00000100
#define	USB_OTG_DCTL_CGINAK   USB_OTG_DCTL_CGINAK_Msk
	Clear global IN NAK.
#define	USB_OTG_DCTL_SGONAK_Pos   (9U)
#define	USB_OTG_DCTL_SGONAK_Msk   (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
	0x00000200
#define	USB_OTG_DCTL_SGONAK   USB_OTG_DCTL_SGONAK_Msk
	Set global OUT NAK.
#define	USB_OTG_DCTL_CGONAK_Pos   (10U)
#define	USB_OTG_DCTL_CGONAK_Msk   (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
	0x00000400
#define	USB_OTG_DCTL_CGONAK   USB_OTG_DCTL_CGONAK_Msk
	Clear global OUT NAK.
#define	USB_OTG_DCTL_POPRGDNE_Pos   (11U)
#define	USB_OTG_DCTL_POPRGDNE_Msk   (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
	0x00000800
#define	USB_OTG_DCTL_POPRGDNE   USB_OTG_DCTL_POPRGDNE_Msk
	Power-on programming done.
#define	USB_OTG_DCTL_ENCONTONBNA_Pos   (17U)
#define	USB_OTG_DCTL_ENCONTONBNA_Msk   (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos)
	0x00020000
#define	USB_OTG_DCTL_ENCONTONBNA   USB_OTG_DCTL_ENCONTONBNA_Msk
	Enable continue on BNA.
#define	USB_OTG_DCTL_DSBESLRJCT_Pos   (18U)
#define	USB_OTG_DCTL_DSBESLRJCT_Msk   (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos)
	0x00040000
#define	USB_OTG_DCTL_DSBESLRJCT   USB_OTG_DCTL_DSBESLRJCT_Msk
	Deep sleep BESL reject.
#define	USB_OTG_HFIR_FRIVL_Pos   (0U)
#define	USB_OTG_HFIR_FRIVL_Msk   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
	0x0000FFFF
#define	USB_OTG_HFIR_FRIVL   USB_OTG_HFIR_FRIVL_Msk
	Frame interval.
#define	USB_OTG_HFNUM_FRNUM_Pos   (0U)
#define	USB_OTG_HFNUM_FRNUM_Msk   (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
	0x0000FFFF
#define	USB_OTG_HFNUM_FRNUM   USB_OTG_HFNUM_FRNUM_Msk
	Frame number.
#define	USB_OTG_HFNUM_FTREM_Pos   (16U)
#define	USB_OTG_HFNUM_FTREM_Msk   (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
	0xFFFF0000
#define	USB_OTG_HFNUM_FTREM   USB_OTG_HFNUM_FTREM_Msk
	Frame time remaining.
#define	USB_OTG_DSTS_SUSPSTS_Pos   (0U)
#define	USB_OTG_DSTS_SUSPSTS_Msk   (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
	0x00000001
#define	USB_OTG_DSTS_SUSPSTS   USB_OTG_DSTS_SUSPSTS_Msk
	Suspend status.
#define	USB_OTG_DSTS_ENUMSPD_Pos   (1U)
#define	USB_OTG_DSTS_ENUMSPD_Msk   (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
	0x00000006
#define	USB_OTG_DSTS_ENUMSPD   USB_OTG_DSTS_ENUMSPD_Msk
	Enumerated speed.
#define	USB_OTG_DSTS_ENUMSPD_0   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
	0x00000002
#define	USB_OTG_DSTS_ENUMSPD_1   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
	0x00000004
#define	USB_OTG_DSTS_EERR_Pos   (3U)
#define	USB_OTG_DSTS_EERR_Msk   (0x1UL << USB_OTG_DSTS_EERR_Pos)
	0x00000008
#define	USB_OTG_DSTS_EERR   USB_OTG_DSTS_EERR_Msk
	Erratic error.
#define	USB_OTG_DSTS_FNSOF_Pos   (8U)
#define	USB_OTG_DSTS_FNSOF_Msk   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
	0x003FFF00
#define	USB_OTG_DSTS_FNSOF   USB_OTG_DSTS_FNSOF_Msk
	Frame number of the received SOF.
#define	USB_OTG_GAHBCFG_GINT_Pos   (0U)
#define	USB_OTG_GAHBCFG_GINT_Msk   (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
	0x00000001
#define	USB_OTG_GAHBCFG_GINT   USB_OTG_GAHBCFG_GINT_Msk
	Global interrupt mask.
#define	USB_OTG_GAHBCFG_HBSTLEN_Pos   (1U)
#define	USB_OTG_GAHBCFG_HBSTLEN_Msk   (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
	0x0000001E
#define	USB_OTG_GAHBCFG_HBSTLEN   USB_OTG_GAHBCFG_HBSTLEN_Msk
	Burst length/type.
#define	USB_OTG_GAHBCFG_HBSTLEN_0   (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
	Single.
#define	USB_OTG_GAHBCFG_HBSTLEN_1   (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
	INCR.
#define	USB_OTG_GAHBCFG_HBSTLEN_2   (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
	INCR4.
#define	USB_OTG_GAHBCFG_HBSTLEN_3   (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
	INCR8.
#define	USB_OTG_GAHBCFG_HBSTLEN_4   (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
	INCR16.
#define	USB_OTG_GAHBCFG_DMAEN_Pos   (5U)
#define	USB_OTG_GAHBCFG_DMAEN_Msk   (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
	0x00000020
#define	USB_OTG_GAHBCFG_DMAEN   USB_OTG_GAHBCFG_DMAEN_Msk
	DMA enable.
#define	USB_OTG_GAHBCFG_TXFELVL_Pos   (7U)
#define	USB_OTG_GAHBCFG_TXFELVL_Msk   (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
	0x00000080
#define	USB_OTG_GAHBCFG_TXFELVL   USB_OTG_GAHBCFG_TXFELVL_Msk
	TxFIFO empty level.
#define	USB_OTG_GAHBCFG_PTXFELVL_Pos   (8U)
#define	USB_OTG_GAHBCFG_PTXFELVL_Msk   (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
	0x00000100
#define	USB_OTG_GAHBCFG_PTXFELVL   USB_OTG_GAHBCFG_PTXFELVL_Msk
	Periodic TxFIFO empty level.
#define	USB_OTG_GUSBCFG_TOCAL_Pos   (0U)
#define	USB_OTG_GUSBCFG_TOCAL_Msk   (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
	0x00000007
#define	USB_OTG_GUSBCFG_TOCAL   USB_OTG_GUSBCFG_TOCAL_Msk
	FS timeout calibration.
#define	USB_OTG_GUSBCFG_TOCAL_0   (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
	0x00000001
#define	USB_OTG_GUSBCFG_TOCAL_1   (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
	0x00000002
#define	USB_OTG_GUSBCFG_TOCAL_2   (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
	0x00000004
#define	USB_OTG_GUSBCFG_PHYSEL_Pos   (6U)
#define	USB_OTG_GUSBCFG_PHYSEL_Msk   (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
	0x00000040
#define	USB_OTG_GUSBCFG_PHYSEL   USB_OTG_GUSBCFG_PHYSEL_Msk
	USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select.
#define	USB_OTG_GUSBCFG_SRPCAP_Pos   (8U)
#define	USB_OTG_GUSBCFG_SRPCAP_Msk   (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
	0x00000100
#define	USB_OTG_GUSBCFG_SRPCAP   USB_OTG_GUSBCFG_SRPCAP_Msk
	SRP-capable.
#define	USB_OTG_GUSBCFG_HNPCAP_Pos   (9U)
#define	USB_OTG_GUSBCFG_HNPCAP_Msk   (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
	0x00000200
#define	USB_OTG_GUSBCFG_HNPCAP   USB_OTG_GUSBCFG_HNPCAP_Msk
	HNP-capable.
#define	USB_OTG_GUSBCFG_TRDT_Pos   (10U)
#define	USB_OTG_GUSBCFG_TRDT_Msk   (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
	0x00003C00
#define	USB_OTG_GUSBCFG_TRDT   USB_OTG_GUSBCFG_TRDT_Msk
	USB turnaround time.
#define	USB_OTG_GUSBCFG_TRDT_0   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
	0x00000400
#define	USB_OTG_GUSBCFG_TRDT_1   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
	0x00000800
#define	USB_OTG_GUSBCFG_TRDT_2   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
	0x00001000
#define	USB_OTG_GUSBCFG_TRDT_3   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
	0x00002000
#define	USB_OTG_GUSBCFG_PHYLPCS_Pos   (15U)
#define	USB_OTG_GUSBCFG_PHYLPCS_Msk   (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
	0x00008000
#define	USB_OTG_GUSBCFG_PHYLPCS   USB_OTG_GUSBCFG_PHYLPCS_Msk
	PHY Low-power clock select.
#define	USB_OTG_GUSBCFG_ULPIFSLS_Pos   (17U)
#define	USB_OTG_GUSBCFG_ULPIFSLS_Msk   (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
	0x00020000
#define	USB_OTG_GUSBCFG_ULPIFSLS   USB_OTG_GUSBCFG_ULPIFSLS_Msk
	ULPI FS/LS select.
#define	USB_OTG_GUSBCFG_ULPIAR_Pos   (18U)
#define	USB_OTG_GUSBCFG_ULPIAR_Msk   (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
	0x00040000
#define	USB_OTG_GUSBCFG_ULPIAR   USB_OTG_GUSBCFG_ULPIAR_Msk
	ULPI Auto-resume.
#define	USB_OTG_GUSBCFG_ULPICSM_Pos   (19U)
#define	USB_OTG_GUSBCFG_ULPICSM_Msk   (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
	0x00080000
#define	USB_OTG_GUSBCFG_ULPICSM   USB_OTG_GUSBCFG_ULPICSM_Msk
	ULPI Clock SuspendM.
#define	USB_OTG_GUSBCFG_ULPIEVBUSD_Pos   (20U)
#define	USB_OTG_GUSBCFG_ULPIEVBUSD_Msk   (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
	0x00100000
#define	USB_OTG_GUSBCFG_ULPIEVBUSD   USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
	ULPI External VBUS Drive.
#define	USB_OTG_GUSBCFG_ULPIEVBUSI_Pos   (21U)
#define	USB_OTG_GUSBCFG_ULPIEVBUSI_Msk   (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
	0x00200000
#define	USB_OTG_GUSBCFG_ULPIEVBUSI   USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
	ULPI external VBUS indicator.
#define	USB_OTG_GUSBCFG_TSDPS_Pos   (22U)
#define	USB_OTG_GUSBCFG_TSDPS_Msk   (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
	0x00400000
#define	USB_OTG_GUSBCFG_TSDPS   USB_OTG_GUSBCFG_TSDPS_Msk
	TermSel DLine pulsing selection.
#define	USB_OTG_GUSBCFG_PCCI_Pos   (23U)
#define	USB_OTG_GUSBCFG_PCCI_Msk   (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
	0x00800000
#define	USB_OTG_GUSBCFG_PCCI   USB_OTG_GUSBCFG_PCCI_Msk
	Indicator complement.
#define	USB_OTG_GUSBCFG_PTCI_Pos   (24U)
#define	USB_OTG_GUSBCFG_PTCI_Msk   (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
	0x01000000
#define	USB_OTG_GUSBCFG_PTCI   USB_OTG_GUSBCFG_PTCI_Msk
	Indicator pass through.
#define	USB_OTG_GUSBCFG_ULPIIPD_Pos   (25U)
#define	USB_OTG_GUSBCFG_ULPIIPD_Msk   (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
	0x02000000
#define	USB_OTG_GUSBCFG_ULPIIPD   USB_OTG_GUSBCFG_ULPIIPD_Msk
	ULPI interface protect disable.
#define	USB_OTG_GUSBCFG_FHMOD_Pos   (29U)
#define	USB_OTG_GUSBCFG_FHMOD_Msk   (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
	0x20000000
#define	USB_OTG_GUSBCFG_FHMOD   USB_OTG_GUSBCFG_FHMOD_Msk
	Forced host mode.
#define	USB_OTG_GUSBCFG_FDMOD_Pos   (30U)
#define	USB_OTG_GUSBCFG_FDMOD_Msk   (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
	0x40000000
#define	USB_OTG_GUSBCFG_FDMOD   USB_OTG_GUSBCFG_FDMOD_Msk
	Forced peripheral mode.
#define	USB_OTG_GUSBCFG_CTXPKT_Pos   (31U)
#define	USB_OTG_GUSBCFG_CTXPKT_Msk   (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
	0x80000000
#define	USB_OTG_GUSBCFG_CTXPKT   USB_OTG_GUSBCFG_CTXPKT_Msk
	Corrupt Tx packet for debug propose only; must be kept at reset value.
#define	USB_OTG_GRSTCTL_CSRST_Pos   (0U)
#define	USB_OTG_GRSTCTL_CSRST_Msk   (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
	0x00000001
#define	USB_OTG_GRSTCTL_CSRST   USB_OTG_GRSTCTL_CSRST_Msk
	Core soft reset.
#define	USB_OTG_GRSTCTL_HSRST_Pos   (1U)
#define	USB_OTG_GRSTCTL_HSRST_Msk   (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
	0x00000002
#define	USB_OTG_GRSTCTL_HSRST   USB_OTG_GRSTCTL_HSRST_Msk
	HCLK soft reset.
#define	USB_OTG_GRSTCTL_FCRST_Pos   (2U)
#define	USB_OTG_GRSTCTL_FCRST_Msk   (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
	0x00000004
#define	USB_OTG_GRSTCTL_FCRST   USB_OTG_GRSTCTL_FCRST_Msk
	Host frame counter reset.
#define	USB_OTG_GRSTCTL_RXFFLSH_Pos   (4U)
#define	USB_OTG_GRSTCTL_RXFFLSH_Msk   (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
	0x00000010
#define	USB_OTG_GRSTCTL_RXFFLSH   USB_OTG_GRSTCTL_RXFFLSH_Msk
	RxFIFO flush.
#define	USB_OTG_GRSTCTL_TXFFLSH_Pos   (5U)
#define	USB_OTG_GRSTCTL_TXFFLSH_Msk   (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
	0x00000020
#define	USB_OTG_GRSTCTL_TXFFLSH   USB_OTG_GRSTCTL_TXFFLSH_Msk
	TxFIFO flush.
#define	USB_OTG_GRSTCTL_TXFNUM_Pos   (6U)
#define	USB_OTG_GRSTCTL_TXFNUM_Msk   (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
	0x000007C0
#define	USB_OTG_GRSTCTL_TXFNUM   USB_OTG_GRSTCTL_TXFNUM_Msk
	TxFIFO number.
#define	USB_OTG_GRSTCTL_TXFNUM_0   (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
	0x00000040
#define	USB_OTG_GRSTCTL_TXFNUM_1   (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
	0x00000080
#define	USB_OTG_GRSTCTL_TXFNUM_2   (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
	0x00000100
#define	USB_OTG_GRSTCTL_TXFNUM_3   (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
	0x00000200
#define	USB_OTG_GRSTCTL_TXFNUM_4   (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
	0x00000400
#define	USB_OTG_GRSTCTL_DMAREQ_Pos   (30U)
#define	USB_OTG_GRSTCTL_DMAREQ_Msk   (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
	0x40000000
#define	USB_OTG_GRSTCTL_DMAREQ   USB_OTG_GRSTCTL_DMAREQ_Msk
	DMA request signal.
#define	USB_OTG_GRSTCTL_AHBIDL_Pos   (31U)
#define	USB_OTG_GRSTCTL_AHBIDL_Msk   (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
	0x80000000
#define	USB_OTG_GRSTCTL_AHBIDL   USB_OTG_GRSTCTL_AHBIDL_Msk
	AHB master idle.
#define	USB_OTG_DIEPMSK_XFRCM_Pos   (0U)
#define	USB_OTG_DIEPMSK_XFRCM_Msk   (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
	0x00000001
#define	USB_OTG_DIEPMSK_XFRCM   USB_OTG_DIEPMSK_XFRCM_Msk
	Transfer completed interrupt mask.
#define	USB_OTG_DIEPMSK_EPDM_Pos   (1U)
#define	USB_OTG_DIEPMSK_EPDM_Msk   (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
	0x00000002
#define	USB_OTG_DIEPMSK_EPDM   USB_OTG_DIEPMSK_EPDM_Msk
	Endpoint disabled interrupt mask.
#define	USB_OTG_DIEPMSK_TOM_Pos   (3U)
#define	USB_OTG_DIEPMSK_TOM_Msk   (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
	0x00000008
#define	USB_OTG_DIEPMSK_TOM   USB_OTG_DIEPMSK_TOM_Msk
	Timeout condition mask (nonisochronous endpoints).
#define	USB_OTG_DIEPMSK_ITTXFEMSK_Pos   (4U)
#define	USB_OTG_DIEPMSK_ITTXFEMSK_Msk   (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
	0x00000010
#define	USB_OTG_DIEPMSK_ITTXFEMSK   USB_OTG_DIEPMSK_ITTXFEMSK_Msk
	IN token received when TxFIFO empty mask.
#define	USB_OTG_DIEPMSK_INEPNMM_Pos   (5U)
#define	USB_OTG_DIEPMSK_INEPNMM_Msk   (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
	0x00000020
#define	USB_OTG_DIEPMSK_INEPNMM   USB_OTG_DIEPMSK_INEPNMM_Msk
	IN token received with EP mismatch mask.
#define	USB_OTG_DIEPMSK_INEPNEM_Pos   (6U)
#define	USB_OTG_DIEPMSK_INEPNEM_Msk   (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
	0x00000040
#define	USB_OTG_DIEPMSK_INEPNEM   USB_OTG_DIEPMSK_INEPNEM_Msk
	IN endpoint NAK effective mask.
#define	USB_OTG_DIEPMSK_TXFURM_Pos   (8U)
#define	USB_OTG_DIEPMSK_TXFURM_Msk   (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
	0x00000100
#define	USB_OTG_DIEPMSK_TXFURM   USB_OTG_DIEPMSK_TXFURM_Msk
	FIFO underrun mask.
#define	USB_OTG_DIEPMSK_BIM_Pos   (9U)
#define	USB_OTG_DIEPMSK_BIM_Msk   (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
	0x00000200
#define	USB_OTG_DIEPMSK_BIM   USB_OTG_DIEPMSK_BIM_Msk
	BNA interrupt mask.
#define	USB_OTG_HPTXSTS_PTXFSAVL_Pos   (0U)
#define	USB_OTG_HPTXSTS_PTXFSAVL_Msk   (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
	0x0000FFFF
#define	USB_OTG_HPTXSTS_PTXFSAVL   USB_OTG_HPTXSTS_PTXFSAVL_Msk
	Periodic transmit data FIFO space available.
#define	USB_OTG_HPTXSTS_PTXQSAV_Pos   (16U)
#define	USB_OTG_HPTXSTS_PTXQSAV_Msk   (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
	0x00FF0000
#define	USB_OTG_HPTXSTS_PTXQSAV   USB_OTG_HPTXSTS_PTXQSAV_Msk
	Periodic transmit request queue space available.
#define	USB_OTG_HPTXSTS_PTXQSAV_0   (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
	0x00010000
#define	USB_OTG_HPTXSTS_PTXQSAV_1   (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
	0x00020000
#define	USB_OTG_HPTXSTS_PTXQSAV_2   (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
	0x00040000
#define	USB_OTG_HPTXSTS_PTXQSAV_3   (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
	0x00080000
#define	USB_OTG_HPTXSTS_PTXQSAV_4   (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
	0x00100000
#define	USB_OTG_HPTXSTS_PTXQSAV_5   (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
	0x00200000
#define	USB_OTG_HPTXSTS_PTXQSAV_6   (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
	0x00400000
#define	USB_OTG_HPTXSTS_PTXQSAV_7   (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
	0x00800000
#define	USB_OTG_HPTXSTS_PTXQTOP_Pos   (24U)
#define	USB_OTG_HPTXSTS_PTXQTOP_Msk   (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
	0xFF000000
#define	USB_OTG_HPTXSTS_PTXQTOP   USB_OTG_HPTXSTS_PTXQTOP_Msk
	Top of the periodic transmit request queue.
#define	USB_OTG_HPTXSTS_PTXQTOP_0   (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
	0x01000000
#define	USB_OTG_HPTXSTS_PTXQTOP_1   (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
	0x02000000
#define	USB_OTG_HPTXSTS_PTXQTOP_2   (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
	0x04000000
#define	USB_OTG_HPTXSTS_PTXQTOP_3   (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
	0x08000000
#define	USB_OTG_HPTXSTS_PTXQTOP_4   (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
	0x10000000
#define	USB_OTG_HPTXSTS_PTXQTOP_5   (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
	0x20000000
#define	USB_OTG_HPTXSTS_PTXQTOP_6   (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
	0x40000000
#define	USB_OTG_HPTXSTS_PTXQTOP_7   (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
	0x80000000
#define	USB_OTG_HAINT_HAINT_Pos   (0U)
#define	USB_OTG_HAINT_HAINT_Msk   (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
	0x0000FFFF
#define	USB_OTG_HAINT_HAINT   USB_OTG_HAINT_HAINT_Msk
	Channel interrupts.
#define	USB_OTG_DOEPMSK_XFRCM_Pos   (0U)
#define	USB_OTG_DOEPMSK_XFRCM_Msk   (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
	0x00000001
#define	USB_OTG_DOEPMSK_XFRCM   USB_OTG_DOEPMSK_XFRCM_Msk
	Transfer completed interrupt mask.
#define	USB_OTG_DOEPMSK_EPDM_Pos   (1U)
#define	USB_OTG_DOEPMSK_EPDM_Msk   (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
	0x00000002
#define	USB_OTG_DOEPMSK_EPDM   USB_OTG_DOEPMSK_EPDM_Msk
	Endpoint disabled interrupt mask.
#define	USB_OTG_DOEPMSK_AHBERRM_Pos   (2U)
#define	USB_OTG_DOEPMSK_AHBERRM_Msk   (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
	0x00000004
#define	USB_OTG_DOEPMSK_AHBERRM   USB_OTG_DOEPMSK_AHBERRM_Msk
	OUT transaction AHB Error interrupt mask.
#define	USB_OTG_DOEPMSK_STUPM_Pos   (3U)
#define	USB_OTG_DOEPMSK_STUPM_Msk   (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
	0x00000008
#define	USB_OTG_DOEPMSK_STUPM   USB_OTG_DOEPMSK_STUPM_Msk
	SETUP phase done mask.
#define	USB_OTG_DOEPMSK_OTEPDM_Pos   (4U)
#define	USB_OTG_DOEPMSK_OTEPDM_Msk   (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
	0x00000010
#define	USB_OTG_DOEPMSK_OTEPDM   USB_OTG_DOEPMSK_OTEPDM_Msk
	OUT token received when endpoint disabled mask.
#define	USB_OTG_DOEPMSK_OTEPSPRM_Pos   (5U)
#define	USB_OTG_DOEPMSK_OTEPSPRM_Msk   (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
	0x00000020
#define	USB_OTG_DOEPMSK_OTEPSPRM   USB_OTG_DOEPMSK_OTEPSPRM_Msk
	Status Phase Received mask.
#define	USB_OTG_DOEPMSK_B2BSTUP_Pos   (6U)
#define	USB_OTG_DOEPMSK_B2BSTUP_Msk   (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
	0x00000040
#define	USB_OTG_DOEPMSK_B2BSTUP   USB_OTG_DOEPMSK_B2BSTUP_Msk
	Back-to-back SETUP packets received mask.
#define	USB_OTG_DOEPMSK_OPEM_Pos   (8U)
#define	USB_OTG_DOEPMSK_OPEM_Msk   (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
	0x00000100
#define	USB_OTG_DOEPMSK_OPEM   USB_OTG_DOEPMSK_OPEM_Msk
	OUT packet error mask.
#define	USB_OTG_DOEPMSK_BOIM_Pos   (9U)
#define	USB_OTG_DOEPMSK_BOIM_Msk   (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
	0x00000200
#define	USB_OTG_DOEPMSK_BOIM   USB_OTG_DOEPMSK_BOIM_Msk
	BNA interrupt mask.
#define	USB_OTG_DOEPMSK_BERRM_Pos   (12U)
#define	USB_OTG_DOEPMSK_BERRM_Msk   (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
	0x00001000
#define	USB_OTG_DOEPMSK_BERRM   USB_OTG_DOEPMSK_BERRM_Msk
	Babble error interrupt mask.
#define	USB_OTG_DOEPMSK_NAKM_Pos   (13U)
#define	USB_OTG_DOEPMSK_NAKM_Msk   (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
	0x00002000
#define	USB_OTG_DOEPMSK_NAKM   USB_OTG_DOEPMSK_NAKM_Msk
	OUT Packet NAK interrupt mask.
#define	USB_OTG_DOEPMSK_NYETM_Pos   (14U)
#define	USB_OTG_DOEPMSK_NYETM_Msk   (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
	0x00004000
#define	USB_OTG_DOEPMSK_NYETM   USB_OTG_DOEPMSK_NYETM_Msk
	NYET interrupt mask.
#define	USB_OTG_GINTSTS_CMOD_Pos   (0U)
#define	USB_OTG_GINTSTS_CMOD_Msk   (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
	0x00000001
#define	USB_OTG_GINTSTS_CMOD   USB_OTG_GINTSTS_CMOD_Msk
	Current mode of operation.
#define	USB_OTG_GINTSTS_MMIS_Pos   (1U)
#define	USB_OTG_GINTSTS_MMIS_Msk   (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
	0x00000002
#define	USB_OTG_GINTSTS_MMIS   USB_OTG_GINTSTS_MMIS_Msk
	Mode mismatch interrupt.
#define	USB_OTG_GINTSTS_OTGINT_Pos   (2U)
#define	USB_OTG_GINTSTS_OTGINT_Msk   (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
	0x00000004
#define	USB_OTG_GINTSTS_OTGINT   USB_OTG_GINTSTS_OTGINT_Msk
	OTG interrupt.
#define	USB_OTG_GINTSTS_SOF_Pos   (3U)
#define	USB_OTG_GINTSTS_SOF_Msk   (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
	0x00000008
#define	USB_OTG_GINTSTS_SOF   USB_OTG_GINTSTS_SOF_Msk
	Start of frame.
#define	USB_OTG_GINTSTS_RXFLVL_Pos   (4U)
#define	USB_OTG_GINTSTS_RXFLVL_Msk   (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
	0x00000010
#define	USB_OTG_GINTSTS_RXFLVL   USB_OTG_GINTSTS_RXFLVL_Msk
	RxFIFO nonempty.
#define	USB_OTG_GINTSTS_NPTXFE_Pos   (5U)
#define	USB_OTG_GINTSTS_NPTXFE_Msk   (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
	0x00000020
#define	USB_OTG_GINTSTS_NPTXFE   USB_OTG_GINTSTS_NPTXFE_Msk
	Nonperiodic TxFIFO empty.
#define	USB_OTG_GINTSTS_GINAKEFF_Pos   (6U)
#define	USB_OTG_GINTSTS_GINAKEFF_Msk   (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
	0x00000040
#define	USB_OTG_GINTSTS_GINAKEFF   USB_OTG_GINTSTS_GINAKEFF_Msk
	Global IN nonperiodic NAK effective.
#define	USB_OTG_GINTSTS_BOUTNAKEFF_Pos   (7U)
#define	USB_OTG_GINTSTS_BOUTNAKEFF_Msk   (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
	0x00000080
#define	USB_OTG_GINTSTS_BOUTNAKEFF   USB_OTG_GINTSTS_BOUTNAKEFF_Msk
	Global OUT NAK effective.
#define	USB_OTG_GINTSTS_ESUSP_Pos   (10U)
#define	USB_OTG_GINTSTS_ESUSP_Msk   (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
	0x00000400
#define	USB_OTG_GINTSTS_ESUSP   USB_OTG_GINTSTS_ESUSP_Msk
	Early suspend.
#define	USB_OTG_GINTSTS_USBSUSP_Pos   (11U)
#define	USB_OTG_GINTSTS_USBSUSP_Msk   (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
	0x00000800
#define	USB_OTG_GINTSTS_USBSUSP   USB_OTG_GINTSTS_USBSUSP_Msk
	USB suspend.
#define	USB_OTG_GINTSTS_USBRST_Pos   (12U)
#define	USB_OTG_GINTSTS_USBRST_Msk   (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
	0x00001000
#define	USB_OTG_GINTSTS_USBRST   USB_OTG_GINTSTS_USBRST_Msk
	USB reset.
#define	USB_OTG_GINTSTS_ENUMDNE_Pos   (13U)
#define	USB_OTG_GINTSTS_ENUMDNE_Msk   (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
	0x00002000
#define	USB_OTG_GINTSTS_ENUMDNE   USB_OTG_GINTSTS_ENUMDNE_Msk
	Enumeration done.
#define	USB_OTG_GINTSTS_ISOODRP_Pos   (14U)
#define	USB_OTG_GINTSTS_ISOODRP_Msk   (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
	0x00004000
#define	USB_OTG_GINTSTS_ISOODRP   USB_OTG_GINTSTS_ISOODRP_Msk
	Isochronous OUT packet dropped interrupt.
#define	USB_OTG_GINTSTS_EOPF_Pos   (15U)
#define	USB_OTG_GINTSTS_EOPF_Msk   (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
	0x00008000
#define	USB_OTG_GINTSTS_EOPF   USB_OTG_GINTSTS_EOPF_Msk
	End of periodic frame interrupt.
#define	USB_OTG_GINTSTS_IEPINT_Pos   (18U)
#define	USB_OTG_GINTSTS_IEPINT_Msk   (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
	0x00040000
#define	USB_OTG_GINTSTS_IEPINT   USB_OTG_GINTSTS_IEPINT_Msk
	IN endpoint interrupt.
#define	USB_OTG_GINTSTS_OEPINT_Pos   (19U)
#define	USB_OTG_GINTSTS_OEPINT_Msk   (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
	0x00080000
#define	USB_OTG_GINTSTS_OEPINT   USB_OTG_GINTSTS_OEPINT_Msk
	OUT endpoint interrupt.
#define	USB_OTG_GINTSTS_IISOIXFR_Pos   (20U)
#define	USB_OTG_GINTSTS_IISOIXFR_Msk   (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
	0x00100000
#define	USB_OTG_GINTSTS_IISOIXFR   USB_OTG_GINTSTS_IISOIXFR_Msk
	Incomplete isochronous IN transfer.
#define	USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos   (21U)
#define	USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk   (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
	0x00200000
#define	USB_OTG_GINTSTS_PXFR_INCOMPISOOUT   USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
	Incomplete periodic transfer.
#define	USB_OTG_GINTSTS_DATAFSUSP_Pos   (22U)
#define	USB_OTG_GINTSTS_DATAFSUSP_Msk   (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
	0x00400000
#define	USB_OTG_GINTSTS_DATAFSUSP   USB_OTG_GINTSTS_DATAFSUSP_Msk
	Data fetch suspended.
#define	USB_OTG_GINTSTS_RSTDET_Pos   (23U)
#define	USB_OTG_GINTSTS_RSTDET_Msk   (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos)
	0x00800000
#define	USB_OTG_GINTSTS_RSTDET   USB_OTG_GINTSTS_RSTDET_Msk
	Reset detected interrupt.
#define	USB_OTG_GINTSTS_HPRTINT_Pos   (24U)
#define	USB_OTG_GINTSTS_HPRTINT_Msk   (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
	0x01000000
#define	USB_OTG_GINTSTS_HPRTINT   USB_OTG_GINTSTS_HPRTINT_Msk
	Host port interrupt.
#define	USB_OTG_GINTSTS_HCINT_Pos   (25U)
#define	USB_OTG_GINTSTS_HCINT_Msk   (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
	0x02000000
#define	USB_OTG_GINTSTS_HCINT   USB_OTG_GINTSTS_HCINT_Msk
	Host channels interrupt.
#define	USB_OTG_GINTSTS_PTXFE_Pos   (26U)
#define	USB_OTG_GINTSTS_PTXFE_Msk   (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
	0x04000000
#define	USB_OTG_GINTSTS_PTXFE   USB_OTG_GINTSTS_PTXFE_Msk
	Periodic TxFIFO empty.
#define	USB_OTG_GINTSTS_LPMINT_Pos   (27U)
#define	USB_OTG_GINTSTS_LPMINT_Msk   (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos)
	0x08000000
#define	USB_OTG_GINTSTS_LPMINT   USB_OTG_GINTSTS_LPMINT_Msk
	LPM interrupt.
#define	USB_OTG_GINTSTS_CIDSCHG_Pos   (28U)
#define	USB_OTG_GINTSTS_CIDSCHG_Msk   (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
	0x10000000
#define	USB_OTG_GINTSTS_CIDSCHG   USB_OTG_GINTSTS_CIDSCHG_Msk
	Connector ID status change.
#define	USB_OTG_GINTSTS_DISCINT_Pos   (29U)
#define	USB_OTG_GINTSTS_DISCINT_Msk   (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
	0x20000000
#define	USB_OTG_GINTSTS_DISCINT   USB_OTG_GINTSTS_DISCINT_Msk
	Disconnect detected interrupt.
#define	USB_OTG_GINTSTS_SRQINT_Pos   (30U)
#define	USB_OTG_GINTSTS_SRQINT_Msk   (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
	0x40000000
#define	USB_OTG_GINTSTS_SRQINT   USB_OTG_GINTSTS_SRQINT_Msk
	Session request/new session detected interrupt.
#define	USB_OTG_GINTSTS_WKUINT_Pos   (31U)
#define	USB_OTG_GINTSTS_WKUINT_Msk   (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
	0x80000000
#define	USB_OTG_GINTSTS_WKUINT   USB_OTG_GINTSTS_WKUINT_Msk
	Resume/remote wakeup detected interrupt.
#define	USB_OTG_GINTMSK_MMISM_Pos   (1U)
#define	USB_OTG_GINTMSK_MMISM_Msk   (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
	0x00000002
#define	USB_OTG_GINTMSK_MMISM   USB_OTG_GINTMSK_MMISM_Msk
	Mode mismatch interrupt mask.
#define	USB_OTG_GINTMSK_OTGINT_Pos   (2U)
#define	USB_OTG_GINTMSK_OTGINT_Msk   (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
	0x00000004
#define	USB_OTG_GINTMSK_OTGINT   USB_OTG_GINTMSK_OTGINT_Msk
	OTG interrupt mask.
#define	USB_OTG_GINTMSK_SOFM_Pos   (3U)
#define	USB_OTG_GINTMSK_SOFM_Msk   (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
	0x00000008
#define	USB_OTG_GINTMSK_SOFM   USB_OTG_GINTMSK_SOFM_Msk
	Start of frame mask.
#define	USB_OTG_GINTMSK_RXFLVLM_Pos   (4U)
#define	USB_OTG_GINTMSK_RXFLVLM_Msk   (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
	0x00000010
#define	USB_OTG_GINTMSK_RXFLVLM   USB_OTG_GINTMSK_RXFLVLM_Msk
	Receive FIFO nonempty mask.
#define	USB_OTG_GINTMSK_NPTXFEM_Pos   (5U)
#define	USB_OTG_GINTMSK_NPTXFEM_Msk   (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
	0x00000020
#define	USB_OTG_GINTMSK_NPTXFEM   USB_OTG_GINTMSK_NPTXFEM_Msk
	Nonperiodic TxFIFO empty mask.
#define	USB_OTG_GINTMSK_GINAKEFFM_Pos   (6U)
#define	USB_OTG_GINTMSK_GINAKEFFM_Msk   (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
	0x00000040
#define	USB_OTG_GINTMSK_GINAKEFFM   USB_OTG_GINTMSK_GINAKEFFM_Msk
	Global nonperiodic IN NAK effective mask.
#define	USB_OTG_GINTMSK_GONAKEFFM_Pos   (7U)
#define	USB_OTG_GINTMSK_GONAKEFFM_Msk   (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
	0x00000080
#define	USB_OTG_GINTMSK_GONAKEFFM   USB_OTG_GINTMSK_GONAKEFFM_Msk
	Global OUT NAK effective mask.
#define	USB_OTG_GINTMSK_ESUSPM_Pos   (10U)
#define	USB_OTG_GINTMSK_ESUSPM_Msk   (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
	0x00000400
#define	USB_OTG_GINTMSK_ESUSPM   USB_OTG_GINTMSK_ESUSPM_Msk
	Early suspend mask.
#define	USB_OTG_GINTMSK_USBSUSPM_Pos   (11U)
#define	USB_OTG_GINTMSK_USBSUSPM_Msk   (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
	0x00000800
#define	USB_OTG_GINTMSK_USBSUSPM   USB_OTG_GINTMSK_USBSUSPM_Msk
	USB suspend mask.
#define	USB_OTG_GINTMSK_USBRST_Pos   (12U)
#define	USB_OTG_GINTMSK_USBRST_Msk   (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
	0x00001000
#define	USB_OTG_GINTMSK_USBRST   USB_OTG_GINTMSK_USBRST_Msk
	USB reset mask.
#define	USB_OTG_GINTMSK_ENUMDNEM_Pos   (13U)
#define	USB_OTG_GINTMSK_ENUMDNEM_Msk   (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
	0x00002000
#define	USB_OTG_GINTMSK_ENUMDNEM   USB_OTG_GINTMSK_ENUMDNEM_Msk
	Enumeration done mask.
#define	USB_OTG_GINTMSK_ISOODRPM_Pos   (14U)
#define	USB_OTG_GINTMSK_ISOODRPM_Msk   (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
	0x00004000
#define	USB_OTG_GINTMSK_ISOODRPM   USB_OTG_GINTMSK_ISOODRPM_Msk
	Isochronous OUT packet dropped interrupt mask.
#define	USB_OTG_GINTMSK_EOPFM_Pos   (15U)
#define	USB_OTG_GINTMSK_EOPFM_Msk   (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
	0x00008000
#define	USB_OTG_GINTMSK_EOPFM   USB_OTG_GINTMSK_EOPFM_Msk
	End of periodic frame interrupt mask.
#define	USB_OTG_GINTMSK_EPMISM_Pos   (17U)
#define	USB_OTG_GINTMSK_EPMISM_Msk   (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
	0x00020000
#define	USB_OTG_GINTMSK_EPMISM   USB_OTG_GINTMSK_EPMISM_Msk
	Endpoint mismatch interrupt mask.
#define	USB_OTG_GINTMSK_IEPINT_Pos   (18U)
#define	USB_OTG_GINTMSK_IEPINT_Msk   (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
	0x00040000
#define	USB_OTG_GINTMSK_IEPINT   USB_OTG_GINTMSK_IEPINT_Msk
	IN endpoints interrupt mask.
#define	USB_OTG_GINTMSK_OEPINT_Pos   (19U)
#define	USB_OTG_GINTMSK_OEPINT_Msk   (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
	0x00080000
#define	USB_OTG_GINTMSK_OEPINT   USB_OTG_GINTMSK_OEPINT_Msk
	OUT endpoints interrupt mask.
#define	USB_OTG_GINTMSK_IISOIXFRM_Pos   (20U)
#define	USB_OTG_GINTMSK_IISOIXFRM_Msk   (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
	0x00100000
#define	USB_OTG_GINTMSK_IISOIXFRM   USB_OTG_GINTMSK_IISOIXFRM_Msk
	Incomplete isochronous IN transfer mask.
#define	USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos   (21U)
#define	USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk   (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
	0x00200000
#define	USB_OTG_GINTMSK_PXFRM_IISOOXFRM   USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
	Incomplete periodic transfer mask.
#define	USB_OTG_GINTMSK_FSUSPM_Pos   (22U)
#define	USB_OTG_GINTMSK_FSUSPM_Msk   (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
	0x00400000
#define	USB_OTG_GINTMSK_FSUSPM   USB_OTG_GINTMSK_FSUSPM_Msk
	Data fetch suspended mask.
#define	USB_OTG_GINTMSK_RSTDEM_Pos   (23U)
#define	USB_OTG_GINTMSK_RSTDEM_Msk   (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos)
	0x00800000
#define	USB_OTG_GINTMSK_RSTDEM   USB_OTG_GINTMSK_RSTDEM_Msk
	Reset detected interrupt mask.
#define	USB_OTG_GINTMSK_PRTIM_Pos   (24U)
#define	USB_OTG_GINTMSK_PRTIM_Msk   (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
	0x01000000
#define	USB_OTG_GINTMSK_PRTIM   USB_OTG_GINTMSK_PRTIM_Msk
	Host port interrupt mask.
#define	USB_OTG_GINTMSK_HCIM_Pos   (25U)
#define	USB_OTG_GINTMSK_HCIM_Msk   (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
	0x02000000
#define	USB_OTG_GINTMSK_HCIM   USB_OTG_GINTMSK_HCIM_Msk
	Host channels interrupt mask.
#define	USB_OTG_GINTMSK_PTXFEM_Pos   (26U)
#define	USB_OTG_GINTMSK_PTXFEM_Msk   (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
	0x04000000
#define	USB_OTG_GINTMSK_PTXFEM   USB_OTG_GINTMSK_PTXFEM_Msk
	Periodic TxFIFO empty mask.
#define	USB_OTG_GINTMSK_LPMINTM_Pos   (27U)
#define	USB_OTG_GINTMSK_LPMINTM_Msk   (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos)
	0x08000000
#define	USB_OTG_GINTMSK_LPMINTM   USB_OTG_GINTMSK_LPMINTM_Msk
	LPM interrupt Mask.
#define	USB_OTG_GINTMSK_CIDSCHGM_Pos   (28U)
#define	USB_OTG_GINTMSK_CIDSCHGM_Msk   (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
	0x10000000
#define	USB_OTG_GINTMSK_CIDSCHGM   USB_OTG_GINTMSK_CIDSCHGM_Msk
	Connector ID status change mask.
#define	USB_OTG_GINTMSK_DISCINT_Pos   (29U)
#define	USB_OTG_GINTMSK_DISCINT_Msk   (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
	0x20000000
#define	USB_OTG_GINTMSK_DISCINT   USB_OTG_GINTMSK_DISCINT_Msk
	Disconnect detected interrupt mask.
#define	USB_OTG_GINTMSK_SRQIM_Pos   (30U)
#define	USB_OTG_GINTMSK_SRQIM_Msk   (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
	0x40000000
#define	USB_OTG_GINTMSK_SRQIM   USB_OTG_GINTMSK_SRQIM_Msk
	Session request/new session detected interrupt mask.
#define	USB_OTG_GINTMSK_WUIM_Pos   (31U)
#define	USB_OTG_GINTMSK_WUIM_Msk   (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
	0x80000000
#define	USB_OTG_GINTMSK_WUIM   USB_OTG_GINTMSK_WUIM_Msk
	Resume/remote wakeup detected interrupt mask.
#define	USB_OTG_DAINT_IEPINT_Pos   (0U)
#define	USB_OTG_DAINT_IEPINT_Msk   (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
	0x0000FFFF
#define	USB_OTG_DAINT_IEPINT   USB_OTG_DAINT_IEPINT_Msk
	IN endpoint interrupt bits.
#define	USB_OTG_DAINT_OEPINT_Pos   (16U)
#define	USB_OTG_DAINT_OEPINT_Msk   (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
	0xFFFF0000
#define	USB_OTG_DAINT_OEPINT   USB_OTG_DAINT_OEPINT_Msk
	OUT endpoint interrupt bits.
#define	USB_OTG_HAINTMSK_HAINTM_Pos   (0U)
#define	USB_OTG_HAINTMSK_HAINTM_Msk   (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
	0x0000FFFF
#define	USB_OTG_HAINTMSK_HAINTM   USB_OTG_HAINTMSK_HAINTM_Msk
	Channel interrupt mask.
#define	USB_OTG_GRXSTSP_EPNUM_Pos   (0U)
#define	USB_OTG_GRXSTSP_EPNUM_Msk   (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
	0x0000000F
#define	USB_OTG_GRXSTSP_EPNUM   USB_OTG_GRXSTSP_EPNUM_Msk
	IN EP interrupt mask bits.
#define	USB_OTG_GRXSTSP_BCNT_Pos   (4U)
#define	USB_OTG_GRXSTSP_BCNT_Msk   (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
	0x00007FF0
#define	USB_OTG_GRXSTSP_BCNT   USB_OTG_GRXSTSP_BCNT_Msk
	OUT EP interrupt mask bits.
#define	USB_OTG_GRXSTSP_DPID_Pos   (15U)
#define	USB_OTG_GRXSTSP_DPID_Msk   (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
	0x00018000
#define	USB_OTG_GRXSTSP_DPID   USB_OTG_GRXSTSP_DPID_Msk
	OUT EP interrupt mask bits.
#define	USB_OTG_GRXSTSP_PKTSTS_Pos   (17U)
#define	USB_OTG_GRXSTSP_PKTSTS_Msk   (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
	0x001E0000
#define	USB_OTG_GRXSTSP_PKTSTS   USB_OTG_GRXSTSP_PKTSTS_Msk
	OUT EP interrupt mask bits.
#define	USB_OTG_DAINTMSK_IEPM_Pos   (0U)
#define	USB_OTG_DAINTMSK_IEPM_Msk   (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
	0x0000FFFF
#define	USB_OTG_DAINTMSK_IEPM   USB_OTG_DAINTMSK_IEPM_Msk
	IN EP interrupt mask bits.
#define	USB_OTG_DAINTMSK_OEPM_Pos   (16U)
#define	USB_OTG_DAINTMSK_OEPM_Msk   (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
	0xFFFF0000
#define	USB_OTG_DAINTMSK_OEPM   USB_OTG_DAINTMSK_OEPM_Msk
	OUT EP interrupt mask bits.
#define	USB_OTG_CHNUM_Pos   (0U)
#define	USB_OTG_CHNUM_Msk   (0xFUL << USB_OTG_CHNUM_Pos)
	0x0000000F
#define	USB_OTG_CHNUM   USB_OTG_CHNUM_Msk
	Channel number.
#define	USB_OTG_CHNUM_0   (0x1UL << USB_OTG_CHNUM_Pos)
	0x00000001
#define	USB_OTG_CHNUM_1   (0x2UL << USB_OTG_CHNUM_Pos)
	0x00000002
#define	USB_OTG_CHNUM_2   (0x4UL << USB_OTG_CHNUM_Pos)
	0x00000004
#define	USB_OTG_CHNUM_3   (0x8UL << USB_OTG_CHNUM_Pos)
	0x00000008
#define	USB_OTG_BCNT_Pos   (4U)
#define	USB_OTG_BCNT_Msk   (0x7FFUL << USB_OTG_BCNT_Pos)
	0x00007FF0
#define	USB_OTG_BCNT   USB_OTG_BCNT_Msk
	Byte count.
#define	USB_OTG_DPID_Pos   (15U)
#define	USB_OTG_DPID_Msk   (0x3UL << USB_OTG_DPID_Pos)
	0x00018000
#define	USB_OTG_DPID   USB_OTG_DPID_Msk
	Data PID.
#define	USB_OTG_DPID_0   (0x1UL << USB_OTG_DPID_Pos)
	0x00008000
#define	USB_OTG_DPID_1   (0x2UL << USB_OTG_DPID_Pos)
	0x00010000
#define	USB_OTG_PKTSTS_Pos   (17U)
#define	USB_OTG_PKTSTS_Msk   (0xFUL << USB_OTG_PKTSTS_Pos)
	0x001E0000
#define	USB_OTG_PKTSTS   USB_OTG_PKTSTS_Msk
	Packet status.
#define	USB_OTG_PKTSTS_0   (0x1UL << USB_OTG_PKTSTS_Pos)
	0x00020000
#define	USB_OTG_PKTSTS_1   (0x2UL << USB_OTG_PKTSTS_Pos)
	0x00040000
#define	USB_OTG_PKTSTS_2   (0x4UL << USB_OTG_PKTSTS_Pos)
	0x00080000
#define	USB_OTG_PKTSTS_3   (0x8UL << USB_OTG_PKTSTS_Pos)
	0x00100000
#define	USB_OTG_EPNUM_Pos   (0U)
#define	USB_OTG_EPNUM_Msk   (0xFUL << USB_OTG_EPNUM_Pos)
	0x0000000F
#define	USB_OTG_EPNUM   USB_OTG_EPNUM_Msk
	Endpoint number.
#define	USB_OTG_EPNUM_0   (0x1UL << USB_OTG_EPNUM_Pos)
	0x00000001
#define	USB_OTG_EPNUM_1   (0x2UL << USB_OTG_EPNUM_Pos)
	0x00000002
#define	USB_OTG_EPNUM_2   (0x4UL << USB_OTG_EPNUM_Pos)
	0x00000004
#define	USB_OTG_EPNUM_3   (0x8UL << USB_OTG_EPNUM_Pos)
	0x00000008
#define	USB_OTG_FRMNUM_Pos   (21U)
#define	USB_OTG_FRMNUM_Msk   (0xFUL << USB_OTG_FRMNUM_Pos)
	0x01E00000
#define	USB_OTG_FRMNUM   USB_OTG_FRMNUM_Msk
	Frame number.
#define	USB_OTG_FRMNUM_0   (0x1UL << USB_OTG_FRMNUM_Pos)
	0x00200000
#define	USB_OTG_FRMNUM_1   (0x2UL << USB_OTG_FRMNUM_Pos)
	0x00400000
#define	USB_OTG_FRMNUM_2   (0x4UL << USB_OTG_FRMNUM_Pos)
	0x00800000
#define	USB_OTG_FRMNUM_3   (0x8UL << USB_OTG_FRMNUM_Pos)
	0x01000000
#define	USB_OTG_GRXFSIZ_RXFD_Pos   (0U)
#define	USB_OTG_GRXFSIZ_RXFD_Msk   (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
	0x0000FFFF
#define	USB_OTG_GRXFSIZ_RXFD   USB_OTG_GRXFSIZ_RXFD_Msk
	RxFIFO depth.
#define	USB_OTG_DVBUSDIS_VBUSDT_Pos   (0U)
#define	USB_OTG_DVBUSDIS_VBUSDT_Msk   (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
	0x0000FFFF
#define	USB_OTG_DVBUSDIS_VBUSDT   USB_OTG_DVBUSDIS_VBUSDT_Msk
	Device VBUS discharge time.
#define	USB_OTG_NPTXFSA_Pos   (0U)
#define	USB_OTG_NPTXFSA_Msk   (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
	0x0000FFFF
#define	USB_OTG_NPTXFSA   USB_OTG_NPTXFSA_Msk
	Nonperiodic transmit RAM start address.
#define	USB_OTG_NPTXFD_Pos   (16U)
#define	USB_OTG_NPTXFD_Msk   (0xFFFFUL << USB_OTG_NPTXFD_Pos)
	0xFFFF0000
#define	USB_OTG_NPTXFD   USB_OTG_NPTXFD_Msk
	Nonperiodic TxFIFO depth.
#define	USB_OTG_TX0FSA_Pos   (0U)
#define	USB_OTG_TX0FSA_Msk   (0xFFFFUL << USB_OTG_TX0FSA_Pos)
	0x0000FFFF
#define	USB_OTG_TX0FSA   USB_OTG_TX0FSA_Msk
	Endpoint 0 transmit RAM start address.
#define	USB_OTG_TX0FD_Pos   (16U)
#define	USB_OTG_TX0FD_Msk   (0xFFFFUL << USB_OTG_TX0FD_Pos)
	0xFFFF0000
#define	USB_OTG_TX0FD   USB_OTG_TX0FD_Msk
	Endpoint 0 TxFIFO depth.
#define	USB_OTG_DVBUSPULSE_DVBUSP_Pos   (0U)
#define	USB_OTG_DVBUSPULSE_DVBUSP_Msk   (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
	0x00000FFF
#define	USB_OTG_DVBUSPULSE_DVBUSP   USB_OTG_DVBUSPULSE_DVBUSP_Msk
	Device VBUS pulsing time.
#define	USB_OTG_GNPTXSTS_NPTXFSAV_Pos   (0U)
#define	USB_OTG_GNPTXSTS_NPTXFSAV_Msk   (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
	0x0000FFFF
#define	USB_OTG_GNPTXSTS_NPTXFSAV   USB_OTG_GNPTXSTS_NPTXFSAV_Msk
	Nonperiodic TxFIFO space available.
#define	USB_OTG_GNPTXSTS_NPTQXSAV_Pos   (16U)
#define	USB_OTG_GNPTXSTS_NPTQXSAV_Msk   (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
	0x00FF0000
#define	USB_OTG_GNPTXSTS_NPTQXSAV   USB_OTG_GNPTXSTS_NPTQXSAV_Msk
	Nonperiodic transmit request queue space available.
#define	USB_OTG_GNPTXSTS_NPTQXSAV_0   (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
	0x00010000
#define	USB_OTG_GNPTXSTS_NPTQXSAV_1   (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
	0x00020000
#define	USB_OTG_GNPTXSTS_NPTQXSAV_2   (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
	0x00040000
#define	USB_OTG_GNPTXSTS_NPTQXSAV_3   (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
	0x00080000
#define	USB_OTG_GNPTXSTS_NPTQXSAV_4   (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
	0x00100000
#define	USB_OTG_GNPTXSTS_NPTQXSAV_5   (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
	0x00200000
#define	USB_OTG_GNPTXSTS_NPTQXSAV_6   (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
	0x00400000
#define	USB_OTG_GNPTXSTS_NPTQXSAV_7   (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
	0x00800000
#define	USB_OTG_GNPTXSTS_NPTXQTOP_Pos   (24U)
#define	USB_OTG_GNPTXSTS_NPTXQTOP_Msk   (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
	0x7F000000
#define	USB_OTG_GNPTXSTS_NPTXQTOP   USB_OTG_GNPTXSTS_NPTXQTOP_Msk
	Top of the nonperiodic transmit request queue.
#define	USB_OTG_GNPTXSTS_NPTXQTOP_0   (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
	0x01000000
#define	USB_OTG_GNPTXSTS_NPTXQTOP_1   (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
	0x02000000
#define	USB_OTG_GNPTXSTS_NPTXQTOP_2   (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
	0x04000000
#define	USB_OTG_GNPTXSTS_NPTXQTOP_3   (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
	0x08000000
#define	USB_OTG_GNPTXSTS_NPTXQTOP_4   (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
	0x10000000
#define	USB_OTG_GNPTXSTS_NPTXQTOP_5   (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
	0x20000000
#define	USB_OTG_GNPTXSTS_NPTXQTOP_6   (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
	0x40000000
#define	USB_OTG_DTHRCTL_NONISOTHREN_Pos   (0U)
#define	USB_OTG_DTHRCTL_NONISOTHREN_Msk   (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
	0x00000001
#define	USB_OTG_DTHRCTL_NONISOTHREN   USB_OTG_DTHRCTL_NONISOTHREN_Msk
	Nonisochronous IN endpoints threshold enable.
#define	USB_OTG_DTHRCTL_ISOTHREN_Pos   (1U)
#define	USB_OTG_DTHRCTL_ISOTHREN_Msk   (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
	0x00000002
#define	USB_OTG_DTHRCTL_ISOTHREN   USB_OTG_DTHRCTL_ISOTHREN_Msk
	ISO IN endpoint threshold enable.
#define	USB_OTG_DTHRCTL_TXTHRLEN_Pos   (2U)
#define	USB_OTG_DTHRCTL_TXTHRLEN_Msk   (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
	0x000007FC
#define	USB_OTG_DTHRCTL_TXTHRLEN   USB_OTG_DTHRCTL_TXTHRLEN_Msk
	Transmit threshold length.
#define	USB_OTG_DTHRCTL_TXTHRLEN_0   (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
	0x00000004
#define	USB_OTG_DTHRCTL_TXTHRLEN_1   (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
	0x00000008
#define	USB_OTG_DTHRCTL_TXTHRLEN_2   (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
	0x00000010
#define	USB_OTG_DTHRCTL_TXTHRLEN_3   (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
	0x00000020
#define	USB_OTG_DTHRCTL_TXTHRLEN_4   (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
	0x00000040
#define	USB_OTG_DTHRCTL_TXTHRLEN_5   (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
	0x00000080
#define	USB_OTG_DTHRCTL_TXTHRLEN_6   (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
	0x00000100
#define	USB_OTG_DTHRCTL_TXTHRLEN_7   (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
	0x00000200
#define	USB_OTG_DTHRCTL_TXTHRLEN_8   (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
	0x00000400
#define	USB_OTG_DTHRCTL_RXTHREN_Pos   (16U)
#define	USB_OTG_DTHRCTL_RXTHREN_Msk   (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
	0x00010000
#define	USB_OTG_DTHRCTL_RXTHREN   USB_OTG_DTHRCTL_RXTHREN_Msk
	Receive threshold enable.
#define	USB_OTG_DTHRCTL_RXTHRLEN_Pos   (17U)
#define	USB_OTG_DTHRCTL_RXTHRLEN_Msk   (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
	0x03FE0000
#define	USB_OTG_DTHRCTL_RXTHRLEN   USB_OTG_DTHRCTL_RXTHRLEN_Msk
	Receive threshold length.
#define	USB_OTG_DTHRCTL_RXTHRLEN_0   (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
	0x00020000
#define	USB_OTG_DTHRCTL_RXTHRLEN_1   (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
	0x00040000
#define	USB_OTG_DTHRCTL_RXTHRLEN_2   (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
	0x00080000
#define	USB_OTG_DTHRCTL_RXTHRLEN_3   (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
	0x00100000
#define	USB_OTG_DTHRCTL_RXTHRLEN_4   (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
	0x00200000
#define	USB_OTG_DTHRCTL_RXTHRLEN_5   (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
	0x00400000
#define	USB_OTG_DTHRCTL_RXTHRLEN_6   (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
	0x00800000
#define	USB_OTG_DTHRCTL_RXTHRLEN_7   (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
	0x01000000
#define	USB_OTG_DTHRCTL_RXTHRLEN_8   (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
	0x02000000
#define	USB_OTG_DTHRCTL_ARPEN_Pos   (27U)
#define	USB_OTG_DTHRCTL_ARPEN_Msk   (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
	0x08000000
#define	USB_OTG_DTHRCTL_ARPEN   USB_OTG_DTHRCTL_ARPEN_Msk
	Arbiter parking enable.
#define	USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos   (0U)
#define	USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk   (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
	0x0000FFFF
#define	USB_OTG_DIEPEMPMSK_INEPTXFEM   USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
	IN EP Tx FIFO empty interrupt mask bits.
#define	USB_OTG_DEACHINT_IEP1INT_Pos   (1U)
#define	USB_OTG_DEACHINT_IEP1INT_Msk   (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
	0x00000002
#define	USB_OTG_DEACHINT_IEP1INT   USB_OTG_DEACHINT_IEP1INT_Msk
	IN endpoint 1interrupt bit.
#define	USB_OTG_DEACHINT_OEP1INT_Pos   (17U)
#define	USB_OTG_DEACHINT_OEP1INT_Msk   (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
	0x00020000
#define	USB_OTG_DEACHINT_OEP1INT   USB_OTG_DEACHINT_OEP1INT_Msk
	OUT endpoint 1 interrupt bit.
#define	USB_OTG_GCCFG_DCDET_Pos   (0U)
#define	USB_OTG_GCCFG_DCDET_Msk   (0x1UL << USB_OTG_GCCFG_DCDET_Pos)
	0x00000001
#define	USB_OTG_GCCFG_DCDET   USB_OTG_GCCFG_DCDET_Msk
	Data contact detection (DCD) status.
#define	USB_OTG_GCCFG_PDET_Pos   (1U)
#define	USB_OTG_GCCFG_PDET_Msk   (0x1UL << USB_OTG_GCCFG_PDET_Pos)
	0x00000002
#define	USB_OTG_GCCFG_PDET   USB_OTG_GCCFG_PDET_Msk
	Primary detection (PD) status.
#define	USB_OTG_GCCFG_SDET_Pos   (2U)
#define	USB_OTG_GCCFG_SDET_Msk   (0x1UL << USB_OTG_GCCFG_SDET_Pos)
	0x00000004
#define	USB_OTG_GCCFG_SDET   USB_OTG_GCCFG_SDET_Msk
	Secondary detection (SD) status.
#define	USB_OTG_GCCFG_PS2DET_Pos   (3U)
#define	USB_OTG_GCCFG_PS2DET_Msk   (0x1UL << USB_OTG_GCCFG_PS2DET_Pos)
	0x00000008
#define	USB_OTG_GCCFG_PS2DET   USB_OTG_GCCFG_PS2DET_Msk
	DM pull-up detection status.
#define	USB_OTG_GCCFG_PWRDWN_Pos   (16U)
#define	USB_OTG_GCCFG_PWRDWN_Msk   (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
	0x00010000
#define	USB_OTG_GCCFG_PWRDWN   USB_OTG_GCCFG_PWRDWN_Msk
	Power down.
#define	USB_OTG_GCCFG_BCDEN_Pos   (17U)
#define	USB_OTG_GCCFG_BCDEN_Msk   (0x1UL << USB_OTG_GCCFG_BCDEN_Pos)
	0x00020000
#define	USB_OTG_GCCFG_BCDEN   USB_OTG_GCCFG_BCDEN_Msk
	Battery charging detector (BCD) enable.
#define	USB_OTG_GCCFG_DCDEN_Pos   (18U)
#define	USB_OTG_GCCFG_DCDEN_Msk   (0x1UL << USB_OTG_GCCFG_DCDEN_Pos)
	0x00040000
#define	USB_OTG_GCCFG_DCDEN   USB_OTG_GCCFG_DCDEN_Msk
	Data contact detection (DCD) mode enable.
#define	USB_OTG_GCCFG_PDEN_Pos   (19U)
#define	USB_OTG_GCCFG_PDEN_Msk   (0x1UL << USB_OTG_GCCFG_PDEN_Pos)
	0x00080000
#define	USB_OTG_GCCFG_PDEN   USB_OTG_GCCFG_PDEN_Msk
	Primary detection (PD) mode enable.
#define	USB_OTG_GCCFG_SDEN_Pos   (20U)
#define	USB_OTG_GCCFG_SDEN_Msk   (0x1UL << USB_OTG_GCCFG_SDEN_Pos)
	0x00100000
#define	USB_OTG_GCCFG_SDEN   USB_OTG_GCCFG_SDEN_Msk
	Secondary detection (SD) mode enable.
#define	USB_OTG_GCCFG_VBDEN_Pos   (21U)
#define	USB_OTG_GCCFG_VBDEN_Msk   (0x1UL << USB_OTG_GCCFG_VBDEN_Pos)
	0x00200000
#define	USB_OTG_GCCFG_VBDEN   USB_OTG_GCCFG_VBDEN_Msk
	Secondary detection (SD) mode enable.
#define	USB_OTG_GPWRDN_ADPMEN_Pos   (0U)
#define	USB_OTG_GPWRDN_ADPMEN_Msk   (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos)
	0x00000001
#define	USB_OTG_GPWRDN_ADPMEN   USB_OTG_GPWRDN_ADPMEN_Msk
	ADP module enable.
#define	USB_OTG_GPWRDN_ADPIF_Pos   (23U)
#define	USB_OTG_GPWRDN_ADPIF_Msk   (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos)
	0x00800000
#define	USB_OTG_GPWRDN_ADPIF   USB_OTG_GPWRDN_ADPIF_Msk
	ADP Interrupt flag.
#define	USB_OTG_DEACHINTMSK_IEP1INTM_Pos   (1U)
#define	USB_OTG_DEACHINTMSK_IEP1INTM_Msk   (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
	0x00000002
#define	USB_OTG_DEACHINTMSK_IEP1INTM   USB_OTG_DEACHINTMSK_IEP1INTM_Msk
	IN Endpoint 1 interrupt mask bit.
#define	USB_OTG_DEACHINTMSK_OEP1INTM_Pos   (17U)
#define	USB_OTG_DEACHINTMSK_OEP1INTM_Msk   (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
	0x00020000
#define	USB_OTG_DEACHINTMSK_OEP1INTM   USB_OTG_DEACHINTMSK_OEP1INTM_Msk
	OUT Endpoint 1 interrupt mask bit.
#define	USB_OTG_CID_PRODUCT_ID_Pos   (0U)
#define	USB_OTG_CID_PRODUCT_ID_Msk   (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
	0xFFFFFFFF
#define	USB_OTG_CID_PRODUCT_ID   USB_OTG_CID_PRODUCT_ID_Msk
	Product ID field.
#define	USB_OTG_GLPMCFG_LPMEN_Pos   (0U)
#define	USB_OTG_GLPMCFG_LPMEN_Msk   (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos)
	0x00000001
#define	USB_OTG_GLPMCFG_LPMEN   USB_OTG_GLPMCFG_LPMEN_Msk
	LPM support enable.
#define	USB_OTG_GLPMCFG_LPMACK_Pos   (1U)
#define	USB_OTG_GLPMCFG_LPMACK_Msk   (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos)
	0x00000002
#define	USB_OTG_GLPMCFG_LPMACK   USB_OTG_GLPMCFG_LPMACK_Msk
	LPM Token acknowledge enable.
#define	USB_OTG_GLPMCFG_BESL_Pos   (2U)
#define	USB_OTG_GLPMCFG_BESL_Msk   (0xFUL << USB_OTG_GLPMCFG_BESL_Pos)
	0x0000003C
#define	USB_OTG_GLPMCFG_BESL   USB_OTG_GLPMCFG_BESL_Msk
	BESL value received with last ACKed LPM Token.
#define	USB_OTG_GLPMCFG_REMWAKE_Pos   (6U)
#define	USB_OTG_GLPMCFG_REMWAKE_Msk   (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos)
	0x00000040
#define	USB_OTG_GLPMCFG_REMWAKE   USB_OTG_GLPMCFG_REMWAKE_Msk
	bRemoteWake value received with last ACKed LPM Token
#define	USB_OTG_GLPMCFG_L1SSEN_Pos   (7U)
#define	USB_OTG_GLPMCFG_L1SSEN_Msk   (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos)
	0x00000080
#define	USB_OTG_GLPMCFG_L1SSEN   USB_OTG_GLPMCFG_L1SSEN_Msk
	L1 shallow sleep enable.
#define	USB_OTG_GLPMCFG_BESLTHRS_Pos   (8U)
#define	USB_OTG_GLPMCFG_BESLTHRS_Msk   (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos)
	0x00000F00
#define	USB_OTG_GLPMCFG_BESLTHRS   USB_OTG_GLPMCFG_BESLTHRS_Msk
	BESL threshold.
#define	USB_OTG_GLPMCFG_L1DSEN_Pos   (12U)
#define	USB_OTG_GLPMCFG_L1DSEN_Msk   (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos)
	0x00001000
#define	USB_OTG_GLPMCFG_L1DSEN   USB_OTG_GLPMCFG_L1DSEN_Msk
	L1 deep sleep enable.
#define	USB_OTG_GLPMCFG_LPMRSP_Pos   (13U)
#define	USB_OTG_GLPMCFG_LPMRSP_Msk   (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos)
	0x00006000
#define	USB_OTG_GLPMCFG_LPMRSP   USB_OTG_GLPMCFG_LPMRSP_Msk
	LPM response.
#define	USB_OTG_GLPMCFG_SLPSTS_Pos   (15U)
#define	USB_OTG_GLPMCFG_SLPSTS_Msk   (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos)
	0x00008000
#define	USB_OTG_GLPMCFG_SLPSTS   USB_OTG_GLPMCFG_SLPSTS_Msk
	Port sleep status.
#define	USB_OTG_GLPMCFG_L1RSMOK_Pos   (16U)
#define	USB_OTG_GLPMCFG_L1RSMOK_Msk   (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos)
	0x00010000
#define	USB_OTG_GLPMCFG_L1RSMOK   USB_OTG_GLPMCFG_L1RSMOK_Msk
	Sleep State Resume OK.
#define	USB_OTG_GLPMCFG_LPMCHIDX_Pos   (17U)
#define	USB_OTG_GLPMCFG_LPMCHIDX_Msk   (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos)
	0x001E0000
#define	USB_OTG_GLPMCFG_LPMCHIDX   USB_OTG_GLPMCFG_LPMCHIDX_Msk
	LPM Channel Index.
#define	USB_OTG_GLPMCFG_LPMRCNT_Pos   (21U)
#define	USB_OTG_GLPMCFG_LPMRCNT_Msk   (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos)
	0x00E00000
#define	USB_OTG_GLPMCFG_LPMRCNT   USB_OTG_GLPMCFG_LPMRCNT_Msk
	LPM retry count.
#define	USB_OTG_GLPMCFG_SNDLPM_Pos   (24U)
#define	USB_OTG_GLPMCFG_SNDLPM_Msk   (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos)
	0x01000000
#define	USB_OTG_GLPMCFG_SNDLPM   USB_OTG_GLPMCFG_SNDLPM_Msk
	Send LPM transaction.
#define	USB_OTG_GLPMCFG_LPMRCNTSTS_Pos   (25U)
#define	USB_OTG_GLPMCFG_LPMRCNTSTS_Msk   (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos)
	0x0E000000
#define	USB_OTG_GLPMCFG_LPMRCNTSTS   USB_OTG_GLPMCFG_LPMRCNTSTS_Msk
	LPM retry count status.
#define	USB_OTG_GLPMCFG_ENBESL_Pos   (28U)
#define	USB_OTG_GLPMCFG_ENBESL_Msk   (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos)
	0x10000000
#define	USB_OTG_GLPMCFG_ENBESL   USB_OTG_GLPMCFG_ENBESL_Msk
	Enable best effort service latency.
#define	USB_OTG_DIEPEACHMSK1_XFRCM_Pos   (0U)
#define	USB_OTG_DIEPEACHMSK1_XFRCM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
	0x00000001
#define	USB_OTG_DIEPEACHMSK1_XFRCM   USB_OTG_DIEPEACHMSK1_XFRCM_Msk
	Transfer completed interrupt mask.
#define	USB_OTG_DIEPEACHMSK1_EPDM_Pos   (1U)
#define	USB_OTG_DIEPEACHMSK1_EPDM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
	0x00000002
#define	USB_OTG_DIEPEACHMSK1_EPDM   USB_OTG_DIEPEACHMSK1_EPDM_Msk
	Endpoint disabled interrupt mask.
#define	USB_OTG_DIEPEACHMSK1_TOM_Pos   (3U)
#define	USB_OTG_DIEPEACHMSK1_TOM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
	0x00000008
#define	USB_OTG_DIEPEACHMSK1_TOM   USB_OTG_DIEPEACHMSK1_TOM_Msk
	Timeout condition mask (nonisochronous endpoints).
#define	USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos   (4U)
#define	USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
	0x00000010
#define	USB_OTG_DIEPEACHMSK1_ITTXFEMSK   USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
	IN token received when TxFIFO empty mask.
#define	USB_OTG_DIEPEACHMSK1_INEPNMM_Pos   (5U)
#define	USB_OTG_DIEPEACHMSK1_INEPNMM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
	0x00000020
#define	USB_OTG_DIEPEACHMSK1_INEPNMM   USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
	IN token received with EP mismatch mask.
#define	USB_OTG_DIEPEACHMSK1_INEPNEM_Pos   (6U)
#define	USB_OTG_DIEPEACHMSK1_INEPNEM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
	0x00000040
#define	USB_OTG_DIEPEACHMSK1_INEPNEM   USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
	IN endpoint NAK effective mask.
#define	USB_OTG_DIEPEACHMSK1_TXFURM_Pos   (8U)
#define	USB_OTG_DIEPEACHMSK1_TXFURM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
	0x00000100
#define	USB_OTG_DIEPEACHMSK1_TXFURM   USB_OTG_DIEPEACHMSK1_TXFURM_Msk
	FIFO underrun mask.
#define	USB_OTG_DIEPEACHMSK1_BIM_Pos   (9U)
#define	USB_OTG_DIEPEACHMSK1_BIM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
	0x00000200
#define	USB_OTG_DIEPEACHMSK1_BIM   USB_OTG_DIEPEACHMSK1_BIM_Msk
	BNA interrupt mask.
#define	USB_OTG_DIEPEACHMSK1_NAKM_Pos   (13U)
#define	USB_OTG_DIEPEACHMSK1_NAKM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
	0x00002000
#define	USB_OTG_DIEPEACHMSK1_NAKM   USB_OTG_DIEPEACHMSK1_NAKM_Msk
	NAK interrupt mask.
#define	USB_OTG_HPRT_PCSTS_Pos   (0U)
#define	USB_OTG_HPRT_PCSTS_Msk   (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
	0x00000001
#define	USB_OTG_HPRT_PCSTS   USB_OTG_HPRT_PCSTS_Msk
	Port connect status.
#define	USB_OTG_HPRT_PCDET_Pos   (1U)
#define	USB_OTG_HPRT_PCDET_Msk   (0x1UL << USB_OTG_HPRT_PCDET_Pos)
	0x00000002
#define	USB_OTG_HPRT_PCDET   USB_OTG_HPRT_PCDET_Msk
	Port connect detected.
#define	USB_OTG_HPRT_PENA_Pos   (2U)
#define	USB_OTG_HPRT_PENA_Msk   (0x1UL << USB_OTG_HPRT_PENA_Pos)
	0x00000004
#define	USB_OTG_HPRT_PENA   USB_OTG_HPRT_PENA_Msk
	Port enable.
#define	USB_OTG_HPRT_PENCHNG_Pos   (3U)
#define	USB_OTG_HPRT_PENCHNG_Msk   (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
	0x00000008
#define	USB_OTG_HPRT_PENCHNG   USB_OTG_HPRT_PENCHNG_Msk
	Port enable/disable change.
#define	USB_OTG_HPRT_POCA_Pos   (4U)
#define	USB_OTG_HPRT_POCA_Msk   (0x1UL << USB_OTG_HPRT_POCA_Pos)
	0x00000010
#define	USB_OTG_HPRT_POCA   USB_OTG_HPRT_POCA_Msk
	Port overcurrent active.
#define	USB_OTG_HPRT_POCCHNG_Pos   (5U)
#define	USB_OTG_HPRT_POCCHNG_Msk   (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
	0x00000020
#define	USB_OTG_HPRT_POCCHNG   USB_OTG_HPRT_POCCHNG_Msk
	Port overcurrent change.
#define	USB_OTG_HPRT_PRES_Pos   (6U)
#define	USB_OTG_HPRT_PRES_Msk   (0x1UL << USB_OTG_HPRT_PRES_Pos)
	0x00000040
#define	USB_OTG_HPRT_PRES   USB_OTG_HPRT_PRES_Msk
	Port resume.
#define	USB_OTG_HPRT_PSUSP_Pos   (7U)
#define	USB_OTG_HPRT_PSUSP_Msk   (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
	0x00000080
#define	USB_OTG_HPRT_PSUSP   USB_OTG_HPRT_PSUSP_Msk
	Port suspend.
#define	USB_OTG_HPRT_PRST_Pos   (8U)
#define	USB_OTG_HPRT_PRST_Msk   (0x1UL << USB_OTG_HPRT_PRST_Pos)
	0x00000100
#define	USB_OTG_HPRT_PRST   USB_OTG_HPRT_PRST_Msk
	Port reset.
#define	USB_OTG_HPRT_PLSTS_Pos   (10U)
#define	USB_OTG_HPRT_PLSTS_Msk   (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
	0x00000C00
#define	USB_OTG_HPRT_PLSTS   USB_OTG_HPRT_PLSTS_Msk
	Port line status.
#define	USB_OTG_HPRT_PLSTS_0   (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
	0x00000400
#define	USB_OTG_HPRT_PLSTS_1   (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
	0x00000800
#define	USB_OTG_HPRT_PPWR_Pos   (12U)
#define	USB_OTG_HPRT_PPWR_Msk   (0x1UL << USB_OTG_HPRT_PPWR_Pos)
	0x00001000
#define	USB_OTG_HPRT_PPWR   USB_OTG_HPRT_PPWR_Msk
	Port power.
#define	USB_OTG_HPRT_PTCTL_Pos   (13U)
#define	USB_OTG_HPRT_PTCTL_Msk   (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
	0x0001E000
#define	USB_OTG_HPRT_PTCTL   USB_OTG_HPRT_PTCTL_Msk
	Port test control.
#define	USB_OTG_HPRT_PTCTL_0   (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
	0x00002000
#define	USB_OTG_HPRT_PTCTL_1   (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
	0x00004000
#define	USB_OTG_HPRT_PTCTL_2   (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
	0x00008000
#define	USB_OTG_HPRT_PTCTL_3   (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
	0x00010000
#define	USB_OTG_HPRT_PSPD_Pos   (17U)
#define	USB_OTG_HPRT_PSPD_Msk   (0x3UL << USB_OTG_HPRT_PSPD_Pos)
	0x00060000
#define	USB_OTG_HPRT_PSPD   USB_OTG_HPRT_PSPD_Msk
	Port speed.
#define	USB_OTG_HPRT_PSPD_0   (0x1UL << USB_OTG_HPRT_PSPD_Pos)
	0x00020000
#define	USB_OTG_HPRT_PSPD_1   (0x2UL << USB_OTG_HPRT_PSPD_Pos)
	0x00040000
#define	USB_OTG_DOEPEACHMSK1_XFRCM_Pos   (0U)
#define	USB_OTG_DOEPEACHMSK1_XFRCM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
	0x00000001
#define	USB_OTG_DOEPEACHMSK1_XFRCM   USB_OTG_DOEPEACHMSK1_XFRCM_Msk
	Transfer completed interrupt mask.
#define	USB_OTG_DOEPEACHMSK1_EPDM_Pos   (1U)
#define	USB_OTG_DOEPEACHMSK1_EPDM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
	0x00000002
#define	USB_OTG_DOEPEACHMSK1_EPDM   USB_OTG_DOEPEACHMSK1_EPDM_Msk
	Endpoint disabled interrupt mask.
#define	USB_OTG_DOEPEACHMSK1_TOM_Pos   (3U)
#define	USB_OTG_DOEPEACHMSK1_TOM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
	0x00000008
#define	USB_OTG_DOEPEACHMSK1_TOM   USB_OTG_DOEPEACHMSK1_TOM_Msk
	Timeout condition mask.
#define	USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos   (4U)
#define	USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
	0x00000010
#define	USB_OTG_DOEPEACHMSK1_ITTXFEMSK   USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
	IN token received when TxFIFO empty mask.
#define	USB_OTG_DOEPEACHMSK1_INEPNMM_Pos   (5U)
#define	USB_OTG_DOEPEACHMSK1_INEPNMM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
	0x00000020
#define	USB_OTG_DOEPEACHMSK1_INEPNMM   USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
	IN token received with EP mismatch mask.
#define	USB_OTG_DOEPEACHMSK1_INEPNEM_Pos   (6U)
#define	USB_OTG_DOEPEACHMSK1_INEPNEM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
	0x00000040
#define	USB_OTG_DOEPEACHMSK1_INEPNEM   USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
	IN endpoint NAK effective mask.
#define	USB_OTG_DOEPEACHMSK1_TXFURM_Pos   (8U)
#define	USB_OTG_DOEPEACHMSK1_TXFURM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
	0x00000100
#define	USB_OTG_DOEPEACHMSK1_TXFURM   USB_OTG_DOEPEACHMSK1_TXFURM_Msk
	OUT packet error mask.
#define	USB_OTG_DOEPEACHMSK1_BIM_Pos   (9U)
#define	USB_OTG_DOEPEACHMSK1_BIM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
	0x00000200
#define	USB_OTG_DOEPEACHMSK1_BIM   USB_OTG_DOEPEACHMSK1_BIM_Msk
	BNA interrupt mask.
#define	USB_OTG_DOEPEACHMSK1_BERRM_Pos   (12U)
#define	USB_OTG_DOEPEACHMSK1_BERRM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
	0x00001000
#define	USB_OTG_DOEPEACHMSK1_BERRM   USB_OTG_DOEPEACHMSK1_BERRM_Msk
	Bubble error interrupt mask.
#define	USB_OTG_DOEPEACHMSK1_NAKM_Pos   (13U)
#define	USB_OTG_DOEPEACHMSK1_NAKM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
	0x00002000
#define	USB_OTG_DOEPEACHMSK1_NAKM   USB_OTG_DOEPEACHMSK1_NAKM_Msk
	NAK interrupt mask.
#define	USB_OTG_DOEPEACHMSK1_NYETM_Pos   (14U)
#define	USB_OTG_DOEPEACHMSK1_NYETM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
	0x00004000
#define	USB_OTG_DOEPEACHMSK1_NYETM   USB_OTG_DOEPEACHMSK1_NYETM_Msk
	NYET interrupt mask.
#define	USB_OTG_HPTXFSIZ_PTXSA_Pos   (0U)
#define	USB_OTG_HPTXFSIZ_PTXSA_Msk   (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
	0x0000FFFF
#define	USB_OTG_HPTXFSIZ_PTXSA   USB_OTG_HPTXFSIZ_PTXSA_Msk
	Host periodic TxFIFO start address.
#define	USB_OTG_HPTXFSIZ_PTXFD_Pos   (16U)
#define	USB_OTG_HPTXFSIZ_PTXFD_Msk   (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
	0xFFFF0000
#define	USB_OTG_HPTXFSIZ_PTXFD   USB_OTG_HPTXFSIZ_PTXFD_Msk
	Host periodic TxFIFO depth.
#define	USB_OTG_DIEPCTL_MPSIZ_Pos   (0U)
#define	USB_OTG_DIEPCTL_MPSIZ_Msk   (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
	0x000007FF
#define	USB_OTG_DIEPCTL_MPSIZ   USB_OTG_DIEPCTL_MPSIZ_Msk
	Maximum packet size.
#define	USB_OTG_DIEPCTL_USBAEP_Pos   (15U)
#define	USB_OTG_DIEPCTL_USBAEP_Msk   (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
	0x00008000
#define	USB_OTG_DIEPCTL_USBAEP   USB_OTG_DIEPCTL_USBAEP_Msk
	USB active endpoint.
#define	USB_OTG_DIEPCTL_EONUM_DPID_Pos   (16U)
#define	USB_OTG_DIEPCTL_EONUM_DPID_Msk   (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
	0x00010000
#define	USB_OTG_DIEPCTL_EONUM_DPID   USB_OTG_DIEPCTL_EONUM_DPID_Msk
	Even/odd frame.
#define	USB_OTG_DIEPCTL_NAKSTS_Pos   (17U)
#define	USB_OTG_DIEPCTL_NAKSTS_Msk   (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
	0x00020000
#define	USB_OTG_DIEPCTL_NAKSTS   USB_OTG_DIEPCTL_NAKSTS_Msk
	NAK status.
#define	USB_OTG_DIEPCTL_EPTYP_Pos   (18U)
#define	USB_OTG_DIEPCTL_EPTYP_Msk   (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
	0x000C0000
#define	USB_OTG_DIEPCTL_EPTYP   USB_OTG_DIEPCTL_EPTYP_Msk
	Endpoint type.
#define	USB_OTG_DIEPCTL_EPTYP_0   (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
	0x00040000
#define	USB_OTG_DIEPCTL_EPTYP_1   (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
	0x00080000
#define	USB_OTG_DIEPCTL_STALL_Pos   (21U)
#define	USB_OTG_DIEPCTL_STALL_Msk   (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
	0x00200000
#define	USB_OTG_DIEPCTL_STALL   USB_OTG_DIEPCTL_STALL_Msk
	STALL handshake.
#define	USB_OTG_DIEPCTL_TXFNUM_Pos   (22U)
#define	USB_OTG_DIEPCTL_TXFNUM_Msk   (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
	0x03C00000
#define	USB_OTG_DIEPCTL_TXFNUM   USB_OTG_DIEPCTL_TXFNUM_Msk
	TxFIFO number.
#define	USB_OTG_DIEPCTL_TXFNUM_0   (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
	0x00400000
#define	USB_OTG_DIEPCTL_TXFNUM_1   (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
	0x00800000
#define	USB_OTG_DIEPCTL_TXFNUM_2   (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
	0x01000000
#define	USB_OTG_DIEPCTL_TXFNUM_3   (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
	0x02000000
#define	USB_OTG_DIEPCTL_CNAK_Pos   (26U)
#define	USB_OTG_DIEPCTL_CNAK_Msk   (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
	0x04000000
#define	USB_OTG_DIEPCTL_CNAK   USB_OTG_DIEPCTL_CNAK_Msk
	Clear NAK.
#define	USB_OTG_DIEPCTL_SNAK_Pos   (27U)
#define	USB_OTG_DIEPCTL_SNAK_Msk   (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
	0x08000000
#define	USB_OTG_DIEPCTL_SNAK   USB_OTG_DIEPCTL_SNAK_Msk
	Set NAK.
#define	USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos   (28U)
#define	USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk   (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
	0x10000000
#define	USB_OTG_DIEPCTL_SD0PID_SEVNFRM   USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
	Set DATA0 PID.
#define	USB_OTG_DIEPCTL_SODDFRM_Pos   (29U)
#define	USB_OTG_DIEPCTL_SODDFRM_Msk   (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
	0x20000000
#define	USB_OTG_DIEPCTL_SODDFRM   USB_OTG_DIEPCTL_SODDFRM_Msk
	Set odd frame.
#define	USB_OTG_DIEPCTL_EPDIS_Pos   (30U)
#define	USB_OTG_DIEPCTL_EPDIS_Msk   (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
	0x40000000
#define	USB_OTG_DIEPCTL_EPDIS   USB_OTG_DIEPCTL_EPDIS_Msk
	Endpoint disable.
#define	USB_OTG_DIEPCTL_EPENA_Pos   (31U)
#define	USB_OTG_DIEPCTL_EPENA_Msk   (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
	0x80000000
#define	USB_OTG_DIEPCTL_EPENA   USB_OTG_DIEPCTL_EPENA_Msk
	Endpoint enable.
#define	USB_OTG_HCCHAR_MPSIZ_Pos   (0U)
#define	USB_OTG_HCCHAR_MPSIZ_Msk   (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
	0x000007FF
#define	USB_OTG_HCCHAR_MPSIZ   USB_OTG_HCCHAR_MPSIZ_Msk
	Maximum packet size.
#define	USB_OTG_HCCHAR_EPNUM_Pos   (11U)
#define	USB_OTG_HCCHAR_EPNUM_Msk   (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
	0x00007800
#define	USB_OTG_HCCHAR_EPNUM   USB_OTG_HCCHAR_EPNUM_Msk
	Endpoint number.
#define	USB_OTG_HCCHAR_EPNUM_0   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
	0x00000800
#define	USB_OTG_HCCHAR_EPNUM_1   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
	0x00001000
#define	USB_OTG_HCCHAR_EPNUM_2   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
	0x00002000
#define	USB_OTG_HCCHAR_EPNUM_3   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
	0x00004000
#define	USB_OTG_HCCHAR_EPDIR_Pos   (15U)
#define	USB_OTG_HCCHAR_EPDIR_Msk   (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
	0x00008000
#define	USB_OTG_HCCHAR_EPDIR   USB_OTG_HCCHAR_EPDIR_Msk
	Endpoint direction.
#define	USB_OTG_HCCHAR_LSDEV_Pos   (17U)
#define	USB_OTG_HCCHAR_LSDEV_Msk   (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
	0x00020000
#define	USB_OTG_HCCHAR_LSDEV   USB_OTG_HCCHAR_LSDEV_Msk
	Low-speed device.
#define	USB_OTG_HCCHAR_EPTYP_Pos   (18U)
#define	USB_OTG_HCCHAR_EPTYP_Msk   (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
	0x000C0000
#define	USB_OTG_HCCHAR_EPTYP   USB_OTG_HCCHAR_EPTYP_Msk
	Endpoint type.
#define	USB_OTG_HCCHAR_EPTYP_0   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
	0x00040000
#define	USB_OTG_HCCHAR_EPTYP_1   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
	0x00080000
#define	USB_OTG_HCCHAR_MC_Pos   (20U)
#define	USB_OTG_HCCHAR_MC_Msk   (0x3UL << USB_OTG_HCCHAR_MC_Pos)
	0x00300000
#define	USB_OTG_HCCHAR_MC   USB_OTG_HCCHAR_MC_Msk
	Multi Count (MC) / Error Count (EC).
#define	USB_OTG_HCCHAR_MC_0   (0x1UL << USB_OTG_HCCHAR_MC_Pos)
	0x00100000
#define	USB_OTG_HCCHAR_MC_1   (0x2UL << USB_OTG_HCCHAR_MC_Pos)
	0x00200000
#define	USB_OTG_HCCHAR_DAD_Pos   (22U)
#define	USB_OTG_HCCHAR_DAD_Msk   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
	0x1FC00000
#define	USB_OTG_HCCHAR_DAD   USB_OTG_HCCHAR_DAD_Msk
	Device address.
#define	USB_OTG_HCCHAR_DAD_0   (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
	0x00400000
#define	USB_OTG_HCCHAR_DAD_1   (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
	0x00800000
#define	USB_OTG_HCCHAR_DAD_2   (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
	0x01000000
#define	USB_OTG_HCCHAR_DAD_3   (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
	0x02000000
#define	USB_OTG_HCCHAR_DAD_4   (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
	0x04000000
#define	USB_OTG_HCCHAR_DAD_5   (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
	0x08000000
#define	USB_OTG_HCCHAR_DAD_6   (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
	0x10000000
#define	USB_OTG_HCCHAR_ODDFRM_Pos   (29U)
#define	USB_OTG_HCCHAR_ODDFRM_Msk   (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
	0x20000000
#define	USB_OTG_HCCHAR_ODDFRM   USB_OTG_HCCHAR_ODDFRM_Msk
	Odd frame.
#define	USB_OTG_HCCHAR_CHDIS_Pos   (30U)
#define	USB_OTG_HCCHAR_CHDIS_Msk   (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
	0x40000000
#define	USB_OTG_HCCHAR_CHDIS   USB_OTG_HCCHAR_CHDIS_Msk
	Channel disable.
#define	USB_OTG_HCCHAR_CHENA_Pos   (31U)
#define	USB_OTG_HCCHAR_CHENA_Msk   (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
	0x80000000
#define	USB_OTG_HCCHAR_CHENA   USB_OTG_HCCHAR_CHENA_Msk
	Channel enable.
#define	USB_OTG_HCSPLT_PRTADDR_Pos   (0U)
#define	USB_OTG_HCSPLT_PRTADDR_Msk   (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
	0x0000007F
#define	USB_OTG_HCSPLT_PRTADDR   USB_OTG_HCSPLT_PRTADDR_Msk
	Port address.
#define	USB_OTG_HCSPLT_PRTADDR_0   (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
	0x00000001
#define	USB_OTG_HCSPLT_PRTADDR_1   (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
	0x00000002
#define	USB_OTG_HCSPLT_PRTADDR_2   (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
	0x00000004
#define	USB_OTG_HCSPLT_PRTADDR_3   (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
	0x00000008
#define	USB_OTG_HCSPLT_PRTADDR_4   (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
	0x00000010
#define	USB_OTG_HCSPLT_PRTADDR_5   (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
	0x00000020
#define	USB_OTG_HCSPLT_PRTADDR_6   (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
	0x00000040
#define	USB_OTG_HCSPLT_HUBADDR_Pos   (7U)
#define	USB_OTG_HCSPLT_HUBADDR_Msk   (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
	0x00003F80
#define	USB_OTG_HCSPLT_HUBADDR   USB_OTG_HCSPLT_HUBADDR_Msk
	Hub address.
#define	USB_OTG_HCSPLT_HUBADDR_0   (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
	0x00000080
#define	USB_OTG_HCSPLT_HUBADDR_1   (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
	0x00000100
#define	USB_OTG_HCSPLT_HUBADDR_2   (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
	0x00000200
#define	USB_OTG_HCSPLT_HUBADDR_3   (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
	0x00000400
#define	USB_OTG_HCSPLT_HUBADDR_4   (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
	0x00000800
#define	USB_OTG_HCSPLT_HUBADDR_5   (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
	0x00001000
#define	USB_OTG_HCSPLT_HUBADDR_6   (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
	0x00002000
#define	USB_OTG_HCSPLT_XACTPOS_Pos   (14U)
#define	USB_OTG_HCSPLT_XACTPOS_Msk   (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
	0x0000C000
#define	USB_OTG_HCSPLT_XACTPOS   USB_OTG_HCSPLT_XACTPOS_Msk
	XACTPOS.
#define	USB_OTG_HCSPLT_XACTPOS_0   (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
	0x00004000
#define	USB_OTG_HCSPLT_XACTPOS_1   (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
	0x00008000
#define	USB_OTG_HCSPLT_COMPLSPLT_Pos   (16U)
#define	USB_OTG_HCSPLT_COMPLSPLT_Msk   (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
	0x00010000
#define	USB_OTG_HCSPLT_COMPLSPLT   USB_OTG_HCSPLT_COMPLSPLT_Msk
	Do complete split.
#define	USB_OTG_HCSPLT_SPLITEN_Pos   (31U)
#define	USB_OTG_HCSPLT_SPLITEN_Msk   (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
	0x80000000
#define	USB_OTG_HCSPLT_SPLITEN   USB_OTG_HCSPLT_SPLITEN_Msk
	Split enable.
#define	USB_OTG_HCINT_XFRC_Pos   (0U)
#define	USB_OTG_HCINT_XFRC_Msk   (0x1UL << USB_OTG_HCINT_XFRC_Pos)
	0x00000001
#define	USB_OTG_HCINT_XFRC   USB_OTG_HCINT_XFRC_Msk
	Transfer completed.
#define	USB_OTG_HCINT_CHH_Pos   (1U)
#define	USB_OTG_HCINT_CHH_Msk   (0x1UL << USB_OTG_HCINT_CHH_Pos)
	0x00000002
#define	USB_OTG_HCINT_CHH   USB_OTG_HCINT_CHH_Msk
	Channel halted.
#define	USB_OTG_HCINT_AHBERR_Pos   (2U)
#define	USB_OTG_HCINT_AHBERR_Msk   (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
	0x00000004
#define	USB_OTG_HCINT_AHBERR   USB_OTG_HCINT_AHBERR_Msk
	AHB error.
#define	USB_OTG_HCINT_STALL_Pos   (3U)
#define	USB_OTG_HCINT_STALL_Msk   (0x1UL << USB_OTG_HCINT_STALL_Pos)
	0x00000008
#define	USB_OTG_HCINT_STALL   USB_OTG_HCINT_STALL_Msk
	STALL response received interrupt.
#define	USB_OTG_HCINT_NAK_Pos   (4U)
#define	USB_OTG_HCINT_NAK_Msk   (0x1UL << USB_OTG_HCINT_NAK_Pos)
	0x00000010
#define	USB_OTG_HCINT_NAK   USB_OTG_HCINT_NAK_Msk
	NAK response received interrupt.
#define	USB_OTG_HCINT_ACK_Pos   (5U)
#define	USB_OTG_HCINT_ACK_Msk   (0x1UL << USB_OTG_HCINT_ACK_Pos)
	0x00000020
#define	USB_OTG_HCINT_ACK   USB_OTG_HCINT_ACK_Msk
	ACK response received/transmitted interrupt.
#define	USB_OTG_HCINT_NYET_Pos   (6U)
#define	USB_OTG_HCINT_NYET_Msk   (0x1UL << USB_OTG_HCINT_NYET_Pos)
	0x00000040
#define	USB_OTG_HCINT_NYET   USB_OTG_HCINT_NYET_Msk
	Response received interrupt.
#define	USB_OTG_HCINT_TXERR_Pos   (7U)
#define	USB_OTG_HCINT_TXERR_Msk   (0x1UL << USB_OTG_HCINT_TXERR_Pos)
	0x00000080
#define	USB_OTG_HCINT_TXERR   USB_OTG_HCINT_TXERR_Msk
	Transaction error.
#define	USB_OTG_HCINT_BBERR_Pos   (8U)
#define	USB_OTG_HCINT_BBERR_Msk   (0x1UL << USB_OTG_HCINT_BBERR_Pos)
	0x00000100
#define	USB_OTG_HCINT_BBERR   USB_OTG_HCINT_BBERR_Msk
	Babble error.
#define	USB_OTG_HCINT_FRMOR_Pos   (9U)
#define	USB_OTG_HCINT_FRMOR_Msk   (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
	0x00000200
#define	USB_OTG_HCINT_FRMOR   USB_OTG_HCINT_FRMOR_Msk
	Frame overrun.
#define	USB_OTG_HCINT_DTERR_Pos   (10U)
#define	USB_OTG_HCINT_DTERR_Msk   (0x1UL << USB_OTG_HCINT_DTERR_Pos)
	0x00000400
#define	USB_OTG_HCINT_DTERR   USB_OTG_HCINT_DTERR_Msk
	Data toggle error.
#define	USB_OTG_DIEPINT_XFRC_Pos   (0U)
#define	USB_OTG_DIEPINT_XFRC_Msk   (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
	0x00000001
#define	USB_OTG_DIEPINT_XFRC   USB_OTG_DIEPINT_XFRC_Msk
	Transfer completed interrupt.
#define	USB_OTG_DIEPINT_EPDISD_Pos   (1U)
#define	USB_OTG_DIEPINT_EPDISD_Msk   (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
	0x00000002
#define	USB_OTG_DIEPINT_EPDISD   USB_OTG_DIEPINT_EPDISD_Msk
	Endpoint disabled interrupt.
#define	USB_OTG_DIEPINT_AHBERR_Pos   (2U)
#define	USB_OTG_DIEPINT_AHBERR_Msk   (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
	0x00000004
#define	USB_OTG_DIEPINT_AHBERR   USB_OTG_DIEPINT_AHBERR_Msk
	AHB Error (AHBErr) during an IN transaction.
#define	USB_OTG_DIEPINT_TOC_Pos   (3U)
#define	USB_OTG_DIEPINT_TOC_Msk   (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
	0x00000008
#define	USB_OTG_DIEPINT_TOC   USB_OTG_DIEPINT_TOC_Msk
	Timeout condition.
#define	USB_OTG_DIEPINT_ITTXFE_Pos   (4U)
#define	USB_OTG_DIEPINT_ITTXFE_Msk   (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
	0x00000010
#define	USB_OTG_DIEPINT_ITTXFE   USB_OTG_DIEPINT_ITTXFE_Msk
	IN token received when TxFIFO is empty.
#define	USB_OTG_DIEPINT_INEPNM_Pos   (5U)
#define	USB_OTG_DIEPINT_INEPNM_Msk   (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
	0x00000020
#define	USB_OTG_DIEPINT_INEPNM   USB_OTG_DIEPINT_INEPNM_Msk
	IN token received with EP mismatch.
#define	USB_OTG_DIEPINT_INEPNE_Pos   (6U)
#define	USB_OTG_DIEPINT_INEPNE_Msk   (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
	0x00000040
#define	USB_OTG_DIEPINT_INEPNE   USB_OTG_DIEPINT_INEPNE_Msk
	IN endpoint NAK effective.
#define	USB_OTG_DIEPINT_TXFE_Pos   (7U)
#define	USB_OTG_DIEPINT_TXFE_Msk   (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
	0x00000080
#define	USB_OTG_DIEPINT_TXFE   USB_OTG_DIEPINT_TXFE_Msk
	Transmit FIFO empty.
#define	USB_OTG_DIEPINT_TXFIFOUDRN_Pos   (8U)
#define	USB_OTG_DIEPINT_TXFIFOUDRN_Msk   (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
	0x00000100
#define	USB_OTG_DIEPINT_TXFIFOUDRN   USB_OTG_DIEPINT_TXFIFOUDRN_Msk
	Transmit Fifo Underrun.
#define	USB_OTG_DIEPINT_BNA_Pos   (9U)
#define	USB_OTG_DIEPINT_BNA_Msk   (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
	0x00000200
#define	USB_OTG_DIEPINT_BNA   USB_OTG_DIEPINT_BNA_Msk
	Buffer not available interrupt.
#define	USB_OTG_DIEPINT_PKTDRPSTS_Pos   (11U)
#define	USB_OTG_DIEPINT_PKTDRPSTS_Msk   (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
	0x00000800
#define	USB_OTG_DIEPINT_PKTDRPSTS   USB_OTG_DIEPINT_PKTDRPSTS_Msk
	Packet dropped status.
#define	USB_OTG_DIEPINT_BERR_Pos   (12U)
#define	USB_OTG_DIEPINT_BERR_Msk   (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
	0x00001000
#define	USB_OTG_DIEPINT_BERR   USB_OTG_DIEPINT_BERR_Msk
	Babble error interrupt.
#define	USB_OTG_DIEPINT_NAK_Pos   (13U)
#define	USB_OTG_DIEPINT_NAK_Msk   (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
	0x00002000
#define	USB_OTG_DIEPINT_NAK   USB_OTG_DIEPINT_NAK_Msk
	NAK interrupt.
#define	USB_OTG_HCINTMSK_XFRCM_Pos   (0U)
#define	USB_OTG_HCINTMSK_XFRCM_Msk   (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
	0x00000001
#define	USB_OTG_HCINTMSK_XFRCM   USB_OTG_HCINTMSK_XFRCM_Msk
	Transfer completed mask.
#define	USB_OTG_HCINTMSK_CHHM_Pos   (1U)
#define	USB_OTG_HCINTMSK_CHHM_Msk   (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
	0x00000002
#define	USB_OTG_HCINTMSK_CHHM   USB_OTG_HCINTMSK_CHHM_Msk
	Channel halted mask.
#define	USB_OTG_HCINTMSK_AHBERR_Pos   (2U)
#define	USB_OTG_HCINTMSK_AHBERR_Msk   (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
	0x00000004
#define	USB_OTG_HCINTMSK_AHBERR   USB_OTG_HCINTMSK_AHBERR_Msk
	AHB error.
#define	USB_OTG_HCINTMSK_STALLM_Pos   (3U)
#define	USB_OTG_HCINTMSK_STALLM_Msk   (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
	0x00000008
#define	USB_OTG_HCINTMSK_STALLM   USB_OTG_HCINTMSK_STALLM_Msk
	STALL response received interrupt mask.
#define	USB_OTG_HCINTMSK_NAKM_Pos   (4U)
#define	USB_OTG_HCINTMSK_NAKM_Msk   (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
	0x00000010
#define	USB_OTG_HCINTMSK_NAKM   USB_OTG_HCINTMSK_NAKM_Msk
	NAK response received interrupt mask.
#define	USB_OTG_HCINTMSK_ACKM_Pos   (5U)
#define	USB_OTG_HCINTMSK_ACKM_Msk   (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
	0x00000020
#define	USB_OTG_HCINTMSK_ACKM   USB_OTG_HCINTMSK_ACKM_Msk
	ACK response received/transmitted interrupt mask.
#define	USB_OTG_HCINTMSK_NYET_Pos   (6U)
#define	USB_OTG_HCINTMSK_NYET_Msk   (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
	0x00000040
#define	USB_OTG_HCINTMSK_NYET   USB_OTG_HCINTMSK_NYET_Msk
	response received interrupt mask
#define	USB_OTG_HCINTMSK_TXERRM_Pos   (7U)
#define	USB_OTG_HCINTMSK_TXERRM_Msk   (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
	0x00000080
#define	USB_OTG_HCINTMSK_TXERRM   USB_OTG_HCINTMSK_TXERRM_Msk
	Transaction error mask.
#define	USB_OTG_HCINTMSK_BBERRM_Pos   (8U)
#define	USB_OTG_HCINTMSK_BBERRM_Msk   (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
	0x00000100
#define	USB_OTG_HCINTMSK_BBERRM   USB_OTG_HCINTMSK_BBERRM_Msk
	Babble error mask.
#define	USB_OTG_HCINTMSK_FRMORM_Pos   (9U)
#define	USB_OTG_HCINTMSK_FRMORM_Msk   (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
	0x00000200
#define	USB_OTG_HCINTMSK_FRMORM   USB_OTG_HCINTMSK_FRMORM_Msk
	Frame overrun mask.
#define	USB_OTG_HCINTMSK_DTERRM_Pos   (10U)
#define	USB_OTG_HCINTMSK_DTERRM_Msk   (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
	0x00000400
#define	USB_OTG_HCINTMSK_DTERRM   USB_OTG_HCINTMSK_DTERRM_Msk
	Data toggle error mask.
#define	USB_OTG_DIEPTSIZ_XFRSIZ_Pos   (0U)
#define	USB_OTG_DIEPTSIZ_XFRSIZ_Msk   (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
	0x0007FFFF
#define	USB_OTG_DIEPTSIZ_XFRSIZ   USB_OTG_DIEPTSIZ_XFRSIZ_Msk
	Transfer size.
#define	USB_OTG_DIEPTSIZ_PKTCNT_Pos   (19U)
#define	USB_OTG_DIEPTSIZ_PKTCNT_Msk   (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
	0x1FF80000
#define	USB_OTG_DIEPTSIZ_PKTCNT   USB_OTG_DIEPTSIZ_PKTCNT_Msk
	Packet count.
#define	USB_OTG_DIEPTSIZ_MULCNT_Pos   (29U)
#define	USB_OTG_DIEPTSIZ_MULCNT_Msk   (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
	0x60000000
#define	USB_OTG_DIEPTSIZ_MULCNT   USB_OTG_DIEPTSIZ_MULCNT_Msk
	Packet count.
#define	USB_OTG_HCTSIZ_XFRSIZ_Pos   (0U)
#define	USB_OTG_HCTSIZ_XFRSIZ_Msk   (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
	0x0007FFFF
#define	USB_OTG_HCTSIZ_XFRSIZ   USB_OTG_HCTSIZ_XFRSIZ_Msk
	Transfer size.
#define	USB_OTG_HCTSIZ_PKTCNT_Pos   (19U)
#define	USB_OTG_HCTSIZ_PKTCNT_Msk   (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
	0x1FF80000
#define	USB_OTG_HCTSIZ_PKTCNT   USB_OTG_HCTSIZ_PKTCNT_Msk
	Packet count.
#define	USB_OTG_HCTSIZ_DOPING_Pos   (31U)
#define	USB_OTG_HCTSIZ_DOPING_Msk   (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
	0x80000000
#define	USB_OTG_HCTSIZ_DOPING   USB_OTG_HCTSIZ_DOPING_Msk
	Do PING.
#define	USB_OTG_HCTSIZ_DPID_Pos   (29U)
#define	USB_OTG_HCTSIZ_DPID_Msk   (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
	0x60000000
#define	USB_OTG_HCTSIZ_DPID   USB_OTG_HCTSIZ_DPID_Msk
	Data PID.
#define	USB_OTG_HCTSIZ_DPID_0   (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
	0x20000000
#define	USB_OTG_HCTSIZ_DPID_1   (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
	0x40000000
#define	USB_OTG_DIEPDMA_DMAADDR_Pos   (0U)
#define	USB_OTG_DIEPDMA_DMAADDR_Msk   (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
	0xFFFFFFFF
#define	USB_OTG_DIEPDMA_DMAADDR   USB_OTG_DIEPDMA_DMAADDR_Msk
	DMA address.
#define	USB_OTG_HCDMA_DMAADDR_Pos   (0U)
#define	USB_OTG_HCDMA_DMAADDR_Msk   (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
	0xFFFFFFFF
#define	USB_OTG_HCDMA_DMAADDR   USB_OTG_HCDMA_DMAADDR_Msk
	DMA address.
#define	USB_OTG_DTXFSTS_INEPTFSAV_Pos   (0U)
#define	USB_OTG_DTXFSTS_INEPTFSAV_Msk   (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
	0x0000FFFF
#define	USB_OTG_DTXFSTS_INEPTFSAV   USB_OTG_DTXFSTS_INEPTFSAV_Msk
	IN endpoint TxFIFO space available.
#define	USB_OTG_DIEPTXF_INEPTXSA_Pos   (0U)
#define	USB_OTG_DIEPTXF_INEPTXSA_Msk   (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
	0x0000FFFF
#define	USB_OTG_DIEPTXF_INEPTXSA   USB_OTG_DIEPTXF_INEPTXSA_Msk
	IN endpoint FIFOx transmit RAM start address.
#define	USB_OTG_DIEPTXF_INEPTXFD_Pos   (16U)
#define	USB_OTG_DIEPTXF_INEPTXFD_Msk   (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
	0xFFFF0000
#define	USB_OTG_DIEPTXF_INEPTXFD   USB_OTG_DIEPTXF_INEPTXFD_Msk
	IN endpoint TxFIFO depth.
#define	USB_OTG_DOEPCTL_MPSIZ_Pos   (0U)
#define	USB_OTG_DOEPCTL_MPSIZ_Msk   (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
	0x000007FF
#define	USB_OTG_DOEPCTL_MPSIZ   USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */
	Bit 1.
#define	USB_OTG_DOEPCTL_USBAEP_Pos   (15U)
#define	USB_OTG_DOEPCTL_USBAEP_Msk   (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
	0x00008000
#define	USB_OTG_DOEPCTL_USBAEP   USB_OTG_DOEPCTL_USBAEP_Msk
	USB active endpoint.
#define	USB_OTG_DOEPCTL_NAKSTS_Pos   (17U)
#define	USB_OTG_DOEPCTL_NAKSTS_Msk   (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
	0x00020000
#define	USB_OTG_DOEPCTL_NAKSTS   USB_OTG_DOEPCTL_NAKSTS_Msk
	NAK status.
#define	USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos   (28U)
#define	USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk   (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
	0x10000000
#define	USB_OTG_DOEPCTL_SD0PID_SEVNFRM   USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
	Set DATA0 PID.
#define	USB_OTG_DOEPCTL_SODDFRM_Pos   (29U)
#define	USB_OTG_DOEPCTL_SODDFRM_Msk   (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
	0x20000000
#define	USB_OTG_DOEPCTL_SODDFRM   USB_OTG_DOEPCTL_SODDFRM_Msk
	Set odd frame.
#define	USB_OTG_DOEPCTL_EPTYP_Pos   (18U)
#define	USB_OTG_DOEPCTL_EPTYP_Msk   (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
	0x000C0000
#define	USB_OTG_DOEPCTL_EPTYP   USB_OTG_DOEPCTL_EPTYP_Msk
	Endpoint type.
#define	USB_OTG_DOEPCTL_EPTYP_0   (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
	0x00040000
#define	USB_OTG_DOEPCTL_EPTYP_1   (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
	0x00080000
#define	USB_OTG_DOEPCTL_SNPM_Pos   (20U)
#define	USB_OTG_DOEPCTL_SNPM_Msk   (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
	0x00100000
#define	USB_OTG_DOEPCTL_SNPM   USB_OTG_DOEPCTL_SNPM_Msk
	Snoop mode.
#define	USB_OTG_DOEPCTL_STALL_Pos   (21U)
#define	USB_OTG_DOEPCTL_STALL_Msk   (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
	0x00200000
#define	USB_OTG_DOEPCTL_STALL   USB_OTG_DOEPCTL_STALL_Msk
	STALL handshake.
#define	USB_OTG_DOEPCTL_CNAK_Pos   (26U)
#define	USB_OTG_DOEPCTL_CNAK_Msk   (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
	0x04000000
#define	USB_OTG_DOEPCTL_CNAK   USB_OTG_DOEPCTL_CNAK_Msk
	Clear NAK.
#define	USB_OTG_DOEPCTL_SNAK_Pos   (27U)
#define	USB_OTG_DOEPCTL_SNAK_Msk   (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
	0x08000000
#define	USB_OTG_DOEPCTL_SNAK   USB_OTG_DOEPCTL_SNAK_Msk
	Set NAK.
#define	USB_OTG_DOEPCTL_EPDIS_Pos   (30U)
#define	USB_OTG_DOEPCTL_EPDIS_Msk   (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
	0x40000000
#define	USB_OTG_DOEPCTL_EPDIS   USB_OTG_DOEPCTL_EPDIS_Msk
	Endpoint disable.
#define	USB_OTG_DOEPCTL_EPENA_Pos   (31U)
#define	USB_OTG_DOEPCTL_EPENA_Msk   (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
	0x80000000
#define	USB_OTG_DOEPCTL_EPENA   USB_OTG_DOEPCTL_EPENA_Msk
	Endpoint enable.
#define	USB_OTG_DOEPINT_XFRC_Pos   (0U)
#define	USB_OTG_DOEPINT_XFRC_Msk   (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
	0x00000001
#define	USB_OTG_DOEPINT_XFRC   USB_OTG_DOEPINT_XFRC_Msk
	Transfer completed interrupt.
#define	USB_OTG_DOEPINT_EPDISD_Pos   (1U)
#define	USB_OTG_DOEPINT_EPDISD_Msk   (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
	0x00000002
#define	USB_OTG_DOEPINT_EPDISD   USB_OTG_DOEPINT_EPDISD_Msk
	Endpoint disabled interrupt.
#define	USB_OTG_DOEPINT_AHBERR_Pos   (2U)
#define	USB_OTG_DOEPINT_AHBERR_Msk   (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
	0x00000004
#define	USB_OTG_DOEPINT_AHBERR   USB_OTG_DOEPINT_AHBERR_Msk
	AHB Error (AHBErr) during an OUT transaction.
#define	USB_OTG_DOEPINT_STUP_Pos   (3U)
#define	USB_OTG_DOEPINT_STUP_Msk   (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
	0x00000008
#define	USB_OTG_DOEPINT_STUP   USB_OTG_DOEPINT_STUP_Msk
	SETUP phase done.
#define	USB_OTG_DOEPINT_OTEPDIS_Pos   (4U)
#define	USB_OTG_DOEPINT_OTEPDIS_Msk   (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
	0x00000010
#define	USB_OTG_DOEPINT_OTEPDIS   USB_OTG_DOEPINT_OTEPDIS_Msk
	OUT token received when endpoint disabled.
#define	USB_OTG_DOEPINT_OTEPSPR_Pos   (5U)
#define	USB_OTG_DOEPINT_OTEPSPR_Msk   (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
	0x00000020
#define	USB_OTG_DOEPINT_OTEPSPR   USB_OTG_DOEPINT_OTEPSPR_Msk
	OUT Status Phase Received interrupt.
#define	USB_OTG_DOEPINT_B2BSTUP_Pos   (6U)
#define	USB_OTG_DOEPINT_B2BSTUP_Msk   (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
	0x00000040
#define	USB_OTG_DOEPINT_B2BSTUP   USB_OTG_DOEPINT_B2BSTUP_Msk
	Back-to-back SETUP packets received.
#define	USB_OTG_DOEPINT_OUTPKTERR_Pos   (8U)
#define	USB_OTG_DOEPINT_OUTPKTERR_Msk   (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
	0x00000100
#define	USB_OTG_DOEPINT_OUTPKTERR   USB_OTG_DOEPINT_OUTPKTERR_Msk
	OUT packet error.
#define	USB_OTG_DOEPINT_BNA_Pos   (9U)
#define	USB_OTG_DOEPINT_BNA_Msk   (0x1UL << USB_OTG_DOEPINT_BNA_Pos)
	0x00000200
#define	USB_OTG_DOEPINT_BNA   USB_OTG_DOEPINT_BNA_Msk
	Buffer not available interrupt.
#define	USB_OTG_DOEPINT_BERR_Pos   (12U)
#define	USB_OTG_DOEPINT_BERR_Msk   (0x1UL << USB_OTG_DOEPINT_BERR_Pos)
	0x00001000
#define	USB_OTG_DOEPINT_BERR   USB_OTG_DOEPINT_BERR_Msk
	Babble error interrupt.
#define	USB_OTG_DOEPINT_NAK_Pos   (13U)
#define	USB_OTG_DOEPINT_NAK_Msk   (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
	0x00002000
#define	USB_OTG_DOEPINT_NAK   USB_OTG_DOEPINT_NAK_Msk
	NAK Packet is transmitted by the device.
#define	USB_OTG_DOEPINT_NYET_Pos   (14U)
#define	USB_OTG_DOEPINT_NYET_Msk   (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
	0x00004000
#define	USB_OTG_DOEPINT_NYET   USB_OTG_DOEPINT_NYET_Msk
	NYET interrupt.
#define	USB_OTG_DOEPINT_STPKTRX_Pos   (15U)
#define	USB_OTG_DOEPINT_STPKTRX_Msk   (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
	0x00008000
#define	USB_OTG_DOEPINT_STPKTRX   USB_OTG_DOEPINT_STPKTRX_Msk
	Setup Packet Received.
#define	USB_OTG_DOEPTSIZ_XFRSIZ_Pos   (0U)
#define	USB_OTG_DOEPTSIZ_XFRSIZ_Msk   (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
	0x0007FFFF
#define	USB_OTG_DOEPTSIZ_XFRSIZ   USB_OTG_DOEPTSIZ_XFRSIZ_Msk
	Transfer size.
#define	USB_OTG_DOEPTSIZ_PKTCNT_Pos   (19U)
#define	USB_OTG_DOEPTSIZ_PKTCNT_Msk   (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
	0x1FF80000
#define	USB_OTG_DOEPTSIZ_PKTCNT   USB_OTG_DOEPTSIZ_PKTCNT_Msk
	Packet count.
#define	USB_OTG_DOEPTSIZ_STUPCNT_Pos   (29U)
#define	USB_OTG_DOEPTSIZ_STUPCNT_Msk   (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
	0x60000000
#define	USB_OTG_DOEPTSIZ_STUPCNT   USB_OTG_DOEPTSIZ_STUPCNT_Msk
	SETUP packet count.
#define	USB_OTG_DOEPTSIZ_STUPCNT_0   (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
	0x20000000
#define	USB_OTG_DOEPTSIZ_STUPCNT_1   (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
	0x40000000
#define	USB_OTG_PCGCCTL_STOPCLK_Pos   (0U)
#define	USB_OTG_PCGCCTL_STOPCLK_Msk   (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
	0x00000001
#define	USB_OTG_PCGCCTL_STOPCLK   USB_OTG_PCGCCTL_STOPCLK_Msk
	SETUP packet count.
#define	USB_OTG_PCGCCTL_GATECLK_Pos   (1U)
#define	USB_OTG_PCGCCTL_GATECLK_Msk   (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
	0x00000002
#define	USB_OTG_PCGCCTL_GATECLK   USB_OTG_PCGCCTL_GATECLK_Msk
	Bit 0.
#define	USB_OTG_PCGCCTL_PHYSUSP_Pos   (4U)
#define	USB_OTG_PCGCCTL_PHYSUSP_Msk   (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
	0x00000010
#define	USB_OTG_PCGCCTL_PHYSUSP   USB_OTG_PCGCCTL_PHYSUSP_Msk
	Bit 1.
#define	IS_ADC_ALL_INSTANCE(INSTANCE)
#define	IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE)
#define	IS_ADC_COMMON_INSTANCE(INSTANCE)
#define	IS_CORDIC_ALL_INSTANCE(INSTANCE)
#define	IS_FMAC_ALL_INSTANCE(INSTANCE)
#define	IS_COMP_ALL_INSTANCE(INSTANCE)
#define	IS_COMP_COMMON_INSTANCE(INSTANCE)
#define	IS_COMP_WINDOWMODE_INSTANCE(INSTANCE)
#define	IS_DTS_ALL_INSTANCE(INSTANCE)
#define	IS_CRC_ALL_INSTANCE(INSTANCE)
#define	IS_DAC_ALL_INSTANCE(INSTANCE)
#define	IS_DCMI_ALL_INSTANCE(__INSTANCE__)
#define	IS_DLYB_ALL_INSTANCE(INSTANCE)
#define	IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE)
#define	IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE)
#define	IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE)
#define	IS_DMA_ALL_INSTANCE(INSTANCE)
#define	IS_BDMA_CHANNEL_INSTANCE(INSTANCE)
#define	IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)
#define	IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)
#define	IS_DMA_STREAM_INSTANCE(INSTANCE)
#define	IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)
#define	IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE)
#define	IS_DMA2D_ALL_INSTANCE(__INSTANCE__)
#define	IS_PSSI_ALL_INSTANCE(INSTANCE)
#define	IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE)
#define	IS_FDCAN_ALL_INSTANCE(__INSTANCE__)
#define	IS_FDCAN_TT_INSTANCE(__INSTANCE__)
#define	IS_GPIO_ALL_INSTANCE(INSTANCE)
#define	IS_GPIO_AF_INSTANCE(INSTANCE)
#define	IS_GPIO_LOCK_INSTANCE(INSTANCE)
#define	IS_HSEM_ALL_INSTANCE(INSTANCE)
#define	HSEM_CPU1_COREID   (0x00000003UL) /* Semaphore Core CM7 ID */
#define	HSEM_CR_COREID_CPU1   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
#define	HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
#define	HSEM_SEMID_MIN   (0U) /* HSEM ID Min*/
#define	HSEM_SEMID_MAX   (31U) /* HSEM ID Max */
#define	HSEM_PROCESSID_MIN   (0U) /* HSEM Process ID Min */
#define	HSEM_PROCESSID_MAX   (255U) /* HSEM Process ID Max */
#define	HSEM_CLEAR_KEY_MIN   (0U) /* HSEM clear Key Min value */
#define	HSEM_CLEAR_KEY_MAX   (0xFFFFU) /* HSEM clear Key Max value */
#define	IS_I2C_ALL_INSTANCE(INSTANCE)
#define	IS_SMBUS_ALL_INSTANCE(INSTANCE)
#define	IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)
#define	IS_I2S_ALL_INSTANCE(INSTANCE)
#define	IS_LTDC_ALL_INSTANCE(INSTANCE)
#define	IS_RNG_ALL_INSTANCE(INSTANCE)
#define	IS_RTC_ALL_INSTANCE(INSTANCE)
#define	IS_SDMMC_ALL_INSTANCE(_INSTANCE_)
#define	IS_SPI_ALL_INSTANCE(INSTANCE)
#define	IS_SPI_HIGHEND_INSTANCE(INSTANCE)
#define	IS_SWPMI_INSTANCE(INSTANCE)
#define	IS_LPTIM_INSTANCE(INSTANCE)
#define	IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)
#define	IS_TIM_INSTANCE(INSTANCE)
#define	IS_TIM_CC1_INSTANCE(INSTANCE)
#define	IS_TIM_CC2_INSTANCE(INSTANCE)
#define	IS_TIM_CC3_INSTANCE(INSTANCE)
#define	IS_TIM_CC4_INSTANCE(INSTANCE)
#define	IS_TIM_CC5_INSTANCE(INSTANCE)
#define	IS_TIM_CC6_INSTANCE(INSTANCE)
#define	IS_TIM_ADVANCED_INSTANCE(__INSTANCE__)
#define	IS_TIM_XOR_INSTANCE(INSTANCE)
#define	IS_TIM_DMA_INSTANCE(INSTANCE)
#define	IS_TIM_DMA_CC_INSTANCE(INSTANCE)
#define	IS_TIM_CCDMA_INSTANCE(INSTANCE)
#define	IS_TIM_DMABURST_INSTANCE(INSTANCE)
#define	IS_TIM_ETR_INSTANCE(INSTANCE)
#define	IS_TIM_REMAP_INSTANCE(INSTANCE)
#define	IS_TIM_ETRSEL_INSTANCE(INSTANCE)
#define	IS_TIM_MASTER_INSTANCE(INSTANCE)
#define	IS_TIM_SLAVE_INSTANCE(INSTANCE)
#define	IS_TIM_TRGO2_INSTANCE(INSTANCE)
#define	IS_TIM_TISEL_INSTANCE(INSTANCE)
#define	IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)
#define	IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)
#define	IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)
#define	IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL)
#define	IS_TIM_BREAK_INSTANCE(INSTANCE)
#define	IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE)
#define	IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL)
#define	IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)
#define	IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)
#define	IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)
#define	IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)
#define	IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)
#define	IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)
#define	IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)
#define	IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)
#define	IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)
#define	IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)
#define	IS_TIM_BKIN2_INSTANCE(INSTANCE)
#define	IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__)
#define	IS_USART_INSTANCE(INSTANCE)
#define	IS_UART_SPI_SLAVE_INSTANCE(INSTANCE)
#define	IS_UART_INSTANCE(INSTANCE)
#define	IS_UART_FIFO_INSTANCE(INSTANCE)
#define	IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE)
#define	IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)
#define	IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)
#define	IS_UART_HWFLOW_INSTANCE(INSTANCE)
#define	IS_UART_LIN_INSTANCE(INSTANCE)
#define	IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)
#define	IS_IRDA_INSTANCE(INSTANCE)
#define	IS_SMARTCARD_INSTANCE(INSTANCE)
#define	IS_LPUART_INSTANCE(INSTANCE)
#define	IS_IWDG_ALL_INSTANCE(INSTANCE)
#define	IS_USB_ALL_INSTANCE(INSTANCE)
#define	IS_WWDG_ALL_INSTANCE(INSTANCE)
#define	IS_MDIOS_ALL_INSTANCE(INSTANCE)
#define	IS_CEC_ALL_INSTANCE(__INSTANCE__)
#define	IS_SAI_ALL_INSTANCE(INSTANCE)
#define	IS_SPDIFRX_ALL_INSTANCE(INSTANCE)
#define	IS_OPAMP_ALL_INSTANCE(INSTANCE)
#define	IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE)
#define	IS_PCD_ALL_INSTANCE(INSTANCE)
#define	IS_HCD_ALL_INSTANCE(INSTANCE)
#define	HASH_RNG_IRQn   RNG_IRQn
#define	TIM1_BRK_TIM9_IRQn   TIM1_BRK_IRQn
#define	TIM1_UP_TIM10_IRQn   TIM1_UP_IRQn
#define	TIM1_TRG_COM_TIM11_IRQn   TIM1_TRG_COM_IRQn
#define	PVD_IRQn   PVD_AVD_IRQn
#define	DCMI_IRQn   DCMI_PSSI_IRQn
#define	HASH_RNG_IRQHandler   RNG_IRQHandler
#define	TIM1_BRK_TIM9_IRQHandler   TIM1_BRK_IRQHandler
#define	TIM1_UP_TIM9_IRQHandler   TIM1_UP_IRQHandler
#define	TIM1_TRG_COM_TIM11_IRQHandler   TIM1_TRG_COM_IRQHandler
#define	PVD_IRQHandler   PVD_AVD_IRQHandler
#define	COMP_IRQHandler   COMP1_IRQHandler

Enumerations
enum	IRQn_Type {   NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , MemoryManagement_IRQn = -12 , BusFault_IRQn = -11 ,   UsageFault_IRQn = -10 , SVCall_IRQn = -5 , DebugMonitor_IRQn = -4 , PendSV_IRQn = -2 ,   SysTick_IRQn = -1 , WWDG_IRQn = 0 , PVD_AVD_IRQn = 1 , TAMP_STAMP_IRQn = 2 ,   RTC_WKUP_IRQn = 3 , FLASH_IRQn = 4 , RCC_IRQn = 5 , EXTI0_IRQn = 6 ,   EXTI1_IRQn = 7 , EXTI2_IRQn = 8 , EXTI3_IRQn = 9 , EXTI4_IRQn = 10 ,   DMA1_Stream0_IRQn = 11 , DMA1_Stream1_IRQn = 12 , DMA1_Stream2_IRQn = 13 , DMA1_Stream3_IRQn = 14 ,   DMA1_Stream4_IRQn = 15 , DMA1_Stream5_IRQn = 16 , DMA1_Stream6_IRQn = 17 , ADC_IRQn = 18 ,   FDCAN1_IT0_IRQn = 19 , FDCAN2_IT0_IRQn = 20 , FDCAN1_IT1_IRQn = 21 , FDCAN2_IT1_IRQn = 22 ,   EXTI9_5_IRQn = 23 , TIM1_BRK_IRQn = 24 , TIM1_UP_IRQn = 25 , TIM1_TRG_COM_IRQn = 26 ,   TIM1_CC_IRQn = 27 , TIM2_IRQn = 28 , TIM3_IRQn = 29 , TIM4_IRQn = 30 ,   I2C1_EV_IRQn = 31 , I2C1_ER_IRQn = 32 , I2C2_EV_IRQn = 33 , I2C2_ER_IRQn = 34 ,   SPI1_IRQn = 35 , SPI2_IRQn = 36 , USART1_IRQn = 37 , USART2_IRQn = 38 ,   USART3_IRQn = 39 , EXTI15_10_IRQn = 40 , RTC_Alarm_IRQn = 41 , TIM8_BRK_TIM12_IRQn = 43 ,   TIM8_UP_TIM13_IRQn = 44 , TIM8_TRG_COM_TIM14_IRQn = 45 , TIM8_CC_IRQn = 46 , DMA1_Stream7_IRQn = 47 ,   FMC_IRQn = 48 , SDMMC1_IRQn = 49 , TIM5_IRQn = 50 , SPI3_IRQn = 51 ,   UART4_IRQn = 52 , UART5_IRQn = 53 , TIM6_DAC_IRQn = 54 , TIM7_IRQn = 55 ,   DMA2_Stream0_IRQn = 56 , DMA2_Stream1_IRQn = 57 , DMA2_Stream2_IRQn = 58 , DMA2_Stream3_IRQn = 59 ,   DMA2_Stream4_IRQn = 60 , ETH_IRQn = 61 , ETH_WKUP_IRQn = 62 , FDCAN_CAL_IRQn = 63 ,   DMA2_Stream5_IRQn = 68 , DMA2_Stream6_IRQn = 69 , DMA2_Stream7_IRQn = 70 , USART6_IRQn = 71 ,   I2C3_EV_IRQn = 72 , I2C3_ER_IRQn = 73 , OTG_HS_EP1_OUT_IRQn = 74 , OTG_HS_EP1_IN_IRQn = 75 ,   OTG_HS_WKUP_IRQn = 76 , OTG_HS_IRQn = 77 , DCMI_PSSI_IRQn = 78 , RNG_IRQn = 80 ,   FPU_IRQn = 81 , UART7_IRQn = 82 , UART8_IRQn = 83 , SPI4_IRQn = 84 ,   SPI5_IRQn = 85 , SPI6_IRQn = 86 , SAI1_IRQn = 87 , LTDC_IRQn = 88 ,   LTDC_ER_IRQn = 89 , DMA2D_IRQn = 90 , OCTOSPI1_IRQn = 92 , LPTIM1_IRQn = 93 ,   CEC_IRQn = 94 , I2C4_EV_IRQn = 95 , I2C4_ER_IRQn = 96 , SPDIF_RX_IRQn = 97 ,   DMAMUX1_OVR_IRQn = 102 , DFSDM1_FLT0_IRQn = 110 , DFSDM1_FLT1_IRQn = 111 , DFSDM1_FLT2_IRQn = 112 ,   DFSDM1_FLT3_IRQn = 113 , SWPMI1_IRQn = 115 , TIM15_IRQn = 116 , TIM16_IRQn = 117 ,   TIM17_IRQn = 118 , MDIOS_WKUP_IRQn = 119 , MDIOS_IRQn = 120 , MDMA_IRQn = 122 ,   SDMMC2_IRQn = 124 , HSEM1_IRQn = 125 , ADC3_IRQn = 127 , DMAMUX2_OVR_IRQn = 128 ,   BDMA_Channel0_IRQn = 129 , BDMA_Channel1_IRQn = 130 , BDMA_Channel2_IRQn = 131 , BDMA_Channel3_IRQn = 132 ,   BDMA_Channel4_IRQn = 133 , BDMA_Channel5_IRQn = 134 , BDMA_Channel6_IRQn = 135 , BDMA_Channel7_IRQn = 136 ,   COMP_IRQn = 137 , LPTIM2_IRQn = 138 , LPTIM3_IRQn = 139 , LPTIM4_IRQn = 140 ,   LPTIM5_IRQn = 141 , LPUART1_IRQn = 142 , CRS_IRQn = 144 , ECC_IRQn = 145 ,   SAI4_IRQn = 146 , DTS_IRQn = 147 , WAKEUP_PIN_IRQn = 149 , OCTOSPI2_IRQn = 150 ,   FMAC_IRQn = 153 , CORDIC_IRQn = 154 , UART9_IRQn = 155 , USART10_IRQn = 156 ,   I2C5_EV_IRQn = 157 , I2C5_ER_IRQn = 158 , FDCAN3_IT0_IRQn = 159 , FDCAN3_IT1_IRQn = 160 ,   TIM23_IRQn = 161 , TIM24_IRQn = 162 }
	STM32H7XX Interrupt Number Definition, according to the selected device in Library_configuration_section. More...

Detailed Description

CMSIS STM32H723xx Device Peripheral Access Layer Header File.

Author

MCD Application Team

     This file contains:
      - Data structures and the address mapping for all peripherals
      - Peripheral's registers declarations and bits definition
      - Macros to access peripheral's registers hardware

Attention

Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32h723xx.h.